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663e8e51
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1/*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (c) 2006-2007 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
8167ee88 20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
663e8e51
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21 *
22 * Tested features (i82559):
23 * PXE boot (i386) no valid link
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 */
35
36#if defined(TARGET_I386)
37# warning "PXE boot still not working!"
38#endif
39
663e8e51 40#include <stddef.h> /* offsetof */
b84a5c6f 41#include <stdbool.h>
87ecb68b
PB
42#include "hw.h"
43#include "pci.h"
44#include "net.h"
663e8e51
TS
45#include "eeprom93xx.h"
46
47/* Common declarations for all PCI devices. */
48
663e8e51
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49#define PCI_CONFIG_8(offset, value) \
50 (pci_conf[offset] = (value))
51#define PCI_CONFIG_16(offset, value) \
52 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
53#define PCI_CONFIG_32(offset, value) \
54 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
55
56#define KiB 1024
57
aac443e6 58/* Debug EEPRO100 card. */
663e8e51
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59//~ #define DEBUG_EEPRO100
60
61#ifdef DEBUG_EEPRO100
001faf32 62#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
663e8e51 63#else
001faf32 64#define logout(fmt, ...) ((void)0)
663e8e51
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65#endif
66
67/* Set flags to 0 to disable debug output. */
aac443e6
SW
68#define INT 1 /* interrupt related actions */
69#define MDI 1 /* mdi related actions */
70#define OTHER 1
71#define RXTX 1
72#define EEPROM 1 /* eeprom related actions */
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73
74#define TRACE(flag, command) ((flag) ? (command) : (void)0)
75
76#define missing(text) assert(!"feature is missing in this emulation: " text)
77
78#define MAX_ETH_FRAME_SIZE 1514
79
80/* This driver supports several different devices which are declared here. */
c4c270e2 81#define i82550 0x82550
663e8e51 82#define i82551 0x82551
c4c270e2 83#define i82557A 0x82557a
663e8e51
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84#define i82557B 0x82557b
85#define i82557C 0x82557c
c4c270e2 86#define i82558A 0x82558a
663e8e51 87#define i82558B 0x82558b
c4c270e2
SW
88#define i82559A 0x82559a
89#define i82559B 0x82559b
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90#define i82559C 0x82559c
91#define i82559ER 0x82559e
92#define i82562 0x82562
93
aac443e6 94/* Use 64 word EEPROM. TODO: could be a runtime option. */
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95#define EEPROM_SIZE 64
96
97#define PCI_MEM_SIZE (4 * KiB)
98#define PCI_IO_SIZE 64
99#define PCI_FLASH_SIZE (128 * KiB)
100
101#define BIT(n) (1 << (n))
102#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
103
104/* The SCB accepts the following controls for the Tx and Rx units: */
105#define CU_NOP 0x0000 /* No operation. */
106#define CU_START 0x0010 /* CU start. */
107#define CU_RESUME 0x0020 /* CU resume. */
108#define CU_STATSADDR 0x0040 /* Load dump counters address. */
109#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
110#define CU_CMD_BASE 0x0060 /* Load CU base address. */
111#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
112#define CU_SRESUME 0x00a0 /* CU static resume. */
113
114#define RU_NOP 0x0000
115#define RX_START 0x0001
116#define RX_RESUME 0x0002
117#define RX_ABORT 0x0004
118#define RX_ADDR_LOAD 0x0006
119#define RX_RESUMENR 0x0007
120#define INT_MASK 0x0100
121#define DRVR_INT 0x0200 /* Driver generated interrupt. */
122
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123/* Offsets to the various registers.
124 All accesses need not be longword aligned. */
125enum speedo_offsets {
126 SCBStatus = 0,
127 SCBAck = 1,
128 SCBCmd = 2, /* Rx/Command Unit command and status. */
129 SCBIntmask = 3,
130 SCBPointer = 4, /* General purpose pointer. */
131 SCBPort = 8, /* Misc. commands and operands. */
132 SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
133 SCBCtrlMDI = 16, /* MDI interface control. */
134 SCBEarlyRx = 20, /* Early receive byte count. */
3257d2b6 135 SCBFlow = 24,
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136};
137
138/* A speedo3 transmit buffer descriptor with two buffers... */
139typedef struct {
140 uint16_t status;
141 uint16_t command;
142 uint32_t link; /* void * */
143 uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */
144 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
145 uint8_t tx_threshold; /* transmit threshold */
146 uint8_t tbd_count; /* TBD number */
147 //~ /* This constitutes two "TBD" entries: hdr and data */
148 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
149 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
150 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
151 //~ int32_t tx_buf_size1; /* Length of Tx data. */
c227f099 152} eepro100_tx_t;
663e8e51
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153
154/* Receive frame descriptor. */
155typedef struct {
156 int16_t status;
157 uint16_t command;
158 uint32_t link; /* struct RxFD * */
159 uint32_t rx_buf_addr; /* void * */
160 uint16_t count;
161 uint16_t size;
162 char packet[MAX_ETH_FRAME_SIZE + 4];
c227f099 163} eepro100_rx_t;
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164
165typedef struct {
166 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
167 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
168 tx_multiple_collisions, tx_total_collisions;
169 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
170 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
171 rx_short_frame_errors;
172 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
173 uint16_t xmt_tco_frames, rcv_tco_frames;
174 uint32_t complete;
c227f099 175} eepro100_stats_t;
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176
177typedef enum {
178 cu_idle = 0,
179 cu_suspended = 1,
180 cu_active = 2,
181 cu_lpq_active = 2,
182 cu_hqp_active = 3
c227f099 183} cu_state_t;
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184
185typedef enum {
186 ru_idle = 0,
187 ru_suspended = 1,
188 ru_no_resources = 2,
189 ru_ready = 4
c227f099 190} ru_state_t;
663e8e51 191
663e8e51 192typedef struct {
273a2142 193 PCIDevice dev;
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194#if 1
195 uint8_t cmd;
196 uint32_t start;
197 uint32_t stop;
4e3db917
AJ
198 uint8_t boundary;
199 uint8_t tsr;
200 uint8_t tpsr;
201 uint16_t tcnt;
202 uint16_t rcnt;
203 uint32_t rsar;
204 uint8_t rsr;
205 uint8_t rxcr;
206 uint8_t isr;
207 uint8_t dcfg;
208 uint8_t imr;
209 uint8_t phys[6]; /* mac address */
210 uint8_t curpag;
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211 uint8_t mult[8]; /* multicast mask array */
212 int mmio_index;
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213 VLANClientState *vc;
214#endif
215 uint8_t scb_stat; /* SCB stat/ack byte */
216 uint8_t int_stat; /* PCI interrupt status */
217 uint32_t region[3]; /* PCI region addresses */
218 uint8_t macaddr[6];
4e3db917 219 uint32_t statcounter[19];
663e8e51 220 uint16_t mdimem[32];
c227f099 221 eeprom_t *eeprom;
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TS
222 uint32_t device; /* device variant */
223 uint32_t pointer;
224 /* (cu_base + cu_offset) address the next command block in the command block list. */
225 uint32_t cu_base; /* CU base address */
226 uint32_t cu_offset; /* CU address offset */
227 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
228 uint32_t ru_base; /* RU base address */
229 uint32_t ru_offset; /* RU address offset */
c227f099 230 uint32_t statsaddr; /* pointer to eepro100_stats_t */
4e3db917 231 eepro100_stats_t statistics; /* statistical counters */
663e8e51
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232#if 0
233 uint16_t status;
234#endif
235
236 /* Configuration bytes. */
237 uint8_t configuration[22];
238
239 /* Data in mem is always in the byte order of the controller (le). */
240 uint8_t mem[PCI_MEM_SIZE];
241} EEPRO100State;
242
243/* Default values for MDI (PHY) registers */
244static const uint16_t eepro100_mdi_default[] = {
245 /* MDI Registers 0 - 6, 7 */
246 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
247 /* MDI Registers 8 - 15 */
248 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
249 /* MDI Registers 16 - 31 */
250 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
251 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
252};
253
254/* Readonly mask for MDI (PHY) registers */
255static const uint16_t eepro100_mdi_mask[] = {
256 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
257 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
258 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
259 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
260};
261
262#define POLYNOMIAL 0x04c11db6
263
264/* From FreeBSD */
265/* XXX: optimize */
266static int compute_mcast_idx(const uint8_t * ep)
267{
268 uint32_t crc;
269 int carry, i, j;
270 uint8_t b;
271
272 crc = 0xffffffff;
273 for (i = 0; i < 6; i++) {
274 b = *ep++;
275 for (j = 0; j < 8; j++) {
276 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
277 crc <<= 1;
278 b >>= 1;
aac443e6 279 if (carry) {
663e8e51 280 crc = ((crc ^ POLYNOMIAL) | carry);
aac443e6 281 }
663e8e51
TS
282 }
283 }
284 return (crc >> 26);
285}
286
287#if defined(DEBUG_EEPRO100)
288static const char *nic_dump(const uint8_t * buf, unsigned size)
289{
290 static char dump[3 * 16 + 1];
291 char *p = &dump[0];
aac443e6 292 if (size > 16) {
663e8e51 293 size = 16;
aac443e6 294 }
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295 while (size-- > 0) {
296 p += sprintf(p, " %02x", *buf++);
297 }
298 return dump;
299}
300#endif /* DEBUG_EEPRO100 */
301
302enum scb_stat_ack {
303 stat_ack_not_ours = 0x00,
304 stat_ack_sw_gen = 0x04,
305 stat_ack_rnr = 0x10,
306 stat_ack_cu_idle = 0x20,
307 stat_ack_frame_rx = 0x40,
308 stat_ack_cu_cmd_done = 0x80,
309 stat_ack_not_present = 0xFF,
310 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
311 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
312};
313
314static void disable_interrupt(EEPRO100State * s)
315{
316 if (s->int_stat) {
aac443e6 317 TRACE(INT, logout("interrupt disabled\n"));
273a2142 318 qemu_irq_lower(s->dev.irq[0]);
663e8e51
TS
319 s->int_stat = 0;
320 }
321}
322
323static void enable_interrupt(EEPRO100State * s)
324{
325 if (!s->int_stat) {
aac443e6 326 TRACE(INT, logout("interrupt enabled\n"));
273a2142 327 qemu_irq_raise(s->dev.irq[0]);
663e8e51
TS
328 s->int_stat = 1;
329 }
330}
331
332static void eepro100_acknowledge(EEPRO100State * s)
333{
334 s->scb_stat &= ~s->mem[SCBAck];
335 s->mem[SCBAck] = s->scb_stat;
336 if (s->scb_stat == 0) {
337 disable_interrupt(s);
338 }
339}
340
341static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
342{
343 uint8_t mask = ~s->mem[SCBIntmask];
344 s->mem[SCBAck] |= stat;
345 stat = s->scb_stat = s->mem[SCBAck];
346 stat &= (mask | 0x0f);
347 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
348 if (stat && (mask & 0x01)) {
349 /* SCB mask and SCB Bit M do not disable interrupt. */
350 enable_interrupt(s);
351 } else if (s->int_stat) {
352 disable_interrupt(s);
353 }
354}
355
356static void eepro100_cx_interrupt(EEPRO100State * s)
357{
358 /* CU completed action command. */
359 /* Transmit not ok (82557 only, not in emulation). */
360 eepro100_interrupt(s, 0x80);
361}
362
363static void eepro100_cna_interrupt(EEPRO100State * s)
364{
365 /* CU left the active state. */
366 eepro100_interrupt(s, 0x20);
367}
368
369static void eepro100_fr_interrupt(EEPRO100State * s)
370{
371 /* RU received a complete frame. */
372 eepro100_interrupt(s, 0x40);
373}
374
375#if 0
376static void eepro100_rnr_interrupt(EEPRO100State * s)
377{
378 /* RU is not ready. */
379 eepro100_interrupt(s, 0x10);
380}
381#endif
382
383static void eepro100_mdi_interrupt(EEPRO100State * s)
384{
385 /* MDI completed read or write cycle. */
386 eepro100_interrupt(s, 0x08);
387}
388
389static void eepro100_swi_interrupt(EEPRO100State * s)
390{
391 /* Software has requested an interrupt. */
392 eepro100_interrupt(s, 0x04);
393}
394
395#if 0
396static void eepro100_fcp_interrupt(EEPRO100State * s)
397{
398 /* Flow control pause interrupt (82558 and later). */
399 eepro100_interrupt(s, 0x01);
400}
401#endif
402
403static void pci_reset(EEPRO100State * s)
404{
405 uint32_t device = s->device;
273a2142 406 uint8_t *pci_conf = s->dev.config;
663e8e51 407
aac443e6 408 TRACE(OTHER, logout("%p\n", s));
663e8e51
TS
409
410 /* PCI Vendor ID */
deb54399 411 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
d6fd1e66 412 /* PCI Device ID depends on device and is set below. */
663e8e51
TS
413 /* PCI Command */
414 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
415 /* PCI Status */
416 PCI_CONFIG_16(PCI_STATUS, 0x2800);
417 /* PCI Revision ID */
418 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
419 /* PCI Class Code */
420 PCI_CONFIG_8(0x09, 0x00);
173a543b 421 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
663e8e51
TS
422 /* PCI Cache Line Size */
423 /* check cache line size!!! */
424 //~ PCI_CONFIG_8(0x0c, 0x00);
425 /* PCI Latency Timer */
426 PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks
427 /* PCI Header Type */
428 /* BIST (built-in self test) */
429#if defined(TARGET_I386)
430// !!! workaround for buggy bios
431//~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
432#endif
433#if 0
434 /* PCI Base Address Registers */
435 /* CSR Memory Mapped Base Address */
436 PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
437 PCI_ADDRESS_SPACE_MEM | PCI_ADDRESS_SPACE_MEM_PREFETCH);
438 /* CSR I/O Mapped Base Address */
439 PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_ADDRESS_SPACE_IO);
440#if 0
441 /* Flash Memory Mapped Base Address */
442 PCI_CONFIG_32(PCI_BASE_ADDRESS_2, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM);
443#endif
444#endif
445 /* Expansion ROM Base Address (depends on boot disable!!!) */
446 PCI_CONFIG_32(0x30, 0x00000000);
447 /* Capability Pointer */
448 PCI_CONFIG_8(0x34, 0xdc);
aac443e6 449 /* Interrupt Line */
663e8e51
TS
450 /* Interrupt Pin */
451 PCI_CONFIG_8(0x3d, 1); // interrupt pin 0
452 /* Minimum Grant */
453 PCI_CONFIG_8(0x3e, 0x08);
454 /* Maximum Latency */
455 PCI_CONFIG_8(0x3f, 0x18);
456 /* Power Management Capabilities / Next Item Pointer / Capability ID */
457 PCI_CONFIG_32(0xdc, 0x7e210001);
458
459 switch (device) {
460 case i82551:
d6fd1e66 461 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
663e8e51
TS
462 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
463 break;
464 case i82557B:
d6fd1e66 465 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
663e8e51
TS
466 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
467 break;
468 case i82557C:
d6fd1e66 469 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
663e8e51
TS
470 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
471 break;
472 case i82558B:
d6fd1e66 473 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
663e8e51
TS
474 PCI_CONFIG_16(PCI_STATUS, 0x2810);
475 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
476 break;
477 case i82559C:
d6fd1e66 478 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
663e8e51
TS
479 PCI_CONFIG_16(PCI_STATUS, 0x2810);
480 //~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
481 break;
482 case i82559ER:
d6fd1e66 483 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
663e8e51
TS
484 PCI_CONFIG_16(PCI_STATUS, 0x2810);
485 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
486 break;
487 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
488 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
489 default:
490 logout("Device %X is undefined!\n", device);
491 }
492
493 if (device == i82557C || device == i82558B || device == i82559C) {
494 logout("Get device id and revision from EEPROM!!!\n");
495 }
496}
497
498static void nic_selective_reset(EEPRO100State * s)
499{
500 size_t i;
501 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
502 //~ eeprom93xx_reset(s->eeprom);
503 memcpy(eeprom_contents, s->macaddr, 6);
504 eeprom_contents[0xa] = 0x4000;
505 uint16_t sum = 0;
506 for (i = 0; i < EEPROM_SIZE - 1; i++) {
507 sum += eeprom_contents[i];
508 }
509 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
aac443e6 510 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
663e8e51
TS
511
512 memset(s->mem, 0, sizeof(s->mem));
513 uint32_t val = BIT(21);
514 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
515
516 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
517 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
518}
519
520static void nic_reset(void *opaque)
521{
769cf7a5 522 EEPRO100State *s = opaque;
aac443e6 523 TRACE(OTHER, logout("%p\n", s));
663e8e51
TS
524 nic_selective_reset(s);
525}
526
527#if defined(DEBUG_EEPRO100)
6a0b9cc9 528static const char * const reg[PCI_IO_SIZE / 4] = {
663e8e51
TS
529 "Command/Status",
530 "General Pointer",
531 "Port",
532 "EEPROM/Flash Control",
533 "MDI Control",
534 "Receive DMA Byte Count",
aac443e6 535 "Flow control",
663e8e51
TS
536 "General Status/Control"
537};
538
539static char *regname(uint32_t addr)
540{
541 static char buf[16];
542 if (addr < PCI_IO_SIZE) {
543 const char *r = reg[addr / 4];
544 if (r != 0) {
41cbc23c 545 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
663e8e51 546 } else {
41cbc23c 547 snprintf(buf, sizeof(buf), "0x%02x", addr);
663e8e51
TS
548 }
549 } else {
41cbc23c 550 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
663e8e51
TS
551 }
552 return buf;
553}
554#endif /* DEBUG_EEPRO100 */
555
556#if 0
557static uint16_t eepro100_read_status(EEPRO100State * s)
558{
559 uint16_t val = s->status;
aac443e6 560 TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
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561 return val;
562}
563
564static void eepro100_write_status(EEPRO100State * s, uint16_t val)
565{
aac443e6 566 TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
TS
567 s->status = val;
568}
569#endif
570
571/*****************************************************************************
572 *
573 * Command emulation.
574 *
575 ****************************************************************************/
576
577#if 0
578static uint16_t eepro100_read_command(EEPRO100State * s)
579{
580 uint16_t val = 0xffff;
aac443e6 581 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
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582 return val;
583}
584#endif
585
0859df68
NS
586static bool device_supports_eTxCB(EEPRO100State * s)
587{
588 return (s->device != i82557B && s->device != i82557C);
589}
590
663e8e51
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591/* Commands that can be put in a command list entry. */
592enum commands {
593 CmdNOp = 0,
594 CmdIASetup = 1,
595 CmdConfigure = 2,
596 CmdMulticastList = 3,
597 CmdTx = 4,
598 CmdTDR = 5, /* load microcode */
599 CmdDump = 6,
600 CmdDiagnose = 7,
601
602 /* And some extra flags: */
603 CmdSuspend = 0x4000, /* Suspend after completion. */
604 CmdIntr = 0x2000, /* Interrupt after completion. */
605 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
606};
607
c227f099 608static cu_state_t get_cu_state(EEPRO100State * s)
663e8e51
TS
609{
610 return ((s->mem[SCBStatus] >> 6) & 0x03);
611}
612
c227f099 613static void set_cu_state(EEPRO100State * s, cu_state_t state)
663e8e51
TS
614{
615 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
616}
617
c227f099 618static ru_state_t get_ru_state(EEPRO100State * s)
663e8e51
TS
619{
620 return ((s->mem[SCBStatus] >> 2) & 0x0f);
621}
622
c227f099 623static void set_ru_state(EEPRO100State * s, ru_state_t state)
663e8e51
TS
624{
625 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
626}
627
628static void dump_statistics(EEPRO100State * s)
629{
630 /* Dump statistical data. Most data is never changed by the emulation
631 * and always 0, so we first just copy the whole block and then those
632 * values which really matter.
633 * Number of data should check configuration!!!
634 */
635 cpu_physical_memory_write(s->statsaddr, (uint8_t *) & s->statistics, 64);
636 stl_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
637 stl_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
638 stl_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
639 stl_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
640 //~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
641 //~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
642 //~ missing("CU dump statistical counters");
643}
644
645static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
646{
c227f099 647 eepro100_tx_t tx;
663e8e51
TS
648 uint32_t cb_address;
649 switch (val) {
650 case CU_NOP:
651 /* No operation. */
652 break;
653 case CU_START:
654 if (get_cu_state(s) != cu_idle) {
655 /* Intel documentation says that CU must be idle for the CU
656 * start command. Intel driver for Linux also starts the CU
657 * from suspended state. */
658 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
659 //~ assert(!"wrong CU state");
660 }
661 set_cu_state(s, cu_active);
662 s->cu_offset = s->pointer;
663 next_command:
664 cb_address = s->cu_base + s->cu_offset;
665 cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx));
666 uint16_t status = le16_to_cpu(tx.status);
667 uint16_t command = le16_to_cpu(tx.command);
668 logout
669 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
670 val, status, command, tx.link);
671 bool bit_el = ((command & 0x8000) != 0);
672 bool bit_s = ((command & 0x4000) != 0);
673 bool bit_i = ((command & 0x2000) != 0);
674 bool bit_nc = ((command & 0x0010) != 0);
675 //~ bool bit_sf = ((command & 0x0008) != 0);
676 uint16_t cmd = command & 0x0007;
677 s->cu_offset = le32_to_cpu(tx.link);
678 switch (cmd) {
679 case CmdNOp:
680 /* Do nothing. */
681 break;
682 case CmdIASetup:
683 cpu_physical_memory_read(cb_address + 8, &s->macaddr[0], 6);
aac443e6 684 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)));
663e8e51
TS
685 break;
686 case CmdConfigure:
687 cpu_physical_memory_read(cb_address + 8, &s->configuration[0],
688 sizeof(s->configuration));
aac443e6 689 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
663e8e51
TS
690 break;
691 case CmdMulticastList:
692 //~ missing("multicast list");
693 break;
694 case CmdTx:
695 (void)0;
696 uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr);
697 uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff);
aac443e6 698 TRACE(RXTX, logout
663e8e51 699 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
aac443e6 700 tbd_array, tcb_bytes, tx.tbd_count));
663e8e51
TS
701 assert(!bit_nc);
702 //~ assert(!bit_sf);
703 assert(tcb_bytes <= 2600);
704 /* Next assertion fails for local configuration. */
705 //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
706 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
707 logout
708 ("illegal values of TBD array address and TCB byte count!\n");
709 }
24e6f355
RD
710 // sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes
711 uint8_t buf[2600];
663e8e51
TS
712 uint16_t size = 0;
713 uint32_t tbd_address = cb_address + 0x10;
714 assert(tcb_bytes <= sizeof(buf));
715 while (size < tcb_bytes) {
716 uint32_t tx_buffer_address = ldl_phys(tbd_address);
717 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
718 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
719 tbd_address += 8;
aac443e6 720 TRACE(RXTX, logout
663e8e51 721 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
aac443e6 722 tx_buffer_address, tx_buffer_size));
24e6f355 723 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
663e8e51
TS
724 cpu_physical_memory_read(tx_buffer_address, &buf[size],
725 tx_buffer_size);
726 size += tx_buffer_size;
727 }
728 if (tbd_array == 0xffffffff) {
729 /* Simplified mode. Was already handled by code above. */
730 } else {
731 /* Flexible mode. */
732 uint8_t tbd_count = 0;
0859df68 733 if (device_supports_eTxCB(s) && !(s->configuration[6] & BIT(4))) {
3f9cb1c1 734 /* Extended Flexible TCB. */
663e8e51
TS
735 assert(tcb_bytes == 0);
736 for (; tbd_count < 2; tbd_count++) {
737 uint32_t tx_buffer_address = ldl_phys(tbd_address);
738 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
739 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
740 tbd_address += 8;
aac443e6 741 TRACE(RXTX, logout
3f9cb1c1 742 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
aac443e6 743 tx_buffer_address, tx_buffer_size));
24e6f355 744 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
663e8e51
TS
745 cpu_physical_memory_read(tx_buffer_address, &buf[size],
746 tx_buffer_size);
747 size += tx_buffer_size;
748 if (tx_buffer_el & 1) {
749 break;
750 }
751 }
752 }
753 tbd_address = tbd_array;
754 for (; tbd_count < tx.tbd_count; tbd_count++) {
755 uint32_t tx_buffer_address = ldl_phys(tbd_address);
756 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
757 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
758 tbd_address += 8;
aac443e6 759 TRACE(RXTX, logout
663e8e51 760 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
aac443e6 761 tx_buffer_address, tx_buffer_size));
24e6f355 762 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
663e8e51
TS
763 cpu_physical_memory_read(tx_buffer_address, &buf[size],
764 tx_buffer_size);
765 size += tx_buffer_size;
766 if (tx_buffer_el & 1) {
767 break;
768 }
769 }
770 }
aac443e6 771 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
663e8e51
TS
772 qemu_send_packet(s->vc, buf, size);
773 s->statistics.tx_good_frames++;
774 /* Transmit with bad status would raise an CX/TNO interrupt.
775 * (82557 only). Emulation never has bad status. */
776 //~ eepro100_cx_interrupt(s);
777 break;
778 case CmdTDR:
aac443e6 779 TRACE(OTHER, logout("load microcode\n"));
663e8e51
TS
780 /* Starting with offset 8, the command contains
781 * 64 dwords microcode which we just ignore here. */
782 break;
783 default:
784 missing("undefined command");
785 }
786 /* Write new status (success). */
787 stw_phys(cb_address, status | 0x8000 | 0x2000);
788 if (bit_i) {
789 /* CU completed action. */
790 eepro100_cx_interrupt(s);
791 }
792 if (bit_el) {
aac443e6 793 /* CU becomes idle. Terminate command loop. */
663e8e51
TS
794 set_cu_state(s, cu_idle);
795 eepro100_cna_interrupt(s);
796 } else if (bit_s) {
797 /* CU becomes suspended. */
798 set_cu_state(s, cu_suspended);
799 eepro100_cna_interrupt(s);
800 } else {
801 /* More entries in list. */
aac443e6 802 TRACE(OTHER, logout("CU list with at least one more entry\n"));
663e8e51
TS
803 goto next_command;
804 }
aac443e6 805 TRACE(OTHER, logout("CU list empty\n"));
663e8e51
TS
806 /* List is empty. Now CU is idle or suspended. */
807 break;
808 case CU_RESUME:
809 if (get_cu_state(s) != cu_suspended) {
810 logout("bad CU resume from CU state %u\n", get_cu_state(s));
811 /* Workaround for bad Linux eepro100 driver which resumes
812 * from idle state. */
813 //~ missing("cu resume");
814 set_cu_state(s, cu_suspended);
815 }
816 if (get_cu_state(s) == cu_suspended) {
aac443e6 817 TRACE(OTHER, logout("CU resuming\n"));
663e8e51
TS
818 set_cu_state(s, cu_active);
819 goto next_command;
820 }
821 break;
822 case CU_STATSADDR:
823 /* Load dump counters address. */
824 s->statsaddr = s->pointer;
aac443e6 825 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
663e8e51
TS
826 break;
827 case CU_SHOWSTATS:
828 /* Dump statistical counters. */
aac443e6 829 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
663e8e51
TS
830 dump_statistics(s);
831 break;
832 case CU_CMD_BASE:
833 /* Load CU base. */
aac443e6 834 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
663e8e51
TS
835 s->cu_base = s->pointer;
836 break;
837 case CU_DUMPSTATS:
838 /* Dump and reset statistical counters. */
aac443e6 839 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
663e8e51
TS
840 dump_statistics(s);
841 memset(&s->statistics, 0, sizeof(s->statistics));
842 break;
843 case CU_SRESUME:
844 /* CU static resume. */
845 missing("CU static resume");
846 break;
847 default:
848 missing("Undefined CU command");
849 }
850}
851
852static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
853{
854 switch (val) {
855 case RU_NOP:
856 /* No operation. */
857 break;
858 case RX_START:
859 /* RU start. */
860 if (get_ru_state(s) != ru_idle) {
861 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
862 //~ assert(!"wrong RU state");
863 }
864 set_ru_state(s, ru_ready);
865 s->ru_offset = s->pointer;
aac443e6 866 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
663e8e51
TS
867 break;
868 case RX_RESUME:
869 /* Restart RU. */
870 if (get_ru_state(s) != ru_suspended) {
871 logout("RU state is %u, should be %u\n", get_ru_state(s),
872 ru_suspended);
873 //~ assert(!"wrong RU state");
874 }
875 set_ru_state(s, ru_ready);
876 break;
877 case RX_ADDR_LOAD:
878 /* Load RU base. */
aac443e6 879 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
663e8e51
TS
880 s->ru_base = s->pointer;
881 break;
882 default:
883 logout("val=0x%02x (undefined RU command)\n", val);
884 missing("Undefined SU command");
885 }
886}
887
888static void eepro100_write_command(EEPRO100State * s, uint8_t val)
889{
890 eepro100_ru_command(s, val & 0x0f);
891 eepro100_cu_command(s, val & 0xf0);
892 if ((val) == 0) {
aac443e6 893 TRACE(OTHER, logout("val=0x%02x\n", val));
663e8e51
TS
894 }
895 /* Clear command byte after command was accepted. */
896 s->mem[SCBCmd] = 0;
897}
898
899/*****************************************************************************
900 *
901 * EEPROM emulation.
902 *
903 ****************************************************************************/
904
905#define EEPROM_CS 0x02
906#define EEPROM_SK 0x01
907#define EEPROM_DI 0x04
908#define EEPROM_DO 0x08
909
910static uint16_t eepro100_read_eeprom(EEPRO100State * s)
911{
912 uint16_t val;
913 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
914 if (eeprom93xx_read(s->eeprom)) {
915 val |= EEPROM_DO;
916 } else {
917 val &= ~EEPROM_DO;
918 }
aac443e6 919 TRACE(EEPROM, logout("val=0x%04x\n", val));
663e8e51
TS
920 return val;
921}
922
c227f099 923static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
663e8e51 924{
aac443e6 925 TRACE(EEPROM, logout("val=0x%02x\n", val));
663e8e51
TS
926
927 /* mask unwriteable bits */
928 //~ val = SET_MASKED(val, 0x31, eeprom->value);
929
930 int eecs = ((val & EEPROM_CS) != 0);
931 int eesk = ((val & EEPROM_SK) != 0);
932 int eedi = ((val & EEPROM_DI) != 0);
933 eeprom93xx_write(eeprom, eecs, eesk, eedi);
934}
935
936static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
937{
938 s->pointer = le32_to_cpu(val);
aac443e6 939 TRACE(OTHER, logout("val=0x%08x\n", val));
663e8e51
TS
940}
941
942/*****************************************************************************
943 *
944 * MDI emulation.
945 *
946 ****************************************************************************/
947
948#if defined(DEBUG_EEPRO100)
6a0b9cc9 949static const char * const mdi_op_name[] = {
663e8e51
TS
950 "opcode 0",
951 "write",
952 "read",
953 "opcode 3"
954};
955
6a0b9cc9 956static const char * const mdi_reg_name[] = {
663e8e51
TS
957 "Control",
958 "Status",
959 "PHY Identification (Word 1)",
960 "PHY Identification (Word 2)",
961 "Auto-Negotiation Advertisement",
962 "Auto-Negotiation Link Partner Ability",
963 "Auto-Negotiation Expansion"
964};
aac443e6
SW
965
966static const char *reg2name(uint8_t reg)
967{
968 static char buffer[10];
969 const char *p = buffer;
970 if (reg < ARRAY_SIZE(mdi_reg_name)) {
971 p = mdi_reg_name[reg];
972 } else {
973 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
974 }
975 return p;
976}
663e8e51
TS
977#endif /* DEBUG_EEPRO100 */
978
979static uint32_t eepro100_read_mdi(EEPRO100State * s)
980{
981 uint32_t val;
982 memcpy(&val, &s->mem[0x10], sizeof(val));
983
984#ifdef DEBUG_EEPRO100
985 uint8_t raiseint = (val & BIT(29)) >> 29;
986 uint8_t opcode = (val & BITS(27, 26)) >> 26;
987 uint8_t phy = (val & BITS(25, 21)) >> 21;
988 uint8_t reg = (val & BITS(20, 16)) >> 16;
989 uint16_t data = (val & BITS(15, 0));
990#endif
991 /* Emulation takes no time to finish MDI transaction. */
992 val |= BIT(28);
993 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
994 val, raiseint, mdi_op_name[opcode], phy,
aac443e6 995 reg2name(reg), data));
663e8e51
TS
996 return val;
997}
998
663e8e51
TS
999static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1000{
1001 uint8_t raiseint = (val & BIT(29)) >> 29;
1002 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1003 uint8_t phy = (val & BITS(25, 21)) >> 21;
1004 uint8_t reg = (val & BITS(20, 16)) >> 16;
1005 uint16_t data = (val & BITS(15, 0));
aac443e6
SW
1006 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1007 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
663e8e51
TS
1008 if (phy != 1) {
1009 /* Unsupported PHY address. */
1010 //~ logout("phy must be 1 but is %u\n", phy);
1011 data = 0;
1012 } else if (opcode != 1 && opcode != 2) {
1013 /* Unsupported opcode. */
1014 logout("opcode must be 1 or 2 but is %u\n", opcode);
1015 data = 0;
1016 } else if (reg > 6) {
1017 /* Unsupported register. */
1018 logout("register must be 0...6 but is %u\n", reg);
1019 data = 0;
1020 } else {
1021 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1022 val, raiseint, mdi_op_name[opcode], phy,
aac443e6 1023 reg2name(reg), data));
663e8e51
TS
1024 if (opcode == 1) {
1025 /* MDI write */
1026 switch (reg) {
1027 case 0: /* Control Register */
1028 if (data & 0x8000) {
1029 /* Reset status and control registers to default. */
1030 s->mdimem[0] = eepro100_mdi_default[0];
1031 s->mdimem[1] = eepro100_mdi_default[1];
1032 data = s->mdimem[reg];
1033 } else {
1034 /* Restart Auto Configuration = Normal Operation */
1035 data &= ~0x0200;
1036 }
1037 break;
1038 case 1: /* Status Register */
1039 missing("not writable");
1040 data = s->mdimem[reg];
1041 break;
1042 case 2: /* PHY Identification Register (Word 1) */
1043 case 3: /* PHY Identification Register (Word 2) */
1044 missing("not implemented");
1045 break;
1046 case 4: /* Auto-Negotiation Advertisement Register */
1047 case 5: /* Auto-Negotiation Link Partner Ability Register */
1048 break;
1049 case 6: /* Auto-Negotiation Expansion Register */
1050 default:
1051 missing("not implemented");
1052 }
1053 s->mdimem[reg] = data;
1054 } else if (opcode == 2) {
1055 /* MDI read */
1056 switch (reg) {
1057 case 0: /* Control Register */
1058 if (data & 0x8000) {
1059 /* Reset status and control registers to default. */
1060 s->mdimem[0] = eepro100_mdi_default[0];
1061 s->mdimem[1] = eepro100_mdi_default[1];
1062 }
1063 break;
1064 case 1: /* Status Register */
1065 s->mdimem[reg] |= 0x0020;
1066 break;
1067 case 2: /* PHY Identification Register (Word 1) */
1068 case 3: /* PHY Identification Register (Word 2) */
1069 case 4: /* Auto-Negotiation Advertisement Register */
1070 break;
1071 case 5: /* Auto-Negotiation Link Partner Ability Register */
1072 s->mdimem[reg] = 0x41fe;
1073 break;
1074 case 6: /* Auto-Negotiation Expansion Register */
1075 s->mdimem[reg] = 0x0001;
1076 break;
1077 }
1078 data = s->mdimem[reg];
1079 }
1080 /* Emulation takes no time to finish MDI transaction.
1081 * Set MDI bit in SCB status register. */
1082 s->mem[SCBAck] |= 0x08;
1083 val |= BIT(28);
1084 if (raiseint) {
1085 eepro100_mdi_interrupt(s);
1086 }
1087 }
1088 val = (val & 0xffff0000) + data;
1089 memcpy(&s->mem[0x10], &val, sizeof(val));
1090}
1091
1092/*****************************************************************************
1093 *
1094 * Port emulation.
1095 *
1096 ****************************************************************************/
1097
1098#define PORT_SOFTWARE_RESET 0
1099#define PORT_SELFTEST 1
1100#define PORT_SELECTIVE_RESET 2
1101#define PORT_DUMP 3
1102#define PORT_SELECTION_MASK 3
1103
1104typedef struct {
1105 uint32_t st_sign; /* Self Test Signature */
1106 uint32_t st_result; /* Self Test Results */
c227f099 1107} eepro100_selftest_t;
663e8e51
TS
1108
1109static uint32_t eepro100_read_port(EEPRO100State * s)
1110{
1111 return 0;
1112}
1113
1114static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1115{
1116 val = le32_to_cpu(val);
1117 uint32_t address = (val & ~PORT_SELECTION_MASK);
1118 uint8_t selection = (val & PORT_SELECTION_MASK);
1119 switch (selection) {
1120 case PORT_SOFTWARE_RESET:
1121 nic_reset(s);
1122 break;
1123 case PORT_SELFTEST:
aac443e6 1124 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
c227f099 1125 eepro100_selftest_t data;
663e8e51
TS
1126 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1127 data.st_sign = 0xffffffff;
1128 data.st_result = 0;
1129 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1130 break;
1131 case PORT_SELECTIVE_RESET:
aac443e6 1132 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
663e8e51
TS
1133 nic_selective_reset(s);
1134 break;
1135 default:
1136 logout("val=0x%08x\n", val);
1137 missing("unknown port selection");
1138 }
1139}
1140
1141/*****************************************************************************
1142 *
1143 * General hardware emulation.
1144 *
1145 ****************************************************************************/
1146
1147static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1148{
1149 uint8_t val;
1150 if (addr <= sizeof(s->mem) - sizeof(val)) {
1151 memcpy(&val, &s->mem[addr], sizeof(val));
1152 }
1153
1154 switch (addr) {
1155 case SCBStatus:
1156 //~ val = eepro100_read_status(s);
aac443e6 1157 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS
1158 break;
1159 case SCBAck:
1160 //~ val = eepro100_read_status(s);
aac443e6 1161 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS
1162 break;
1163 case SCBCmd:
aac443e6 1164 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS
1165 //~ val = eepro100_read_command(s);
1166 break;
1167 case SCBIntmask:
aac443e6 1168 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS
1169 break;
1170 case SCBPort + 3:
aac443e6 1171 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS
1172 break;
1173 case SCBeeprom:
1174 val = eepro100_read_eeprom(s);
1175 break;
1176 case 0x1b: /* PMDR (power management driver register) */
1177 val = 0;
aac443e6 1178 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS
1179 break;
1180 case 0x1d: /* general status register */
1181 /* 100 Mbps full duplex, valid link */
1182 val = 0x07;
aac443e6 1183 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
663e8e51
TS
1184 break;
1185 default:
1186 logout("addr=%s val=0x%02x\n", regname(addr), val);
1187 missing("unknown byte read");
1188 }
1189 return val;
1190}
1191
1192static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1193{
1194 uint16_t val;
1195 if (addr <= sizeof(s->mem) - sizeof(val)) {
1196 memcpy(&val, &s->mem[addr], sizeof(val));
1197 }
1198
663e8e51
TS
1199 switch (addr) {
1200 case SCBStatus:
1201 //~ val = eepro100_read_status(s);
aac443e6 1202 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS
1203 break;
1204 case SCBeeprom:
1205 val = eepro100_read_eeprom(s);
aac443e6 1206 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS
1207 break;
1208 default:
1209 logout("addr=%s val=0x%04x\n", regname(addr), val);
1210 missing("unknown word read");
1211 }
1212 return val;
1213}
1214
1215static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1216{
1217 uint32_t val;
1218 if (addr <= sizeof(s->mem) - sizeof(val)) {
1219 memcpy(&val, &s->mem[addr], sizeof(val));
1220 }
1221
1222 switch (addr) {
1223 case SCBStatus:
1224 //~ val = eepro100_read_status(s);
aac443e6 1225 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS
1226 break;
1227 case SCBPointer:
1228 //~ val = eepro100_read_pointer(s);
aac443e6 1229 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS
1230 break;
1231 case SCBPort:
1232 val = eepro100_read_port(s);
aac443e6 1233 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS
1234 break;
1235 case SCBCtrlMDI:
1236 val = eepro100_read_mdi(s);
1237 break;
1238 default:
1239 logout("addr=%s val=0x%08x\n", regname(addr), val);
1240 missing("unknown longword read");
1241 }
1242 return val;
1243}
1244
1245static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1246{
1247 if (addr <= sizeof(s->mem) - sizeof(val)) {
1248 memcpy(&s->mem[addr], &val, sizeof(val));
1249 }
1250
aac443e6 1251 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS
1252
1253 switch (addr) {
1254 case SCBStatus:
1255 //~ eepro100_write_status(s, val);
1256 break;
1257 case SCBAck:
1258 eepro100_acknowledge(s);
1259 break;
1260 case SCBCmd:
1261 eepro100_write_command(s, val);
1262 break;
1263 case SCBIntmask:
1264 if (val & BIT(1)) {
1265 eepro100_swi_interrupt(s);
1266 }
1267 eepro100_interrupt(s, 0);
1268 break;
1269 case SCBPort + 3:
aac443e6 1270 case SCBFlow: /* does not exist on 82557 */
3257d2b6
TS
1271 case SCBFlow + 1:
1272 case SCBFlow + 2:
1273 case SCBFlow + 3:
aac443e6 1274 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS
1275 break;
1276 case SCBeeprom:
1277 eepro100_write_eeprom(s->eeprom, val);
1278 break;
1279 default:
1280 logout("addr=%s val=0x%02x\n", regname(addr), val);
1281 missing("unknown byte write");
1282 }
1283}
1284
1285static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1286{
1287 if (addr <= sizeof(s->mem) - sizeof(val)) {
1288 memcpy(&s->mem[addr], &val, sizeof(val));
1289 }
1290
aac443e6 1291 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS
1292
1293 switch (addr) {
1294 case SCBStatus:
1295 //~ eepro100_write_status(s, val);
1296 eepro100_acknowledge(s);
1297 break;
1298 case SCBCmd:
1299 eepro100_write_command(s, val);
1300 eepro100_write1(s, SCBIntmask, val >> 8);
1301 break;
1302 case SCBeeprom:
1303 eepro100_write_eeprom(s->eeprom, val);
1304 break;
1305 default:
1306 logout("addr=%s val=0x%04x\n", regname(addr), val);
1307 missing("unknown word write");
1308 }
1309}
1310
1311static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1312{
1313 if (addr <= sizeof(s->mem) - sizeof(val)) {
1314 memcpy(&s->mem[addr], &val, sizeof(val));
1315 }
1316
1317 switch (addr) {
1318 case SCBPointer:
1319 eepro100_write_pointer(s, val);
1320 break;
1321 case SCBPort:
aac443e6 1322 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS
1323 eepro100_write_port(s, val);
1324 break;
1325 case SCBCtrlMDI:
1326 eepro100_write_mdi(s, val);
1327 break;
1328 default:
1329 logout("addr=%s val=0x%08x\n", regname(addr), val);
1330 missing("unknown longword write");
1331 }
1332}
1333
aac443e6
SW
1334/*****************************************************************************
1335 *
1336 * Port mapped I/O.
1337 *
1338 ****************************************************************************/
1339
663e8e51
TS
1340static uint32_t ioport_read1(void *opaque, uint32_t addr)
1341{
1342 EEPRO100State *s = opaque;
1343 //~ logout("addr=%s\n", regname(addr));
1344 return eepro100_read1(s, addr - s->region[1]);
1345}
1346
1347static uint32_t ioport_read2(void *opaque, uint32_t addr)
1348{
1349 EEPRO100State *s = opaque;
1350 return eepro100_read2(s, addr - s->region[1]);
1351}
1352
1353static uint32_t ioport_read4(void *opaque, uint32_t addr)
1354{
1355 EEPRO100State *s = opaque;
1356 return eepro100_read4(s, addr - s->region[1]);
1357}
1358
1359static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1360{
1361 EEPRO100State *s = opaque;
1362 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1363 eepro100_write1(s, addr - s->region[1], val);
1364}
1365
1366static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1367{
1368 EEPRO100State *s = opaque;
1369 eepro100_write2(s, addr - s->region[1], val);
1370}
1371
1372static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1373{
1374 EEPRO100State *s = opaque;
1375 eepro100_write4(s, addr - s->region[1], val);
1376}
1377
1378/***********************************************************/
1379/* PCI EEPRO100 definitions */
1380
663e8e51
TS
1381static void pci_map(PCIDevice * pci_dev, int region_num,
1382 uint32_t addr, uint32_t size, int type)
1383{
273a2142 1384 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
663e8e51 1385
aac443e6
SW
1386 TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1387 region_num, addr, size, type));
663e8e51
TS
1388
1389 assert(region_num == 1);
1390 register_ioport_write(addr, size, 1, ioport_write1, s);
1391 register_ioport_read(addr, size, 1, ioport_read1, s);
1392 register_ioport_write(addr, size, 2, ioport_write2, s);
1393 register_ioport_read(addr, size, 2, ioport_read2, s);
1394 register_ioport_write(addr, size, 4, ioport_write4, s);
1395 register_ioport_read(addr, size, 4, ioport_read4, s);
1396
1397 s->region[region_num] = addr;
1398}
1399
aac443e6
SW
1400/*****************************************************************************
1401 *
1402 * Memory mapped I/O.
1403 *
1404 ****************************************************************************/
1405
c227f099 1406static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
663e8e51
TS
1407{
1408 EEPRO100State *s = opaque;
663e8e51
TS
1409 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1410 eepro100_write1(s, addr, val);
1411}
1412
c227f099 1413static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
663e8e51
TS
1414{
1415 EEPRO100State *s = opaque;
663e8e51
TS
1416 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1417 eepro100_write2(s, addr, val);
1418}
1419
c227f099 1420static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
663e8e51
TS
1421{
1422 EEPRO100State *s = opaque;
663e8e51
TS
1423 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1424 eepro100_write4(s, addr, val);
1425}
1426
c227f099 1427static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
663e8e51
TS
1428{
1429 EEPRO100State *s = opaque;
663e8e51
TS
1430 //~ logout("addr=%s\n", regname(addr));
1431 return eepro100_read1(s, addr);
1432}
1433
c227f099 1434static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
663e8e51
TS
1435{
1436 EEPRO100State *s = opaque;
663e8e51
TS
1437 //~ logout("addr=%s\n", regname(addr));
1438 return eepro100_read2(s, addr);
1439}
1440
c227f099 1441static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
663e8e51
TS
1442{
1443 EEPRO100State *s = opaque;
663e8e51
TS
1444 //~ logout("addr=%s\n", regname(addr));
1445 return eepro100_read4(s, addr);
1446}
1447
d60efc6b 1448static CPUWriteMemoryFunc * const pci_mmio_write[] = {
663e8e51
TS
1449 pci_mmio_writeb,
1450 pci_mmio_writew,
1451 pci_mmio_writel
1452};
1453
d60efc6b 1454static CPUReadMemoryFunc * const pci_mmio_read[] = {
663e8e51
TS
1455 pci_mmio_readb,
1456 pci_mmio_readw,
1457 pci_mmio_readl
1458};
1459
1460static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1461 uint32_t addr, uint32_t size, int type)
1462{
273a2142 1463 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
663e8e51 1464
aac443e6
SW
1465 TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1466 region_num, addr, size, type));
663e8e51
TS
1467
1468 if (region_num == 0) {
1469 /* Map control / status registers. */
273a2142
JQ
1470 cpu_register_physical_memory(addr, size, s->mmio_index);
1471 s->region[region_num] = addr;
663e8e51
TS
1472 }
1473}
1474
e3f5ec2b 1475static int nic_can_receive(VLANClientState *vc)
663e8e51 1476{
e3f5ec2b 1477 EEPRO100State *s = vc->opaque;
aac443e6 1478 TRACE(RXTX, logout("%p\n", s));
663e8e51
TS
1479 return get_ru_state(s) == ru_ready;
1480 //~ return !eepro100_buffer_full(s);
1481}
1482
4f1c942b 1483static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size)
663e8e51
TS
1484{
1485 /* TODO:
1486 * - Magic packets should set bit 30 in power management driver register.
1487 * - Interesting packets should set bit 29 in power management driver register.
1488 */
e3f5ec2b 1489 EEPRO100State *s = vc->opaque;
663e8e51
TS
1490 uint16_t rfd_status = 0xa000;
1491 static const uint8_t broadcast_macaddr[6] =
1492 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1493
1494 /* TODO: check multiple IA bit. */
1495 assert(!(s->configuration[20] & BIT(6)));
1496
1497 if (s->configuration[8] & 0x80) {
1498 /* CSMA is disabled. */
1499 logout("%p received while CSMA is disabled\n", s);
4f1c942b 1500 return -1;
663e8e51
TS
1501 } else if (size < 64 && (s->configuration[7] & 1)) {
1502 /* Short frame and configuration byte 7/0 (discard short receive) set:
1503 * Short frame is discarded */
067d01de 1504 logout("%p received short frame (%zu byte)\n", s, size);
663e8e51 1505 s->statistics.rx_short_frame_errors++;
4f1c942b 1506 //~ return -1;
663e8e51
TS
1507 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) {
1508 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1509 * Long frames are discarded. */
067d01de 1510 logout("%p received long frame (%zu byte), ignored\n", s, size);
4f1c942b 1511 return -1;
663e8e51
TS
1512 } else if (memcmp(buf, s->macaddr, 6) == 0) { // !!!
1513 /* Frame matches individual address. */
1514 /* TODO: check configuration byte 15/4 (ignore U/L). */
067d01de 1515 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
663e8e51
TS
1516 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1517 /* Broadcast frame. */
067d01de 1518 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
663e8e51
TS
1519 rfd_status |= 0x0002;
1520 } else if (buf[0] & 0x01) { // !!!
1521 /* Multicast frame. */
067d01de 1522 TRACE(RXTX, logout("%p received multicast, len=%zu\n", s, size));
663e8e51
TS
1523 /* TODO: check multicast all bit. */
1524 assert(!(s->configuration[21] & BIT(3)));
1525 int mcast_idx = compute_mcast_idx(buf);
1526 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) {
4f1c942b 1527 return size;
663e8e51
TS
1528 }
1529 rfd_status |= 0x0002;
1530 } else if (s->configuration[15] & 1) {
1531 /* Promiscuous: receive all. */
067d01de 1532 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
663e8e51
TS
1533 rfd_status |= 0x0004;
1534 } else {
067d01de 1535 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
aac443e6 1536 nic_dump(buf, size)));
4f1c942b 1537 return size;
663e8e51
TS
1538 }
1539
1540 if (get_ru_state(s) != ru_ready) {
aac443e6
SW
1541 /* No resources available. */
1542 logout("no resources, state=%u\n", get_ru_state(s));
663e8e51 1543 s->statistics.rx_resource_errors++;
aac443e6 1544 //~ assert(!"no resources");
4f1c942b 1545 return -1;
663e8e51
TS
1546 }
1547 //~ !!!
1548//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
c227f099 1549 eepro100_rx_t rx;
663e8e51 1550 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
c227f099 1551 offsetof(eepro100_rx_t, packet));
663e8e51
TS
1552 uint16_t rfd_command = le16_to_cpu(rx.command);
1553 uint16_t rfd_size = le16_to_cpu(rx.size);
1554 assert(size <= rfd_size);
1555 if (size < 64) {
1556 rfd_status |= 0x0080;
1557 }
aac443e6
SW
1558 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1559 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
c227f099 1560 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
663e8e51 1561 rfd_status);
c227f099 1562 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
663e8e51
TS
1563 /* Early receive interrupt not supported. */
1564 //~ eepro100_er_interrupt(s);
1565 /* Receive CRC Transfer not supported. */
1566 assert(!(s->configuration[18] & 4));
1567 /* TODO: check stripping enable bit. */
1568 //~ assert(!(s->configuration[17] & 1));
1569 cpu_physical_memory_write(s->ru_base + s->ru_offset +
c227f099 1570 offsetof(eepro100_rx_t, packet), buf, size);
663e8e51
TS
1571 s->statistics.rx_good_frames++;
1572 eepro100_fr_interrupt(s);
1573 s->ru_offset = le32_to_cpu(rx.link);
1574 if (rfd_command & 0x8000) {
1575 /* EL bit is set, so this was the last frame. */
1576 assert(0);
1577 }
1578 if (rfd_command & 0x4000) {
1579 /* S bit is set. */
1580 set_ru_state(s, ru_suspended);
1581 }
4f1c942b 1582 return size;
663e8e51
TS
1583}
1584
1585static int nic_load(QEMUFile * f, void *opaque, int version_id)
1586{
769cf7a5 1587 EEPRO100State *s = opaque;
2657c663 1588 int i;
663e8e51
TS
1589 int ret;
1590
4e3db917 1591 if (version_id > 3)
663e8e51 1592 return -EINVAL;
4e3db917
AJ
1593
1594 if (version_id >= 3) {
1595 ret = pci_device_load(&s->dev, f);
1596 if (ret < 0)
1597 return ret;
663e8e51
TS
1598 }
1599
4e3db917
AJ
1600 if (version_id >= 2) {
1601 qemu_get_8s(f, &s->rxcr);
1602 } else {
1603 s->rxcr = 0x0c;
663e8e51
TS
1604 }
1605
1606 qemu_get_8s(f, &s->cmd);
1607 qemu_get_be32s(f, &s->start);
1608 qemu_get_be32s(f, &s->stop);
4e3db917
AJ
1609 qemu_get_8s(f, &s->boundary);
1610 qemu_get_8s(f, &s->tsr);
1611 qemu_get_8s(f, &s->tpsr);
1612 qemu_get_be16s(f, &s->tcnt);
1613 qemu_get_be16s(f, &s->rcnt);
1614 qemu_get_be32s(f, &s->rsar);
1615 qemu_get_8s(f, &s->rsr);
1616 qemu_get_8s(f, &s->isr);
1617 qemu_get_8s(f, &s->dcfg);
1618 qemu_get_8s(f, &s->imr);
1619 qemu_get_buffer(f, s->phys, 6);
1620 qemu_get_8s(f, &s->curpag);
663e8e51
TS
1621 qemu_get_buffer(f, s->mult, 8);
1622 qemu_get_buffer(f, s->mem, sizeof(s->mem));
1623
aac443e6 1624 /* Restore all members of struct between scv_stat and mem. */
2657c663
AZ
1625 qemu_get_8s(f, &s->scb_stat);
1626 qemu_get_8s(f, &s->int_stat);
4e3db917 1627 for (i = 0; i < 3; i++) {
2657c663 1628 qemu_get_be32s(f, &s->region[i]);
aac443e6 1629 }
2657c663 1630 qemu_get_buffer(f, s->macaddr, 6);
4e3db917
AJ
1631 for (i = 0; i < 19; i++) {
1632 qemu_get_be32s(f, &s->statcounter[i]);
1633 }
1634 for (i = 0; i < 32; i++) {
2657c663 1635 qemu_get_be16s(f, &s->mdimem[i]);
aac443e6
SW
1636 }
1637 /* The eeprom should be saved and restored by its own routines. */
2657c663
AZ
1638 qemu_get_be32s(f, &s->device);
1639 qemu_get_be32s(f, &s->pointer);
1640 qemu_get_be32s(f, &s->cu_base);
1641 qemu_get_be32s(f, &s->cu_offset);
1642 qemu_get_be32s(f, &s->ru_base);
1643 qemu_get_be32s(f, &s->ru_offset);
1644 qemu_get_be32s(f, &s->statsaddr);
aac443e6 1645 /* Restore epro100_stats_t statistics. */
2657c663
AZ
1646 qemu_get_be32s(f, &s->statistics.tx_good_frames);
1647 qemu_get_be32s(f, &s->statistics.tx_max_collisions);
1648 qemu_get_be32s(f, &s->statistics.tx_late_collisions);
1649 qemu_get_be32s(f, &s->statistics.tx_underruns);
1650 qemu_get_be32s(f, &s->statistics.tx_lost_crs);
1651 qemu_get_be32s(f, &s->statistics.tx_deferred);
1652 qemu_get_be32s(f, &s->statistics.tx_single_collisions);
1653 qemu_get_be32s(f, &s->statistics.tx_multiple_collisions);
1654 qemu_get_be32s(f, &s->statistics.tx_total_collisions);
1655 qemu_get_be32s(f, &s->statistics.rx_good_frames);
1656 qemu_get_be32s(f, &s->statistics.rx_crc_errors);
1657 qemu_get_be32s(f, &s->statistics.rx_alignment_errors);
1658 qemu_get_be32s(f, &s->statistics.rx_resource_errors);
1659 qemu_get_be32s(f, &s->statistics.rx_overrun_errors);
1660 qemu_get_be32s(f, &s->statistics.rx_cdt_errors);
1661 qemu_get_be32s(f, &s->statistics.rx_short_frame_errors);
1662 qemu_get_be32s(f, &s->statistics.fc_xmt_pause);
1663 qemu_get_be32s(f, &s->statistics.fc_rcv_pause);
1664 qemu_get_be32s(f, &s->statistics.fc_rcv_unsupported);
1665 qemu_get_be16s(f, &s->statistics.xmt_tco_frames);
1666 qemu_get_be16s(f, &s->statistics.rcv_tco_frames);
1667 qemu_get_be32s(f, &s->statistics.complete);
1668#if 0
1669 qemu_get_be16s(f, &s->status);
1670#endif
1671
1672 /* Configuration bytes. */
1673 qemu_get_buffer(f, s->configuration, sizeof(s->configuration));
1674
663e8e51
TS
1675 return 0;
1676}
1677
1678static void nic_save(QEMUFile * f, void *opaque)
1679{
769cf7a5 1680 EEPRO100State *s = opaque;
2657c663 1681 int i;
663e8e51 1682
273a2142 1683 pci_device_save(&s->dev, f);
663e8e51 1684
4e3db917
AJ
1685 qemu_put_8s(f, &s->rxcr);
1686
663e8e51
TS
1687 qemu_put_8s(f, &s->cmd);
1688 qemu_put_be32s(f, &s->start);
1689 qemu_put_be32s(f, &s->stop);
4e3db917
AJ
1690 qemu_put_8s(f, &s->boundary);
1691 qemu_put_8s(f, &s->tsr);
1692 qemu_put_8s(f, &s->tpsr);
1693 qemu_put_be16s(f, &s->tcnt);
1694 qemu_put_be16s(f, &s->rcnt);
1695 qemu_put_be32s(f, &s->rsar);
1696 qemu_put_8s(f, &s->rsr);
1697 qemu_put_8s(f, &s->isr);
1698 qemu_put_8s(f, &s->dcfg);
1699 qemu_put_8s(f, &s->imr);
1700 qemu_put_buffer(f, s->phys, 6);
1701 qemu_put_8s(f, &s->curpag);
663e8e51
TS
1702 qemu_put_buffer(f, s->mult, 8);
1703 qemu_put_buffer(f, s->mem, sizeof(s->mem));
2657c663 1704
aac443e6 1705 /* Save all members of struct between scv_stat and mem. */
2657c663
AZ
1706 qemu_put_8s(f, &s->scb_stat);
1707 qemu_put_8s(f, &s->int_stat);
4e3db917 1708 for (i = 0; i < 3; i++) {
2657c663 1709 qemu_put_be32s(f, &s->region[i]);
aac443e6 1710 }
2657c663 1711 qemu_put_buffer(f, s->macaddr, 6);
4e3db917
AJ
1712 for (i = 0; i < 19; i++) {
1713 qemu_put_be32s(f, &s->statcounter[i]);
1714 }
1715 for (i = 0; i < 32; i++) {
2657c663 1716 qemu_put_be16s(f, &s->mdimem[i]);
aac443e6
SW
1717 }
1718 /* The eeprom should be saved and restored by its own routines. */
2657c663
AZ
1719 qemu_put_be32s(f, &s->device);
1720 qemu_put_be32s(f, &s->pointer);
1721 qemu_put_be32s(f, &s->cu_base);
1722 qemu_put_be32s(f, &s->cu_offset);
1723 qemu_put_be32s(f, &s->ru_base);
1724 qemu_put_be32s(f, &s->ru_offset);
1725 qemu_put_be32s(f, &s->statsaddr);
aac443e6 1726 /* Save epro100_stats_t statistics. */
2657c663
AZ
1727 qemu_put_be32s(f, &s->statistics.tx_good_frames);
1728 qemu_put_be32s(f, &s->statistics.tx_max_collisions);
1729 qemu_put_be32s(f, &s->statistics.tx_late_collisions);
1730 qemu_put_be32s(f, &s->statistics.tx_underruns);
1731 qemu_put_be32s(f, &s->statistics.tx_lost_crs);
1732 qemu_put_be32s(f, &s->statistics.tx_deferred);
1733 qemu_put_be32s(f, &s->statistics.tx_single_collisions);
1734 qemu_put_be32s(f, &s->statistics.tx_multiple_collisions);
1735 qemu_put_be32s(f, &s->statistics.tx_total_collisions);
1736 qemu_put_be32s(f, &s->statistics.rx_good_frames);
1737 qemu_put_be32s(f, &s->statistics.rx_crc_errors);
1738 qemu_put_be32s(f, &s->statistics.rx_alignment_errors);
1739 qemu_put_be32s(f, &s->statistics.rx_resource_errors);
1740 qemu_put_be32s(f, &s->statistics.rx_overrun_errors);
1741 qemu_put_be32s(f, &s->statistics.rx_cdt_errors);
1742 qemu_put_be32s(f, &s->statistics.rx_short_frame_errors);
1743 qemu_put_be32s(f, &s->statistics.fc_xmt_pause);
1744 qemu_put_be32s(f, &s->statistics.fc_rcv_pause);
1745 qemu_put_be32s(f, &s->statistics.fc_rcv_unsupported);
1746 qemu_put_be16s(f, &s->statistics.xmt_tco_frames);
1747 qemu_put_be16s(f, &s->statistics.rcv_tco_frames);
1748 qemu_put_be32s(f, &s->statistics.complete);
1749#if 0
1750 qemu_put_be16s(f, &s->status);
1751#endif
1752
1753 /* Configuration bytes. */
1754 qemu_put_buffer(f, s->configuration, sizeof(s->configuration));
663e8e51
TS
1755}
1756
b946a153
AL
1757static void nic_cleanup(VLANClientState *vc)
1758{
1759 EEPRO100State *s = vc->opaque;
1760
1761 unregister_savevm(vc->model, s);
1762
1763 eeprom93xx_free(s->eeprom);
1764}
1765
c4c270e2 1766static int pci_nic_uninit(PCIDevice *pci_dev)
b946a153 1767{
c4c270e2 1768 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
b946a153
AL
1769
1770 cpu_unregister_io_memory(s->mmio_index);
1771
1772 return 0;
1773}
1774
81a322d4 1775static int nic_init(PCIDevice *pci_dev, uint32_t device)
663e8e51 1776{
273a2142 1777 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
663e8e51 1778
aac443e6 1779 TRACE(OTHER, logout("\n"));
663e8e51 1780
273a2142 1781 s->dev.unregister = pci_nic_uninit;
663e8e51 1782
663e8e51 1783 s->device = device;
663e8e51
TS
1784
1785 pci_reset(s);
1786
1787 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1788 * i82559 and later support 64 or 256 word EEPROM. */
1789 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1790
1791 /* Handler for memory-mapped I/O */
273a2142 1792 s->mmio_index =
1eed09cb 1793 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
663e8e51 1794
273a2142 1795 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
663e8e51
TS
1796 PCI_ADDRESS_SPACE_MEM |
1797 PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_mmio_map);
273a2142 1798 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_ADDRESS_SPACE_IO,
663e8e51 1799 pci_map);
273a2142 1800 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_ADDRESS_SPACE_MEM,
663e8e51
TS
1801 pci_mmio_map);
1802
273a2142 1803 qdev_get_macaddr(&s->dev.qdev, s->macaddr);
663e8e51
TS
1804 logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));
1805 assert(s->region[1] == 0);
1806
1807 nic_reset(s);
1808
273a2142 1809 s->vc = qdev_get_vlan_client(&s->dev.qdev,
463af534 1810 nic_can_receive, nic_receive, NULL,
b946a153 1811 nic_cleanup, s);
663e8e51 1812
7cb7434b 1813 qemu_format_nic_info_str(s->vc, s->macaddr);
aac443e6 1814 TRACE(OTHER, logout("%s\n", s->vc->info_str));
663e8e51 1815
a08d4367 1816 qemu_register_reset(nic_reset, s);
663e8e51 1817
4e3db917 1818 register_savevm(s->vc->model, -1, 3, nic_save, nic_load, s);
81a322d4 1819 return 0;
663e8e51
TS
1820}
1821
c4c270e2
SW
1822static int pci_i82550_init(PCIDevice *pci_dev)
1823{
1824 return nic_init(pci_dev, i82550);
1825}
1826
1827static int pci_i82551_init(PCIDevice *pci_dev)
1828{
1829 return nic_init(pci_dev, i82551);
1830}
1831
1832static int pci_i82557a_init(PCIDevice *pci_dev)
1833{
1834 return nic_init(pci_dev, i82557A);
1835}
1836
1837static int pci_i82557b_init(PCIDevice *pci_dev)
1838{
1839 return nic_init(pci_dev, i82557B);
1840}
1841
1842static int pci_i82557c_init(PCIDevice *pci_dev)
1843{
1844 return nic_init(pci_dev, i82557C);
1845}
1846
1847static int pci_i82558a_init(PCIDevice *pci_dev)
1848{
1849 return nic_init(pci_dev, i82558A);
1850}
1851
1852static int pci_i82558b_init(PCIDevice *pci_dev)
1853{
1854 return nic_init(pci_dev, i82558B);
1855}
1856
1857static int pci_i82559a_init(PCIDevice *pci_dev)
1858{
1859 return nic_init(pci_dev, i82559A);
1860}
1861
1862static int pci_i82559b_init(PCIDevice *pci_dev)
1863{
1864 return nic_init(pci_dev, i82559B);
1865}
1866
1867static int pci_i82559c_init(PCIDevice *pci_dev)
9d07d757 1868{
c4c270e2 1869 return nic_init(pci_dev, i82559C);
9d07d757
PB
1870}
1871
c4c270e2 1872static int pci_i82559er_init(PCIDevice *pci_dev)
663e8e51 1873{
c4c270e2 1874 return nic_init(pci_dev, i82559ER);
663e8e51
TS
1875}
1876
c4c270e2 1877static int pci_i82562_init(PCIDevice *pci_dev)
663e8e51 1878{
c4c270e2 1879 return nic_init(pci_dev, i82562);
663e8e51
TS
1880}
1881
0aab0d3a
GH
1882static PCIDeviceInfo eepro100_info[] = {
1883 {
c4c270e2
SW
1884 .qdev.name = "i82550",
1885 .qdev.size = sizeof(EEPRO100State),
1886 .init = pci_i82550_init,
1887 },{
0aab0d3a 1888 .qdev.name = "i82551",
273a2142 1889 .qdev.size = sizeof(EEPRO100State),
0aab0d3a 1890 .init = pci_i82551_init,
c4c270e2
SW
1891 },{
1892 .qdev.name = "i82557a",
1893 .qdev.size = sizeof(EEPRO100State),
1894 .init = pci_i82557a_init,
0aab0d3a
GH
1895 },{
1896 .qdev.name = "i82557b",
273a2142 1897 .qdev.size = sizeof(EEPRO100State),
0aab0d3a 1898 .init = pci_i82557b_init,
c4c270e2
SW
1899 },{
1900 .qdev.name = "i82557c",
1901 .qdev.size = sizeof(EEPRO100State),
1902 .init = pci_i82557c_init,
1903 },{
1904 .qdev.name = "i82558a",
1905 .qdev.size = sizeof(EEPRO100State),
1906 .init = pci_i82558a_init,
1907 },{
1908 .qdev.name = "i82558b",
1909 .qdev.size = sizeof(EEPRO100State),
1910 .init = pci_i82558b_init,
1911 },{
1912 .qdev.name = "i82559a",
1913 .qdev.size = sizeof(EEPRO100State),
1914 .init = pci_i82559a_init,
1915 },{
1916 .qdev.name = "i82559b",
1917 .qdev.size = sizeof(EEPRO100State),
1918 .init = pci_i82559b_init,
1919 },{
1920 .qdev.name = "i82559c",
1921 .qdev.size = sizeof(EEPRO100State),
1922 .init = pci_i82559c_init,
0aab0d3a
GH
1923 },{
1924 .qdev.name = "i82559er",
273a2142 1925 .qdev.size = sizeof(EEPRO100State),
0aab0d3a 1926 .init = pci_i82559er_init,
c4c270e2
SW
1927 },{
1928 .qdev.name = "i82562",
1929 .qdev.size = sizeof(EEPRO100State),
1930 .init = pci_i82562_init,
0aab0d3a
GH
1931 },{
1932 /* end of list */
1933 }
1934};
1935
9d07d757 1936static void eepro100_register_devices(void)
663e8e51 1937{
0aab0d3a 1938 pci_qdev_register_many(eepro100_info);
663e8e51
TS
1939}
1940
9d07d757 1941device_init(eepro100_register_devices)