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Commit | Line | Data |
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663e8e51 TS |
1 | /* |
2 | * QEMU i8255x (PRO100) emulation | |
3 | * | |
1b4f97d6 | 4 | * Copyright (C) 2006-2011 Stefan Weil |
663e8e51 TS |
5 | * |
6 | * Portions of the code are copies from grub / etherboot eepro100.c | |
7 | * and linux e100.c. | |
8 | * | |
230a167c | 9 | * This program is free software: you can redistribute it and/or modify |
663e8e51 | 10 | * it under the terms of the GNU General Public License as published by |
230a167c SW |
11 | * the Free Software Foundation, either version 2 of the License, or |
12 | * (at your option) version 3 or any later version. | |
663e8e51 TS |
13 | * |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
230a167c | 20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
663e8e51 TS |
21 | * |
22 | * Tested features (i82559): | |
e5e23ab8 | 23 | * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok |
663e8e51 TS |
24 | * Linux networking (i386) ok |
25 | * | |
26 | * Untested: | |
663e8e51 TS |
27 | * Windows networking |
28 | * | |
29 | * References: | |
30 | * | |
31 | * Intel 8255x 10/100 Mbps Ethernet Controller Family | |
32 | * Open Source Software Developer Manual | |
ba19f2de SW |
33 | * |
34 | * TODO: | |
35 | * * PHY emulation should be separated from nic emulation. | |
36 | * Most nic emulations could share the same phy code. | |
37 | * * i82550 is untested. It is programmed like the i82559. | |
38 | * * i82562 is untested. It is programmed like the i82559. | |
39 | * * Power management (i82558 and later) is not implemented. | |
40 | * * Wake-on-LAN is not implemented. | |
663e8e51 TS |
41 | */ |
42 | ||
663e8e51 | 43 | #include <stddef.h> /* offsetof */ |
87ecb68b PB |
44 | #include "hw.h" |
45 | #include "pci.h" | |
46 | #include "net.h" | |
663e8e51 | 47 | #include "eeprom93xx.h" |
1ca4d09a | 48 | #include "sysemu.h" |
16ef60c9 | 49 | #include "dma.h" |
663e8e51 | 50 | |
792f1d63 SW |
51 | /* QEMU sends frames smaller than 60 bytes to ethernet nics. |
52 | * Such frames are rejected by real nics and their emulations. | |
53 | * To avoid this behaviour, other nic emulations pad received | |
54 | * frames. The following definition enables this padding for | |
55 | * eepro100, too. We keep the define around in case it might | |
56 | * become useful the future if the core networking is ever | |
57 | * changed to pad short packets itself. */ | |
58 | #define CONFIG_PAD_RECEIVED_FRAMES | |
59 | ||
663e8e51 TS |
60 | #define KiB 1024 |
61 | ||
aac443e6 | 62 | /* Debug EEPRO100 card. */ |
ce0e58b3 SW |
63 | #if 0 |
64 | # define DEBUG_EEPRO100 | |
65 | #endif | |
663e8e51 TS |
66 | |
67 | #ifdef DEBUG_EEPRO100 | |
001faf32 | 68 | #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) |
663e8e51 | 69 | #else |
001faf32 | 70 | #define logout(fmt, ...) ((void)0) |
663e8e51 TS |
71 | #endif |
72 | ||
73 | /* Set flags to 0 to disable debug output. */ | |
aac443e6 SW |
74 | #define INT 1 /* interrupt related actions */ |
75 | #define MDI 1 /* mdi related actions */ | |
76 | #define OTHER 1 | |
77 | #define RXTX 1 | |
78 | #define EEPROM 1 /* eeprom related actions */ | |
663e8e51 TS |
79 | |
80 | #define TRACE(flag, command) ((flag) ? (command) : (void)0) | |
81 | ||
7f1e9d4e | 82 | #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n") |
663e8e51 TS |
83 | |
84 | #define MAX_ETH_FRAME_SIZE 1514 | |
85 | ||
86 | /* This driver supports several different devices which are declared here. */ | |
c4c270e2 | 87 | #define i82550 0x82550 |
663e8e51 | 88 | #define i82551 0x82551 |
c4c270e2 | 89 | #define i82557A 0x82557a |
663e8e51 TS |
90 | #define i82557B 0x82557b |
91 | #define i82557C 0x82557c | |
c4c270e2 | 92 | #define i82558A 0x82558a |
663e8e51 | 93 | #define i82558B 0x82558b |
c4c270e2 SW |
94 | #define i82559A 0x82559a |
95 | #define i82559B 0x82559b | |
663e8e51 TS |
96 | #define i82559C 0x82559c |
97 | #define i82559ER 0x82559e | |
98 | #define i82562 0x82562 | |
db667a12 | 99 | #define i82801 0x82801 |
663e8e51 | 100 | |
aac443e6 | 101 | /* Use 64 word EEPROM. TODO: could be a runtime option. */ |
663e8e51 TS |
102 | #define EEPROM_SIZE 64 |
103 | ||
104 | #define PCI_MEM_SIZE (4 * KiB) | |
105 | #define PCI_IO_SIZE 64 | |
106 | #define PCI_FLASH_SIZE (128 * KiB) | |
107 | ||
108 | #define BIT(n) (1 << (n)) | |
109 | #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) | |
110 | ||
111 | /* The SCB accepts the following controls for the Tx and Rx units: */ | |
112 | #define CU_NOP 0x0000 /* No operation. */ | |
113 | #define CU_START 0x0010 /* CU start. */ | |
114 | #define CU_RESUME 0x0020 /* CU resume. */ | |
115 | #define CU_STATSADDR 0x0040 /* Load dump counters address. */ | |
116 | #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ | |
117 | #define CU_CMD_BASE 0x0060 /* Load CU base address. */ | |
118 | #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ | |
119 | #define CU_SRESUME 0x00a0 /* CU static resume. */ | |
120 | ||
121 | #define RU_NOP 0x0000 | |
122 | #define RX_START 0x0001 | |
123 | #define RX_RESUME 0x0002 | |
e824012b | 124 | #define RU_ABORT 0x0004 |
663e8e51 TS |
125 | #define RX_ADDR_LOAD 0x0006 |
126 | #define RX_RESUMENR 0x0007 | |
127 | #define INT_MASK 0x0100 | |
128 | #define DRVR_INT 0x0200 /* Driver generated interrupt. */ | |
129 | ||
558c8634 SW |
130 | typedef struct { |
131 | PCIDeviceInfo pci; | |
132 | uint32_t device; | |
558c8634 SW |
133 | uint8_t stats_size; |
134 | bool has_extended_tcb_support; | |
135 | bool power_management; | |
136 | } E100PCIDeviceInfo; | |
137 | ||
663e8e51 TS |
138 | /* Offsets to the various registers. |
139 | All accesses need not be longword aligned. */ | |
e5e23ab8 | 140 | typedef enum { |
0908bba1 | 141 | SCBStatus = 0, /* Status Word. */ |
663e8e51 TS |
142 | SCBAck = 1, |
143 | SCBCmd = 2, /* Rx/Command Unit command and status. */ | |
144 | SCBIntmask = 3, | |
145 | SCBPointer = 4, /* General purpose pointer. */ | |
146 | SCBPort = 8, /* Misc. commands and operands. */ | |
0908bba1 SW |
147 | SCBflash = 12, /* Flash memory control. */ |
148 | SCBeeprom = 14, /* EEPROM control. */ | |
663e8e51 TS |
149 | SCBCtrlMDI = 16, /* MDI interface control. */ |
150 | SCBEarlyRx = 20, /* Early receive byte count. */ | |
0908bba1 SW |
151 | SCBFlow = 24, /* Flow Control. */ |
152 | SCBpmdr = 27, /* Power Management Driver. */ | |
153 | SCBgctrl = 28, /* General Control. */ | |
154 | SCBgstat = 29, /* General Status. */ | |
e5e23ab8 | 155 | } E100RegisterOffset; |
663e8e51 TS |
156 | |
157 | /* A speedo3 transmit buffer descriptor with two buffers... */ | |
158 | typedef struct { | |
159 | uint16_t status; | |
160 | uint16_t command; | |
161 | uint32_t link; /* void * */ | |
7b8737de | 162 | uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */ |
663e8e51 TS |
163 | uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */ |
164 | uint8_t tx_threshold; /* transmit threshold */ | |
165 | uint8_t tbd_count; /* TBD number */ | |
e7493b25 SW |
166 | #if 0 |
167 | /* This constitutes two "TBD" entries: hdr and data */ | |
168 | uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */ | |
169 | int32_t tx_buf_size0; /* Length of Tx hdr. */ | |
170 | uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ | |
171 | int32_t tx_buf_size1; /* Length of Tx data. */ | |
172 | #endif | |
c227f099 | 173 | } eepro100_tx_t; |
663e8e51 TS |
174 | |
175 | /* Receive frame descriptor. */ | |
176 | typedef struct { | |
177 | int16_t status; | |
178 | uint16_t command; | |
179 | uint32_t link; /* struct RxFD * */ | |
180 | uint32_t rx_buf_addr; /* void * */ | |
181 | uint16_t count; | |
182 | uint16_t size; | |
27112f18 | 183 | /* Ethernet frame data follows. */ |
c227f099 | 184 | } eepro100_rx_t; |
663e8e51 | 185 | |
ced5296a SW |
186 | typedef enum { |
187 | COMMAND_EL = BIT(15), | |
188 | COMMAND_S = BIT(14), | |
189 | COMMAND_I = BIT(13), | |
190 | COMMAND_NC = BIT(4), | |
191 | COMMAND_SF = BIT(3), | |
192 | COMMAND_CMD = BITS(2, 0), | |
193 | } scb_command_bit; | |
194 | ||
195 | typedef enum { | |
196 | STATUS_C = BIT(15), | |
197 | STATUS_OK = BIT(13), | |
198 | } scb_status_bit; | |
199 | ||
663e8e51 TS |
200 | typedef struct { |
201 | uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, | |
cc02c66c SW |
202 | tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, |
203 | tx_multiple_collisions, tx_total_collisions; | |
663e8e51 | 204 | uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, |
cc02c66c SW |
205 | rx_resource_errors, rx_overrun_errors, rx_cdt_errors, |
206 | rx_short_frame_errors; | |
663e8e51 TS |
207 | uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; |
208 | uint16_t xmt_tco_frames, rcv_tco_frames; | |
ba42b646 SW |
209 | /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */ |
210 | uint32_t reserved[4]; | |
c227f099 | 211 | } eepro100_stats_t; |
663e8e51 TS |
212 | |
213 | typedef enum { | |
214 | cu_idle = 0, | |
215 | cu_suspended = 1, | |
216 | cu_active = 2, | |
217 | cu_lpq_active = 2, | |
218 | cu_hqp_active = 3 | |
c227f099 | 219 | } cu_state_t; |
663e8e51 TS |
220 | |
221 | typedef enum { | |
222 | ru_idle = 0, | |
223 | ru_suspended = 1, | |
224 | ru_no_resources = 2, | |
225 | ru_ready = 4 | |
c227f099 | 226 | } ru_state_t; |
663e8e51 | 227 | |
663e8e51 | 228 | typedef struct { |
273a2142 | 229 | PCIDevice dev; |
010ec629 SW |
230 | /* Hash register (multicast mask array, multiple individual addresses). */ |
231 | uint8_t mult[8]; | |
5e6ffdde AK |
232 | MemoryRegion mmio_bar; |
233 | MemoryRegion io_bar; | |
234 | MemoryRegion flash_bar; | |
e00e365e | 235 | NICState *nic; |
508ef936 | 236 | NICConf conf; |
663e8e51 TS |
237 | uint8_t scb_stat; /* SCB stat/ack byte */ |
238 | uint8_t int_stat; /* PCI interrupt status */ | |
3706c43f | 239 | /* region must not be saved by nic_save. */ |
663e8e51 | 240 | uint16_t mdimem[32]; |
c227f099 | 241 | eeprom_t *eeprom; |
663e8e51 | 242 | uint32_t device; /* device variant */ |
663e8e51 TS |
243 | /* (cu_base + cu_offset) address the next command block in the command block list. */ |
244 | uint32_t cu_base; /* CU base address */ | |
245 | uint32_t cu_offset; /* CU address offset */ | |
246 | /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */ | |
247 | uint32_t ru_base; /* RU base address */ | |
248 | uint32_t ru_offset; /* RU address offset */ | |
c227f099 | 249 | uint32_t statsaddr; /* pointer to eepro100_stats_t */ |
ba42b646 | 250 | |
f3a52e50 SW |
251 | /* Temporary status information (no need to save these values), |
252 | * used while processing CU commands. */ | |
253 | eepro100_tx_t tx; /* transmit buffer descriptor */ | |
254 | uint32_t cb_address; /* = cu_base + cu_offset */ | |
255 | ||
ba42b646 SW |
256 | /* Statistical counters. Also used for wake-up packet (i82559). */ |
257 | eepro100_stats_t statistics; | |
258 | ||
e5e23ab8 SW |
259 | /* Data in mem is always in the byte order of the controller (le). |
260 | * It must be dword aligned to allow direct access to 32 bit values. */ | |
261 | uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));; | |
262 | ||
663e8e51 TS |
263 | /* Configuration bytes. */ |
264 | uint8_t configuration[22]; | |
265 | ||
151b2986 JQ |
266 | /* vmstate for each particular nic */ |
267 | VMStateDescription *vmstate; | |
ba42b646 SW |
268 | |
269 | /* Quasi static device properties (no need to save them). */ | |
270 | uint16_t stats_size; | |
271 | bool has_extended_tcb_support; | |
663e8e51 TS |
272 | } EEPRO100State; |
273 | ||
6cded3a4 SW |
274 | /* Word indices in EEPROM. */ |
275 | typedef enum { | |
276 | EEPROM_CNFG_MDIX = 0x03, | |
277 | EEPROM_ID = 0x05, | |
278 | EEPROM_PHY_ID = 0x06, | |
279 | EEPROM_VENDOR_ID = 0x0c, | |
280 | EEPROM_CONFIG_ASF = 0x0d, | |
281 | EEPROM_DEVICE_ID = 0x23, | |
282 | EEPROM_SMBUS_ADDR = 0x90, | |
283 | } EEPROMOffset; | |
284 | ||
b1e87018 SW |
285 | /* Bit values for EEPROM ID word. */ |
286 | typedef enum { | |
287 | EEPROM_ID_MDM = BIT(0), /* Modem */ | |
288 | EEPROM_ID_STB = BIT(1), /* Standby Enable */ | |
289 | EEPROM_ID_WMR = BIT(2), /* ??? */ | |
290 | EEPROM_ID_WOL = BIT(5), /* Wake on LAN */ | |
291 | EEPROM_ID_DPD = BIT(6), /* Deep Power Down */ | |
292 | EEPROM_ID_ALT = BIT(7), /* */ | |
293 | /* BITS(10, 8) device revision */ | |
294 | EEPROM_ID_BD = BIT(11), /* boot disable */ | |
295 | EEPROM_ID_ID = BIT(13), /* id bit */ | |
296 | /* BITS(15, 14) signature */ | |
297 | EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */ | |
298 | } eeprom_id_bit; | |
299 | ||
663e8e51 TS |
300 | /* Default values for MDI (PHY) registers */ |
301 | static const uint16_t eepro100_mdi_default[] = { | |
302 | /* MDI Registers 0 - 6, 7 */ | |
303 | 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, | |
304 | /* MDI Registers 8 - 15 */ | |
305 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
306 | /* MDI Registers 16 - 31 */ | |
307 | 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
308 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
309 | }; | |
310 | ||
311 | /* Readonly mask for MDI (PHY) registers */ | |
312 | static const uint16_t eepro100_mdi_mask[] = { | |
313 | 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, | |
314 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
315 | 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | |
316 | 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, | |
317 | }; | |
318 | ||
319 | #define POLYNOMIAL 0x04c11db6 | |
320 | ||
321 | /* From FreeBSD */ | |
322 | /* XXX: optimize */ | |
7b8737de | 323 | static unsigned compute_mcast_idx(const uint8_t * ep) |
663e8e51 TS |
324 | { |
325 | uint32_t crc; | |
326 | int carry, i, j; | |
327 | uint8_t b; | |
328 | ||
329 | crc = 0xffffffff; | |
330 | for (i = 0; i < 6; i++) { | |
331 | b = *ep++; | |
332 | for (j = 0; j < 8; j++) { | |
333 | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); | |
334 | crc <<= 1; | |
335 | b >>= 1; | |
aac443e6 | 336 | if (carry) { |
663e8e51 | 337 | crc = ((crc ^ POLYNOMIAL) | carry); |
aac443e6 | 338 | } |
663e8e51 TS |
339 | } |
340 | } | |
7b8737de | 341 | return (crc & BITS(7, 2)) >> 2; |
663e8e51 TS |
342 | } |
343 | ||
e5e23ab8 SW |
344 | /* Read a 16 bit control/status (CSR) register. */ |
345 | static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr) | |
346 | { | |
347 | assert(!((uintptr_t)&s->mem[addr] & 1)); | |
348 | return le16_to_cpup((uint16_t *)&s->mem[addr]); | |
349 | } | |
350 | ||
351 | /* Read a 32 bit control/status (CSR) register. */ | |
352 | static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr) | |
353 | { | |
354 | assert(!((uintptr_t)&s->mem[addr] & 3)); | |
355 | return le32_to_cpup((uint32_t *)&s->mem[addr]); | |
356 | } | |
357 | ||
358 | /* Write a 16 bit control/status (CSR) register. */ | |
359 | static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr, | |
360 | uint16_t val) | |
361 | { | |
362 | assert(!((uintptr_t)&s->mem[addr] & 1)); | |
363 | cpu_to_le16w((uint16_t *)&s->mem[addr], val); | |
364 | } | |
365 | ||
366 | /* Read a 32 bit control/status (CSR) register. */ | |
367 | static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr, | |
368 | uint32_t val) | |
369 | { | |
370 | assert(!((uintptr_t)&s->mem[addr] & 3)); | |
371 | cpu_to_le32w((uint32_t *)&s->mem[addr], val); | |
372 | } | |
373 | ||
663e8e51 TS |
374 | #if defined(DEBUG_EEPRO100) |
375 | static const char *nic_dump(const uint8_t * buf, unsigned size) | |
376 | { | |
377 | static char dump[3 * 16 + 1]; | |
378 | char *p = &dump[0]; | |
aac443e6 | 379 | if (size > 16) { |
663e8e51 | 380 | size = 16; |
aac443e6 | 381 | } |
663e8e51 TS |
382 | while (size-- > 0) { |
383 | p += sprintf(p, " %02x", *buf++); | |
384 | } | |
385 | return dump; | |
386 | } | |
387 | #endif /* DEBUG_EEPRO100 */ | |
388 | ||
389 | enum scb_stat_ack { | |
390 | stat_ack_not_ours = 0x00, | |
391 | stat_ack_sw_gen = 0x04, | |
392 | stat_ack_rnr = 0x10, | |
393 | stat_ack_cu_idle = 0x20, | |
394 | stat_ack_frame_rx = 0x40, | |
395 | stat_ack_cu_cmd_done = 0x80, | |
396 | stat_ack_not_present = 0xFF, | |
397 | stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), | |
398 | stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), | |
399 | }; | |
400 | ||
401 | static void disable_interrupt(EEPRO100State * s) | |
402 | { | |
403 | if (s->int_stat) { | |
aac443e6 | 404 | TRACE(INT, logout("interrupt disabled\n")); |
273a2142 | 405 | qemu_irq_lower(s->dev.irq[0]); |
663e8e51 TS |
406 | s->int_stat = 0; |
407 | } | |
408 | } | |
409 | ||
410 | static void enable_interrupt(EEPRO100State * s) | |
411 | { | |
412 | if (!s->int_stat) { | |
aac443e6 | 413 | TRACE(INT, logout("interrupt enabled\n")); |
273a2142 | 414 | qemu_irq_raise(s->dev.irq[0]); |
663e8e51 TS |
415 | s->int_stat = 1; |
416 | } | |
417 | } | |
418 | ||
419 | static void eepro100_acknowledge(EEPRO100State * s) | |
420 | { | |
421 | s->scb_stat &= ~s->mem[SCBAck]; | |
422 | s->mem[SCBAck] = s->scb_stat; | |
423 | if (s->scb_stat == 0) { | |
424 | disable_interrupt(s); | |
425 | } | |
426 | } | |
427 | ||
e715c8e8 | 428 | static void eepro100_interrupt(EEPRO100State * s, uint8_t status) |
663e8e51 TS |
429 | { |
430 | uint8_t mask = ~s->mem[SCBIntmask]; | |
e715c8e8 SW |
431 | s->mem[SCBAck] |= status; |
432 | status = s->scb_stat = s->mem[SCBAck]; | |
433 | status &= (mask | 0x0f); | |
e7493b25 SW |
434 | #if 0 |
435 | status &= (~s->mem[SCBIntmask] | 0x0xf); | |
436 | #endif | |
e715c8e8 | 437 | if (status && (mask & 0x01)) { |
663e8e51 TS |
438 | /* SCB mask and SCB Bit M do not disable interrupt. */ |
439 | enable_interrupt(s); | |
440 | } else if (s->int_stat) { | |
441 | disable_interrupt(s); | |
442 | } | |
443 | } | |
444 | ||
445 | static void eepro100_cx_interrupt(EEPRO100State * s) | |
446 | { | |
447 | /* CU completed action command. */ | |
448 | /* Transmit not ok (82557 only, not in emulation). */ | |
449 | eepro100_interrupt(s, 0x80); | |
450 | } | |
451 | ||
452 | static void eepro100_cna_interrupt(EEPRO100State * s) | |
453 | { | |
454 | /* CU left the active state. */ | |
455 | eepro100_interrupt(s, 0x20); | |
456 | } | |
457 | ||
458 | static void eepro100_fr_interrupt(EEPRO100State * s) | |
459 | { | |
460 | /* RU received a complete frame. */ | |
461 | eepro100_interrupt(s, 0x40); | |
462 | } | |
463 | ||
663e8e51 TS |
464 | static void eepro100_rnr_interrupt(EEPRO100State * s) |
465 | { | |
466 | /* RU is not ready. */ | |
467 | eepro100_interrupt(s, 0x10); | |
468 | } | |
663e8e51 TS |
469 | |
470 | static void eepro100_mdi_interrupt(EEPRO100State * s) | |
471 | { | |
472 | /* MDI completed read or write cycle. */ | |
473 | eepro100_interrupt(s, 0x08); | |
474 | } | |
475 | ||
476 | static void eepro100_swi_interrupt(EEPRO100State * s) | |
477 | { | |
478 | /* Software has requested an interrupt. */ | |
479 | eepro100_interrupt(s, 0x04); | |
480 | } | |
481 | ||
482 | #if 0 | |
483 | static void eepro100_fcp_interrupt(EEPRO100State * s) | |
484 | { | |
485 | /* Flow control pause interrupt (82558 and later). */ | |
486 | eepro100_interrupt(s, 0x01); | |
487 | } | |
488 | #endif | |
489 | ||
558c8634 | 490 | static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device) |
663e8e51 TS |
491 | { |
492 | uint32_t device = s->device; | |
273a2142 | 493 | uint8_t *pci_conf = s->dev.config; |
663e8e51 | 494 | |
aac443e6 | 495 | TRACE(OTHER, logout("%p\n", s)); |
663e8e51 | 496 | |
663e8e51 | 497 | /* PCI Status */ |
ae543b49 SW |
498 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | |
499 | PCI_STATUS_FAST_BACK); | |
663e8e51 | 500 | /* PCI Latency Timer */ |
15e89f59 | 501 | pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */ |
ae543b49 | 502 | /* Capability Pointer is set by PCI framework. */ |
f62719ca SW |
503 | /* Interrupt Line */ |
504 | /* Interrupt Pin */ | |
505 | pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */ | |
663e8e51 | 506 | /* Minimum Grant */ |
15e89f59 | 507 | pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08); |
663e8e51 | 508 | /* Maximum Latency */ |
15e89f59 | 509 | pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18); |
663e8e51 | 510 | |
558c8634 SW |
511 | s->stats_size = e100_device->stats_size; |
512 | s->has_extended_tcb_support = e100_device->has_extended_tcb_support; | |
513 | ||
663e8e51 | 514 | switch (device) { |
ba42b646 | 515 | case i82550: |
663e8e51 | 516 | case i82551: |
ba42b646 | 517 | case i82557A: |
663e8e51 | 518 | case i82557B: |
663e8e51 | 519 | case i82557C: |
ba42b646 | 520 | case i82558A: |
663e8e51 | 521 | case i82558B: |
ba42b646 | 522 | case i82559A: |
ba42b646 | 523 | case i82559B: |
558c8634 SW |
524 | case i82559ER: |
525 | case i82562: | |
db667a12 | 526 | case i82801: |
663e8e51 | 527 | case i82559C: |
663e8e51 | 528 | break; |
663e8e51 TS |
529 | default: |
530 | logout("Device %X is undefined!\n", device); | |
531 | } | |
532 | ||
3dec59a1 SW |
533 | /* Standard TxCB. */ |
534 | s->configuration[6] |= BIT(4); | |
535 | ||
558c8634 | 536 | /* Standard statistical counters. */ |
ba42b646 SW |
537 | s->configuration[6] |= BIT(5); |
538 | ||
539 | if (s->stats_size == 80) { | |
540 | /* TODO: check TCO Statistical Counters bit. Documentation not clear. */ | |
541 | if (s->configuration[6] & BIT(2)) { | |
542 | /* TCO statistical counters. */ | |
543 | assert(s->configuration[6] & BIT(5)); | |
544 | } else { | |
545 | if (s->configuration[6] & BIT(5)) { | |
546 | /* No extended statistical counters, i82557 compatible. */ | |
547 | s->stats_size = 64; | |
548 | } else { | |
549 | /* i82558 compatible. */ | |
550 | s->stats_size = 76; | |
551 | } | |
552 | } | |
553 | } else { | |
554 | if (s->configuration[6] & BIT(5)) { | |
555 | /* No extended statistical counters. */ | |
556 | s->stats_size = 64; | |
557 | } | |
558 | } | |
559 | assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics)); | |
560 | ||
558c8634 | 561 | if (e100_device->power_management) { |
ba42b646 | 562 | /* Power Management Capabilities */ |
8bbd1ce2 | 563 | int cfg_offset = 0xdc; |
ca77089d IY |
564 | int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM, |
565 | cfg_offset, PCI_PM_SIZEOF); | |
8bbd1ce2 MT |
566 | assert(r >= 0); |
567 | pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21); | |
ae543b49 | 568 | #if 0 /* TODO: replace dummy code for power management emulation. */ |
8bbd1ce2 MT |
569 | /* TODO: Power Management Control / Status. */ |
570 | pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000); | |
571 | /* TODO: Ethernet Power Consumption Registers (i82559 and later). */ | |
572 | pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000); | |
ae543b49 | 573 | #endif |
ba42b646 SW |
574 | } |
575 | ||
576 | #if EEPROM_SIZE > 0 | |
663e8e51 | 577 | if (device == i82557C || device == i82558B || device == i82559C) { |
e7493b25 SW |
578 | /* |
579 | TODO: get vendor id from EEPROM for i82557C or later. | |
580 | TODO: get device id from EEPROM for i82557C or later. | |
581 | TODO: status bit 4 can be disabled by EEPROM for i82558, i82559. | |
582 | TODO: header type is determined by EEPROM for i82559. | |
583 | TODO: get subsystem id from EEPROM for i82557C or later. | |
584 | TODO: get subsystem vendor id from EEPROM for i82557C or later. | |
585 | TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later. | |
586 | TODO: capability pointer depends on EEPROM for i82558. | |
587 | */ | |
663e8e51 TS |
588 | logout("Get device id and revision from EEPROM!!!\n"); |
589 | } | |
ba42b646 | 590 | #endif /* EEPROM_SIZE > 0 */ |
663e8e51 TS |
591 | } |
592 | ||
593 | static void nic_selective_reset(EEPRO100State * s) | |
594 | { | |
595 | size_t i; | |
596 | uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); | |
e7493b25 SW |
597 | #if 0 |
598 | eeprom93xx_reset(s->eeprom); | |
599 | #endif | |
508ef936 | 600 | memcpy(eeprom_contents, s->conf.macaddr.a, 6); |
b1e87018 | 601 | eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID; |
f4e94dfe RD |
602 | if (s->device == i82557B || s->device == i82557C) |
603 | eeprom_contents[5] = 0x0100; | |
6cded3a4 | 604 | eeprom_contents[EEPROM_PHY_ID] = 1; |
663e8e51 TS |
605 | uint16_t sum = 0; |
606 | for (i = 0; i < EEPROM_SIZE - 1; i++) { | |
607 | sum += eeprom_contents[i]; | |
608 | } | |
609 | eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; | |
aac443e6 | 610 | TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1])); |
663e8e51 TS |
611 | |
612 | memset(s->mem, 0, sizeof(s->mem)); | |
e5e23ab8 | 613 | e100_write_reg4(s, SCBCtrlMDI, BIT(21)); |
663e8e51 TS |
614 | |
615 | assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); | |
616 | memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); | |
617 | } | |
618 | ||
619 | static void nic_reset(void *opaque) | |
620 | { | |
769cf7a5 | 621 | EEPRO100State *s = opaque; |
aac443e6 | 622 | TRACE(OTHER, logout("%p\n", s)); |
010ec629 | 623 | /* TODO: Clearing of hash register for selective reset, too? */ |
7b8737de | 624 | memset(&s->mult[0], 0, sizeof(s->mult)); |
663e8e51 TS |
625 | nic_selective_reset(s); |
626 | } | |
627 | ||
628 | #if defined(DEBUG_EEPRO100) | |
b8f6ba0d | 629 | static const char * const e100_reg[PCI_IO_SIZE / 4] = { |
663e8e51 TS |
630 | "Command/Status", |
631 | "General Pointer", | |
632 | "Port", | |
633 | "EEPROM/Flash Control", | |
634 | "MDI Control", | |
635 | "Receive DMA Byte Count", | |
b8f6ba0d | 636 | "Flow Control", |
663e8e51 TS |
637 | "General Status/Control" |
638 | }; | |
639 | ||
640 | static char *regname(uint32_t addr) | |
641 | { | |
ec169288 | 642 | static char buf[32]; |
663e8e51 | 643 | if (addr < PCI_IO_SIZE) { |
b8f6ba0d | 644 | const char *r = e100_reg[addr / 4]; |
663e8e51 | 645 | if (r != 0) { |
41cbc23c | 646 | snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4); |
663e8e51 | 647 | } else { |
41cbc23c | 648 | snprintf(buf, sizeof(buf), "0x%02x", addr); |
663e8e51 TS |
649 | } |
650 | } else { | |
41cbc23c | 651 | snprintf(buf, sizeof(buf), "??? 0x%08x", addr); |
663e8e51 TS |
652 | } |
653 | return buf; | |
654 | } | |
655 | #endif /* DEBUG_EEPRO100 */ | |
656 | ||
663e8e51 TS |
657 | /***************************************************************************** |
658 | * | |
659 | * Command emulation. | |
660 | * | |
661 | ****************************************************************************/ | |
662 | ||
663 | #if 0 | |
664 | static uint16_t eepro100_read_command(EEPRO100State * s) | |
665 | { | |
666 | uint16_t val = 0xffff; | |
e7493b25 | 667 | TRACE(OTHER, logout("val=0x%04x\n", val)); |
663e8e51 TS |
668 | return val; |
669 | } | |
670 | #endif | |
671 | ||
672 | /* Commands that can be put in a command list entry. */ | |
673 | enum commands { | |
674 | CmdNOp = 0, | |
675 | CmdIASetup = 1, | |
676 | CmdConfigure = 2, | |
677 | CmdMulticastList = 3, | |
678 | CmdTx = 4, | |
679 | CmdTDR = 5, /* load microcode */ | |
680 | CmdDump = 6, | |
681 | CmdDiagnose = 7, | |
682 | ||
683 | /* And some extra flags: */ | |
684 | CmdSuspend = 0x4000, /* Suspend after completion. */ | |
685 | CmdIntr = 0x2000, /* Interrupt after completion. */ | |
686 | CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ | |
687 | }; | |
688 | ||
c227f099 | 689 | static cu_state_t get_cu_state(EEPRO100State * s) |
663e8e51 | 690 | { |
ced5296a | 691 | return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6); |
663e8e51 TS |
692 | } |
693 | ||
c227f099 | 694 | static void set_cu_state(EEPRO100State * s, cu_state_t state) |
663e8e51 | 695 | { |
ced5296a | 696 | s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6); |
663e8e51 TS |
697 | } |
698 | ||
c227f099 | 699 | static ru_state_t get_ru_state(EEPRO100State * s) |
663e8e51 | 700 | { |
ced5296a | 701 | return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2); |
663e8e51 TS |
702 | } |
703 | ||
c227f099 | 704 | static void set_ru_state(EEPRO100State * s, ru_state_t state) |
663e8e51 | 705 | { |
ced5296a | 706 | s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2); |
663e8e51 TS |
707 | } |
708 | ||
709 | static void dump_statistics(EEPRO100State * s) | |
710 | { | |
711 | /* Dump statistical data. Most data is never changed by the emulation | |
712 | * and always 0, so we first just copy the whole block and then those | |
713 | * values which really matter. | |
714 | * Number of data should check configuration!!! | |
715 | */ | |
16ef60c9 EGM |
716 | pci_dma_write(&s->dev, s->statsaddr, |
717 | (uint8_t *) &s->statistics, s->stats_size); | |
718 | stl_le_pci_dma(&s->dev, s->statsaddr + 0, | |
719 | s->statistics.tx_good_frames); | |
720 | stl_le_pci_dma(&s->dev, s->statsaddr + 36, | |
721 | s->statistics.rx_good_frames); | |
722 | stl_le_pci_dma(&s->dev, s->statsaddr + 48, | |
723 | s->statistics.rx_resource_errors); | |
724 | stl_le_pci_dma(&s->dev, s->statsaddr + 60, | |
725 | s->statistics.rx_short_frame_errors); | |
e7493b25 | 726 | #if 0 |
16ef60c9 EGM |
727 | stw_le_pci_dma(&s->dev, s->statsaddr + 76, s->statistics.xmt_tco_frames); |
728 | stw_le_pci_dma(&s->dev, s->statsaddr + 78, s->statistics.rcv_tco_frames); | |
e7493b25 SW |
729 | missing("CU dump statistical counters"); |
730 | #endif | |
663e8e51 TS |
731 | } |
732 | ||
3d0f4b9b SW |
733 | static void read_cb(EEPRO100State *s) |
734 | { | |
16ef60c9 | 735 | pci_dma_read(&s->dev, s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx)); |
3d0f4b9b SW |
736 | s->tx.status = le16_to_cpu(s->tx.status); |
737 | s->tx.command = le16_to_cpu(s->tx.command); | |
738 | s->tx.link = le32_to_cpu(s->tx.link); | |
739 | s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr); | |
740 | s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes); | |
741 | } | |
742 | ||
f3a52e50 SW |
743 | static void tx_command(EEPRO100State *s) |
744 | { | |
7b8737de | 745 | uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr); |
f3a52e50 SW |
746 | uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff); |
747 | /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */ | |
748 | uint8_t buf[2600]; | |
749 | uint16_t size = 0; | |
750 | uint32_t tbd_address = s->cb_address + 0x10; | |
751 | TRACE(RXTX, logout | |
752 | ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n", | |
753 | tbd_array, tcb_bytes, s->tx.tbd_count)); | |
754 | ||
755 | if (tcb_bytes > 2600) { | |
756 | logout("TCB byte count too large, using 2600\n"); | |
757 | tcb_bytes = 2600; | |
758 | } | |
759 | if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { | |
760 | logout | |
761 | ("illegal values of TBD array address and TCB byte count!\n"); | |
762 | } | |
763 | assert(tcb_bytes <= sizeof(buf)); | |
764 | while (size < tcb_bytes) { | |
16ef60c9 EGM |
765 | uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address); |
766 | uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4); | |
e7493b25 | 767 | #if 0 |
16ef60c9 | 768 | uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6); |
e7493b25 | 769 | #endif |
f3a52e50 SW |
770 | tbd_address += 8; |
771 | TRACE(RXTX, logout | |
772 | ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n", | |
773 | tx_buffer_address, tx_buffer_size)); | |
774 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); | |
16ef60c9 | 775 | pci_dma_read(&s->dev, tx_buffer_address, &buf[size], tx_buffer_size); |
f3a52e50 SW |
776 | size += tx_buffer_size; |
777 | } | |
778 | if (tbd_array == 0xffffffff) { | |
779 | /* Simplified mode. Was already handled by code above. */ | |
780 | } else { | |
781 | /* Flexible mode. */ | |
782 | uint8_t tbd_count = 0; | |
783 | if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) { | |
784 | /* Extended Flexible TCB. */ | |
785 | for (; tbd_count < 2; tbd_count++) { | |
16ef60c9 EGM |
786 | uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, |
787 | tbd_address); | |
788 | uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, | |
789 | tbd_address + 4); | |
790 | uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, | |
791 | tbd_address + 6); | |
f3a52e50 SW |
792 | tbd_address += 8; |
793 | TRACE(RXTX, logout | |
794 | ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n", | |
795 | tx_buffer_address, tx_buffer_size)); | |
796 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); | |
16ef60c9 EGM |
797 | pci_dma_read(&s->dev, tx_buffer_address, |
798 | &buf[size], tx_buffer_size); | |
f3a52e50 SW |
799 | size += tx_buffer_size; |
800 | if (tx_buffer_el & 1) { | |
801 | break; | |
802 | } | |
803 | } | |
804 | } | |
805 | tbd_address = tbd_array; | |
806 | for (; tbd_count < s->tx.tbd_count; tbd_count++) { | |
16ef60c9 EGM |
807 | uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address); |
808 | uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4); | |
809 | uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6); | |
f3a52e50 SW |
810 | tbd_address += 8; |
811 | TRACE(RXTX, logout | |
812 | ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n", | |
813 | tx_buffer_address, tx_buffer_size)); | |
814 | tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); | |
16ef60c9 EGM |
815 | pci_dma_read(&s->dev, tx_buffer_address, |
816 | &buf[size], tx_buffer_size); | |
f3a52e50 SW |
817 | size += tx_buffer_size; |
818 | if (tx_buffer_el & 1) { | |
819 | break; | |
820 | } | |
821 | } | |
822 | } | |
823 | TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size))); | |
824 | qemu_send_packet(&s->nic->nc, buf, size); | |
825 | s->statistics.tx_good_frames++; | |
826 | /* Transmit with bad status would raise an CX/TNO interrupt. | |
827 | * (82557 only). Emulation never has bad status. */ | |
e7493b25 SW |
828 | #if 0 |
829 | eepro100_cx_interrupt(s); | |
830 | #endif | |
f3a52e50 SW |
831 | } |
832 | ||
7b8737de SW |
833 | static void set_multicast_list(EEPRO100State *s) |
834 | { | |
835 | uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0); | |
836 | uint16_t i; | |
837 | memset(&s->mult[0], 0, sizeof(s->mult)); | |
838 | TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count)); | |
839 | for (i = 0; i < multicast_count; i += 6) { | |
840 | uint8_t multicast_addr[6]; | |
16ef60c9 | 841 | pci_dma_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6); |
7b8737de SW |
842 | TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6))); |
843 | unsigned mcast_idx = compute_mcast_idx(multicast_addr); | |
844 | assert(mcast_idx < 64); | |
845 | s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7)); | |
846 | } | |
847 | } | |
848 | ||
5fa9a0ae | 849 | static void action_command(EEPRO100State *s) |
663e8e51 | 850 | { |
5fa9a0ae | 851 | for (;;) { |
3d0f4b9b SW |
852 | bool bit_el; |
853 | bool bit_s; | |
854 | bool bit_i; | |
855 | bool bit_nc; | |
75f5a6cc | 856 | uint16_t ok_status = STATUS_OK; |
3d0f4b9b SW |
857 | s->cb_address = s->cu_base + s->cu_offset; |
858 | read_cb(s); | |
859 | bit_el = ((s->tx.command & COMMAND_EL) != 0); | |
860 | bit_s = ((s->tx.command & COMMAND_S) != 0); | |
861 | bit_i = ((s->tx.command & COMMAND_I) != 0); | |
862 | bit_nc = ((s->tx.command & COMMAND_NC) != 0); | |
863 | #if 0 | |
864 | bool bit_sf = ((s->tx.command & COMMAND_SF) != 0); | |
865 | #endif | |
866 | s->cu_offset = s->tx.link; | |
867 | TRACE(OTHER, | |
868 | logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n", | |
869 | s->tx.status, s->tx.command, s->tx.link)); | |
870 | switch (s->tx.command & COMMAND_CMD) { | |
663e8e51 TS |
871 | case CmdNOp: |
872 | /* Do nothing. */ | |
873 | break; | |
874 | case CmdIASetup: | |
16ef60c9 | 875 | pci_dma_read(&s->dev, s->cb_address + 8, &s->conf.macaddr.a[0], 6); |
ce0e58b3 | 876 | TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6))); |
663e8e51 TS |
877 | break; |
878 | case CmdConfigure: | |
16ef60c9 EGM |
879 | pci_dma_read(&s->dev, s->cb_address + 8, |
880 | &s->configuration[0], sizeof(s->configuration)); | |
010ec629 SW |
881 | TRACE(OTHER, logout("configuration: %s\n", |
882 | nic_dump(&s->configuration[0], 16))); | |
883 | TRACE(OTHER, logout("configuration: %s\n", | |
884 | nic_dump(&s->configuration[16], | |
885 | ARRAY_SIZE(s->configuration) - 16))); | |
886 | if (s->configuration[20] & BIT(6)) { | |
887 | TRACE(OTHER, logout("Multiple IA bit\n")); | |
888 | } | |
663e8e51 TS |
889 | break; |
890 | case CmdMulticastList: | |
7b8737de | 891 | set_multicast_list(s); |
663e8e51 TS |
892 | break; |
893 | case CmdTx: | |
7f1e9d4e KW |
894 | if (bit_nc) { |
895 | missing("CmdTx: NC = 0"); | |
75f5a6cc | 896 | ok_status = 0; |
7f1e9d4e KW |
897 | break; |
898 | } | |
f3a52e50 | 899 | tx_command(s); |
663e8e51 TS |
900 | break; |
901 | case CmdTDR: | |
aac443e6 | 902 | TRACE(OTHER, logout("load microcode\n")); |
663e8e51 TS |
903 | /* Starting with offset 8, the command contains |
904 | * 64 dwords microcode which we just ignore here. */ | |
905 | break; | |
f80a7fc3 SW |
906 | case CmdDiagnose: |
907 | TRACE(OTHER, logout("diagnose\n")); | |
908 | /* Make sure error flag is not set. */ | |
909 | s->tx.status = 0; | |
910 | break; | |
663e8e51 TS |
911 | default: |
912 | missing("undefined command"); | |
75f5a6cc | 913 | ok_status = 0; |
7f1e9d4e | 914 | break; |
663e8e51 | 915 | } |
7f1e9d4e | 916 | /* Write new status. */ |
16ef60c9 EGM |
917 | stw_le_pci_dma(&s->dev, s->cb_address, |
918 | s->tx.status | ok_status | STATUS_C); | |
663e8e51 TS |
919 | if (bit_i) { |
920 | /* CU completed action. */ | |
921 | eepro100_cx_interrupt(s); | |
922 | } | |
923 | if (bit_el) { | |
aac443e6 | 924 | /* CU becomes idle. Terminate command loop. */ |
663e8e51 TS |
925 | set_cu_state(s, cu_idle); |
926 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 927 | break; |
663e8e51 | 928 | } else if (bit_s) { |
5fa9a0ae | 929 | /* CU becomes suspended. Terminate command loop. */ |
663e8e51 TS |
930 | set_cu_state(s, cu_suspended); |
931 | eepro100_cna_interrupt(s); | |
5fa9a0ae | 932 | break; |
663e8e51 TS |
933 | } else { |
934 | /* More entries in list. */ | |
aac443e6 | 935 | TRACE(OTHER, logout("CU list with at least one more entry\n")); |
663e8e51 | 936 | } |
5fa9a0ae SW |
937 | } |
938 | TRACE(OTHER, logout("CU list empty\n")); | |
939 | /* List is empty. Now CU is idle or suspended. */ | |
940 | } | |
941 | ||
942 | static void eepro100_cu_command(EEPRO100State * s, uint8_t val) | |
943 | { | |
cb25a3fb | 944 | cu_state_t cu_state; |
5fa9a0ae SW |
945 | switch (val) { |
946 | case CU_NOP: | |
947 | /* No operation. */ | |
948 | break; | |
949 | case CU_START: | |
cb25a3fb SW |
950 | cu_state = get_cu_state(s); |
951 | if (cu_state != cu_idle && cu_state != cu_suspended) { | |
952 | /* Intel documentation says that CU must be idle or suspended | |
953 | * for the CU start command. */ | |
954 | logout("unexpected CU state is %u\n", cu_state); | |
5fa9a0ae SW |
955 | } |
956 | set_cu_state(s, cu_active); | |
27a05006 | 957 | s->cu_offset = e100_read_reg4(s, SCBPointer); |
5fa9a0ae | 958 | action_command(s); |
663e8e51 TS |
959 | break; |
960 | case CU_RESUME: | |
961 | if (get_cu_state(s) != cu_suspended) { | |
962 | logout("bad CU resume from CU state %u\n", get_cu_state(s)); | |
963 | /* Workaround for bad Linux eepro100 driver which resumes | |
964 | * from idle state. */ | |
e7493b25 SW |
965 | #if 0 |
966 | missing("cu resume"); | |
967 | #endif | |
663e8e51 TS |
968 | set_cu_state(s, cu_suspended); |
969 | } | |
970 | if (get_cu_state(s) == cu_suspended) { | |
aac443e6 | 971 | TRACE(OTHER, logout("CU resuming\n")); |
663e8e51 | 972 | set_cu_state(s, cu_active); |
5fa9a0ae | 973 | action_command(s); |
663e8e51 TS |
974 | } |
975 | break; | |
976 | case CU_STATSADDR: | |
977 | /* Load dump counters address. */ | |
27a05006 | 978 | s->statsaddr = e100_read_reg4(s, SCBPointer); |
aac443e6 | 979 | TRACE(OTHER, logout("val=0x%02x (status address)\n", val)); |
663e8e51 TS |
980 | break; |
981 | case CU_SHOWSTATS: | |
982 | /* Dump statistical counters. */ | |
aac443e6 | 983 | TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val)); |
663e8e51 | 984 | dump_statistics(s); |
16ef60c9 | 985 | stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005); |
663e8e51 TS |
986 | break; |
987 | case CU_CMD_BASE: | |
988 | /* Load CU base. */ | |
aac443e6 | 989 | TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val)); |
27a05006 | 990 | s->cu_base = e100_read_reg4(s, SCBPointer); |
663e8e51 TS |
991 | break; |
992 | case CU_DUMPSTATS: | |
993 | /* Dump and reset statistical counters. */ | |
aac443e6 | 994 | TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val)); |
663e8e51 | 995 | dump_statistics(s); |
16ef60c9 | 996 | stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007); |
663e8e51 TS |
997 | memset(&s->statistics, 0, sizeof(s->statistics)); |
998 | break; | |
999 | case CU_SRESUME: | |
1000 | /* CU static resume. */ | |
1001 | missing("CU static resume"); | |
1002 | break; | |
1003 | default: | |
1004 | missing("Undefined CU command"); | |
1005 | } | |
1006 | } | |
1007 | ||
1008 | static void eepro100_ru_command(EEPRO100State * s, uint8_t val) | |
1009 | { | |
1010 | switch (val) { | |
1011 | case RU_NOP: | |
1012 | /* No operation. */ | |
1013 | break; | |
1014 | case RX_START: | |
1015 | /* RU start. */ | |
1016 | if (get_ru_state(s) != ru_idle) { | |
1017 | logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle); | |
e7493b25 SW |
1018 | #if 0 |
1019 | assert(!"wrong RU state"); | |
1020 | #endif | |
663e8e51 TS |
1021 | } |
1022 | set_ru_state(s, ru_ready); | |
27a05006 | 1023 | s->ru_offset = e100_read_reg4(s, SCBPointer); |
aac443e6 | 1024 | TRACE(OTHER, logout("val=0x%02x (rx start)\n", val)); |
663e8e51 TS |
1025 | break; |
1026 | case RX_RESUME: | |
1027 | /* Restart RU. */ | |
1028 | if (get_ru_state(s) != ru_suspended) { | |
1029 | logout("RU state is %u, should be %u\n", get_ru_state(s), | |
1030 | ru_suspended); | |
e7493b25 SW |
1031 | #if 0 |
1032 | assert(!"wrong RU state"); | |
1033 | #endif | |
663e8e51 TS |
1034 | } |
1035 | set_ru_state(s, ru_ready); | |
1036 | break; | |
e824012b SW |
1037 | case RU_ABORT: |
1038 | /* RU abort. */ | |
1039 | if (get_ru_state(s) == ru_ready) { | |
1040 | eepro100_rnr_interrupt(s); | |
1041 | } | |
1042 | set_ru_state(s, ru_idle); | |
1043 | break; | |
663e8e51 TS |
1044 | case RX_ADDR_LOAD: |
1045 | /* Load RU base. */ | |
aac443e6 | 1046 | TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val)); |
27a05006 | 1047 | s->ru_base = e100_read_reg4(s, SCBPointer); |
663e8e51 TS |
1048 | break; |
1049 | default: | |
1050 | logout("val=0x%02x (undefined RU command)\n", val); | |
1051 | missing("Undefined SU command"); | |
1052 | } | |
1053 | } | |
1054 | ||
1055 | static void eepro100_write_command(EEPRO100State * s, uint8_t val) | |
1056 | { | |
1057 | eepro100_ru_command(s, val & 0x0f); | |
1058 | eepro100_cu_command(s, val & 0xf0); | |
1059 | if ((val) == 0) { | |
aac443e6 | 1060 | TRACE(OTHER, logout("val=0x%02x\n", val)); |
663e8e51 TS |
1061 | } |
1062 | /* Clear command byte after command was accepted. */ | |
1063 | s->mem[SCBCmd] = 0; | |
1064 | } | |
1065 | ||
1066 | /***************************************************************************** | |
1067 | * | |
1068 | * EEPROM emulation. | |
1069 | * | |
1070 | ****************************************************************************/ | |
1071 | ||
1072 | #define EEPROM_CS 0x02 | |
1073 | #define EEPROM_SK 0x01 | |
1074 | #define EEPROM_DI 0x04 | |
1075 | #define EEPROM_DO 0x08 | |
1076 | ||
1077 | static uint16_t eepro100_read_eeprom(EEPRO100State * s) | |
1078 | { | |
e5e23ab8 | 1079 | uint16_t val = e100_read_reg2(s, SCBeeprom); |
663e8e51 TS |
1080 | if (eeprom93xx_read(s->eeprom)) { |
1081 | val |= EEPROM_DO; | |
1082 | } else { | |
1083 | val &= ~EEPROM_DO; | |
1084 | } | |
aac443e6 | 1085 | TRACE(EEPROM, logout("val=0x%04x\n", val)); |
663e8e51 TS |
1086 | return val; |
1087 | } | |
1088 | ||
c227f099 | 1089 | static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
663e8e51 | 1090 | { |
aac443e6 | 1091 | TRACE(EEPROM, logout("val=0x%02x\n", val)); |
663e8e51 | 1092 | |
ebabb67a | 1093 | /* mask unwritable bits */ |
e7493b25 SW |
1094 | #if 0 |
1095 | val = SET_MASKED(val, 0x31, eeprom->value); | |
1096 | #endif | |
663e8e51 TS |
1097 | |
1098 | int eecs = ((val & EEPROM_CS) != 0); | |
1099 | int eesk = ((val & EEPROM_SK) != 0); | |
1100 | int eedi = ((val & EEPROM_DI) != 0); | |
1101 | eeprom93xx_write(eeprom, eecs, eesk, eedi); | |
1102 | } | |
1103 | ||
663e8e51 TS |
1104 | /***************************************************************************** |
1105 | * | |
1106 | * MDI emulation. | |
1107 | * | |
1108 | ****************************************************************************/ | |
1109 | ||
1110 | #if defined(DEBUG_EEPRO100) | |
6a0b9cc9 | 1111 | static const char * const mdi_op_name[] = { |
663e8e51 TS |
1112 | "opcode 0", |
1113 | "write", | |
1114 | "read", | |
1115 | "opcode 3" | |
1116 | }; | |
1117 | ||
6a0b9cc9 | 1118 | static const char * const mdi_reg_name[] = { |
663e8e51 TS |
1119 | "Control", |
1120 | "Status", | |
1121 | "PHY Identification (Word 1)", | |
1122 | "PHY Identification (Word 2)", | |
1123 | "Auto-Negotiation Advertisement", | |
1124 | "Auto-Negotiation Link Partner Ability", | |
1125 | "Auto-Negotiation Expansion" | |
1126 | }; | |
aac443e6 SW |
1127 | |
1128 | static const char *reg2name(uint8_t reg) | |
1129 | { | |
1130 | static char buffer[10]; | |
1131 | const char *p = buffer; | |
1132 | if (reg < ARRAY_SIZE(mdi_reg_name)) { | |
1133 | p = mdi_reg_name[reg]; | |
1134 | } else { | |
1135 | snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg); | |
1136 | } | |
1137 | return p; | |
1138 | } | |
663e8e51 TS |
1139 | #endif /* DEBUG_EEPRO100 */ |
1140 | ||
1141 | static uint32_t eepro100_read_mdi(EEPRO100State * s) | |
1142 | { | |
e5e23ab8 | 1143 | uint32_t val = e100_read_reg4(s, SCBCtrlMDI); |
663e8e51 TS |
1144 | |
1145 | #ifdef DEBUG_EEPRO100 | |
1146 | uint8_t raiseint = (val & BIT(29)) >> 29; | |
1147 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1148 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1149 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1150 | uint16_t data = (val & BITS(15, 0)); | |
1151 | #endif | |
1152 | /* Emulation takes no time to finish MDI transaction. */ | |
1153 | val |= BIT(28); | |
1154 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1155 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1156 | reg2name(reg), data)); |
663e8e51 TS |
1157 | return val; |
1158 | } | |
1159 | ||
0113f48d | 1160 | static void eepro100_write_mdi(EEPRO100State *s) |
663e8e51 | 1161 | { |
0113f48d | 1162 | uint32_t val = e100_read_reg4(s, SCBCtrlMDI); |
663e8e51 TS |
1163 | uint8_t raiseint = (val & BIT(29)) >> 29; |
1164 | uint8_t opcode = (val & BITS(27, 26)) >> 26; | |
1165 | uint8_t phy = (val & BITS(25, 21)) >> 21; | |
1166 | uint8_t reg = (val & BITS(20, 16)) >> 16; | |
1167 | uint16_t data = (val & BITS(15, 0)); | |
aac443e6 SW |
1168 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", |
1169 | val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); | |
663e8e51 TS |
1170 | if (phy != 1) { |
1171 | /* Unsupported PHY address. */ | |
e7493b25 SW |
1172 | #if 0 |
1173 | logout("phy must be 1 but is %u\n", phy); | |
1174 | #endif | |
663e8e51 TS |
1175 | data = 0; |
1176 | } else if (opcode != 1 && opcode != 2) { | |
1177 | /* Unsupported opcode. */ | |
1178 | logout("opcode must be 1 or 2 but is %u\n", opcode); | |
1179 | data = 0; | |
1180 | } else if (reg > 6) { | |
1181 | /* Unsupported register. */ | |
1182 | logout("register must be 0...6 but is %u\n", reg); | |
1183 | data = 0; | |
1184 | } else { | |
1185 | TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", | |
1186 | val, raiseint, mdi_op_name[opcode], phy, | |
aac443e6 | 1187 | reg2name(reg), data)); |
663e8e51 TS |
1188 | if (opcode == 1) { |
1189 | /* MDI write */ | |
1190 | switch (reg) { | |
1191 | case 0: /* Control Register */ | |
1192 | if (data & 0x8000) { | |
1193 | /* Reset status and control registers to default. */ | |
1194 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1195 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1196 | data = s->mdimem[reg]; | |
1197 | } else { | |
1198 | /* Restart Auto Configuration = Normal Operation */ | |
1199 | data &= ~0x0200; | |
1200 | } | |
1201 | break; | |
1202 | case 1: /* Status Register */ | |
1203 | missing("not writable"); | |
1204 | data = s->mdimem[reg]; | |
1205 | break; | |
1206 | case 2: /* PHY Identification Register (Word 1) */ | |
1207 | case 3: /* PHY Identification Register (Word 2) */ | |
1208 | missing("not implemented"); | |
1209 | break; | |
1210 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1211 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1212 | break; | |
1213 | case 6: /* Auto-Negotiation Expansion Register */ | |
1214 | default: | |
1215 | missing("not implemented"); | |
1216 | } | |
1217 | s->mdimem[reg] = data; | |
1218 | } else if (opcode == 2) { | |
1219 | /* MDI read */ | |
1220 | switch (reg) { | |
1221 | case 0: /* Control Register */ | |
1222 | if (data & 0x8000) { | |
1223 | /* Reset status and control registers to default. */ | |
1224 | s->mdimem[0] = eepro100_mdi_default[0]; | |
1225 | s->mdimem[1] = eepro100_mdi_default[1]; | |
1226 | } | |
1227 | break; | |
1228 | case 1: /* Status Register */ | |
1229 | s->mdimem[reg] |= 0x0020; | |
1230 | break; | |
1231 | case 2: /* PHY Identification Register (Word 1) */ | |
1232 | case 3: /* PHY Identification Register (Word 2) */ | |
1233 | case 4: /* Auto-Negotiation Advertisement Register */ | |
1234 | break; | |
1235 | case 5: /* Auto-Negotiation Link Partner Ability Register */ | |
1236 | s->mdimem[reg] = 0x41fe; | |
1237 | break; | |
1238 | case 6: /* Auto-Negotiation Expansion Register */ | |
1239 | s->mdimem[reg] = 0x0001; | |
1240 | break; | |
1241 | } | |
1242 | data = s->mdimem[reg]; | |
1243 | } | |
1244 | /* Emulation takes no time to finish MDI transaction. | |
1245 | * Set MDI bit in SCB status register. */ | |
1246 | s->mem[SCBAck] |= 0x08; | |
1247 | val |= BIT(28); | |
1248 | if (raiseint) { | |
1249 | eepro100_mdi_interrupt(s); | |
1250 | } | |
1251 | } | |
1252 | val = (val & 0xffff0000) + data; | |
e5e23ab8 | 1253 | e100_write_reg4(s, SCBCtrlMDI, val); |
663e8e51 TS |
1254 | } |
1255 | ||
1256 | /***************************************************************************** | |
1257 | * | |
1258 | * Port emulation. | |
1259 | * | |
1260 | ****************************************************************************/ | |
1261 | ||
1262 | #define PORT_SOFTWARE_RESET 0 | |
1263 | #define PORT_SELFTEST 1 | |
1264 | #define PORT_SELECTIVE_RESET 2 | |
1265 | #define PORT_DUMP 3 | |
1266 | #define PORT_SELECTION_MASK 3 | |
1267 | ||
1268 | typedef struct { | |
1269 | uint32_t st_sign; /* Self Test Signature */ | |
1270 | uint32_t st_result; /* Self Test Results */ | |
c227f099 | 1271 | } eepro100_selftest_t; |
663e8e51 TS |
1272 | |
1273 | static uint32_t eepro100_read_port(EEPRO100State * s) | |
1274 | { | |
1275 | return 0; | |
1276 | } | |
1277 | ||
3fd3d0b4 | 1278 | static void eepro100_write_port(EEPRO100State *s) |
663e8e51 | 1279 | { |
3fd3d0b4 | 1280 | uint32_t val = e100_read_reg4(s, SCBPort); |
663e8e51 TS |
1281 | uint32_t address = (val & ~PORT_SELECTION_MASK); |
1282 | uint8_t selection = (val & PORT_SELECTION_MASK); | |
1283 | switch (selection) { | |
1284 | case PORT_SOFTWARE_RESET: | |
1285 | nic_reset(s); | |
1286 | break; | |
1287 | case PORT_SELFTEST: | |
aac443e6 | 1288 | TRACE(OTHER, logout("selftest address=0x%08x\n", address)); |
c227f099 | 1289 | eepro100_selftest_t data; |
16ef60c9 | 1290 | pci_dma_read(&s->dev, address, (uint8_t *) &data, sizeof(data)); |
663e8e51 TS |
1291 | data.st_sign = 0xffffffff; |
1292 | data.st_result = 0; | |
16ef60c9 | 1293 | pci_dma_write(&s->dev, address, (uint8_t *) &data, sizeof(data)); |
663e8e51 TS |
1294 | break; |
1295 | case PORT_SELECTIVE_RESET: | |
aac443e6 | 1296 | TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address)); |
663e8e51 TS |
1297 | nic_selective_reset(s); |
1298 | break; | |
1299 | default: | |
1300 | logout("val=0x%08x\n", val); | |
1301 | missing("unknown port selection"); | |
1302 | } | |
1303 | } | |
1304 | ||
1305 | /***************************************************************************** | |
1306 | * | |
1307 | * General hardware emulation. | |
1308 | * | |
1309 | ****************************************************************************/ | |
1310 | ||
1311 | static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr) | |
1312 | { | |
ef476062 | 1313 | uint8_t val = 0; |
663e8e51 | 1314 | if (addr <= sizeof(s->mem) - sizeof(val)) { |
e5e23ab8 | 1315 | val = s->mem[addr]; |
663e8e51 TS |
1316 | } |
1317 | ||
1318 | switch (addr) { | |
1319 | case SCBStatus: | |
663e8e51 | 1320 | case SCBAck: |
aac443e6 | 1321 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1322 | break; |
1323 | case SCBCmd: | |
aac443e6 | 1324 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
e7493b25 SW |
1325 | #if 0 |
1326 | val = eepro100_read_command(s); | |
1327 | #endif | |
663e8e51 TS |
1328 | break; |
1329 | case SCBIntmask: | |
aac443e6 | 1330 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1331 | break; |
1332 | case SCBPort + 3: | |
aac443e6 | 1333 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1334 | break; |
1335 | case SCBeeprom: | |
1336 | val = eepro100_read_eeprom(s); | |
1337 | break; | |
0113f48d SW |
1338 | case SCBCtrlMDI: |
1339 | case SCBCtrlMDI + 1: | |
1340 | case SCBCtrlMDI + 2: | |
1341 | case SCBCtrlMDI + 3: | |
1342 | val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3))); | |
1343 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); | |
1344 | break; | |
0908bba1 | 1345 | case SCBpmdr: /* Power Management Driver Register */ |
663e8e51 | 1346 | val = 0; |
aac443e6 | 1347 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 | 1348 | break; |
a39bd017 SW |
1349 | case SCBgctrl: /* General Control Register */ |
1350 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); | |
1351 | break; | |
0908bba1 | 1352 | case SCBgstat: /* General Status Register */ |
663e8e51 TS |
1353 | /* 100 Mbps full duplex, valid link */ |
1354 | val = 0x07; | |
aac443e6 | 1355 | TRACE(OTHER, logout("addr=General Status val=%02x\n", val)); |
663e8e51 TS |
1356 | break; |
1357 | default: | |
1358 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1359 | missing("unknown byte read"); | |
1360 | } | |
1361 | return val; | |
1362 | } | |
1363 | ||
1364 | static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr) | |
1365 | { | |
ef476062 | 1366 | uint16_t val = 0; |
663e8e51 | 1367 | if (addr <= sizeof(s->mem) - sizeof(val)) { |
e5e23ab8 | 1368 | val = e100_read_reg2(s, addr); |
663e8e51 TS |
1369 | } |
1370 | ||
663e8e51 TS |
1371 | switch (addr) { |
1372 | case SCBStatus: | |
dbbaaff6 | 1373 | case SCBCmd: |
aac443e6 | 1374 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1375 | break; |
1376 | case SCBeeprom: | |
1377 | val = eepro100_read_eeprom(s); | |
aac443e6 | 1378 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 | 1379 | break; |
0113f48d SW |
1380 | case SCBCtrlMDI: |
1381 | case SCBCtrlMDI + 2: | |
1382 | val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3))); | |
1383 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); | |
1384 | break; | |
663e8e51 TS |
1385 | default: |
1386 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1387 | missing("unknown word read"); | |
1388 | } | |
1389 | return val; | |
1390 | } | |
1391 | ||
1392 | static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr) | |
1393 | { | |
ef476062 | 1394 | uint32_t val = 0; |
663e8e51 | 1395 | if (addr <= sizeof(s->mem) - sizeof(val)) { |
e5e23ab8 | 1396 | val = e100_read_reg4(s, addr); |
663e8e51 TS |
1397 | } |
1398 | ||
1399 | switch (addr) { | |
1400 | case SCBStatus: | |
aac443e6 | 1401 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1402 | break; |
1403 | case SCBPointer: | |
aac443e6 | 1404 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1405 | break; |
1406 | case SCBPort: | |
1407 | val = eepro100_read_port(s); | |
aac443e6 | 1408 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 | 1409 | break; |
072476ea SW |
1410 | case SCBflash: |
1411 | val = eepro100_read_eeprom(s); | |
1412 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); | |
1413 | break; | |
663e8e51 TS |
1414 | case SCBCtrlMDI: |
1415 | val = eepro100_read_mdi(s); | |
1416 | break; | |
1417 | default: | |
1418 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1419 | missing("unknown longword read"); | |
1420 | } | |
1421 | return val; | |
1422 | } | |
1423 | ||
1424 | static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) | |
1425 | { | |
e74818f3 SW |
1426 | /* SCBStatus is readonly. */ |
1427 | if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) { | |
e5e23ab8 | 1428 | s->mem[addr] = val; |
663e8e51 TS |
1429 | } |
1430 | ||
663e8e51 TS |
1431 | switch (addr) { |
1432 | case SCBStatus: | |
1b4f97d6 | 1433 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1434 | break; |
1435 | case SCBAck: | |
1b4f97d6 | 1436 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1437 | eepro100_acknowledge(s); |
1438 | break; | |
1439 | case SCBCmd: | |
1b4f97d6 | 1440 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1441 | eepro100_write_command(s, val); |
1442 | break; | |
1443 | case SCBIntmask: | |
1b4f97d6 | 1444 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1445 | if (val & BIT(1)) { |
1446 | eepro100_swi_interrupt(s); | |
1447 | } | |
1448 | eepro100_interrupt(s, 0); | |
1449 | break; | |
27a05006 SW |
1450 | case SCBPointer: |
1451 | case SCBPointer + 1: | |
1452 | case SCBPointer + 2: | |
1453 | case SCBPointer + 3: | |
1454 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); | |
1455 | break; | |
3fd3d0b4 SW |
1456 | case SCBPort: |
1457 | case SCBPort + 1: | |
1458 | case SCBPort + 2: | |
1459 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); | |
1460 | break; | |
663e8e51 | 1461 | case SCBPort + 3: |
3fd3d0b4 SW |
1462 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
1463 | eepro100_write_port(s); | |
1464 | break; | |
aac443e6 | 1465 | case SCBFlow: /* does not exist on 82557 */ |
3257d2b6 TS |
1466 | case SCBFlow + 1: |
1467 | case SCBFlow + 2: | |
0908bba1 | 1468 | case SCBpmdr: /* does not exist on 82557 */ |
aac443e6 | 1469 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1470 | break; |
1471 | case SCBeeprom: | |
1b4f97d6 | 1472 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); |
663e8e51 TS |
1473 | eepro100_write_eeprom(s->eeprom, val); |
1474 | break; | |
0113f48d SW |
1475 | case SCBCtrlMDI: |
1476 | case SCBCtrlMDI + 1: | |
1477 | case SCBCtrlMDI + 2: | |
1478 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); | |
1479 | break; | |
1480 | case SCBCtrlMDI + 3: | |
1481 | TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); | |
1482 | eepro100_write_mdi(s); | |
1483 | break; | |
663e8e51 TS |
1484 | default: |
1485 | logout("addr=%s val=0x%02x\n", regname(addr), val); | |
1486 | missing("unknown byte write"); | |
1487 | } | |
1488 | } | |
1489 | ||
1490 | static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) | |
1491 | { | |
e74818f3 SW |
1492 | /* SCBStatus is readonly. */ |
1493 | if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) { | |
e5e23ab8 | 1494 | e100_write_reg2(s, addr, val); |
663e8e51 TS |
1495 | } |
1496 | ||
663e8e51 TS |
1497 | switch (addr) { |
1498 | case SCBStatus: | |
1b4f97d6 | 1499 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
e74818f3 | 1500 | s->mem[SCBAck] = (val >> 8); |
663e8e51 TS |
1501 | eepro100_acknowledge(s); |
1502 | break; | |
1503 | case SCBCmd: | |
1b4f97d6 | 1504 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1505 | eepro100_write_command(s, val); |
1506 | eepro100_write1(s, SCBIntmask, val >> 8); | |
1507 | break; | |
27a05006 SW |
1508 | case SCBPointer: |
1509 | case SCBPointer + 2: | |
1510 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); | |
1511 | break; | |
3fd3d0b4 SW |
1512 | case SCBPort: |
1513 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); | |
1514 | break; | |
1515 | case SCBPort + 2: | |
1516 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); | |
1517 | eepro100_write_port(s); | |
1518 | break; | |
663e8e51 | 1519 | case SCBeeprom: |
1b4f97d6 | 1520 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); |
663e8e51 TS |
1521 | eepro100_write_eeprom(s->eeprom, val); |
1522 | break; | |
0113f48d SW |
1523 | case SCBCtrlMDI: |
1524 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); | |
1525 | break; | |
1526 | case SCBCtrlMDI + 2: | |
1527 | TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); | |
1528 | eepro100_write_mdi(s); | |
1529 | break; | |
663e8e51 TS |
1530 | default: |
1531 | logout("addr=%s val=0x%04x\n", regname(addr), val); | |
1532 | missing("unknown word write"); | |
1533 | } | |
1534 | } | |
1535 | ||
1536 | static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) | |
1537 | { | |
1538 | if (addr <= sizeof(s->mem) - sizeof(val)) { | |
e5e23ab8 | 1539 | e100_write_reg4(s, addr, val); |
663e8e51 TS |
1540 | } |
1541 | ||
1542 | switch (addr) { | |
1543 | case SCBPointer: | |
27a05006 | 1544 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
663e8e51 TS |
1545 | break; |
1546 | case SCBPort: | |
aac443e6 | 1547 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
3fd3d0b4 | 1548 | eepro100_write_port(s); |
663e8e51 | 1549 | break; |
072476ea SW |
1550 | case SCBflash: |
1551 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); | |
1552 | val = val >> 16; | |
1553 | eepro100_write_eeprom(s->eeprom, val); | |
1554 | break; | |
663e8e51 | 1555 | case SCBCtrlMDI: |
0113f48d SW |
1556 | TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); |
1557 | eepro100_write_mdi(s); | |
663e8e51 TS |
1558 | break; |
1559 | default: | |
1560 | logout("addr=%s val=0x%08x\n", regname(addr), val); | |
1561 | missing("unknown longword write"); | |
1562 | } | |
1563 | } | |
1564 | ||
5e6ffdde AK |
1565 | static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr, |
1566 | unsigned size) | |
663e8e51 TS |
1567 | { |
1568 | EEPRO100State *s = opaque; | |
663e8e51 | 1569 | |
5e6ffdde AK |
1570 | switch (size) { |
1571 | case 1: return eepro100_read1(s, addr); | |
1572 | case 2: return eepro100_read2(s, addr); | |
1573 | case 4: return eepro100_read4(s, addr); | |
1574 | default: abort(); | |
1575 | } | |
663e8e51 TS |
1576 | } |
1577 | ||
5e6ffdde AK |
1578 | static void eepro100_write(void *opaque, target_phys_addr_t addr, |
1579 | uint64_t data, unsigned size) | |
663e8e51 TS |
1580 | { |
1581 | EEPRO100State *s = opaque; | |
663e8e51 | 1582 | |
5e6ffdde AK |
1583 | switch (size) { |
1584 | case 1: return eepro100_write1(s, addr, data); | |
1585 | case 2: return eepro100_write2(s, addr, data); | |
1586 | case 4: return eepro100_write4(s, addr, data); | |
1587 | default: abort(); | |
1588 | } | |
663e8e51 TS |
1589 | } |
1590 | ||
5e6ffdde AK |
1591 | static const MemoryRegionOps eepro100_ops = { |
1592 | .read = eepro100_read, | |
1593 | .write = eepro100_write, | |
1594 | .endianness = DEVICE_LITTLE_ENDIAN, | |
663e8e51 TS |
1595 | }; |
1596 | ||
e00e365e | 1597 | static int nic_can_receive(VLANClientState *nc) |
663e8e51 | 1598 | { |
e00e365e | 1599 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
aac443e6 | 1600 | TRACE(RXTX, logout("%p\n", s)); |
663e8e51 | 1601 | return get_ru_state(s) == ru_ready; |
e7493b25 SW |
1602 | #if 0 |
1603 | return !eepro100_buffer_full(s); | |
1604 | #endif | |
663e8e51 TS |
1605 | } |
1606 | ||
e00e365e | 1607 | static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size) |
663e8e51 TS |
1608 | { |
1609 | /* TODO: | |
1610 | * - Magic packets should set bit 30 in power management driver register. | |
1611 | * - Interesting packets should set bit 29 in power management driver register. | |
1612 | */ | |
e00e365e | 1613 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
663e8e51 | 1614 | uint16_t rfd_status = 0xa000; |
792f1d63 SW |
1615 | #if defined(CONFIG_PAD_RECEIVED_FRAMES) |
1616 | uint8_t min_buf[60]; | |
1617 | #endif | |
663e8e51 TS |
1618 | static const uint8_t broadcast_macaddr[6] = |
1619 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
1620 | ||
792f1d63 SW |
1621 | #if defined(CONFIG_PAD_RECEIVED_FRAMES) |
1622 | /* Pad to minimum Ethernet frame length */ | |
1623 | if (size < sizeof(min_buf)) { | |
1624 | memcpy(min_buf, buf, size); | |
1625 | memset(&min_buf[size], 0, sizeof(min_buf) - size); | |
1626 | buf = min_buf; | |
1627 | size = sizeof(min_buf); | |
1628 | } | |
1629 | #endif | |
1630 | ||
663e8e51 TS |
1631 | if (s->configuration[8] & 0x80) { |
1632 | /* CSMA is disabled. */ | |
1633 | logout("%p received while CSMA is disabled\n", s); | |
4f1c942b | 1634 | return -1; |
792f1d63 | 1635 | #if !defined(CONFIG_PAD_RECEIVED_FRAMES) |
ced5296a | 1636 | } else if (size < 64 && (s->configuration[7] & BIT(0))) { |
663e8e51 TS |
1637 | /* Short frame and configuration byte 7/0 (discard short receive) set: |
1638 | * Short frame is discarded */ | |
067d01de | 1639 | logout("%p received short frame (%zu byte)\n", s, size); |
663e8e51 | 1640 | s->statistics.rx_short_frame_errors++; |
e7493b25 SW |
1641 | return -1; |
1642 | #endif | |
ced5296a | 1643 | } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) { |
663e8e51 TS |
1644 | /* Long frame and configuration byte 18/3 (long receive ok) not set: |
1645 | * Long frames are discarded. */ | |
067d01de | 1646 | logout("%p received long frame (%zu byte), ignored\n", s, size); |
4f1c942b | 1647 | return -1; |
e7493b25 | 1648 | } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */ |
663e8e51 TS |
1649 | /* Frame matches individual address. */ |
1650 | /* TODO: check configuration byte 15/4 (ignore U/L). */ | |
067d01de | 1651 | TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size)); |
663e8e51 TS |
1652 | } else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
1653 | /* Broadcast frame. */ | |
067d01de | 1654 | TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size)); |
663e8e51 | 1655 | rfd_status |= 0x0002; |
7b8737de | 1656 | } else if (buf[0] & 0x01) { |
663e8e51 | 1657 | /* Multicast frame. */ |
7b8737de | 1658 | TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size))); |
7f1e9d4e | 1659 | if (s->configuration[21] & BIT(3)) { |
7b8737de SW |
1660 | /* Multicast all bit is set, receive all multicast frames. */ |
1661 | } else { | |
1662 | unsigned mcast_idx = compute_mcast_idx(buf); | |
1663 | assert(mcast_idx < 64); | |
1664 | if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) { | |
1665 | /* Multicast frame is allowed in hash table. */ | |
ced5296a | 1666 | } else if (s->configuration[15] & BIT(0)) { |
7b8737de SW |
1667 | /* Promiscuous: receive all. */ |
1668 | rfd_status |= 0x0004; | |
1669 | } else { | |
1670 | TRACE(RXTX, logout("%p multicast ignored\n", s)); | |
1671 | return -1; | |
1672 | } | |
663e8e51 | 1673 | } |
7b8737de | 1674 | /* TODO: Next not for promiscuous mode? */ |
663e8e51 | 1675 | rfd_status |= 0x0002; |
ced5296a | 1676 | } else if (s->configuration[15] & BIT(0)) { |
663e8e51 | 1677 | /* Promiscuous: receive all. */ |
067d01de | 1678 | TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size)); |
663e8e51 | 1679 | rfd_status |= 0x0004; |
010ec629 SW |
1680 | } else if (s->configuration[20] & BIT(6)) { |
1681 | /* Multiple IA bit set. */ | |
1682 | unsigned mcast_idx = compute_mcast_idx(buf); | |
1683 | assert(mcast_idx < 64); | |
1684 | if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) { | |
1685 | TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s)); | |
1686 | } else { | |
1687 | TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s)); | |
1688 | return -1; | |
1689 | } | |
663e8e51 | 1690 | } else { |
067d01de | 1691 | TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size, |
aac443e6 | 1692 | nic_dump(buf, size))); |
4f1c942b | 1693 | return size; |
663e8e51 TS |
1694 | } |
1695 | ||
1696 | if (get_ru_state(s) != ru_ready) { | |
aac443e6 SW |
1697 | /* No resources available. */ |
1698 | logout("no resources, state=%u\n", get_ru_state(s)); | |
e824012b SW |
1699 | /* TODO: RNR interrupt only at first failed frame? */ |
1700 | eepro100_rnr_interrupt(s); | |
663e8e51 | 1701 | s->statistics.rx_resource_errors++; |
e7493b25 SW |
1702 | #if 0 |
1703 | assert(!"no resources"); | |
1704 | #endif | |
4f1c942b | 1705 | return -1; |
663e8e51 | 1706 | } |
e7493b25 | 1707 | /* !!! */ |
c227f099 | 1708 | eepro100_rx_t rx; |
16ef60c9 EGM |
1709 | pci_dma_read(&s->dev, s->ru_base + s->ru_offset, |
1710 | (uint8_t *) &rx, sizeof(eepro100_rx_t)); | |
663e8e51 TS |
1711 | uint16_t rfd_command = le16_to_cpu(rx.command); |
1712 | uint16_t rfd_size = le16_to_cpu(rx.size); | |
7f1e9d4e KW |
1713 | |
1714 | if (size > rfd_size) { | |
1715 | logout("Receive buffer (%" PRId16 " bytes) too small for data " | |
1716 | "(%zu bytes); data truncated\n", rfd_size, size); | |
1717 | size = rfd_size; | |
1718 | } | |
792f1d63 | 1719 | #if !defined(CONFIG_PAD_RECEIVED_FRAMES) |
663e8e51 TS |
1720 | if (size < 64) { |
1721 | rfd_status |= 0x0080; | |
1722 | } | |
792f1d63 | 1723 | #endif |
aac443e6 SW |
1724 | TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", |
1725 | rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); | |
16ef60c9 EGM |
1726 | stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset + |
1727 | offsetof(eepro100_rx_t, status), rfd_status); | |
1728 | stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset + | |
1729 | offsetof(eepro100_rx_t, count), size); | |
663e8e51 | 1730 | /* Early receive interrupt not supported. */ |
e7493b25 SW |
1731 | #if 0 |
1732 | eepro100_er_interrupt(s); | |
1733 | #endif | |
663e8e51 | 1734 | /* Receive CRC Transfer not supported. */ |
ced5296a | 1735 | if (s->configuration[18] & BIT(2)) { |
7f1e9d4e KW |
1736 | missing("Receive CRC Transfer"); |
1737 | return -1; | |
1738 | } | |
663e8e51 | 1739 | /* TODO: check stripping enable bit. */ |
e7493b25 SW |
1740 | #if 0 |
1741 | assert(!(s->configuration[17] & BIT(0))); | |
1742 | #endif | |
16ef60c9 EGM |
1743 | pci_dma_write(&s->dev, s->ru_base + s->ru_offset + |
1744 | sizeof(eepro100_rx_t), buf, size); | |
663e8e51 TS |
1745 | s->statistics.rx_good_frames++; |
1746 | eepro100_fr_interrupt(s); | |
1747 | s->ru_offset = le32_to_cpu(rx.link); | |
ced5296a | 1748 | if (rfd_command & COMMAND_EL) { |
663e8e51 | 1749 | /* EL bit is set, so this was the last frame. */ |
7f1e9d4e KW |
1750 | logout("receive: Running out of frames\n"); |
1751 | set_ru_state(s, ru_suspended); | |
663e8e51 | 1752 | } |
ced5296a | 1753 | if (rfd_command & COMMAND_S) { |
663e8e51 TS |
1754 | /* S bit is set. */ |
1755 | set_ru_state(s, ru_suspended); | |
1756 | } | |
4f1c942b | 1757 | return size; |
663e8e51 TS |
1758 | } |
1759 | ||
151b2986 JQ |
1760 | static const VMStateDescription vmstate_eepro100 = { |
1761 | .version_id = 3, | |
1762 | .minimum_version_id = 2, | |
1763 | .minimum_version_id_old = 2, | |
1764 | .fields = (VMStateField []) { | |
1765 | VMSTATE_PCI_DEVICE(dev, EEPRO100State), | |
1766 | VMSTATE_UNUSED(32), | |
1767 | VMSTATE_BUFFER(mult, EEPRO100State), | |
1768 | VMSTATE_BUFFER(mem, EEPRO100State), | |
1769 | /* Save all members of struct between scb_stat and mem. */ | |
1770 | VMSTATE_UINT8(scb_stat, EEPRO100State), | |
1771 | VMSTATE_UINT8(int_stat, EEPRO100State), | |
1772 | VMSTATE_UNUSED(3*4), | |
1773 | VMSTATE_MACADDR(conf.macaddr, EEPRO100State), | |
1774 | VMSTATE_UNUSED(19*4), | |
1775 | VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32), | |
1776 | /* The eeprom should be saved and restored by its own routines. */ | |
1777 | VMSTATE_UINT32(device, EEPRO100State), | |
1778 | /* TODO check device. */ | |
151b2986 JQ |
1779 | VMSTATE_UINT32(cu_base, EEPRO100State), |
1780 | VMSTATE_UINT32(cu_offset, EEPRO100State), | |
1781 | VMSTATE_UINT32(ru_base, EEPRO100State), | |
1782 | VMSTATE_UINT32(ru_offset, EEPRO100State), | |
1783 | VMSTATE_UINT32(statsaddr, EEPRO100State), | |
ba42b646 | 1784 | /* Save eepro100_stats_t statistics. */ |
151b2986 JQ |
1785 | VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State), |
1786 | VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State), | |
1787 | VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State), | |
1788 | VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State), | |
1789 | VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State), | |
1790 | VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State), | |
1791 | VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State), | |
1792 | VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State), | |
1793 | VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State), | |
1794 | VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State), | |
1795 | VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State), | |
1796 | VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State), | |
1797 | VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State), | |
1798 | VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State), | |
1799 | VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State), | |
1800 | VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State), | |
1801 | VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State), | |
1802 | VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State), | |
1803 | VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State), | |
1804 | VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State), | |
1805 | VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State), | |
151b2986 JQ |
1806 | /* Configuration bytes. */ |
1807 | VMSTATE_BUFFER(configuration, EEPRO100State), | |
1808 | VMSTATE_END_OF_LIST() | |
aac443e6 | 1809 | } |
151b2986 | 1810 | }; |
663e8e51 | 1811 | |
e00e365e | 1812 | static void nic_cleanup(VLANClientState *nc) |
b946a153 | 1813 | { |
e00e365e | 1814 | EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
b946a153 | 1815 | |
e00e365e | 1816 | s->nic = NULL; |
b946a153 AL |
1817 | } |
1818 | ||
c4c270e2 | 1819 | static int pci_nic_uninit(PCIDevice *pci_dev) |
b946a153 | 1820 | { |
c4c270e2 | 1821 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
b946a153 | 1822 | |
5e6ffdde AK |
1823 | memory_region_destroy(&s->mmio_bar); |
1824 | memory_region_destroy(&s->io_bar); | |
1825 | memory_region_destroy(&s->flash_bar); | |
0be71e32 | 1826 | vmstate_unregister(&pci_dev->qdev, s->vmstate, s); |
5fce2b3e | 1827 | eeprom93xx_free(&pci_dev->qdev, s->eeprom); |
e00e365e | 1828 | qemu_del_vlan_client(&s->nic->nc); |
b946a153 AL |
1829 | return 0; |
1830 | } | |
1831 | ||
e00e365e MM |
1832 | static NetClientInfo net_eepro100_info = { |
1833 | .type = NET_CLIENT_TYPE_NIC, | |
1834 | .size = sizeof(NICState), | |
1835 | .can_receive = nic_can_receive, | |
1836 | .receive = nic_receive, | |
1837 | .cleanup = nic_cleanup, | |
1838 | }; | |
1839 | ||
558c8634 | 1840 | static int e100_nic_init(PCIDevice *pci_dev) |
663e8e51 | 1841 | { |
273a2142 | 1842 | EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); |
558c8634 SW |
1843 | E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev, |
1844 | pci_dev->qdev.info); | |
663e8e51 | 1845 | |
aac443e6 | 1846 | TRACE(OTHER, logout("\n")); |
663e8e51 | 1847 | |
558c8634 | 1848 | s->device = e100_device->device; |
663e8e51 | 1849 | |
558c8634 | 1850 | e100_pci_reset(s, e100_device); |
663e8e51 TS |
1851 | |
1852 | /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM, | |
1853 | * i82559 and later support 64 or 256 word EEPROM. */ | |
5fce2b3e | 1854 | s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE); |
663e8e51 TS |
1855 | |
1856 | /* Handler for memory-mapped I/O */ | |
5e6ffdde AK |
1857 | memory_region_init_io(&s->mmio_bar, &eepro100_ops, s, "eepro100-mmio", |
1858 | PCI_MEM_SIZE); | |
e824b2cc | 1859 | pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar); |
5e6ffdde AK |
1860 | memory_region_init_io(&s->io_bar, &eepro100_ops, s, "eepro100-io", |
1861 | PCI_IO_SIZE); | |
e824b2cc | 1862 | pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); |
5e6ffdde AK |
1863 | /* FIXME: flash aliases to mmio?! */ |
1864 | memory_region_init_io(&s->flash_bar, &eepro100_ops, s, "eepro100-flash", | |
1865 | PCI_FLASH_SIZE); | |
e824b2cc | 1866 | pci_register_bar(&s->dev, 2, 0, &s->flash_bar); |
663e8e51 | 1867 | |
508ef936 | 1868 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
ce0e58b3 | 1869 | logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)); |
663e8e51 TS |
1870 | |
1871 | nic_reset(s); | |
1872 | ||
e00e365e MM |
1873 | s->nic = qemu_new_nic(&net_eepro100_info, &s->conf, |
1874 | pci_dev->qdev.info->name, pci_dev->qdev.id, s); | |
663e8e51 | 1875 | |
e00e365e MM |
1876 | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
1877 | TRACE(OTHER, logout("%s\n", s->nic->nc.info_str)); | |
663e8e51 | 1878 | |
a08d4367 | 1879 | qemu_register_reset(nic_reset, s); |
663e8e51 | 1880 | |
7267c094 | 1881 | s->vmstate = g_malloc(sizeof(vmstate_eepro100)); |
151b2986 | 1882 | memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100)); |
e00e365e | 1883 | s->vmstate->name = s->nic->nc.model; |
0be71e32 | 1884 | vmstate_register(&pci_dev->qdev, -1, s->vmstate, s); |
4e9df06a | 1885 | |
1ca4d09a GN |
1886 | add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0"); |
1887 | ||
81a322d4 | 1888 | return 0; |
663e8e51 TS |
1889 | } |
1890 | ||
558c8634 | 1891 | static E100PCIDeviceInfo e100_devices[] = { |
0aab0d3a | 1892 | { |
558c8634 SW |
1893 | .pci.qdev.name = "i82550", |
1894 | .pci.qdev.desc = "Intel i82550 Ethernet", | |
1895 | .device = i82550, | |
1896 | /* TODO: check device id. */ | |
ad03502b | 1897 | .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT, |
558c8634 | 1898 | /* Revision ID: 0x0c, 0x0d, 0x0e. */ |
ad03502b | 1899 | .pci.revision = 0x0e, |
558c8634 SW |
1900 | /* TODO: check size of statistical counters. */ |
1901 | .stats_size = 80, | |
1902 | /* TODO: check extended tcb support. */ | |
1903 | .has_extended_tcb_support = true, | |
1904 | .power_management = true, | |
c4c270e2 | 1905 | },{ |
558c8634 SW |
1906 | .pci.qdev.name = "i82551", |
1907 | .pci.qdev.desc = "Intel i82551 Ethernet", | |
1908 | .device = i82551, | |
ad03502b | 1909 | .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT, |
558c8634 | 1910 | /* Revision ID: 0x0f, 0x10. */ |
ad03502b | 1911 | .pci.revision = 0x0f, |
558c8634 SW |
1912 | /* TODO: check size of statistical counters. */ |
1913 | .stats_size = 80, | |
1914 | .has_extended_tcb_support = true, | |
1915 | .power_management = true, | |
0aab0d3a | 1916 | },{ |
558c8634 SW |
1917 | .pci.qdev.name = "i82557a", |
1918 | .pci.qdev.desc = "Intel i82557A Ethernet", | |
1919 | .device = i82557A, | |
ad03502b IY |
1920 | .pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
1921 | .pci.revision = 0x01, | |
558c8634 | 1922 | .power_management = false, |
c4c270e2 | 1923 | },{ |
558c8634 SW |
1924 | .pci.qdev.name = "i82557b", |
1925 | .pci.qdev.desc = "Intel i82557B Ethernet", | |
1926 | .device = i82557B, | |
ad03502b IY |
1927 | .pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
1928 | .pci.revision = 0x02, | |
558c8634 | 1929 | .power_management = false, |
c4c270e2 | 1930 | },{ |
558c8634 SW |
1931 | .pci.qdev.name = "i82557c", |
1932 | .pci.qdev.desc = "Intel i82557C Ethernet", | |
1933 | .device = i82557C, | |
ad03502b IY |
1934 | .pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
1935 | .pci.revision = 0x03, | |
558c8634 | 1936 | .power_management = false, |
c4c270e2 | 1937 | },{ |
558c8634 SW |
1938 | .pci.qdev.name = "i82558a", |
1939 | .pci.qdev.desc = "Intel i82558A Ethernet", | |
1940 | .device = i82558A, | |
ad03502b IY |
1941 | .pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
1942 | .pci.revision = 0x04, | |
558c8634 SW |
1943 | .stats_size = 76, |
1944 | .has_extended_tcb_support = true, | |
1945 | .power_management = true, | |
c4c270e2 | 1946 | },{ |
558c8634 SW |
1947 | .pci.qdev.name = "i82558b", |
1948 | .pci.qdev.desc = "Intel i82558B Ethernet", | |
1949 | .device = i82558B, | |
ad03502b IY |
1950 | .pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
1951 | .pci.revision = 0x05, | |
558c8634 SW |
1952 | .stats_size = 76, |
1953 | .has_extended_tcb_support = true, | |
1954 | .power_management = true, | |
c4c270e2 | 1955 | },{ |
558c8634 SW |
1956 | .pci.qdev.name = "i82559a", |
1957 | .pci.qdev.desc = "Intel i82559A Ethernet", | |
1958 | .device = i82559A, | |
ad03502b IY |
1959 | .pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
1960 | .pci.revision = 0x06, | |
558c8634 SW |
1961 | .stats_size = 80, |
1962 | .has_extended_tcb_support = true, | |
1963 | .power_management = true, | |
c4c270e2 | 1964 | },{ |
558c8634 SW |
1965 | .pci.qdev.name = "i82559b", |
1966 | .pci.qdev.desc = "Intel i82559B Ethernet", | |
1967 | .device = i82559B, | |
ad03502b IY |
1968 | .pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
1969 | .pci.revision = 0x07, | |
558c8634 SW |
1970 | .stats_size = 80, |
1971 | .has_extended_tcb_support = true, | |
1972 | .power_management = true, | |
0aab0d3a | 1973 | },{ |
558c8634 SW |
1974 | .pci.qdev.name = "i82559c", |
1975 | .pci.qdev.desc = "Intel i82559C Ethernet", | |
1976 | .device = i82559C, | |
ad03502b | 1977 | .pci.device_id = PCI_DEVICE_ID_INTEL_82557, |
558c8634 | 1978 | #if 0 |
ad03502b | 1979 | .pci.revision = 0x08, |
558c8634 SW |
1980 | #endif |
1981 | /* TODO: Windows wants revision id 0x0c. */ | |
ad03502b IY |
1982 | .pci.revision = 0x0c, |
1983 | #if EEPROM_SIZE > 0 | |
1984 | .pci.subsystem_vendor_id = PCI_VENDOR_ID_INTEL, | |
1985 | .pci.subsystem_id = 0x0040, | |
1986 | #endif | |
558c8634 SW |
1987 | .stats_size = 80, |
1988 | .has_extended_tcb_support = true, | |
1989 | .power_management = true, | |
c4c270e2 | 1990 | },{ |
558c8634 SW |
1991 | .pci.qdev.name = "i82559er", |
1992 | .pci.qdev.desc = "Intel i82559ER Ethernet", | |
1993 | .device = i82559ER, | |
ad03502b IY |
1994 | .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT, |
1995 | .pci.revision = 0x09, | |
558c8634 SW |
1996 | .stats_size = 80, |
1997 | .has_extended_tcb_support = true, | |
1998 | .power_management = true, | |
0aab0d3a | 1999 | },{ |
558c8634 SW |
2000 | .pci.qdev.name = "i82562", |
2001 | .pci.qdev.desc = "Intel i82562 Ethernet", | |
2002 | .device = i82562, | |
2003 | /* TODO: check device id. */ | |
ad03502b | 2004 | .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT, |
558c8634 | 2005 | /* TODO: wrong revision id. */ |
ad03502b | 2006 | .pci.revision = 0x0e, |
558c8634 SW |
2007 | .stats_size = 80, |
2008 | .has_extended_tcb_support = true, | |
2009 | .power_management = true, | |
db667a12 SW |
2010 | },{ |
2011 | /* Toshiba Tecra 8200. */ | |
2012 | .pci.qdev.name = "i82801", | |
2013 | .pci.qdev.desc = "Intel i82801 Ethernet", | |
2014 | .device = i82801, | |
ad03502b IY |
2015 | .pci.device_id = 0x2449, |
2016 | .pci.revision = 0x03, | |
db667a12 SW |
2017 | .stats_size = 80, |
2018 | .has_extended_tcb_support = true, | |
2019 | .power_management = true, | |
0aab0d3a GH |
2020 | } |
2021 | }; | |
2022 | ||
558c8634 SW |
2023 | static Property e100_properties[] = { |
2024 | DEFINE_NIC_PROPERTIES(EEPRO100State, conf), | |
2025 | DEFINE_PROP_END_OF_LIST(), | |
2026 | }; | |
2027 | ||
9d07d757 | 2028 | static void eepro100_register_devices(void) |
663e8e51 | 2029 | { |
558c8634 SW |
2030 | size_t i; |
2031 | for (i = 0; i < ARRAY_SIZE(e100_devices); i++) { | |
2032 | PCIDeviceInfo *pci_dev = &e100_devices[i].pci; | |
0389ced4 SW |
2033 | /* We use the same rom file for all device ids. |
2034 | QEMU fixes the device id during rom load. */ | |
ad03502b IY |
2035 | pci_dev->vendor_id = PCI_VENDOR_ID_INTEL; |
2036 | pci_dev->class_id = PCI_CLASS_NETWORK_ETHERNET; | |
5ee8ad71 | 2037 | pci_dev->romfile = "pxe-eepro100.rom"; |
558c8634 SW |
2038 | pci_dev->init = e100_nic_init; |
2039 | pci_dev->exit = pci_nic_uninit; | |
2040 | pci_dev->qdev.props = e100_properties; | |
2041 | pci_dev->qdev.size = sizeof(EEPRO100State); | |
2042 | pci_qdev_register(pci_dev); | |
2043 | } | |
663e8e51 TS |
2044 | } |
2045 | ||
9d07d757 | 2046 | device_init(eepro100_register_devices) |