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eepro100: Fix compiler errors from debug messages
[mirror_qemu.git] / hw / eepro100.c
CommitLineData
663e8e51
TS		 1/*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (c) 2006-2007 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
8167ee88 20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
663e8e51
TS		 21 *
22 * Tested features (i82559):
23 * PXE boot (i386) no valid link
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 */
35
36#if defined(TARGET_I386)
37# warning "PXE boot still not working!"
38#endif
39
663e8e51 40#include <stddef.h> /* offsetof */
b84a5c6f 41#include <stdbool.h>
87ecb68b
PB		 42#include "hw.h"
43#include "pci.h"
44#include "net.h"
663e8e51
TS		 45#include "eeprom93xx.h"
46
47/* Common declarations for all PCI devices. */
48
663e8e51
TS		 49#define PCI_CONFIG_8(offset, value) \
50 (pci_conf[offset] = (value))
51#define PCI_CONFIG_16(offset, value) \
52 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
53#define PCI_CONFIG_32(offset, value) \
54 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
55
56#define KiB 1024
57
aac443e6 58/* Debug EEPRO100 card. */
ce0e58b3
SW		 59#if 0
60# define DEBUG_EEPRO100
61#endif
663e8e51
TS		 62
63#ifdef DEBUG_EEPRO100
001faf32 64#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
663e8e51 65#else
001faf32 66#define logout(fmt, ...) ((void)0)
663e8e51
TS		 67#endif
68
69/* Set flags to 0 to disable debug output. */
aac443e6
SW		 70#define INT 1 /* interrupt related actions */
71#define MDI 1 /* mdi related actions */
72#define OTHER 1
73#define RXTX 1
74#define EEPROM 1 /* eeprom related actions */
663e8e51
TS		 75
76#define TRACE(flag, command) ((flag) ? (command) : (void)0)
77
7f1e9d4e 78#define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
663e8e51
TS		 79
80#define MAX_ETH_FRAME_SIZE 1514
81
82/* This driver supports several different devices which are declared here. */
c4c270e2 83#define i82550 0x82550
663e8e51 84#define i82551 0x82551
c4c270e2 85#define i82557A 0x82557a
663e8e51
TS		 86#define i82557B 0x82557b
87#define i82557C 0x82557c
c4c270e2 88#define i82558A 0x82558a
663e8e51 89#define i82558B 0x82558b
c4c270e2
SW		 90#define i82559A 0x82559a
91#define i82559B 0x82559b
663e8e51
TS		 92#define i82559C 0x82559c
93#define i82559ER 0x82559e
94#define i82562 0x82562
95
aac443e6 96/* Use 64 word EEPROM. TODO: could be a runtime option. */
663e8e51
TS		 97#define EEPROM_SIZE 64
98
99#define PCI_MEM_SIZE (4 * KiB)
100#define PCI_IO_SIZE 64
101#define PCI_FLASH_SIZE (128 * KiB)
102
103#define BIT(n) (1 << (n))
104#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
105
106/* The SCB accepts the following controls for the Tx and Rx units: */
107#define CU_NOP 0x0000 /* No operation. */
108#define CU_START 0x0010 /* CU start. */
109#define CU_RESUME 0x0020 /* CU resume. */
110#define CU_STATSADDR 0x0040 /* Load dump counters address. */
111#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
112#define CU_CMD_BASE 0x0060 /* Load CU base address. */
113#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
114#define CU_SRESUME 0x00a0 /* CU static resume. */
115
116#define RU_NOP 0x0000
117#define RX_START 0x0001
118#define RX_RESUME 0x0002
119#define RX_ABORT 0x0004
120#define RX_ADDR_LOAD 0x0006
121#define RX_RESUMENR 0x0007
122#define INT_MASK 0x0100
123#define DRVR_INT 0x0200 /* Driver generated interrupt. */
124
663e8e51
TS		 125/* Offsets to the various registers.
126 All accesses need not be longword aligned. */
127enum speedo_offsets {
128 SCBStatus = 0,
129 SCBAck = 1,
130 SCBCmd = 2, /* Rx/Command Unit command and status. */
131 SCBIntmask = 3,
132 SCBPointer = 4, /* General purpose pointer. */
133 SCBPort = 8, /* Misc. commands and operands. */
134 SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
135 SCBCtrlMDI = 16, /* MDI interface control. */
136 SCBEarlyRx = 20, /* Early receive byte count. */
3257d2b6 137 SCBFlow = 24,
663e8e51
TS		 138};
139
140/* A speedo3 transmit buffer descriptor with two buffers... */
141typedef struct {
142 uint16_t status;
143 uint16_t command;
144 uint32_t link; /* void * */
7b8737de 145 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
663e8e51
TS		 146 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
147 uint8_t tx_threshold; /* transmit threshold */
148 uint8_t tbd_count; /* TBD number */
149 //~ /* This constitutes two "TBD" entries: hdr and data */
150 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
151 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
152 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
153 //~ int32_t tx_buf_size1; /* Length of Tx data. */
c227f099 154} eepro100_tx_t;
663e8e51
TS		 155
156/* Receive frame descriptor. */
157typedef struct {
158 int16_t status;
159 uint16_t command;
160 uint32_t link; /* struct RxFD * */
161 uint32_t rx_buf_addr; /* void * */
162 uint16_t count;
163 uint16_t size;
164 char packet[MAX_ETH_FRAME_SIZE + 4];
c227f099 165} eepro100_rx_t;
663e8e51
TS		 166
167typedef struct {
168 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
169 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
170 tx_multiple_collisions, tx_total_collisions;
171 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
172 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
173 rx_short_frame_errors;
174 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
175 uint16_t xmt_tco_frames, rcv_tco_frames;
ba42b646
SW		 176 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
177 uint32_t reserved[4];
c227f099 178} eepro100_stats_t;
663e8e51
TS		 179
180typedef enum {
181 cu_idle = 0,
182 cu_suspended = 1,
183 cu_active = 2,
184 cu_lpq_active = 2,
185 cu_hqp_active = 3
c227f099 186} cu_state_t;
663e8e51
TS		 187
188typedef enum {
189 ru_idle = 0,
190 ru_suspended = 1,
191 ru_no_resources = 2,
192 ru_ready = 4
c227f099 193} ru_state_t;
663e8e51 194
663e8e51 195typedef struct {
273a2142 196 PCIDevice dev;
663e8e51
TS		 197 uint8_t mult[8]; /* multicast mask array */
198 int mmio_index;
e00e365e 199 NICState *nic;
508ef936 200 NICConf conf;
663e8e51
TS		 201 uint8_t scb_stat; /* SCB stat/ack byte */
202 uint8_t int_stat; /* PCI interrupt status */
3706c43f 203 /* region must not be saved by nic_save. */
663e8e51 204 uint32_t region[3]; /* PCI region addresses */
663e8e51 205 uint16_t mdimem[32];
c227f099 206 eeprom_t *eeprom;
663e8e51
TS		 207 uint32_t device; /* device variant */
208 uint32_t pointer;
209 /* (cu_base + cu_offset) address the next command block in the command block list. */
210 uint32_t cu_base; /* CU base address */
211 uint32_t cu_offset; /* CU address offset */
212 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
213 uint32_t ru_base; /* RU base address */
214 uint32_t ru_offset; /* RU address offset */
c227f099 215 uint32_t statsaddr; /* pointer to eepro100_stats_t */
ba42b646 216
f3a52e50
SW		 217 /* Temporary status information (no need to save these values),
218 * used while processing CU commands. */
219 eepro100_tx_t tx; /* transmit buffer descriptor */
220 uint32_t cb_address; /* = cu_base + cu_offset */
221
ba42b646
SW		 222 /* Statistical counters. Also used for wake-up packet (i82559). */
223 eepro100_stats_t statistics;
224
663e8e51
TS		 225#if 0
226 uint16_t status;
227#endif
228
229 /* Configuration bytes. */
230 uint8_t configuration[22];
231
232 /* Data in mem is always in the byte order of the controller (le). */
233 uint8_t mem[PCI_MEM_SIZE];
151b2986
JQ		 234 /* vmstate for each particular nic */
235 VMStateDescription *vmstate;
ba42b646
SW		 236
237 /* Quasi static device properties (no need to save them). */
238 uint16_t stats_size;
239 bool has_extended_tcb_support;
663e8e51
TS		 240} EEPRO100State;
241
242/* Default values for MDI (PHY) registers */
243static const uint16_t eepro100_mdi_default[] = {
244 /* MDI Registers 0 - 6, 7 */
245 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
246 /* MDI Registers 8 - 15 */
247 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
248 /* MDI Registers 16 - 31 */
249 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
250 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
251};
252
253/* Readonly mask for MDI (PHY) registers */
254static const uint16_t eepro100_mdi_mask[] = {
255 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
256 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
257 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
258 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
259};
260
ba42b646
SW		 261/* XXX: optimize */
262static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
263{
264 val = cpu_to_le32(val);
265 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
266}
267
663e8e51
TS		 268#define POLYNOMIAL 0x04c11db6
269
270/* From FreeBSD */
271/* XXX: optimize */
7b8737de 272static unsigned compute_mcast_idx(const uint8_t * ep)
663e8e51
TS		 273{
274 uint32_t crc;
275 int carry, i, j;
276 uint8_t b;
277
278 crc = 0xffffffff;
279 for (i = 0; i < 6; i++) {
280 b = *ep++;
281 for (j = 0; j < 8; j++) {
282 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
283 crc <<= 1;
284 b >>= 1;
aac443e6 285 if (carry) {
663e8e51 286 crc = ((crc ^ POLYNOMIAL) | carry);
aac443e6 287 }
663e8e51
TS		 288 }
289 }
7b8737de 290 return (crc & BITS(7, 2)) >> 2;
663e8e51
TS		 291}
292
293#if defined(DEBUG_EEPRO100)
294static const char *nic_dump(const uint8_t * buf, unsigned size)
295{
296 static char dump[3 * 16 + 1];
297 char *p = &dump[0];
aac443e6 298 if (size > 16) {
663e8e51 299 size = 16;
aac443e6 300 }
663e8e51
TS		 301 while (size-- > 0) {
302 p += sprintf(p, " %02x", *buf++);
303 }
304 return dump;
305}
306#endif /* DEBUG_EEPRO100 */
307
308enum scb_stat_ack {
309 stat_ack_not_ours = 0x00,
310 stat_ack_sw_gen = 0x04,
311 stat_ack_rnr = 0x10,
312 stat_ack_cu_idle = 0x20,
313 stat_ack_frame_rx = 0x40,
314 stat_ack_cu_cmd_done = 0x80,
315 stat_ack_not_present = 0xFF,
316 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
317 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
318};
319
320static void disable_interrupt(EEPRO100State * s)
321{
322 if (s->int_stat) {
aac443e6 323 TRACE(INT, logout("interrupt disabled\n"));
273a2142 324 qemu_irq_lower(s->dev.irq[0]);
663e8e51
TS		 325 s->int_stat = 0;
326 }
327}
328
329static void enable_interrupt(EEPRO100State * s)
330{
331 if (!s->int_stat) {
aac443e6 332 TRACE(INT, logout("interrupt enabled\n"));
273a2142 333 qemu_irq_raise(s->dev.irq[0]);
663e8e51
TS		 334 s->int_stat = 1;
335 }
336}
337
338static void eepro100_acknowledge(EEPRO100State * s)
339{
340 s->scb_stat &= ~s->mem[SCBAck];
341 s->mem[SCBAck] = s->scb_stat;
342 if (s->scb_stat == 0) {
343 disable_interrupt(s);
344 }
345}
346
347static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
348{
349 uint8_t mask = ~s->mem[SCBIntmask];
350 s->mem[SCBAck] |= stat;
351 stat = s->scb_stat = s->mem[SCBAck];
352 stat &= (mask | 0x0f);
353 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
354 if (stat && (mask & 0x01)) {
355 /* SCB mask and SCB Bit M do not disable interrupt. */
356 enable_interrupt(s);
357 } else if (s->int_stat) {
358 disable_interrupt(s);
359 }
360}
361
362static void eepro100_cx_interrupt(EEPRO100State * s)
363{
364 /* CU completed action command. */
365 /* Transmit not ok (82557 only, not in emulation). */
366 eepro100_interrupt(s, 0x80);
367}
368
369static void eepro100_cna_interrupt(EEPRO100State * s)
370{
371 /* CU left the active state. */
372 eepro100_interrupt(s, 0x20);
373}
374
375static void eepro100_fr_interrupt(EEPRO100State * s)
376{
377 /* RU received a complete frame. */
378 eepro100_interrupt(s, 0x40);
379}
380
381#if 0
382static void eepro100_rnr_interrupt(EEPRO100State * s)
383{
384 /* RU is not ready. */
385 eepro100_interrupt(s, 0x10);
386}
387#endif
388
389static void eepro100_mdi_interrupt(EEPRO100State * s)
390{
391 /* MDI completed read or write cycle. */
392 eepro100_interrupt(s, 0x08);
393}
394
395static void eepro100_swi_interrupt(EEPRO100State * s)
396{
397 /* Software has requested an interrupt. */
398 eepro100_interrupt(s, 0x04);
399}
400
401#if 0
402static void eepro100_fcp_interrupt(EEPRO100State * s)
403{
404 /* Flow control pause interrupt (82558 and later). */
405 eepro100_interrupt(s, 0x01);
406}
407#endif
408
409static void pci_reset(EEPRO100State * s)
410{
411 uint32_t device = s->device;
273a2142 412 uint8_t *pci_conf = s->dev.config;
ba42b646 413 bool power_management = 1;
663e8e51 414
aac443e6 415 TRACE(OTHER, logout("%p\n", s));
663e8e51
TS		 416
417 /* PCI Vendor ID */
deb54399 418 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
d6fd1e66 419 /* PCI Device ID depends on device and is set below. */
663e8e51 420 /* PCI Command */
508cc6b4 421 /* TODO: this is the default, do not override. */
663e8e51
TS		 422 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
423 /* PCI Status */
508cc6b4 424 /* TODO: Value at RST# should be 0. */
61702408 425 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
663e8e51
TS		 426 /* PCI Revision ID */
427 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
508cc6b4 428 /* TODO: this is the default, do not override. */
663e8e51 429 /* PCI Class Code */
508cc6b4 430 PCI_CONFIG_8(PCI_CLASS_PROG, 0x00);
173a543b 431 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
663e8e51
TS		 432 /* PCI Cache Line Size */
433 /* check cache line size!!! */
434 //~ PCI_CONFIG_8(0x0c, 0x00);
435 /* PCI Latency Timer */
508cc6b4 436 PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks
663e8e51
TS		 437 /* PCI Header Type */
438 /* BIST (built-in self test) */
439#if defined(TARGET_I386)
440// !!! workaround for buggy bios
0392a017 441//~ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0
663e8e51
TS		 442#endif
443#if 0
444 /* PCI Base Address Registers */
445 /* CSR Memory Mapped Base Address */
446 PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
0392a017
IY		 447 PCI_BASE_ADDRESS_SPACE_MEMORY |
448 PCI_BASE_ADDRESS_MEM_PREFETCH);
663e8e51 449 /* CSR I/O Mapped Base Address */
0392a017 450 PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_SPACE_IO);
663e8e51
TS		 451#if 0
452 /* Flash Memory Mapped Base Address */
0392a017
IY		 453 PCI_CONFIG_32(PCI_BASE_ADDRESS_2,
454 0xfffe0000 | PCI_BASE_ADDRESS_SPACE_MEMORY);
663e8e51
TS		 455#endif
456#endif
457 /* Expansion ROM Base Address (depends on boot disable!!!) */
508cc6b4
MT		 458 /* TODO: not needed, set when BAR is registered */
459 PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY);
663e8e51 460 /* Capability Pointer */
508cc6b4
MT		 461 /* TODO: revisions with power_management 1 use this but
462 * do not set new capability list bit in status register. */
463 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc);
aac443e6 464 /* Interrupt Line */
663e8e51 465 /* Interrupt Pin */
508cc6b4
MT		 466 /* TODO: RST# value should be 0 */
467 PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0
663e8e51 468 /* Minimum Grant */
508cc6b4 469 PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
663e8e51 470 /* Maximum Latency */
508cc6b4 471 PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
663e8e51
TS		 472
473 switch (device) {
ba42b646
SW		 474 case i82550:
475 // TODO: check device id.
476 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
477 /* Revision ID: 0x0c, 0x0d, 0x0e. */
478 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
479 // TODO: check size of statistical counters.
480 s->stats_size = 80;
481 // TODO: check extended tcb support.
482 s->has_extended_tcb_support = 1;
483 break;
663e8e51 484 case i82551:
d6fd1e66 485 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
ba42b646 486 /* Revision ID: 0x0f, 0x10. */
663e8e51 487 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
ba42b646
SW		 488 // TODO: check size of statistical counters.
489 s->stats_size = 80;
490 s->has_extended_tcb_support = 1;
491 break;
492 case i82557A:
493 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
494 PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
508cc6b4 495 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
ba42b646 496 power_management = 0;
663e8e51
TS		 497 break;
498 case i82557B:
d6fd1e66 499 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
663e8e51 500 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
508cc6b4 501 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
ba42b646 502 power_management = 0;
663e8e51
TS		 503 break;
504 case i82557C:
d6fd1e66 505 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
663e8e51 506 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
508cc6b4 507 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
ba42b646
SW		 508 power_management = 0;
509 break;
510 case i82558A:
511 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 512 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
513 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
ba42b646
SW		 514 PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
515 s->stats_size = 76;
516 s->has_extended_tcb_support = 1;
663e8e51
TS		 517 break;
518 case i82558B:
d6fd1e66 519 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 520 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
521 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
663e8e51 522 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
ba42b646
SW		 523 s->stats_size = 76;
524 s->has_extended_tcb_support = 1;
525 break;
526 case i82559A:
527 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 528 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
529 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
ba42b646
SW		 530 PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
531 s->stats_size = 80;
532 s->has_extended_tcb_support = 1;
533 break;
534 case i82559B:
535 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 536 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
537 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
ba42b646
SW		 538 PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
539 s->stats_size = 80;
540 s->has_extended_tcb_support = 1;
663e8e51
TS		 541 break;
542 case i82559C:
d6fd1e66 543 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 544 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
545 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
ba42b646
SW		 546 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
547 // TODO: Windows wants revision id 0x0c.
548 PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
549#if EEPROM_SIZE > 0
550 PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
551 PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
552#endif
553 s->stats_size = 80;
554 s->has_extended_tcb_support = 1;
663e8e51
TS		 555 break;
556 case i82559ER:
d6fd1e66 557 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
508cc6b4
MT		 558 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
559 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
663e8e51 560 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
ba42b646
SW		 561 s->stats_size = 80;
562 s->has_extended_tcb_support = 1;
563 break;
564 case i82562:
565 // TODO: check device id.
566 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
567 /* TODO: wrong revision id. */
568 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
569 s->stats_size = 80;
570 s->has_extended_tcb_support = 1;
663e8e51 571 break;
663e8e51
TS		 572 default:
573 logout("Device %X is undefined!\n", device);
574 }
575
ba42b646
SW		 576 s->configuration[6] |= BIT(5);
577
578 if (s->stats_size == 80) {
579 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
580 if (s->configuration[6] & BIT(2)) {
581 /* TCO statistical counters. */
582 assert(s->configuration[6] & BIT(5));
583 } else {
584 if (s->configuration[6] & BIT(5)) {
585 /* No extended statistical counters, i82557 compatible. */
586 s->stats_size = 64;
587 } else {
588 /* i82558 compatible. */
589 s->stats_size = 76;
590 }
591 }
592 } else {
593 if (s->configuration[6] & BIT(5)) {
594 /* No extended statistical counters. */
595 s->stats_size = 64;
596 }
597 }
598 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
599
600 if (power_management) {
601 /* Power Management Capabilities */
602 PCI_CONFIG_8(0xdc, 0x01);
603 /* Next Item Pointer */
604 /* Capability ID */
605 PCI_CONFIG_16(0xde, 0x7e21);
606 /* TODO: Power Management Control / Status. */
607 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
608 }
609
610#if EEPROM_SIZE > 0
663e8e51 611 if (device == i82557C || device == i82558B || device == i82559C) {
ba42b646
SW		 612 // TODO: get vendor id from EEPROM for i82557C or later.
613 // TODO: get device id from EEPROM for i82557C or later.
614 // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
615 // TODO: header type is determined by EEPROM for i82559.
616 // TODO: get subsystem id from EEPROM for i82557C or later.
617 // TODO: get subsystem vendor id from EEPROM for i82557C or later.
618 // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
619 // TODO: capability pointer depends on EEPROM for i82558.
663e8e51
TS		 620 logout("Get device id and revision from EEPROM!!!\n");
621 }
ba42b646 622#endif /* EEPROM_SIZE > 0 */
663e8e51
TS		 623}
624
625static void nic_selective_reset(EEPRO100State * s)
626{
627 size_t i;
628 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
629 //~ eeprom93xx_reset(s->eeprom);
508ef936 630 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
663e8e51 631 eeprom_contents[0xa] = 0x4000;
f4e94dfe
RD		 632 if (s->device == i82557B || s->device == i82557C)
633 eeprom_contents[5] = 0x0100;
663e8e51
TS		 634 uint16_t sum = 0;
635 for (i = 0; i < EEPROM_SIZE - 1; i++) {
636 sum += eeprom_contents[i];
637 }
638 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
aac443e6 639 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
663e8e51
TS		 640
641 memset(s->mem, 0, sizeof(s->mem));
642 uint32_t val = BIT(21);
643 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
644
645 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
646 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
647}
648
649static void nic_reset(void *opaque)
650{
769cf7a5 651 EEPRO100State *s = opaque;
aac443e6 652 TRACE(OTHER, logout("%p\n", s));
7b8737de
SW		 653 /* TODO: Clearing of multicast table for selective reset, too? */
654 memset(&s->mult[0], 0, sizeof(s->mult));
663e8e51
TS		 655 nic_selective_reset(s);
656}
657
658#if defined(DEBUG_EEPRO100)
b8f6ba0d 659static const char * const e100_reg[PCI_IO_SIZE / 4] = {
663e8e51
TS		 660 "Command/Status",
661 "General Pointer",
662 "Port",
663 "EEPROM/Flash Control",
664 "MDI Control",
665 "Receive DMA Byte Count",
b8f6ba0d 666 "Flow Control",
663e8e51
TS		 667 "General Status/Control"
668};
669
670static char *regname(uint32_t addr)
671{
ec169288 672 static char buf[32];
663e8e51 673 if (addr < PCI_IO_SIZE) {
b8f6ba0d 674 const char *r = e100_reg[addr / 4];
663e8e51 675 if (r != 0) {
41cbc23c 676 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
663e8e51 677 } else {
41cbc23c 678 snprintf(buf, sizeof(buf), "0x%02x", addr);
663e8e51
TS		 679 }
680 } else {
41cbc23c 681 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
663e8e51
TS		 682 }
683 return buf;
684}
685#endif /* DEBUG_EEPRO100 */
686
687#if 0
688static uint16_t eepro100_read_status(EEPRO100State * s)
689{
690 uint16_t val = s->status;
aac443e6 691 TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
TS		 692 return val;
693}
694
695static void eepro100_write_status(EEPRO100State * s, uint16_t val)
696{
aac443e6 697 TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
TS		 698 s->status = val;
699}
700#endif
701
702/*****************************************************************************
703 *
704 * Command emulation.
705 *
706 ****************************************************************************/
707
708#if 0
709static uint16_t eepro100_read_command(EEPRO100State * s)
710{
711 uint16_t val = 0xffff;
aac443e6 712 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
TS		 713 return val;
714}
715#endif
716
717/* Commands that can be put in a command list entry. */
718enum commands {
719 CmdNOp = 0,
720 CmdIASetup = 1,
721 CmdConfigure = 2,
722 CmdMulticastList = 3,
723 CmdTx = 4,
724 CmdTDR = 5, /* load microcode */
725 CmdDump = 6,
726 CmdDiagnose = 7,
727
728 /* And some extra flags: */
729 CmdSuspend = 0x4000, /* Suspend after completion. */
730 CmdIntr = 0x2000, /* Interrupt after completion. */
731 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
732};
733
c227f099 734static cu_state_t get_cu_state(EEPRO100State * s)
663e8e51
TS		 735{
736 return ((s->mem[SCBStatus] >> 6) & 0x03);
737}
738
c227f099 739static void set_cu_state(EEPRO100State * s, cu_state_t state)
663e8e51
TS		 740{
741 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
742}
743
c227f099 744static ru_state_t get_ru_state(EEPRO100State * s)
663e8e51
TS		 745{
746 return ((s->mem[SCBStatus] >> 2) & 0x0f);
747}
748
c227f099 749static void set_ru_state(EEPRO100State * s, ru_state_t state)
663e8e51
TS		 750{
751 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
752}
753
754static void dump_statistics(EEPRO100State * s)
755{
756 /* Dump statistical data. Most data is never changed by the emulation
757 * and always 0, so we first just copy the whole block and then those
758 * values which really matter.
759 * Number of data should check configuration!!!
760 */
ba42b646
SW		 761 cpu_physical_memory_write(s->statsaddr,
762 (uint8_t *) & s->statistics, s->stats_size);
763 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
764 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
765 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
766 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
767 //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
768 //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
663e8e51
TS		 769 //~ missing("CU dump statistical counters");
770}
771
f3a52e50
SW		 772static void tx_command(EEPRO100State *s)
773{
7b8737de 774 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
f3a52e50
SW		 775 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
776 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
777 uint8_t buf[2600];
778 uint16_t size = 0;
779 uint32_t tbd_address = s->cb_address + 0x10;
780 TRACE(RXTX, logout
781 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
782 tbd_array, tcb_bytes, s->tx.tbd_count));
783
784 if (tcb_bytes > 2600) {
785 logout("TCB byte count too large, using 2600\n");
786 tcb_bytes = 2600;
787 }
788 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
789 logout
790 ("illegal values of TBD array address and TCB byte count!\n");
791 }
792 assert(tcb_bytes <= sizeof(buf));
793 while (size < tcb_bytes) {
794 uint32_t tx_buffer_address = ldl_phys(tbd_address);
795 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
796 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
797 tbd_address += 8;
798 TRACE(RXTX, logout
799 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
800 tx_buffer_address, tx_buffer_size));
801 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
802 cpu_physical_memory_read(tx_buffer_address, &buf[size],
803 tx_buffer_size);
804 size += tx_buffer_size;
805 }
806 if (tbd_array == 0xffffffff) {
807 /* Simplified mode. Was already handled by code above. */
808 } else {
809 /* Flexible mode. */
810 uint8_t tbd_count = 0;
811 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
812 /* Extended Flexible TCB. */
813 for (; tbd_count < 2; tbd_count++) {
814 uint32_t tx_buffer_address = ldl_phys(tbd_address);
815 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
816 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
817 tbd_address += 8;
818 TRACE(RXTX, logout
819 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
820 tx_buffer_address, tx_buffer_size));
821 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
822 cpu_physical_memory_read(tx_buffer_address, &buf[size],
823 tx_buffer_size);
824 size += tx_buffer_size;
825 if (tx_buffer_el & 1) {
826 break;
827 }
828 }
829 }
830 tbd_address = tbd_array;
831 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
832 uint32_t tx_buffer_address = ldl_phys(tbd_address);
833 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
834 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
835 tbd_address += 8;
836 TRACE(RXTX, logout
837 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
838 tx_buffer_address, tx_buffer_size));
839 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
840 cpu_physical_memory_read(tx_buffer_address, &buf[size],
841 tx_buffer_size);
842 size += tx_buffer_size;
843 if (tx_buffer_el & 1) {
844 break;
845 }
846 }
847 }
848 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
849 qemu_send_packet(&s->nic->nc, buf, size);
850 s->statistics.tx_good_frames++;
851 /* Transmit with bad status would raise an CX/TNO interrupt.
852 * (82557 only). Emulation never has bad status. */
853 //~ eepro100_cx_interrupt(s);
854}
855
7b8737de
SW		 856static void set_multicast_list(EEPRO100State *s)
857{
858 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
859 uint16_t i;
860 memset(&s->mult[0], 0, sizeof(s->mult));
861 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
862 for (i = 0; i < multicast_count; i += 6) {
863 uint8_t multicast_addr[6];
864 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
865 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
866 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
867 assert(mcast_idx < 64);
868 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
869 }
870}
871
5fa9a0ae 872static void action_command(EEPRO100State *s)
663e8e51 873{
5fa9a0ae 874 for (;;) {
f3a52e50
SW		 875 s->cb_address = s->cu_base + s->cu_offset;
876 cpu_physical_memory_read(s->cb_address, (uint8_t *)&s->tx, sizeof(s->tx));
877 uint16_t status = le16_to_cpu(s->tx.status);
878 uint16_t command = le16_to_cpu(s->tx.command);
ce0e58b3
SW		 879 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
880 status, command, s->tx.link);
663e8e51
TS		 881 bool bit_el = ((command & 0x8000) != 0);
882 bool bit_s = ((command & 0x4000) != 0);
883 bool bit_i = ((command & 0x2000) != 0);
884 bool bit_nc = ((command & 0x0010) != 0);
7f1e9d4e 885 bool success = true;
663e8e51
TS		 886 //~ bool bit_sf = ((command & 0x0008) != 0);
887 uint16_t cmd = command & 0x0007;
f3a52e50 888 s->cu_offset = le32_to_cpu(s->tx.link);
663e8e51
TS		 889 switch (cmd) {
890 case CmdNOp:
891 /* Do nothing. */
892 break;
893 case CmdIASetup:
f3a52e50 894 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
ce0e58b3 895 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
663e8e51
TS		 896 break;
897 case CmdConfigure:
f3a52e50 898 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
663e8e51 899 sizeof(s->configuration));
aac443e6 900 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
663e8e51
TS		 901 break;
902 case CmdMulticastList:
7b8737de 903 set_multicast_list(s);
663e8e51
TS		 904 break;
905 case CmdTx:
7f1e9d4e
KW		 906 if (bit_nc) {
907 missing("CmdTx: NC = 0");
908 success = false;
909 break;
910 }
f3a52e50 911 tx_command(s);
663e8e51
TS		 912 break;
913 case CmdTDR:
aac443e6 914 TRACE(OTHER, logout("load microcode\n"));
663e8e51
TS		 915 /* Starting with offset 8, the command contains
916 * 64 dwords microcode which we just ignore here. */
917 break;
918 default:
919 missing("undefined command");
7f1e9d4e
KW		 920 success = false;
921 break;
663e8e51 922 }
7f1e9d4e 923 /* Write new status. */
f3a52e50 924 stw_phys(s->cb_address, status | 0x8000 | (success ? 0x2000 : 0));
663e8e51
TS		 925 if (bit_i) {
926 /* CU completed action. */
927 eepro100_cx_interrupt(s);
928 }
929 if (bit_el) {
aac443e6 930 /* CU becomes idle. Terminate command loop. */
663e8e51
TS		 931 set_cu_state(s, cu_idle);
932 eepro100_cna_interrupt(s);
5fa9a0ae 933 break;
663e8e51 934 } else if (bit_s) {
5fa9a0ae 935 /* CU becomes suspended. Terminate command loop. */
663e8e51
TS		 936 set_cu_state(s, cu_suspended);
937 eepro100_cna_interrupt(s);
5fa9a0ae 938 break;
663e8e51
TS		 939 } else {
940 /* More entries in list. */
aac443e6 941 TRACE(OTHER, logout("CU list with at least one more entry\n"));
663e8e51 942 }
5fa9a0ae
SW		 943 }
944 TRACE(OTHER, logout("CU list empty\n"));
945 /* List is empty. Now CU is idle or suspended. */
946}
947
948static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
949{
950 switch (val) {
951 case CU_NOP:
952 /* No operation. */
953 break;
954 case CU_START:
955 if (get_cu_state(s) != cu_idle) {
956 /* Intel documentation says that CU must be idle for the CU
957 * start command. Intel driver for Linux also starts the CU
958 * from suspended state. */
959 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
960 //~ assert(!"wrong CU state");
961 }
962 set_cu_state(s, cu_active);
963 s->cu_offset = s->pointer;
964 action_command(s);
663e8e51
TS		 965 break;
966 case CU_RESUME:
967 if (get_cu_state(s) != cu_suspended) {
968 logout("bad CU resume from CU state %u\n", get_cu_state(s));
969 /* Workaround for bad Linux eepro100 driver which resumes
970 * from idle state. */
971 //~ missing("cu resume");
972 set_cu_state(s, cu_suspended);
973 }
974 if (get_cu_state(s) == cu_suspended) {
aac443e6 975 TRACE(OTHER, logout("CU resuming\n"));
663e8e51 976 set_cu_state(s, cu_active);
5fa9a0ae 977 action_command(s);
663e8e51
TS		 978 }
979 break;
980 case CU_STATSADDR:
981 /* Load dump counters address. */
982 s->statsaddr = s->pointer;
aac443e6 983 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
663e8e51
TS		 984 break;
985 case CU_SHOWSTATS:
986 /* Dump statistical counters. */
aac443e6 987 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
663e8e51 988 dump_statistics(s);
ba42b646 989 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
663e8e51
TS		 990 break;
991 case CU_CMD_BASE:
992 /* Load CU base. */
aac443e6 993 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
663e8e51
TS		 994 s->cu_base = s->pointer;
995 break;
996 case CU_DUMPSTATS:
997 /* Dump and reset statistical counters. */
aac443e6 998 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
663e8e51 999 dump_statistics(s);
ba42b646 1000 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
663e8e51
TS		 1001 memset(&s->statistics, 0, sizeof(s->statistics));
1002 break;
1003 case CU_SRESUME:
1004 /* CU static resume. */
1005 missing("CU static resume");
1006 break;
1007 default:
1008 missing("Undefined CU command");
1009 }
1010}
1011
1012static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1013{
1014 switch (val) {
1015 case RU_NOP:
1016 /* No operation. */
1017 break;
1018 case RX_START:
1019 /* RU start. */
1020 if (get_ru_state(s) != ru_idle) {
1021 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1022 //~ assert(!"wrong RU state");
1023 }
1024 set_ru_state(s, ru_ready);
1025 s->ru_offset = s->pointer;
aac443e6 1026 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
663e8e51
TS		 1027 break;
1028 case RX_RESUME:
1029 /* Restart RU. */
1030 if (get_ru_state(s) != ru_suspended) {
1031 logout("RU state is %u, should be %u\n", get_ru_state(s),
1032 ru_suspended);
1033 //~ assert(!"wrong RU state");
1034 }
1035 set_ru_state(s, ru_ready);
1036 break;
1037 case RX_ADDR_LOAD:
1038 /* Load RU base. */
aac443e6 1039 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
663e8e51
TS		 1040 s->ru_base = s->pointer;
1041 break;
1042 default:
1043 logout("val=0x%02x (undefined RU command)\n", val);
1044 missing("Undefined SU command");
1045 }
1046}
1047
1048static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1049{
1050 eepro100_ru_command(s, val & 0x0f);
1051 eepro100_cu_command(s, val & 0xf0);
1052 if ((val) == 0) {
aac443e6 1053 TRACE(OTHER, logout("val=0x%02x\n", val));
663e8e51
TS		 1054 }
1055 /* Clear command byte after command was accepted. */
1056 s->mem[SCBCmd] = 0;
1057}
1058
1059/*****************************************************************************
1060 *
1061 * EEPROM emulation.
1062 *
1063 ****************************************************************************/
1064
1065#define EEPROM_CS 0x02
1066#define EEPROM_SK 0x01
1067#define EEPROM_DI 0x04
1068#define EEPROM_DO 0x08
1069
1070static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1071{
1072 uint16_t val;
1073 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1074 if (eeprom93xx_read(s->eeprom)) {
1075 val |= EEPROM_DO;
1076 } else {
1077 val &= ~EEPROM_DO;
1078 }
aac443e6 1079 TRACE(EEPROM, logout("val=0x%04x\n", val));
663e8e51
TS		 1080 return val;
1081}
1082
c227f099 1083static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
663e8e51 1084{
aac443e6 1085 TRACE(EEPROM, logout("val=0x%02x\n", val));
663e8e51
TS		 1086
1087 /* mask unwriteable bits */
1088 //~ val = SET_MASKED(val, 0x31, eeprom->value);
1089
1090 int eecs = ((val & EEPROM_CS) != 0);
1091 int eesk = ((val & EEPROM_SK) != 0);
1092 int eedi = ((val & EEPROM_DI) != 0);
1093 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1094}
1095
1096static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1097{
1098 s->pointer = le32_to_cpu(val);
aac443e6 1099 TRACE(OTHER, logout("val=0x%08x\n", val));
663e8e51
TS		 1100}
1101
1102/*****************************************************************************
1103 *
1104 * MDI emulation.
1105 *
1106 ****************************************************************************/
1107
1108#if defined(DEBUG_EEPRO100)
6a0b9cc9 1109static const char * const mdi_op_name[] = {
663e8e51
TS		 1110 "opcode 0",
1111 "write",
1112 "read",
1113 "opcode 3"
1114};
1115
6a0b9cc9 1116static const char * const mdi_reg_name[] = {
663e8e51
TS		 1117 "Control",
1118 "Status",
1119 "PHY Identification (Word 1)",
1120 "PHY Identification (Word 2)",
1121 "Auto-Negotiation Advertisement",
1122 "Auto-Negotiation Link Partner Ability",
1123 "Auto-Negotiation Expansion"
1124};
aac443e6
SW		 1125
1126static const char *reg2name(uint8_t reg)
1127{
1128 static char buffer[10];
1129 const char *p = buffer;
1130 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1131 p = mdi_reg_name[reg];
1132 } else {
1133 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1134 }
1135 return p;
1136}
663e8e51
TS		 1137#endif /* DEBUG_EEPRO100 */
1138
1139static uint32_t eepro100_read_mdi(EEPRO100State * s)
1140{
1141 uint32_t val;
1142 memcpy(&val, &s->mem[0x10], sizeof(val));
1143
1144#ifdef DEBUG_EEPRO100
1145 uint8_t raiseint = (val & BIT(29)) >> 29;
1146 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1147 uint8_t phy = (val & BITS(25, 21)) >> 21;
1148 uint8_t reg = (val & BITS(20, 16)) >> 16;
1149 uint16_t data = (val & BITS(15, 0));
1150#endif
1151 /* Emulation takes no time to finish MDI transaction. */
1152 val |= BIT(28);
1153 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1154 val, raiseint, mdi_op_name[opcode], phy,
aac443e6 1155 reg2name(reg), data));
663e8e51
TS		 1156 return val;
1157}
1158
663e8e51
TS		 1159static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1160{
1161 uint8_t raiseint = (val & BIT(29)) >> 29;
1162 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1163 uint8_t phy = (val & BITS(25, 21)) >> 21;
1164 uint8_t reg = (val & BITS(20, 16)) >> 16;
1165 uint16_t data = (val & BITS(15, 0));
aac443e6
SW		 1166 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1167 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
663e8e51
TS		 1168 if (phy != 1) {
1169 /* Unsupported PHY address. */
1170 //~ logout("phy must be 1 but is %u\n", phy);
1171 data = 0;
1172 } else if (opcode != 1 && opcode != 2) {
1173 /* Unsupported opcode. */
1174 logout("opcode must be 1 or 2 but is %u\n", opcode);
1175 data = 0;
1176 } else if (reg > 6) {
1177 /* Unsupported register. */
1178 logout("register must be 0...6 but is %u\n", reg);
1179 data = 0;
1180 } else {
1181 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1182 val, raiseint, mdi_op_name[opcode], phy,
aac443e6 1183 reg2name(reg), data));
663e8e51
TS		 1184 if (opcode == 1) {
1185 /* MDI write */
1186 switch (reg) {
1187 case 0: /* Control Register */
1188 if (data & 0x8000) {
1189 /* Reset status and control registers to default. */
1190 s->mdimem[0] = eepro100_mdi_default[0];
1191 s->mdimem[1] = eepro100_mdi_default[1];
1192 data = s->mdimem[reg];
1193 } else {
1194 /* Restart Auto Configuration = Normal Operation */
1195 data &= ~0x0200;
1196 }
1197 break;
1198 case 1: /* Status Register */
1199 missing("not writable");
1200 data = s->mdimem[reg];
1201 break;
1202 case 2: /* PHY Identification Register (Word 1) */
1203 case 3: /* PHY Identification Register (Word 2) */
1204 missing("not implemented");
1205 break;
1206 case 4: /* Auto-Negotiation Advertisement Register */
1207 case 5: /* Auto-Negotiation Link Partner Ability Register */
1208 break;
1209 case 6: /* Auto-Negotiation Expansion Register */
1210 default:
1211 missing("not implemented");
1212 }
1213 s->mdimem[reg] = data;
1214 } else if (opcode == 2) {
1215 /* MDI read */
1216 switch (reg) {
1217 case 0: /* Control Register */
1218 if (data & 0x8000) {
1219 /* Reset status and control registers to default. */
1220 s->mdimem[0] = eepro100_mdi_default[0];
1221 s->mdimem[1] = eepro100_mdi_default[1];
1222 }
1223 break;
1224 case 1: /* Status Register */
1225 s->mdimem[reg] |= 0x0020;
1226 break;
1227 case 2: /* PHY Identification Register (Word 1) */
1228 case 3: /* PHY Identification Register (Word 2) */
1229 case 4: /* Auto-Negotiation Advertisement Register */
1230 break;
1231 case 5: /* Auto-Negotiation Link Partner Ability Register */
1232 s->mdimem[reg] = 0x41fe;
1233 break;
1234 case 6: /* Auto-Negotiation Expansion Register */
1235 s->mdimem[reg] = 0x0001;
1236 break;
1237 }
1238 data = s->mdimem[reg];
1239 }
1240 /* Emulation takes no time to finish MDI transaction.
1241 * Set MDI bit in SCB status register. */
1242 s->mem[SCBAck] |= 0x08;
1243 val |= BIT(28);
1244 if (raiseint) {
1245 eepro100_mdi_interrupt(s);
1246 }
1247 }
1248 val = (val & 0xffff0000) + data;
1249 memcpy(&s->mem[0x10], &val, sizeof(val));
1250}
1251
1252/*****************************************************************************
1253 *
1254 * Port emulation.
1255 *
1256 ****************************************************************************/
1257
1258#define PORT_SOFTWARE_RESET 0
1259#define PORT_SELFTEST 1
1260#define PORT_SELECTIVE_RESET 2
1261#define PORT_DUMP 3
1262#define PORT_SELECTION_MASK 3
1263
1264typedef struct {
1265 uint32_t st_sign; /* Self Test Signature */
1266 uint32_t st_result; /* Self Test Results */
c227f099 1267} eepro100_selftest_t;
663e8e51
TS		 1268
1269static uint32_t eepro100_read_port(EEPRO100State * s)
1270{
1271 return 0;
1272}
1273
1274static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1275{
1276 val = le32_to_cpu(val);
1277 uint32_t address = (val & ~PORT_SELECTION_MASK);
1278 uint8_t selection = (val & PORT_SELECTION_MASK);
1279 switch (selection) {
1280 case PORT_SOFTWARE_RESET:
1281 nic_reset(s);
1282 break;
1283 case PORT_SELFTEST:
aac443e6 1284 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
c227f099 1285 eepro100_selftest_t data;
663e8e51
TS		 1286 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1287 data.st_sign = 0xffffffff;
1288 data.st_result = 0;
1289 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1290 break;
1291 case PORT_SELECTIVE_RESET:
aac443e6 1292 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
663e8e51
TS		 1293 nic_selective_reset(s);
1294 break;
1295 default:
1296 logout("val=0x%08x\n", val);
1297 missing("unknown port selection");
1298 }
1299}
1300
1301/*****************************************************************************
1302 *
1303 * General hardware emulation.
1304 *
1305 ****************************************************************************/
1306
1307static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1308{
1309 uint8_t val;
1310 if (addr <= sizeof(s->mem) - sizeof(val)) {
1311 memcpy(&val, &s->mem[addr], sizeof(val));
1312 }
1313
1314 switch (addr) {
1315 case SCBStatus:
1316 //~ val = eepro100_read_status(s);
aac443e6 1317 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1318 break;
1319 case SCBAck:
1320 //~ val = eepro100_read_status(s);
aac443e6 1321 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1322 break;
1323 case SCBCmd:
aac443e6 1324 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1325 //~ val = eepro100_read_command(s);
1326 break;
1327 case SCBIntmask:
aac443e6 1328 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1329 break;
1330 case SCBPort + 3:
aac443e6 1331 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1332 break;
1333 case SCBeeprom:
1334 val = eepro100_read_eeprom(s);
1335 break;
1336 case 0x1b: /* PMDR (power management driver register) */
1337 val = 0;
aac443e6 1338 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1339 break;
1340 case 0x1d: /* general status register */
1341 /* 100 Mbps full duplex, valid link */
1342 val = 0x07;
aac443e6 1343 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
663e8e51
TS		 1344 break;
1345 default:
1346 logout("addr=%s val=0x%02x\n", regname(addr), val);
1347 missing("unknown byte read");
1348 }
1349 return val;
1350}
1351
1352static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1353{
1354 uint16_t val;
1355 if (addr <= sizeof(s->mem) - sizeof(val)) {
1356 memcpy(&val, &s->mem[addr], sizeof(val));
1357 }
1358
663e8e51
TS		 1359 switch (addr) {
1360 case SCBStatus:
1361 //~ val = eepro100_read_status(s);
dbbaaff6 1362 case SCBCmd:
aac443e6 1363 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS		 1364 break;
1365 case SCBeeprom:
1366 val = eepro100_read_eeprom(s);
aac443e6 1367 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS		 1368 break;
1369 default:
1370 logout("addr=%s val=0x%04x\n", regname(addr), val);
1371 missing("unknown word read");
1372 }
1373 return val;
1374}
1375
1376static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1377{
1378 uint32_t val;
1379 if (addr <= sizeof(s->mem) - sizeof(val)) {
1380 memcpy(&val, &s->mem[addr], sizeof(val));
1381 }
1382
1383 switch (addr) {
1384 case SCBStatus:
1385 //~ val = eepro100_read_status(s);
aac443e6 1386 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1387 break;
1388 case SCBPointer:
1389 //~ val = eepro100_read_pointer(s);
aac443e6 1390 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1391 break;
1392 case SCBPort:
1393 val = eepro100_read_port(s);
aac443e6 1394 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1395 break;
1396 case SCBCtrlMDI:
1397 val = eepro100_read_mdi(s);
1398 break;
1399 default:
1400 logout("addr=%s val=0x%08x\n", regname(addr), val);
1401 missing("unknown longword read");
1402 }
1403 return val;
1404}
1405
1406static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1407{
1408 if (addr <= sizeof(s->mem) - sizeof(val)) {
1409 memcpy(&s->mem[addr], &val, sizeof(val));
1410 }
1411
aac443e6 1412 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1413
1414 switch (addr) {
1415 case SCBStatus:
1416 //~ eepro100_write_status(s, val);
1417 break;
1418 case SCBAck:
1419 eepro100_acknowledge(s);
1420 break;
1421 case SCBCmd:
1422 eepro100_write_command(s, val);
1423 break;
1424 case SCBIntmask:
1425 if (val & BIT(1)) {
1426 eepro100_swi_interrupt(s);
1427 }
1428 eepro100_interrupt(s, 0);
1429 break;
1430 case SCBPort + 3:
aac443e6 1431 case SCBFlow: /* does not exist on 82557 */
3257d2b6
TS		 1432 case SCBFlow + 1:
1433 case SCBFlow + 2:
1434 case SCBFlow + 3:
aac443e6 1435 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1436 break;
1437 case SCBeeprom:
1438 eepro100_write_eeprom(s->eeprom, val);
1439 break;
1440 default:
1441 logout("addr=%s val=0x%02x\n", regname(addr), val);
1442 missing("unknown byte write");
1443 }
1444}
1445
1446static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1447{
1448 if (addr <= sizeof(s->mem) - sizeof(val)) {
1449 memcpy(&s->mem[addr], &val, sizeof(val));
1450 }
1451
aac443e6 1452 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS		 1453
1454 switch (addr) {
1455 case SCBStatus:
1456 //~ eepro100_write_status(s, val);
1457 eepro100_acknowledge(s);
1458 break;
1459 case SCBCmd:
1460 eepro100_write_command(s, val);
1461 eepro100_write1(s, SCBIntmask, val >> 8);
1462 break;
1463 case SCBeeprom:
1464 eepro100_write_eeprom(s->eeprom, val);
1465 break;
1466 default:
1467 logout("addr=%s val=0x%04x\n", regname(addr), val);
1468 missing("unknown word write");
1469 }
1470}
1471
1472static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1473{
1474 if (addr <= sizeof(s->mem) - sizeof(val)) {
1475 memcpy(&s->mem[addr], &val, sizeof(val));
1476 }
1477
1478 switch (addr) {
1479 case SCBPointer:
1480 eepro100_write_pointer(s, val);
1481 break;
1482 case SCBPort:
aac443e6 1483 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1484 eepro100_write_port(s, val);
1485 break;
1486 case SCBCtrlMDI:
1487 eepro100_write_mdi(s, val);
1488 break;
1489 default:
1490 logout("addr=%s val=0x%08x\n", regname(addr), val);
1491 missing("unknown longword write");
1492 }
1493}
1494
aac443e6
SW		 1495/*****************************************************************************
1496 *
1497 * Port mapped I/O.
1498 *
1499 ****************************************************************************/
1500
663e8e51
TS		 1501static uint32_t ioport_read1(void *opaque, uint32_t addr)
1502{
1503 EEPRO100State *s = opaque;
1504 //~ logout("addr=%s\n", regname(addr));
1505 return eepro100_read1(s, addr - s->region[1]);
1506}
1507
1508static uint32_t ioport_read2(void *opaque, uint32_t addr)
1509{
1510 EEPRO100State *s = opaque;
1511 return eepro100_read2(s, addr - s->region[1]);
1512}
1513
1514static uint32_t ioport_read4(void *opaque, uint32_t addr)
1515{
1516 EEPRO100State *s = opaque;
1517 return eepro100_read4(s, addr - s->region[1]);
1518}
1519
1520static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1521{
1522 EEPRO100State *s = opaque;
1523 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1524 eepro100_write1(s, addr - s->region[1], val);
1525}
1526
1527static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1528{
1529 EEPRO100State *s = opaque;
1530 eepro100_write2(s, addr - s->region[1], val);
1531}
1532
1533static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1534{
1535 EEPRO100State *s = opaque;
1536 eepro100_write4(s, addr - s->region[1], val);
1537}
1538
1539/***********************************************************/
1540/* PCI EEPRO100 definitions */
1541
663e8e51 1542static void pci_map(PCIDevice * pci_dev, int region_num,
6e355d90 1543 pcibus_t addr, pcibus_t size, int type)
663e8e51 1544{
273a2142 1545 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
663e8e51 1546
89e8b13c
IY		 1547 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1548 "size=0x%08"FMT_PCIBUS", type=%d\n",
aac443e6 1549 region_num, addr, size, type));
663e8e51
TS		 1550
1551 assert(region_num == 1);
1552 register_ioport_write(addr, size, 1, ioport_write1, s);
1553 register_ioport_read(addr, size, 1, ioport_read1, s);
1554 register_ioport_write(addr, size, 2, ioport_write2, s);
1555 register_ioport_read(addr, size, 2, ioport_read2, s);
1556 register_ioport_write(addr, size, 4, ioport_write4, s);
1557 register_ioport_read(addr, size, 4, ioport_read4, s);
1558
1559 s->region[region_num] = addr;
1560}
1561
aac443e6
SW		 1562/*****************************************************************************
1563 *
1564 * Memory mapped I/O.
1565 *
1566 ****************************************************************************/
1567
c227f099 1568static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
663e8e51
TS		 1569{
1570 EEPRO100State *s = opaque;
663e8e51
TS		 1571 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1572 eepro100_write1(s, addr, val);
1573}
1574
c227f099 1575static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
663e8e51
TS		 1576{
1577 EEPRO100State *s = opaque;
663e8e51
TS		 1578 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1579 eepro100_write2(s, addr, val);
1580}
1581
c227f099 1582static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
663e8e51
TS		 1583{
1584 EEPRO100State *s = opaque;
663e8e51
TS		 1585 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1586 eepro100_write4(s, addr, val);
1587}
1588
c227f099 1589static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
663e8e51
TS		 1590{
1591 EEPRO100State *s = opaque;
663e8e51
TS		 1592 //~ logout("addr=%s\n", regname(addr));
1593 return eepro100_read1(s, addr);
1594}
1595
c227f099 1596static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
663e8e51
TS		 1597{
1598 EEPRO100State *s = opaque;
663e8e51
TS		 1599 //~ logout("addr=%s\n", regname(addr));
1600 return eepro100_read2(s, addr);
1601}
1602
c227f099 1603static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
663e8e51
TS		 1604{
1605 EEPRO100State *s = opaque;
663e8e51
TS		 1606 //~ logout("addr=%s\n", regname(addr));
1607 return eepro100_read4(s, addr);
1608}
1609
d60efc6b 1610static CPUWriteMemoryFunc * const pci_mmio_write[] = {
663e8e51
TS		 1611 pci_mmio_writeb,
1612 pci_mmio_writew,
1613 pci_mmio_writel
1614};
1615
d60efc6b 1616static CPUReadMemoryFunc * const pci_mmio_read[] = {
663e8e51
TS		 1617 pci_mmio_readb,
1618 pci_mmio_readw,
1619 pci_mmio_readl
1620};
1621
1622static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
6e355d90 1623 pcibus_t addr, pcibus_t size, int type)
663e8e51 1624{
273a2142 1625 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
663e8e51 1626
89e8b13c
IY		 1627 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1628 "size=0x%08"FMT_PCIBUS", type=%d\n",
aac443e6 1629 region_num, addr, size, type));
663e8e51
TS		 1630
1631 if (region_num == 0) {
1632 /* Map control / status registers. */
273a2142
JQ		 1633 cpu_register_physical_memory(addr, size, s->mmio_index);
1634 s->region[region_num] = addr;
663e8e51
TS		 1635 }
1636}
1637
e00e365e 1638static int nic_can_receive(VLANClientState *nc)
663e8e51 1639{
e00e365e 1640 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
aac443e6 1641 TRACE(RXTX, logout("%p\n", s));
663e8e51
TS		 1642 return get_ru_state(s) == ru_ready;
1643 //~ return !eepro100_buffer_full(s);
1644}
1645
e00e365e 1646static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
663e8e51
TS		 1647{
1648 /* TODO:
1649 * - Magic packets should set bit 30 in power management driver register.
1650 * - Interesting packets should set bit 29 in power management driver register.
1651 */
e00e365e 1652 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
663e8e51
TS		 1653 uint16_t rfd_status = 0xa000;
1654 static const uint8_t broadcast_macaddr[6] =
1655 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1656
1657 /* TODO: check multiple IA bit. */
7f1e9d4e
KW		 1658 if (s->configuration[20] & BIT(6)) {
1659 missing("Multiple IA bit");
1660 return -1;
1661 }
663e8e51
TS		 1662
1663 if (s->configuration[8] & 0x80) {
1664 /* CSMA is disabled. */
1665 logout("%p received while CSMA is disabled\n", s);
4f1c942b 1666 return -1;
663e8e51
TS		 1667 } else if (size < 64 && (s->configuration[7] & 1)) {
1668 /* Short frame and configuration byte 7/0 (discard short receive) set:
1669 * Short frame is discarded */
067d01de 1670 logout("%p received short frame (%zu byte)\n", s, size);
663e8e51 1671 s->statistics.rx_short_frame_errors++;
4f1c942b 1672 //~ return -1;
663e8e51
TS		 1673 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) {
1674 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1675 * Long frames are discarded. */
067d01de 1676 logout("%p received long frame (%zu byte), ignored\n", s, size);
4f1c942b 1677 return -1;
508ef936 1678 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!!
663e8e51
TS		 1679 /* Frame matches individual address. */
1680 /* TODO: check configuration byte 15/4 (ignore U/L). */
067d01de 1681 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
663e8e51
TS		 1682 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1683 /* Broadcast frame. */
067d01de 1684 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
663e8e51 1685 rfd_status |= 0x0002;
7b8737de 1686 } else if (buf[0] & 0x01) {
663e8e51 1687 /* Multicast frame. */
7b8737de 1688 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
7f1e9d4e 1689 if (s->configuration[21] & BIT(3)) {
7b8737de
SW		 1690 /* Multicast all bit is set, receive all multicast frames. */
1691 } else {
1692 unsigned mcast_idx = compute_mcast_idx(buf);
1693 assert(mcast_idx < 64);
1694 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1695 /* Multicast frame is allowed in hash table. */
1696 } else if (s->configuration[15] & 1) {
1697 /* Promiscuous: receive all. */
1698 rfd_status |= 0x0004;
1699 } else {
1700 TRACE(RXTX, logout("%p multicast ignored\n", s));
1701 return -1;
1702 }
663e8e51 1703 }
7b8737de 1704 /* TODO: Next not for promiscuous mode? */
663e8e51
TS		 1705 rfd_status |= 0x0002;
1706 } else if (s->configuration[15] & 1) {
1707 /* Promiscuous: receive all. */
067d01de 1708 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
663e8e51
TS		 1709 rfd_status |= 0x0004;
1710 } else {
067d01de 1711 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
aac443e6 1712 nic_dump(buf, size)));
4f1c942b 1713 return size;
663e8e51
TS		 1714 }
1715
1716 if (get_ru_state(s) != ru_ready) {
aac443e6
SW		 1717 /* No resources available. */
1718 logout("no resources, state=%u\n", get_ru_state(s));
663e8e51 1719 s->statistics.rx_resource_errors++;
aac443e6 1720 //~ assert(!"no resources");
4f1c942b 1721 return -1;
663e8e51
TS		 1722 }
1723 //~ !!!
1724//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
c227f099 1725 eepro100_rx_t rx;
663e8e51 1726 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
c227f099 1727 offsetof(eepro100_rx_t, packet));
663e8e51
TS		 1728 uint16_t rfd_command = le16_to_cpu(rx.command);
1729 uint16_t rfd_size = le16_to_cpu(rx.size);
7f1e9d4e
KW		 1730
1731 if (size > rfd_size) {
1732 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1733 "(%zu bytes); data truncated\n", rfd_size, size);
1734 size = rfd_size;
1735 }
663e8e51
TS		 1736 if (size < 64) {
1737 rfd_status |= 0x0080;
1738 }
aac443e6
SW		 1739 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1740 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
c227f099 1741 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
663e8e51 1742 rfd_status);
c227f099 1743 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
663e8e51
TS		 1744 /* Early receive interrupt not supported. */
1745 //~ eepro100_er_interrupt(s);
1746 /* Receive CRC Transfer not supported. */
7f1e9d4e
KW		 1747 if (s->configuration[18] & 4) {
1748 missing("Receive CRC Transfer");
1749 return -1;
1750 }
663e8e51
TS		 1751 /* TODO: check stripping enable bit. */
1752 //~ assert(!(s->configuration[17] & 1));
1753 cpu_physical_memory_write(s->ru_base + s->ru_offset +
c227f099 1754 offsetof(eepro100_rx_t, packet), buf, size);
663e8e51
TS		 1755 s->statistics.rx_good_frames++;
1756 eepro100_fr_interrupt(s);
1757 s->ru_offset = le32_to_cpu(rx.link);
1758 if (rfd_command & 0x8000) {
1759 /* EL bit is set, so this was the last frame. */
7f1e9d4e
KW		 1760 logout("receive: Running out of frames\n");
1761 set_ru_state(s, ru_suspended);
663e8e51
TS		 1762 }
1763 if (rfd_command & 0x4000) {
1764 /* S bit is set. */
1765 set_ru_state(s, ru_suspended);
1766 }
4f1c942b 1767 return size;
663e8e51
TS		 1768}
1769
151b2986
JQ		 1770static const VMStateDescription vmstate_eepro100 = {
1771 .version_id = 3,
1772 .minimum_version_id = 2,
1773 .minimum_version_id_old = 2,
1774 .fields = (VMStateField []) {
1775 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1776 VMSTATE_UNUSED(32),
1777 VMSTATE_BUFFER(mult, EEPRO100State),
1778 VMSTATE_BUFFER(mem, EEPRO100State),
1779 /* Save all members of struct between scb_stat and mem. */
1780 VMSTATE_UINT8(scb_stat, EEPRO100State),
1781 VMSTATE_UINT8(int_stat, EEPRO100State),
1782 VMSTATE_UNUSED(3*4),
1783 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1784 VMSTATE_UNUSED(19*4),
1785 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1786 /* The eeprom should be saved and restored by its own routines. */
1787 VMSTATE_UINT32(device, EEPRO100State),
1788 /* TODO check device. */
1789 VMSTATE_UINT32(pointer, EEPRO100State),
1790 VMSTATE_UINT32(cu_base, EEPRO100State),
1791 VMSTATE_UINT32(cu_offset, EEPRO100State),
1792 VMSTATE_UINT32(ru_base, EEPRO100State),
1793 VMSTATE_UINT32(ru_offset, EEPRO100State),
1794 VMSTATE_UINT32(statsaddr, EEPRO100State),
ba42b646 1795 /* Save eepro100_stats_t statistics. */
151b2986
JQ		 1796 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1797 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1798 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1799 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1800 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1801 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1802 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1803 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1804 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1805 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1806 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1807 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1808 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1809 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1810 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1811 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1812 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1813 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1814 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1815 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1816 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
2657c663 1817#if 0
151b2986 1818 VMSTATE_UINT16(status, EEPRO100State),
2657c663 1819#endif
151b2986
JQ		 1820 /* Configuration bytes. */
1821 VMSTATE_BUFFER(configuration, EEPRO100State),
1822 VMSTATE_END_OF_LIST()
aac443e6 1823 }
151b2986 1824};
663e8e51 1825
e00e365e 1826static void nic_cleanup(VLANClientState *nc)
b946a153 1827{
e00e365e 1828 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 1829
e00e365e 1830 s->nic = NULL;
b946a153
AL		 1831}
1832
c4c270e2 1833static int pci_nic_uninit(PCIDevice *pci_dev)
b946a153 1834{
c4c270e2 1835 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
b946a153
AL		 1836
1837 cpu_unregister_io_memory(s->mmio_index);
151b2986 1838 vmstate_unregister(s->vmstate, s);
508ef936 1839 eeprom93xx_free(s->eeprom);
e00e365e 1840 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 1841 return 0;
1842}
1843
e00e365e
MM		 1844static NetClientInfo net_eepro100_info = {
1845 .type = NET_CLIENT_TYPE_NIC,
1846 .size = sizeof(NICState),
1847 .can_receive = nic_can_receive,
1848 .receive = nic_receive,
1849 .cleanup = nic_cleanup,
1850};
1851
81a322d4 1852static int nic_init(PCIDevice *pci_dev, uint32_t device)
663e8e51 1853{
273a2142 1854 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
663e8e51 1855
aac443e6 1856 TRACE(OTHER, logout("\n"));
663e8e51 1857
663e8e51 1858 s->device = device;
663e8e51
TS		 1859
1860 pci_reset(s);
1861
1862 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1863 * i82559 and later support 64 or 256 word EEPROM. */
1864 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1865
1866 /* Handler for memory-mapped I/O */
273a2142 1867 s->mmio_index =
1eed09cb 1868 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
663e8e51 1869
273a2142 1870 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
0392a017
IY		 1871 PCI_BASE_ADDRESS_SPACE_MEMORY |
1872 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1873 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
663e8e51 1874 pci_map);
0392a017 1875 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
663e8e51
TS		 1876 pci_mmio_map);
1877
508ef936 1878 qemu_macaddr_default_if_unset(&s->conf.macaddr);
ce0e58b3 1879 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
663e8e51
TS		 1880 assert(s->region[1] == 0);
1881
1882 nic_reset(s);
1883
e00e365e
MM		 1884 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1885 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
663e8e51 1886
e00e365e
MM		 1887 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1888 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
663e8e51 1889
a08d4367 1890 qemu_register_reset(nic_reset, s);
663e8e51 1891
151b2986
JQ		 1892 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1893 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
e00e365e 1894 s->vmstate->name = s->nic->nc.model;
151b2986 1895 vmstate_register(-1, s->vmstate, s);
4e9df06a 1896
81a322d4 1897 return 0;
663e8e51
TS		 1898}
1899
c4c270e2
SW		 1900static int pci_i82550_init(PCIDevice *pci_dev)
1901{
1902 return nic_init(pci_dev, i82550);
1903}
1904
1905static int pci_i82551_init(PCIDevice *pci_dev)
1906{
1907 return nic_init(pci_dev, i82551);
1908}
1909
1910static int pci_i82557a_init(PCIDevice *pci_dev)
1911{
1912 return nic_init(pci_dev, i82557A);
1913}
1914
1915static int pci_i82557b_init(PCIDevice *pci_dev)
1916{
1917 return nic_init(pci_dev, i82557B);
1918}
1919
1920static int pci_i82557c_init(PCIDevice *pci_dev)
1921{
1922 return nic_init(pci_dev, i82557C);
1923}
1924
1925static int pci_i82558a_init(PCIDevice *pci_dev)
1926{
1927 return nic_init(pci_dev, i82558A);
1928}
1929
1930static int pci_i82558b_init(PCIDevice *pci_dev)
1931{
1932 return nic_init(pci_dev, i82558B);
1933}
1934
1935static int pci_i82559a_init(PCIDevice *pci_dev)
1936{
1937 return nic_init(pci_dev, i82559A);
1938}
1939
1940static int pci_i82559b_init(PCIDevice *pci_dev)
1941{
1942 return nic_init(pci_dev, i82559B);
1943}
1944
1945static int pci_i82559c_init(PCIDevice *pci_dev)
9d07d757 1946{
c4c270e2 1947 return nic_init(pci_dev, i82559C);
9d07d757
PB		 1948}
1949
c4c270e2 1950static int pci_i82559er_init(PCIDevice *pci_dev)
663e8e51 1951{
c4c270e2 1952 return nic_init(pci_dev, i82559ER);
663e8e51
TS		 1953}
1954
c4c270e2 1955static int pci_i82562_init(PCIDevice *pci_dev)
663e8e51 1956{
c4c270e2 1957 return nic_init(pci_dev, i82562);
663e8e51
TS		 1958}
1959
0aab0d3a
GH		 1960static PCIDeviceInfo eepro100_info[] = {
1961 {
c4c270e2
SW		 1962 .qdev.name = "i82550",
1963 .qdev.size = sizeof(EEPRO100State),
1964 .init = pci_i82550_init,
6a90e308 1965 .exit = pci_nic_uninit,
508ef936
GH		 1966 .qdev.props = (Property[]) {
1967 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1968 DEFINE_PROP_END_OF_LIST(),
1969 },
c4c270e2 1970 },{
0aab0d3a 1971 .qdev.name = "i82551",
273a2142 1972 .qdev.size = sizeof(EEPRO100State),
0aab0d3a 1973 .init = pci_i82551_init,
e3936fa5 1974 .exit = pci_nic_uninit,
508ef936
GH		 1975 .qdev.props = (Property[]) {
1976 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1977 DEFINE_PROP_END_OF_LIST(),
1978 },
c4c270e2
SW		 1979 },{
1980 .qdev.name = "i82557a",
1981 .qdev.size = sizeof(EEPRO100State),
1982 .init = pci_i82557a_init,
6a90e308 1983 .exit = pci_nic_uninit,
508ef936
GH		 1984 .qdev.props = (Property[]) {
1985 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1986 DEFINE_PROP_END_OF_LIST(),
1987 },
0aab0d3a
GH		 1988 },{
1989 .qdev.name = "i82557b",
273a2142 1990 .qdev.size = sizeof(EEPRO100State),
0aab0d3a 1991 .init = pci_i82557b_init,
e3936fa5 1992 .exit = pci_nic_uninit,
508ef936
GH		 1993 .qdev.props = (Property[]) {
1994 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1995 DEFINE_PROP_END_OF_LIST(),
1996 },
c4c270e2
SW		 1997 },{
1998 .qdev.name = "i82557c",
1999 .qdev.size = sizeof(EEPRO100State),
2000 .init = pci_i82557c_init,
6a90e308 2001 .exit = pci_nic_uninit,
508ef936
GH		 2002 .qdev.props = (Property[]) {
2003 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2004 DEFINE_PROP_END_OF_LIST(),
2005 },
c4c270e2
SW		 2006 },{
2007 .qdev.name = "i82558a",
2008 .qdev.size = sizeof(EEPRO100State),
2009 .init = pci_i82558a_init,
6a90e308 2010 .exit = pci_nic_uninit,
508ef936
GH		 2011 .qdev.props = (Property[]) {
2012 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2013 DEFINE_PROP_END_OF_LIST(),
2014 },
c4c270e2
SW		 2015 },{
2016 .qdev.name = "i82558b",
2017 .qdev.size = sizeof(EEPRO100State),
2018 .init = pci_i82558b_init,
6a90e308 2019 .exit = pci_nic_uninit,
508ef936
GH		 2020 .qdev.props = (Property[]) {
2021 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2022 DEFINE_PROP_END_OF_LIST(),
2023 },
c4c270e2
SW		 2024 },{
2025 .qdev.name = "i82559a",
2026 .qdev.size = sizeof(EEPRO100State),
2027 .init = pci_i82559a_init,
6a90e308 2028 .exit = pci_nic_uninit,
508ef936
GH		 2029 .qdev.props = (Property[]) {
2030 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2031 DEFINE_PROP_END_OF_LIST(),
2032 },
c4c270e2
SW		 2033 },{
2034 .qdev.name = "i82559b",
2035 .qdev.size = sizeof(EEPRO100State),
2036 .init = pci_i82559b_init,
6a90e308 2037 .exit = pci_nic_uninit,
508ef936
GH		 2038 .qdev.props = (Property[]) {
2039 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2040 DEFINE_PROP_END_OF_LIST(),
2041 },
c4c270e2
SW		 2042 },{
2043 .qdev.name = "i82559c",
2044 .qdev.size = sizeof(EEPRO100State),
2045 .init = pci_i82559c_init,
6a90e308 2046 .exit = pci_nic_uninit,
508ef936
GH		 2047 .qdev.props = (Property[]) {
2048 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2049 DEFINE_PROP_END_OF_LIST(),
2050 },
0aab0d3a
GH		 2051 },{
2052 .qdev.name = "i82559er",
273a2142 2053 .qdev.size = sizeof(EEPRO100State),
0aab0d3a 2054 .init = pci_i82559er_init,
e3936fa5 2055 .exit = pci_nic_uninit,
938a6324 2056 .romfile = "pxe-i82559er.bin",
508ef936
GH		 2057 .qdev.props = (Property[]) {
2058 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2059 DEFINE_PROP_END_OF_LIST(),
2060 },
c4c270e2
SW		 2061 },{
2062 .qdev.name = "i82562",
2063 .qdev.size = sizeof(EEPRO100State),
2064 .init = pci_i82562_init,
6a90e308 2065 .exit = pci_nic_uninit,
508ef936
GH		 2066 .qdev.props = (Property[]) {
2067 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2068 DEFINE_PROP_END_OF_LIST(),
2069 },
0aab0d3a
GH		 2070 },{
2071 /* end of list */
2072 }
2073};
2074
9d07d757 2075static void eepro100_register_devices(void)
663e8e51 2076{
0aab0d3a 2077 pci_qdev_register_many(eepro100_info);
663e8e51
TS		 2078}
2079
9d07d757 2080device_init(eepro100_register_devices)
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