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eepro100: Restructure code (new function tx_command)
[mirror_qemu.git] / hw / eepro100.c
CommitLineData
663e8e51
TS		 1/*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (c) 2006-2007 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
8167ee88 20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
663e8e51
TS		 21 *
22 * Tested features (i82559):
23 * PXE boot (i386) no valid link
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 */
35
36#if defined(TARGET_I386)
37# warning "PXE boot still not working!"
38#endif
39
663e8e51 40#include <stddef.h> /* offsetof */
b84a5c6f 41#include <stdbool.h>
87ecb68b
PB		 42#include "hw.h"
43#include "pci.h"
44#include "net.h"
663e8e51
TS		 45#include "eeprom93xx.h"
46
47/* Common declarations for all PCI devices. */
48
663e8e51
TS		 49#define PCI_CONFIG_8(offset, value) \
50 (pci_conf[offset] = (value))
51#define PCI_CONFIG_16(offset, value) \
52 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
53#define PCI_CONFIG_32(offset, value) \
54 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
55
56#define KiB 1024
57
aac443e6 58/* Debug EEPRO100 card. */
663e8e51
TS		 59//~ #define DEBUG_EEPRO100
60
61#ifdef DEBUG_EEPRO100
001faf32 62#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
663e8e51 63#else
001faf32 64#define logout(fmt, ...) ((void)0)
663e8e51
TS		 65#endif
66
67/* Set flags to 0 to disable debug output. */
aac443e6
SW		 68#define INT 1 /* interrupt related actions */
69#define MDI 1 /* mdi related actions */
70#define OTHER 1
71#define RXTX 1
72#define EEPROM 1 /* eeprom related actions */
663e8e51
TS		 73
74#define TRACE(flag, command) ((flag) ? (command) : (void)0)
75
7f1e9d4e 76#define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
663e8e51
TS		 77
78#define MAX_ETH_FRAME_SIZE 1514
79
80/* This driver supports several different devices which are declared here. */
c4c270e2 81#define i82550 0x82550
663e8e51 82#define i82551 0x82551
c4c270e2 83#define i82557A 0x82557a
663e8e51
TS		 84#define i82557B 0x82557b
85#define i82557C 0x82557c
c4c270e2 86#define i82558A 0x82558a
663e8e51 87#define i82558B 0x82558b
c4c270e2
SW		 88#define i82559A 0x82559a
89#define i82559B 0x82559b
663e8e51
TS		 90#define i82559C 0x82559c
91#define i82559ER 0x82559e
92#define i82562 0x82562
93
aac443e6 94/* Use 64 word EEPROM. TODO: could be a runtime option. */
663e8e51
TS		 95#define EEPROM_SIZE 64
96
97#define PCI_MEM_SIZE (4 * KiB)
98#define PCI_IO_SIZE 64
99#define PCI_FLASH_SIZE (128 * KiB)
100
101#define BIT(n) (1 << (n))
102#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
103
104/* The SCB accepts the following controls for the Tx and Rx units: */
105#define CU_NOP 0x0000 /* No operation. */
106#define CU_START 0x0010 /* CU start. */
107#define CU_RESUME 0x0020 /* CU resume. */
108#define CU_STATSADDR 0x0040 /* Load dump counters address. */
109#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
110#define CU_CMD_BASE 0x0060 /* Load CU base address. */
111#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
112#define CU_SRESUME 0x00a0 /* CU static resume. */
113
114#define RU_NOP 0x0000
115#define RX_START 0x0001
116#define RX_RESUME 0x0002
117#define RX_ABORT 0x0004
118#define RX_ADDR_LOAD 0x0006
119#define RX_RESUMENR 0x0007
120#define INT_MASK 0x0100
121#define DRVR_INT 0x0200 /* Driver generated interrupt. */
122
663e8e51
TS		 123/* Offsets to the various registers.
124 All accesses need not be longword aligned. */
125enum speedo_offsets {
126 SCBStatus = 0,
127 SCBAck = 1,
128 SCBCmd = 2, /* Rx/Command Unit command and status. */
129 SCBIntmask = 3,
130 SCBPointer = 4, /* General purpose pointer. */
131 SCBPort = 8, /* Misc. commands and operands. */
132 SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
133 SCBCtrlMDI = 16, /* MDI interface control. */
134 SCBEarlyRx = 20, /* Early receive byte count. */
3257d2b6 135 SCBFlow = 24,
663e8e51
TS		 136};
137
138/* A speedo3 transmit buffer descriptor with two buffers... */
139typedef struct {
140 uint16_t status;
141 uint16_t command;
142 uint32_t link; /* void * */
143 uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */
144 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
145 uint8_t tx_threshold; /* transmit threshold */
146 uint8_t tbd_count; /* TBD number */
147 //~ /* This constitutes two "TBD" entries: hdr and data */
148 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
149 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
150 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
151 //~ int32_t tx_buf_size1; /* Length of Tx data. */
c227f099 152} eepro100_tx_t;
663e8e51
TS		 153
154/* Receive frame descriptor. */
155typedef struct {
156 int16_t status;
157 uint16_t command;
158 uint32_t link; /* struct RxFD * */
159 uint32_t rx_buf_addr; /* void * */
160 uint16_t count;
161 uint16_t size;
162 char packet[MAX_ETH_FRAME_SIZE + 4];
c227f099 163} eepro100_rx_t;
663e8e51
TS		 164
165typedef struct {
166 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
167 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
168 tx_multiple_collisions, tx_total_collisions;
169 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
170 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
171 rx_short_frame_errors;
172 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
173 uint16_t xmt_tco_frames, rcv_tco_frames;
ba42b646
SW		 174 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
175 uint32_t reserved[4];
c227f099 176} eepro100_stats_t;
663e8e51
TS		 177
178typedef enum {
179 cu_idle = 0,
180 cu_suspended = 1,
181 cu_active = 2,
182 cu_lpq_active = 2,
183 cu_hqp_active = 3
c227f099 184} cu_state_t;
663e8e51
TS		 185
186typedef enum {
187 ru_idle = 0,
188 ru_suspended = 1,
189 ru_no_resources = 2,
190 ru_ready = 4
c227f099 191} ru_state_t;
663e8e51 192
663e8e51 193typedef struct {
273a2142 194 PCIDevice dev;
663e8e51
TS		 195 uint8_t mult[8]; /* multicast mask array */
196 int mmio_index;
e00e365e 197 NICState *nic;
508ef936 198 NICConf conf;
663e8e51
TS		 199 uint8_t scb_stat; /* SCB stat/ack byte */
200 uint8_t int_stat; /* PCI interrupt status */
3706c43f 201 /* region must not be saved by nic_save. */
663e8e51 202 uint32_t region[3]; /* PCI region addresses */
663e8e51 203 uint16_t mdimem[32];
c227f099 204 eeprom_t *eeprom;
663e8e51
TS		 205 uint32_t device; /* device variant */
206 uint32_t pointer;
207 /* (cu_base + cu_offset) address the next command block in the command block list. */
208 uint32_t cu_base; /* CU base address */
209 uint32_t cu_offset; /* CU address offset */
210 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
211 uint32_t ru_base; /* RU base address */
212 uint32_t ru_offset; /* RU address offset */
c227f099 213 uint32_t statsaddr; /* pointer to eepro100_stats_t */
ba42b646 214
f3a52e50
SW		 215 /* Temporary status information (no need to save these values),
216 * used while processing CU commands. */
217 eepro100_tx_t tx; /* transmit buffer descriptor */
218 uint32_t cb_address; /* = cu_base + cu_offset */
219
ba42b646
SW		 220 /* Statistical counters. Also used for wake-up packet (i82559). */
221 eepro100_stats_t statistics;
222
663e8e51
TS		 223#if 0
224 uint16_t status;
225#endif
226
227 /* Configuration bytes. */
228 uint8_t configuration[22];
229
230 /* Data in mem is always in the byte order of the controller (le). */
231 uint8_t mem[PCI_MEM_SIZE];
151b2986
JQ		 232 /* vmstate for each particular nic */
233 VMStateDescription *vmstate;
ba42b646
SW		 234
235 /* Quasi static device properties (no need to save them). */
236 uint16_t stats_size;
237 bool has_extended_tcb_support;
663e8e51
TS		 238} EEPRO100State;
239
240/* Default values for MDI (PHY) registers */
241static const uint16_t eepro100_mdi_default[] = {
242 /* MDI Registers 0 - 6, 7 */
243 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
244 /* MDI Registers 8 - 15 */
245 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
246 /* MDI Registers 16 - 31 */
247 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
248 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
249};
250
251/* Readonly mask for MDI (PHY) registers */
252static const uint16_t eepro100_mdi_mask[] = {
253 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
254 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
255 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
256 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
257};
258
ba42b646
SW		 259/* XXX: optimize */
260static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
261{
262 val = cpu_to_le32(val);
263 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
264}
265
663e8e51
TS		 266#define POLYNOMIAL 0x04c11db6
267
268/* From FreeBSD */
269/* XXX: optimize */
270static int compute_mcast_idx(const uint8_t * ep)
271{
272 uint32_t crc;
273 int carry, i, j;
274 uint8_t b;
275
276 crc = 0xffffffff;
277 for (i = 0; i < 6; i++) {
278 b = *ep++;
279 for (j = 0; j < 8; j++) {
280 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
281 crc <<= 1;
282 b >>= 1;
aac443e6 283 if (carry) {
663e8e51 284 crc = ((crc ^ POLYNOMIAL) | carry);
aac443e6 285 }
663e8e51
TS		 286 }
287 }
288 return (crc >> 26);
289}
290
291#if defined(DEBUG_EEPRO100)
292static const char *nic_dump(const uint8_t * buf, unsigned size)
293{
294 static char dump[3 * 16 + 1];
295 char *p = &dump[0];
aac443e6 296 if (size > 16) {
663e8e51 297 size = 16;
aac443e6 298 }
663e8e51
TS		 299 while (size-- > 0) {
300 p += sprintf(p, " %02x", *buf++);
301 }
302 return dump;
303}
304#endif /* DEBUG_EEPRO100 */
305
306enum scb_stat_ack {
307 stat_ack_not_ours = 0x00,
308 stat_ack_sw_gen = 0x04,
309 stat_ack_rnr = 0x10,
310 stat_ack_cu_idle = 0x20,
311 stat_ack_frame_rx = 0x40,
312 stat_ack_cu_cmd_done = 0x80,
313 stat_ack_not_present = 0xFF,
314 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
315 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
316};
317
318static void disable_interrupt(EEPRO100State * s)
319{
320 if (s->int_stat) {
aac443e6 321 TRACE(INT, logout("interrupt disabled\n"));
273a2142 322 qemu_irq_lower(s->dev.irq[0]);
663e8e51
TS		 323 s->int_stat = 0;
324 }
325}
326
327static void enable_interrupt(EEPRO100State * s)
328{
329 if (!s->int_stat) {
aac443e6 330 TRACE(INT, logout("interrupt enabled\n"));
273a2142 331 qemu_irq_raise(s->dev.irq[0]);
663e8e51
TS		 332 s->int_stat = 1;
333 }
334}
335
336static void eepro100_acknowledge(EEPRO100State * s)
337{
338 s->scb_stat &= ~s->mem[SCBAck];
339 s->mem[SCBAck] = s->scb_stat;
340 if (s->scb_stat == 0) {
341 disable_interrupt(s);
342 }
343}
344
345static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
346{
347 uint8_t mask = ~s->mem[SCBIntmask];
348 s->mem[SCBAck] |= stat;
349 stat = s->scb_stat = s->mem[SCBAck];
350 stat &= (mask | 0x0f);
351 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
352 if (stat && (mask & 0x01)) {
353 /* SCB mask and SCB Bit M do not disable interrupt. */
354 enable_interrupt(s);
355 } else if (s->int_stat) {
356 disable_interrupt(s);
357 }
358}
359
360static void eepro100_cx_interrupt(EEPRO100State * s)
361{
362 /* CU completed action command. */
363 /* Transmit not ok (82557 only, not in emulation). */
364 eepro100_interrupt(s, 0x80);
365}
366
367static void eepro100_cna_interrupt(EEPRO100State * s)
368{
369 /* CU left the active state. */
370 eepro100_interrupt(s, 0x20);
371}
372
373static void eepro100_fr_interrupt(EEPRO100State * s)
374{
375 /* RU received a complete frame. */
376 eepro100_interrupt(s, 0x40);
377}
378
379#if 0
380static void eepro100_rnr_interrupt(EEPRO100State * s)
381{
382 /* RU is not ready. */
383 eepro100_interrupt(s, 0x10);
384}
385#endif
386
387static void eepro100_mdi_interrupt(EEPRO100State * s)
388{
389 /* MDI completed read or write cycle. */
390 eepro100_interrupt(s, 0x08);
391}
392
393static void eepro100_swi_interrupt(EEPRO100State * s)
394{
395 /* Software has requested an interrupt. */
396 eepro100_interrupt(s, 0x04);
397}
398
399#if 0
400static void eepro100_fcp_interrupt(EEPRO100State * s)
401{
402 /* Flow control pause interrupt (82558 and later). */
403 eepro100_interrupt(s, 0x01);
404}
405#endif
406
407static void pci_reset(EEPRO100State * s)
408{
409 uint32_t device = s->device;
273a2142 410 uint8_t *pci_conf = s->dev.config;
ba42b646 411 bool power_management = 1;
663e8e51 412
aac443e6 413 TRACE(OTHER, logout("%p\n", s));
663e8e51
TS		 414
415 /* PCI Vendor ID */
deb54399 416 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
d6fd1e66 417 /* PCI Device ID depends on device and is set below. */
663e8e51 418 /* PCI Command */
508cc6b4 419 /* TODO: this is the default, do not override. */
663e8e51
TS		 420 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
421 /* PCI Status */
508cc6b4 422 /* TODO: Value at RST# should be 0. */
61702408 423 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
663e8e51
TS		 424 /* PCI Revision ID */
425 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
508cc6b4 426 /* TODO: this is the default, do not override. */
663e8e51 427 /* PCI Class Code */
508cc6b4 428 PCI_CONFIG_8(PCI_CLASS_PROG, 0x00);
173a543b 429 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
663e8e51
TS		 430 /* PCI Cache Line Size */
431 /* check cache line size!!! */
432 //~ PCI_CONFIG_8(0x0c, 0x00);
433 /* PCI Latency Timer */
508cc6b4 434 PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks
663e8e51
TS		 435 /* PCI Header Type */
436 /* BIST (built-in self test) */
437#if defined(TARGET_I386)
438// !!! workaround for buggy bios
0392a017 439//~ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0
663e8e51
TS		 440#endif
441#if 0
442 /* PCI Base Address Registers */
443 /* CSR Memory Mapped Base Address */
444 PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
0392a017
IY		 445 PCI_BASE_ADDRESS_SPACE_MEMORY |
446 PCI_BASE_ADDRESS_MEM_PREFETCH);
663e8e51 447 /* CSR I/O Mapped Base Address */
0392a017 448 PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_SPACE_IO);
663e8e51
TS		 449#if 0
450 /* Flash Memory Mapped Base Address */
0392a017
IY		 451 PCI_CONFIG_32(PCI_BASE_ADDRESS_2,
452 0xfffe0000 | PCI_BASE_ADDRESS_SPACE_MEMORY);
663e8e51
TS		 453#endif
454#endif
455 /* Expansion ROM Base Address (depends on boot disable!!!) */
508cc6b4
MT		 456 /* TODO: not needed, set when BAR is registered */
457 PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY);
663e8e51 458 /* Capability Pointer */
508cc6b4
MT		 459 /* TODO: revisions with power_management 1 use this but
460 * do not set new capability list bit in status register. */
461 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc);
aac443e6 462 /* Interrupt Line */
663e8e51 463 /* Interrupt Pin */
508cc6b4
MT		 464 /* TODO: RST# value should be 0 */
465 PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0
663e8e51 466 /* Minimum Grant */
508cc6b4 467 PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
663e8e51 468 /* Maximum Latency */
508cc6b4 469 PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
663e8e51
TS		 470
471 switch (device) {
ba42b646
SW		 472 case i82550:
473 // TODO: check device id.
474 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
475 /* Revision ID: 0x0c, 0x0d, 0x0e. */
476 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
477 // TODO: check size of statistical counters.
478 s->stats_size = 80;
479 // TODO: check extended tcb support.
480 s->has_extended_tcb_support = 1;
481 break;
663e8e51 482 case i82551:
d6fd1e66 483 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
ba42b646 484 /* Revision ID: 0x0f, 0x10. */
663e8e51 485 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
ba42b646
SW		 486 // TODO: check size of statistical counters.
487 s->stats_size = 80;
488 s->has_extended_tcb_support = 1;
489 break;
490 case i82557A:
491 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
492 PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
508cc6b4 493 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
ba42b646 494 power_management = 0;
663e8e51
TS		 495 break;
496 case i82557B:
d6fd1e66 497 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
663e8e51 498 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
508cc6b4 499 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
ba42b646 500 power_management = 0;
663e8e51
TS		 501 break;
502 case i82557C:
d6fd1e66 503 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
663e8e51 504 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
508cc6b4 505 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
ba42b646
SW		 506 power_management = 0;
507 break;
508 case i82558A:
509 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 510 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
511 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
ba42b646
SW		 512 PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
513 s->stats_size = 76;
514 s->has_extended_tcb_support = 1;
663e8e51
TS		 515 break;
516 case i82558B:
d6fd1e66 517 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 518 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
519 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
663e8e51 520 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
ba42b646
SW		 521 s->stats_size = 76;
522 s->has_extended_tcb_support = 1;
523 break;
524 case i82559A:
525 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 526 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
527 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
ba42b646
SW		 528 PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
529 s->stats_size = 80;
530 s->has_extended_tcb_support = 1;
531 break;
532 case i82559B:
533 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 534 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
535 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
ba42b646
SW		 536 PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
537 s->stats_size = 80;
538 s->has_extended_tcb_support = 1;
663e8e51
TS		 539 break;
540 case i82559C:
d6fd1e66 541 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
508cc6b4
MT		 542 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
543 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
ba42b646
SW		 544 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
545 // TODO: Windows wants revision id 0x0c.
546 PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
547#if EEPROM_SIZE > 0
548 PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
549 PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
550#endif
551 s->stats_size = 80;
552 s->has_extended_tcb_support = 1;
663e8e51
TS		 553 break;
554 case i82559ER:
d6fd1e66 555 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
508cc6b4
MT		 556 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
557 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
663e8e51 558 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
ba42b646
SW		 559 s->stats_size = 80;
560 s->has_extended_tcb_support = 1;
561 break;
562 case i82562:
563 // TODO: check device id.
564 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
565 /* TODO: wrong revision id. */
566 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
567 s->stats_size = 80;
568 s->has_extended_tcb_support = 1;
663e8e51 569 break;
663e8e51
TS		 570 default:
571 logout("Device %X is undefined!\n", device);
572 }
573
ba42b646
SW		 574 s->configuration[6] |= BIT(5);
575
576 if (s->stats_size == 80) {
577 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
578 if (s->configuration[6] & BIT(2)) {
579 /* TCO statistical counters. */
580 assert(s->configuration[6] & BIT(5));
581 } else {
582 if (s->configuration[6] & BIT(5)) {
583 /* No extended statistical counters, i82557 compatible. */
584 s->stats_size = 64;
585 } else {
586 /* i82558 compatible. */
587 s->stats_size = 76;
588 }
589 }
590 } else {
591 if (s->configuration[6] & BIT(5)) {
592 /* No extended statistical counters. */
593 s->stats_size = 64;
594 }
595 }
596 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
597
598 if (power_management) {
599 /* Power Management Capabilities */
600 PCI_CONFIG_8(0xdc, 0x01);
601 /* Next Item Pointer */
602 /* Capability ID */
603 PCI_CONFIG_16(0xde, 0x7e21);
604 /* TODO: Power Management Control / Status. */
605 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
606 }
607
608#if EEPROM_SIZE > 0
663e8e51 609 if (device == i82557C || device == i82558B || device == i82559C) {
ba42b646
SW		 610 // TODO: get vendor id from EEPROM for i82557C or later.
611 // TODO: get device id from EEPROM for i82557C or later.
612 // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
613 // TODO: header type is determined by EEPROM for i82559.
614 // TODO: get subsystem id from EEPROM for i82557C or later.
615 // TODO: get subsystem vendor id from EEPROM for i82557C or later.
616 // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
617 // TODO: capability pointer depends on EEPROM for i82558.
663e8e51
TS		 618 logout("Get device id and revision from EEPROM!!!\n");
619 }
ba42b646 620#endif /* EEPROM_SIZE > 0 */
663e8e51
TS		 621}
622
623static void nic_selective_reset(EEPRO100State * s)
624{
625 size_t i;
626 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
627 //~ eeprom93xx_reset(s->eeprom);
508ef936 628 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
663e8e51 629 eeprom_contents[0xa] = 0x4000;
f4e94dfe
RD		 630 if (s->device == i82557B || s->device == i82557C)
631 eeprom_contents[5] = 0x0100;
663e8e51
TS		 632 uint16_t sum = 0;
633 for (i = 0; i < EEPROM_SIZE - 1; i++) {
634 sum += eeprom_contents[i];
635 }
636 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
aac443e6 637 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
663e8e51
TS		 638
639 memset(s->mem, 0, sizeof(s->mem));
640 uint32_t val = BIT(21);
641 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
642
643 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
644 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
645}
646
647static void nic_reset(void *opaque)
648{
769cf7a5 649 EEPRO100State *s = opaque;
aac443e6 650 TRACE(OTHER, logout("%p\n", s));
663e8e51
TS		 651 nic_selective_reset(s);
652}
653
654#if defined(DEBUG_EEPRO100)
b8f6ba0d 655static const char * const e100_reg[PCI_IO_SIZE / 4] = {
663e8e51
TS		 656 "Command/Status",
657 "General Pointer",
658 "Port",
659 "EEPROM/Flash Control",
660 "MDI Control",
661 "Receive DMA Byte Count",
b8f6ba0d 662 "Flow Control",
663e8e51
TS		 663 "General Status/Control"
664};
665
666static char *regname(uint32_t addr)
667{
ec169288 668 static char buf[32];
663e8e51 669 if (addr < PCI_IO_SIZE) {
b8f6ba0d 670 const char *r = e100_reg[addr / 4];
663e8e51 671 if (r != 0) {
41cbc23c 672 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
663e8e51 673 } else {
41cbc23c 674 snprintf(buf, sizeof(buf), "0x%02x", addr);
663e8e51
TS		 675 }
676 } else {
41cbc23c 677 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
663e8e51
TS		 678 }
679 return buf;
680}
681#endif /* DEBUG_EEPRO100 */
682
683#if 0
684static uint16_t eepro100_read_status(EEPRO100State * s)
685{
686 uint16_t val = s->status;
aac443e6 687 TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
TS		 688 return val;
689}
690
691static void eepro100_write_status(EEPRO100State * s, uint16_t val)
692{
aac443e6 693 TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
TS		 694 s->status = val;
695}
696#endif
697
698/*****************************************************************************
699 *
700 * Command emulation.
701 *
702 ****************************************************************************/
703
704#if 0
705static uint16_t eepro100_read_command(EEPRO100State * s)
706{
707 uint16_t val = 0xffff;
aac443e6 708 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
663e8e51
TS		 709 return val;
710}
711#endif
712
713/* Commands that can be put in a command list entry. */
714enum commands {
715 CmdNOp = 0,
716 CmdIASetup = 1,
717 CmdConfigure = 2,
718 CmdMulticastList = 3,
719 CmdTx = 4,
720 CmdTDR = 5, /* load microcode */
721 CmdDump = 6,
722 CmdDiagnose = 7,
723
724 /* And some extra flags: */
725 CmdSuspend = 0x4000, /* Suspend after completion. */
726 CmdIntr = 0x2000, /* Interrupt after completion. */
727 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
728};
729
c227f099 730static cu_state_t get_cu_state(EEPRO100State * s)
663e8e51
TS		 731{
732 return ((s->mem[SCBStatus] >> 6) & 0x03);
733}
734
c227f099 735static void set_cu_state(EEPRO100State * s, cu_state_t state)
663e8e51
TS		 736{
737 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
738}
739
c227f099 740static ru_state_t get_ru_state(EEPRO100State * s)
663e8e51
TS		 741{
742 return ((s->mem[SCBStatus] >> 2) & 0x0f);
743}
744
c227f099 745static void set_ru_state(EEPRO100State * s, ru_state_t state)
663e8e51
TS		 746{
747 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
748}
749
750static void dump_statistics(EEPRO100State * s)
751{
752 /* Dump statistical data. Most data is never changed by the emulation
753 * and always 0, so we first just copy the whole block and then those
754 * values which really matter.
755 * Number of data should check configuration!!!
756 */
ba42b646
SW		 757 cpu_physical_memory_write(s->statsaddr,
758 (uint8_t *) & s->statistics, s->stats_size);
759 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
760 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
761 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
762 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
763 //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
764 //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
663e8e51
TS		 765 //~ missing("CU dump statistical counters");
766}
767
f3a52e50
SW		 768static void tx_command(EEPRO100State *s)
769{
770 uint32_t tbd_array = le32_to_cpu(s->tx.tx_desc_addr);
771 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
772 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
773 uint8_t buf[2600];
774 uint16_t size = 0;
775 uint32_t tbd_address = s->cb_address + 0x10;
776 TRACE(RXTX, logout
777 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
778 tbd_array, tcb_bytes, s->tx.tbd_count));
779
780 if (tcb_bytes > 2600) {
781 logout("TCB byte count too large, using 2600\n");
782 tcb_bytes = 2600;
783 }
784 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
785 logout
786 ("illegal values of TBD array address and TCB byte count!\n");
787 }
788 assert(tcb_bytes <= sizeof(buf));
789 while (size < tcb_bytes) {
790 uint32_t tx_buffer_address = ldl_phys(tbd_address);
791 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
792 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
793 tbd_address += 8;
794 TRACE(RXTX, logout
795 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
796 tx_buffer_address, tx_buffer_size));
797 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
798 cpu_physical_memory_read(tx_buffer_address, &buf[size],
799 tx_buffer_size);
800 size += tx_buffer_size;
801 }
802 if (tbd_array == 0xffffffff) {
803 /* Simplified mode. Was already handled by code above. */
804 } else {
805 /* Flexible mode. */
806 uint8_t tbd_count = 0;
807 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
808 /* Extended Flexible TCB. */
809 for (; tbd_count < 2; tbd_count++) {
810 uint32_t tx_buffer_address = ldl_phys(tbd_address);
811 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
812 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
813 tbd_address += 8;
814 TRACE(RXTX, logout
815 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
816 tx_buffer_address, tx_buffer_size));
817 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
818 cpu_physical_memory_read(tx_buffer_address, &buf[size],
819 tx_buffer_size);
820 size += tx_buffer_size;
821 if (tx_buffer_el & 1) {
822 break;
823 }
824 }
825 }
826 tbd_address = tbd_array;
827 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
828 uint32_t tx_buffer_address = ldl_phys(tbd_address);
829 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
830 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
831 tbd_address += 8;
832 TRACE(RXTX, logout
833 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
834 tx_buffer_address, tx_buffer_size));
835 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
836 cpu_physical_memory_read(tx_buffer_address, &buf[size],
837 tx_buffer_size);
838 size += tx_buffer_size;
839 if (tx_buffer_el & 1) {
840 break;
841 }
842 }
843 }
844 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
845 qemu_send_packet(&s->nic->nc, buf, size);
846 s->statistics.tx_good_frames++;
847 /* Transmit with bad status would raise an CX/TNO interrupt.
848 * (82557 only). Emulation never has bad status. */
849 //~ eepro100_cx_interrupt(s);
850}
851
5fa9a0ae 852static void action_command(EEPRO100State *s)
663e8e51 853{
5fa9a0ae 854 for (;;) {
f3a52e50
SW		 855 s->cb_address = s->cu_base + s->cu_offset;
856 cpu_physical_memory_read(s->cb_address, (uint8_t *)&s->tx, sizeof(s->tx));
857 uint16_t status = le16_to_cpu(s->tx.status);
858 uint16_t command = le16_to_cpu(s->tx.command);
663e8e51
TS		 859 logout
860 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
f3a52e50 861 val, status, command, s->tx.link);
663e8e51
TS		 862 bool bit_el = ((command & 0x8000) != 0);
863 bool bit_s = ((command & 0x4000) != 0);
864 bool bit_i = ((command & 0x2000) != 0);
865 bool bit_nc = ((command & 0x0010) != 0);
7f1e9d4e 866 bool success = true;
663e8e51
TS		 867 //~ bool bit_sf = ((command & 0x0008) != 0);
868 uint16_t cmd = command & 0x0007;
f3a52e50 869 s->cu_offset = le32_to_cpu(s->tx.link);
663e8e51
TS		 870 switch (cmd) {
871 case CmdNOp:
872 /* Do nothing. */
873 break;
874 case CmdIASetup:
f3a52e50 875 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
aac443e6 876 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)));
663e8e51
TS		 877 break;
878 case CmdConfigure:
f3a52e50 879 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
663e8e51 880 sizeof(s->configuration));
aac443e6 881 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
663e8e51
TS		 882 break;
883 case CmdMulticastList:
884 //~ missing("multicast list");
885 break;
886 case CmdTx:
7f1e9d4e
KW		 887 if (bit_nc) {
888 missing("CmdTx: NC = 0");
889 success = false;
890 break;
891 }
f3a52e50 892 tx_command(s);
663e8e51
TS		 893 break;
894 case CmdTDR:
aac443e6 895 TRACE(OTHER, logout("load microcode\n"));
663e8e51
TS		 896 /* Starting with offset 8, the command contains
897 * 64 dwords microcode which we just ignore here. */
898 break;
899 default:
900 missing("undefined command");
7f1e9d4e
KW		 901 success = false;
902 break;
663e8e51 903 }
7f1e9d4e 904 /* Write new status. */
f3a52e50 905 stw_phys(s->cb_address, status | 0x8000 | (success ? 0x2000 : 0));
663e8e51
TS		 906 if (bit_i) {
907 /* CU completed action. */
908 eepro100_cx_interrupt(s);
909 }
910 if (bit_el) {
aac443e6 911 /* CU becomes idle. Terminate command loop. */
663e8e51
TS		 912 set_cu_state(s, cu_idle);
913 eepro100_cna_interrupt(s);
5fa9a0ae 914 break;
663e8e51 915 } else if (bit_s) {
5fa9a0ae 916 /* CU becomes suspended. Terminate command loop. */
663e8e51
TS		 917 set_cu_state(s, cu_suspended);
918 eepro100_cna_interrupt(s);
5fa9a0ae 919 break;
663e8e51
TS		 920 } else {
921 /* More entries in list. */
aac443e6 922 TRACE(OTHER, logout("CU list with at least one more entry\n"));
663e8e51 923 }
5fa9a0ae
SW		 924 }
925 TRACE(OTHER, logout("CU list empty\n"));
926 /* List is empty. Now CU is idle or suspended. */
927}
928
929static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
930{
931 switch (val) {
932 case CU_NOP:
933 /* No operation. */
934 break;
935 case CU_START:
936 if (get_cu_state(s) != cu_idle) {
937 /* Intel documentation says that CU must be idle for the CU
938 * start command. Intel driver for Linux also starts the CU
939 * from suspended state. */
940 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
941 //~ assert(!"wrong CU state");
942 }
943 set_cu_state(s, cu_active);
944 s->cu_offset = s->pointer;
945 action_command(s);
663e8e51
TS		 946 break;
947 case CU_RESUME:
948 if (get_cu_state(s) != cu_suspended) {
949 logout("bad CU resume from CU state %u\n", get_cu_state(s));
950 /* Workaround for bad Linux eepro100 driver which resumes
951 * from idle state. */
952 //~ missing("cu resume");
953 set_cu_state(s, cu_suspended);
954 }
955 if (get_cu_state(s) == cu_suspended) {
aac443e6 956 TRACE(OTHER, logout("CU resuming\n"));
663e8e51 957 set_cu_state(s, cu_active);
5fa9a0ae 958 action_command(s);
663e8e51
TS		 959 }
960 break;
961 case CU_STATSADDR:
962 /* Load dump counters address. */
963 s->statsaddr = s->pointer;
aac443e6 964 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
663e8e51
TS		 965 break;
966 case CU_SHOWSTATS:
967 /* Dump statistical counters. */
aac443e6 968 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
663e8e51 969 dump_statistics(s);
ba42b646 970 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
663e8e51
TS		 971 break;
972 case CU_CMD_BASE:
973 /* Load CU base. */
aac443e6 974 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
663e8e51
TS		 975 s->cu_base = s->pointer;
976 break;
977 case CU_DUMPSTATS:
978 /* Dump and reset statistical counters. */
aac443e6 979 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
663e8e51 980 dump_statistics(s);
ba42b646 981 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
663e8e51
TS		 982 memset(&s->statistics, 0, sizeof(s->statistics));
983 break;
984 case CU_SRESUME:
985 /* CU static resume. */
986 missing("CU static resume");
987 break;
988 default:
989 missing("Undefined CU command");
990 }
991}
992
993static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
994{
995 switch (val) {
996 case RU_NOP:
997 /* No operation. */
998 break;
999 case RX_START:
1000 /* RU start. */
1001 if (get_ru_state(s) != ru_idle) {
1002 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1003 //~ assert(!"wrong RU state");
1004 }
1005 set_ru_state(s, ru_ready);
1006 s->ru_offset = s->pointer;
aac443e6 1007 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
663e8e51
TS		 1008 break;
1009 case RX_RESUME:
1010 /* Restart RU. */
1011 if (get_ru_state(s) != ru_suspended) {
1012 logout("RU state is %u, should be %u\n", get_ru_state(s),
1013 ru_suspended);
1014 //~ assert(!"wrong RU state");
1015 }
1016 set_ru_state(s, ru_ready);
1017 break;
1018 case RX_ADDR_LOAD:
1019 /* Load RU base. */
aac443e6 1020 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
663e8e51
TS		 1021 s->ru_base = s->pointer;
1022 break;
1023 default:
1024 logout("val=0x%02x (undefined RU command)\n", val);
1025 missing("Undefined SU command");
1026 }
1027}
1028
1029static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1030{
1031 eepro100_ru_command(s, val & 0x0f);
1032 eepro100_cu_command(s, val & 0xf0);
1033 if ((val) == 0) {
aac443e6 1034 TRACE(OTHER, logout("val=0x%02x\n", val));
663e8e51
TS		 1035 }
1036 /* Clear command byte after command was accepted. */
1037 s->mem[SCBCmd] = 0;
1038}
1039
1040/*****************************************************************************
1041 *
1042 * EEPROM emulation.
1043 *
1044 ****************************************************************************/
1045
1046#define EEPROM_CS 0x02
1047#define EEPROM_SK 0x01
1048#define EEPROM_DI 0x04
1049#define EEPROM_DO 0x08
1050
1051static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1052{
1053 uint16_t val;
1054 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1055 if (eeprom93xx_read(s->eeprom)) {
1056 val |= EEPROM_DO;
1057 } else {
1058 val &= ~EEPROM_DO;
1059 }
aac443e6 1060 TRACE(EEPROM, logout("val=0x%04x\n", val));
663e8e51
TS		 1061 return val;
1062}
1063
c227f099 1064static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
663e8e51 1065{
aac443e6 1066 TRACE(EEPROM, logout("val=0x%02x\n", val));
663e8e51
TS		 1067
1068 /* mask unwriteable bits */
1069 //~ val = SET_MASKED(val, 0x31, eeprom->value);
1070
1071 int eecs = ((val & EEPROM_CS) != 0);
1072 int eesk = ((val & EEPROM_SK) != 0);
1073 int eedi = ((val & EEPROM_DI) != 0);
1074 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1075}
1076
1077static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1078{
1079 s->pointer = le32_to_cpu(val);
aac443e6 1080 TRACE(OTHER, logout("val=0x%08x\n", val));
663e8e51
TS		 1081}
1082
1083/*****************************************************************************
1084 *
1085 * MDI emulation.
1086 *
1087 ****************************************************************************/
1088
1089#if defined(DEBUG_EEPRO100)
6a0b9cc9 1090static const char * const mdi_op_name[] = {
663e8e51
TS		 1091 "opcode 0",
1092 "write",
1093 "read",
1094 "opcode 3"
1095};
1096
6a0b9cc9 1097static const char * const mdi_reg_name[] = {
663e8e51
TS		 1098 "Control",
1099 "Status",
1100 "PHY Identification (Word 1)",
1101 "PHY Identification (Word 2)",
1102 "Auto-Negotiation Advertisement",
1103 "Auto-Negotiation Link Partner Ability",
1104 "Auto-Negotiation Expansion"
1105};
aac443e6
SW		 1106
1107static const char *reg2name(uint8_t reg)
1108{
1109 static char buffer[10];
1110 const char *p = buffer;
1111 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1112 p = mdi_reg_name[reg];
1113 } else {
1114 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1115 }
1116 return p;
1117}
663e8e51
TS		 1118#endif /* DEBUG_EEPRO100 */
1119
1120static uint32_t eepro100_read_mdi(EEPRO100State * s)
1121{
1122 uint32_t val;
1123 memcpy(&val, &s->mem[0x10], sizeof(val));
1124
1125#ifdef DEBUG_EEPRO100
1126 uint8_t raiseint = (val & BIT(29)) >> 29;
1127 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1128 uint8_t phy = (val & BITS(25, 21)) >> 21;
1129 uint8_t reg = (val & BITS(20, 16)) >> 16;
1130 uint16_t data = (val & BITS(15, 0));
1131#endif
1132 /* Emulation takes no time to finish MDI transaction. */
1133 val |= BIT(28);
1134 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1135 val, raiseint, mdi_op_name[opcode], phy,
aac443e6 1136 reg2name(reg), data));
663e8e51
TS		 1137 return val;
1138}
1139
663e8e51
TS		 1140static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1141{
1142 uint8_t raiseint = (val & BIT(29)) >> 29;
1143 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1144 uint8_t phy = (val & BITS(25, 21)) >> 21;
1145 uint8_t reg = (val & BITS(20, 16)) >> 16;
1146 uint16_t data = (val & BITS(15, 0));
aac443e6
SW		 1147 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1148 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
663e8e51
TS		 1149 if (phy != 1) {
1150 /* Unsupported PHY address. */
1151 //~ logout("phy must be 1 but is %u\n", phy);
1152 data = 0;
1153 } else if (opcode != 1 && opcode != 2) {
1154 /* Unsupported opcode. */
1155 logout("opcode must be 1 or 2 but is %u\n", opcode);
1156 data = 0;
1157 } else if (reg > 6) {
1158 /* Unsupported register. */
1159 logout("register must be 0...6 but is %u\n", reg);
1160 data = 0;
1161 } else {
1162 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1163 val, raiseint, mdi_op_name[opcode], phy,
aac443e6 1164 reg2name(reg), data));
663e8e51
TS		 1165 if (opcode == 1) {
1166 /* MDI write */
1167 switch (reg) {
1168 case 0: /* Control Register */
1169 if (data & 0x8000) {
1170 /* Reset status and control registers to default. */
1171 s->mdimem[0] = eepro100_mdi_default[0];
1172 s->mdimem[1] = eepro100_mdi_default[1];
1173 data = s->mdimem[reg];
1174 } else {
1175 /* Restart Auto Configuration = Normal Operation */
1176 data &= ~0x0200;
1177 }
1178 break;
1179 case 1: /* Status Register */
1180 missing("not writable");
1181 data = s->mdimem[reg];
1182 break;
1183 case 2: /* PHY Identification Register (Word 1) */
1184 case 3: /* PHY Identification Register (Word 2) */
1185 missing("not implemented");
1186 break;
1187 case 4: /* Auto-Negotiation Advertisement Register */
1188 case 5: /* Auto-Negotiation Link Partner Ability Register */
1189 break;
1190 case 6: /* Auto-Negotiation Expansion Register */
1191 default:
1192 missing("not implemented");
1193 }
1194 s->mdimem[reg] = data;
1195 } else if (opcode == 2) {
1196 /* MDI read */
1197 switch (reg) {
1198 case 0: /* Control Register */
1199 if (data & 0x8000) {
1200 /* Reset status and control registers to default. */
1201 s->mdimem[0] = eepro100_mdi_default[0];
1202 s->mdimem[1] = eepro100_mdi_default[1];
1203 }
1204 break;
1205 case 1: /* Status Register */
1206 s->mdimem[reg] |= 0x0020;
1207 break;
1208 case 2: /* PHY Identification Register (Word 1) */
1209 case 3: /* PHY Identification Register (Word 2) */
1210 case 4: /* Auto-Negotiation Advertisement Register */
1211 break;
1212 case 5: /* Auto-Negotiation Link Partner Ability Register */
1213 s->mdimem[reg] = 0x41fe;
1214 break;
1215 case 6: /* Auto-Negotiation Expansion Register */
1216 s->mdimem[reg] = 0x0001;
1217 break;
1218 }
1219 data = s->mdimem[reg];
1220 }
1221 /* Emulation takes no time to finish MDI transaction.
1222 * Set MDI bit in SCB status register. */
1223 s->mem[SCBAck] |= 0x08;
1224 val |= BIT(28);
1225 if (raiseint) {
1226 eepro100_mdi_interrupt(s);
1227 }
1228 }
1229 val = (val & 0xffff0000) + data;
1230 memcpy(&s->mem[0x10], &val, sizeof(val));
1231}
1232
1233/*****************************************************************************
1234 *
1235 * Port emulation.
1236 *
1237 ****************************************************************************/
1238
1239#define PORT_SOFTWARE_RESET 0
1240#define PORT_SELFTEST 1
1241#define PORT_SELECTIVE_RESET 2
1242#define PORT_DUMP 3
1243#define PORT_SELECTION_MASK 3
1244
1245typedef struct {
1246 uint32_t st_sign; /* Self Test Signature */
1247 uint32_t st_result; /* Self Test Results */
c227f099 1248} eepro100_selftest_t;
663e8e51
TS		 1249
1250static uint32_t eepro100_read_port(EEPRO100State * s)
1251{
1252 return 0;
1253}
1254
1255static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1256{
1257 val = le32_to_cpu(val);
1258 uint32_t address = (val & ~PORT_SELECTION_MASK);
1259 uint8_t selection = (val & PORT_SELECTION_MASK);
1260 switch (selection) {
1261 case PORT_SOFTWARE_RESET:
1262 nic_reset(s);
1263 break;
1264 case PORT_SELFTEST:
aac443e6 1265 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
c227f099 1266 eepro100_selftest_t data;
663e8e51
TS		 1267 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1268 data.st_sign = 0xffffffff;
1269 data.st_result = 0;
1270 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1271 break;
1272 case PORT_SELECTIVE_RESET:
aac443e6 1273 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
663e8e51
TS		 1274 nic_selective_reset(s);
1275 break;
1276 default:
1277 logout("val=0x%08x\n", val);
1278 missing("unknown port selection");
1279 }
1280}
1281
1282/*****************************************************************************
1283 *
1284 * General hardware emulation.
1285 *
1286 ****************************************************************************/
1287
1288static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1289{
1290 uint8_t val;
1291 if (addr <= sizeof(s->mem) - sizeof(val)) {
1292 memcpy(&val, &s->mem[addr], sizeof(val));
1293 }
1294
1295 switch (addr) {
1296 case SCBStatus:
1297 //~ val = eepro100_read_status(s);
aac443e6 1298 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1299 break;
1300 case SCBAck:
1301 //~ val = eepro100_read_status(s);
aac443e6 1302 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1303 break;
1304 case SCBCmd:
aac443e6 1305 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1306 //~ val = eepro100_read_command(s);
1307 break;
1308 case SCBIntmask:
aac443e6 1309 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1310 break;
1311 case SCBPort + 3:
aac443e6 1312 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1313 break;
1314 case SCBeeprom:
1315 val = eepro100_read_eeprom(s);
1316 break;
1317 case 0x1b: /* PMDR (power management driver register) */
1318 val = 0;
aac443e6 1319 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1320 break;
1321 case 0x1d: /* general status register */
1322 /* 100 Mbps full duplex, valid link */
1323 val = 0x07;
aac443e6 1324 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
663e8e51
TS		 1325 break;
1326 default:
1327 logout("addr=%s val=0x%02x\n", regname(addr), val);
1328 missing("unknown byte read");
1329 }
1330 return val;
1331}
1332
1333static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1334{
1335 uint16_t val;
1336 if (addr <= sizeof(s->mem) - sizeof(val)) {
1337 memcpy(&val, &s->mem[addr], sizeof(val));
1338 }
1339
663e8e51
TS		 1340 switch (addr) {
1341 case SCBStatus:
1342 //~ val = eepro100_read_status(s);
dbbaaff6 1343 case SCBCmd:
aac443e6 1344 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS		 1345 break;
1346 case SCBeeprom:
1347 val = eepro100_read_eeprom(s);
aac443e6 1348 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS		 1349 break;
1350 default:
1351 logout("addr=%s val=0x%04x\n", regname(addr), val);
1352 missing("unknown word read");
1353 }
1354 return val;
1355}
1356
1357static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1358{
1359 uint32_t val;
1360 if (addr <= sizeof(s->mem) - sizeof(val)) {
1361 memcpy(&val, &s->mem[addr], sizeof(val));
1362 }
1363
1364 switch (addr) {
1365 case SCBStatus:
1366 //~ val = eepro100_read_status(s);
aac443e6 1367 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1368 break;
1369 case SCBPointer:
1370 //~ val = eepro100_read_pointer(s);
aac443e6 1371 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1372 break;
1373 case SCBPort:
1374 val = eepro100_read_port(s);
aac443e6 1375 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1376 break;
1377 case SCBCtrlMDI:
1378 val = eepro100_read_mdi(s);
1379 break;
1380 default:
1381 logout("addr=%s val=0x%08x\n", regname(addr), val);
1382 missing("unknown longword read");
1383 }
1384 return val;
1385}
1386
1387static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1388{
1389 if (addr <= sizeof(s->mem) - sizeof(val)) {
1390 memcpy(&s->mem[addr], &val, sizeof(val));
1391 }
1392
aac443e6 1393 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1394
1395 switch (addr) {
1396 case SCBStatus:
1397 //~ eepro100_write_status(s, val);
1398 break;
1399 case SCBAck:
1400 eepro100_acknowledge(s);
1401 break;
1402 case SCBCmd:
1403 eepro100_write_command(s, val);
1404 break;
1405 case SCBIntmask:
1406 if (val & BIT(1)) {
1407 eepro100_swi_interrupt(s);
1408 }
1409 eepro100_interrupt(s, 0);
1410 break;
1411 case SCBPort + 3:
aac443e6 1412 case SCBFlow: /* does not exist on 82557 */
3257d2b6
TS		 1413 case SCBFlow + 1:
1414 case SCBFlow + 2:
1415 case SCBFlow + 3:
aac443e6 1416 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
663e8e51
TS		 1417 break;
1418 case SCBeeprom:
1419 eepro100_write_eeprom(s->eeprom, val);
1420 break;
1421 default:
1422 logout("addr=%s val=0x%02x\n", regname(addr), val);
1423 missing("unknown byte write");
1424 }
1425}
1426
1427static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1428{
1429 if (addr <= sizeof(s->mem) - sizeof(val)) {
1430 memcpy(&s->mem[addr], &val, sizeof(val));
1431 }
1432
aac443e6 1433 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
663e8e51
TS		 1434
1435 switch (addr) {
1436 case SCBStatus:
1437 //~ eepro100_write_status(s, val);
1438 eepro100_acknowledge(s);
1439 break;
1440 case SCBCmd:
1441 eepro100_write_command(s, val);
1442 eepro100_write1(s, SCBIntmask, val >> 8);
1443 break;
1444 case SCBeeprom:
1445 eepro100_write_eeprom(s->eeprom, val);
1446 break;
1447 default:
1448 logout("addr=%s val=0x%04x\n", regname(addr), val);
1449 missing("unknown word write");
1450 }
1451}
1452
1453static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1454{
1455 if (addr <= sizeof(s->mem) - sizeof(val)) {
1456 memcpy(&s->mem[addr], &val, sizeof(val));
1457 }
1458
1459 switch (addr) {
1460 case SCBPointer:
1461 eepro100_write_pointer(s, val);
1462 break;
1463 case SCBPort:
aac443e6 1464 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
663e8e51
TS		 1465 eepro100_write_port(s, val);
1466 break;
1467 case SCBCtrlMDI:
1468 eepro100_write_mdi(s, val);
1469 break;
1470 default:
1471 logout("addr=%s val=0x%08x\n", regname(addr), val);
1472 missing("unknown longword write");
1473 }
1474}
1475
aac443e6
SW		 1476/*****************************************************************************
1477 *
1478 * Port mapped I/O.
1479 *
1480 ****************************************************************************/
1481
663e8e51
TS		 1482static uint32_t ioport_read1(void *opaque, uint32_t addr)
1483{
1484 EEPRO100State *s = opaque;
1485 //~ logout("addr=%s\n", regname(addr));
1486 return eepro100_read1(s, addr - s->region[1]);
1487}
1488
1489static uint32_t ioport_read2(void *opaque, uint32_t addr)
1490{
1491 EEPRO100State *s = opaque;
1492 return eepro100_read2(s, addr - s->region[1]);
1493}
1494
1495static uint32_t ioport_read4(void *opaque, uint32_t addr)
1496{
1497 EEPRO100State *s = opaque;
1498 return eepro100_read4(s, addr - s->region[1]);
1499}
1500
1501static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1502{
1503 EEPRO100State *s = opaque;
1504 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1505 eepro100_write1(s, addr - s->region[1], val);
1506}
1507
1508static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1509{
1510 EEPRO100State *s = opaque;
1511 eepro100_write2(s, addr - s->region[1], val);
1512}
1513
1514static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1515{
1516 EEPRO100State *s = opaque;
1517 eepro100_write4(s, addr - s->region[1], val);
1518}
1519
1520/***********************************************************/
1521/* PCI EEPRO100 definitions */
1522
663e8e51 1523static void pci_map(PCIDevice * pci_dev, int region_num,
6e355d90 1524 pcibus_t addr, pcibus_t size, int type)
663e8e51 1525{
273a2142 1526 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
663e8e51 1527
89e8b13c
IY		 1528 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1529 "size=0x%08"FMT_PCIBUS", type=%d\n",
aac443e6 1530 region_num, addr, size, type));
663e8e51
TS		 1531
1532 assert(region_num == 1);
1533 register_ioport_write(addr, size, 1, ioport_write1, s);
1534 register_ioport_read(addr, size, 1, ioport_read1, s);
1535 register_ioport_write(addr, size, 2, ioport_write2, s);
1536 register_ioport_read(addr, size, 2, ioport_read2, s);
1537 register_ioport_write(addr, size, 4, ioport_write4, s);
1538 register_ioport_read(addr, size, 4, ioport_read4, s);
1539
1540 s->region[region_num] = addr;
1541}
1542
aac443e6
SW		 1543/*****************************************************************************
1544 *
1545 * Memory mapped I/O.
1546 *
1547 ****************************************************************************/
1548
c227f099 1549static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
663e8e51
TS		 1550{
1551 EEPRO100State *s = opaque;
663e8e51
TS		 1552 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1553 eepro100_write1(s, addr, val);
1554}
1555
c227f099 1556static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
663e8e51
TS		 1557{
1558 EEPRO100State *s = opaque;
663e8e51
TS		 1559 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1560 eepro100_write2(s, addr, val);
1561}
1562
c227f099 1563static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
663e8e51
TS		 1564{
1565 EEPRO100State *s = opaque;
663e8e51
TS		 1566 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1567 eepro100_write4(s, addr, val);
1568}
1569
c227f099 1570static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
663e8e51
TS		 1571{
1572 EEPRO100State *s = opaque;
663e8e51
TS		 1573 //~ logout("addr=%s\n", regname(addr));
1574 return eepro100_read1(s, addr);
1575}
1576
c227f099 1577static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
663e8e51
TS		 1578{
1579 EEPRO100State *s = opaque;
663e8e51
TS		 1580 //~ logout("addr=%s\n", regname(addr));
1581 return eepro100_read2(s, addr);
1582}
1583
c227f099 1584static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
663e8e51
TS		 1585{
1586 EEPRO100State *s = opaque;
663e8e51
TS		 1587 //~ logout("addr=%s\n", regname(addr));
1588 return eepro100_read4(s, addr);
1589}
1590
d60efc6b 1591static CPUWriteMemoryFunc * const pci_mmio_write[] = {
663e8e51
TS		 1592 pci_mmio_writeb,
1593 pci_mmio_writew,
1594 pci_mmio_writel
1595};
1596
d60efc6b 1597static CPUReadMemoryFunc * const pci_mmio_read[] = {
663e8e51
TS		 1598 pci_mmio_readb,
1599 pci_mmio_readw,
1600 pci_mmio_readl
1601};
1602
1603static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
6e355d90 1604 pcibus_t addr, pcibus_t size, int type)
663e8e51 1605{
273a2142 1606 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
663e8e51 1607
89e8b13c
IY		 1608 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1609 "size=0x%08"FMT_PCIBUS", type=%d\n",
aac443e6 1610 region_num, addr, size, type));
663e8e51
TS		 1611
1612 if (region_num == 0) {
1613 /* Map control / status registers. */
273a2142
JQ		 1614 cpu_register_physical_memory(addr, size, s->mmio_index);
1615 s->region[region_num] = addr;
663e8e51
TS		 1616 }
1617}
1618
e00e365e 1619static int nic_can_receive(VLANClientState *nc)
663e8e51 1620{
e00e365e 1621 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
aac443e6 1622 TRACE(RXTX, logout("%p\n", s));
663e8e51
TS		 1623 return get_ru_state(s) == ru_ready;
1624 //~ return !eepro100_buffer_full(s);
1625}
1626
e00e365e 1627static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
663e8e51
TS		 1628{
1629 /* TODO:
1630 * - Magic packets should set bit 30 in power management driver register.
1631 * - Interesting packets should set bit 29 in power management driver register.
1632 */
e00e365e 1633 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
663e8e51
TS		 1634 uint16_t rfd_status = 0xa000;
1635 static const uint8_t broadcast_macaddr[6] =
1636 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1637
1638 /* TODO: check multiple IA bit. */
7f1e9d4e
KW		 1639 if (s->configuration[20] & BIT(6)) {
1640 missing("Multiple IA bit");
1641 return -1;
1642 }
663e8e51
TS		 1643
1644 if (s->configuration[8] & 0x80) {
1645 /* CSMA is disabled. */
1646 logout("%p received while CSMA is disabled\n", s);
4f1c942b 1647 return -1;
663e8e51
TS		 1648 } else if (size < 64 && (s->configuration[7] & 1)) {
1649 /* Short frame and configuration byte 7/0 (discard short receive) set:
1650 * Short frame is discarded */
067d01de 1651 logout("%p received short frame (%zu byte)\n", s, size);
663e8e51 1652 s->statistics.rx_short_frame_errors++;
4f1c942b 1653 //~ return -1;
663e8e51
TS		 1654 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) {
1655 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1656 * Long frames are discarded. */
067d01de 1657 logout("%p received long frame (%zu byte), ignored\n", s, size);
4f1c942b 1658 return -1;
508ef936 1659 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!!
663e8e51
TS		 1660 /* Frame matches individual address. */
1661 /* TODO: check configuration byte 15/4 (ignore U/L). */
067d01de 1662 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
663e8e51
TS		 1663 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1664 /* Broadcast frame. */
067d01de 1665 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
663e8e51
TS		 1666 rfd_status |= 0x0002;
1667 } else if (buf[0] & 0x01) { // !!!
1668 /* Multicast frame. */
067d01de 1669 TRACE(RXTX, logout("%p received multicast, len=%zu\n", s, size));
663e8e51 1670 /* TODO: check multicast all bit. */
7f1e9d4e
KW		 1671 if (s->configuration[21] & BIT(3)) {
1672 missing("Multicast All bit");
1673 }
663e8e51
TS		 1674 int mcast_idx = compute_mcast_idx(buf);
1675 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) {
4f1c942b 1676 return size;
663e8e51
TS		 1677 }
1678 rfd_status |= 0x0002;
1679 } else if (s->configuration[15] & 1) {
1680 /* Promiscuous: receive all. */
067d01de 1681 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
663e8e51
TS		 1682 rfd_status |= 0x0004;
1683 } else {
067d01de 1684 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
aac443e6 1685 nic_dump(buf, size)));
4f1c942b 1686 return size;
663e8e51
TS		 1687 }
1688
1689 if (get_ru_state(s) != ru_ready) {
aac443e6
SW		 1690 /* No resources available. */
1691 logout("no resources, state=%u\n", get_ru_state(s));
663e8e51 1692 s->statistics.rx_resource_errors++;
aac443e6 1693 //~ assert(!"no resources");
4f1c942b 1694 return -1;
663e8e51
TS		 1695 }
1696 //~ !!!
1697//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
c227f099 1698 eepro100_rx_t rx;
663e8e51 1699 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
c227f099 1700 offsetof(eepro100_rx_t, packet));
663e8e51
TS		 1701 uint16_t rfd_command = le16_to_cpu(rx.command);
1702 uint16_t rfd_size = le16_to_cpu(rx.size);
7f1e9d4e
KW		 1703
1704 if (size > rfd_size) {
1705 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1706 "(%zu bytes); data truncated\n", rfd_size, size);
1707 size = rfd_size;
1708 }
663e8e51
TS		 1709 if (size < 64) {
1710 rfd_status |= 0x0080;
1711 }
aac443e6
SW		 1712 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1713 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
c227f099 1714 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
663e8e51 1715 rfd_status);
c227f099 1716 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
663e8e51
TS		 1717 /* Early receive interrupt not supported. */
1718 //~ eepro100_er_interrupt(s);
1719 /* Receive CRC Transfer not supported. */
7f1e9d4e
KW		 1720 if (s->configuration[18] & 4) {
1721 missing("Receive CRC Transfer");
1722 return -1;
1723 }
663e8e51
TS		 1724 /* TODO: check stripping enable bit. */
1725 //~ assert(!(s->configuration[17] & 1));
1726 cpu_physical_memory_write(s->ru_base + s->ru_offset +
c227f099 1727 offsetof(eepro100_rx_t, packet), buf, size);
663e8e51
TS		 1728 s->statistics.rx_good_frames++;
1729 eepro100_fr_interrupt(s);
1730 s->ru_offset = le32_to_cpu(rx.link);
1731 if (rfd_command & 0x8000) {
1732 /* EL bit is set, so this was the last frame. */
7f1e9d4e
KW		 1733 logout("receive: Running out of frames\n");
1734 set_ru_state(s, ru_suspended);
663e8e51
TS		 1735 }
1736 if (rfd_command & 0x4000) {
1737 /* S bit is set. */
1738 set_ru_state(s, ru_suspended);
1739 }
4f1c942b 1740 return size;
663e8e51
TS		 1741}
1742
151b2986
JQ		 1743static const VMStateDescription vmstate_eepro100 = {
1744 .version_id = 3,
1745 .minimum_version_id = 2,
1746 .minimum_version_id_old = 2,
1747 .fields = (VMStateField []) {
1748 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1749 VMSTATE_UNUSED(32),
1750 VMSTATE_BUFFER(mult, EEPRO100State),
1751 VMSTATE_BUFFER(mem, EEPRO100State),
1752 /* Save all members of struct between scb_stat and mem. */
1753 VMSTATE_UINT8(scb_stat, EEPRO100State),
1754 VMSTATE_UINT8(int_stat, EEPRO100State),
1755 VMSTATE_UNUSED(3*4),
1756 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1757 VMSTATE_UNUSED(19*4),
1758 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1759 /* The eeprom should be saved and restored by its own routines. */
1760 VMSTATE_UINT32(device, EEPRO100State),
1761 /* TODO check device. */
1762 VMSTATE_UINT32(pointer, EEPRO100State),
1763 VMSTATE_UINT32(cu_base, EEPRO100State),
1764 VMSTATE_UINT32(cu_offset, EEPRO100State),
1765 VMSTATE_UINT32(ru_base, EEPRO100State),
1766 VMSTATE_UINT32(ru_offset, EEPRO100State),
1767 VMSTATE_UINT32(statsaddr, EEPRO100State),
ba42b646 1768 /* Save eepro100_stats_t statistics. */
151b2986
JQ		 1769 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1770 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1771 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1772 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1773 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1774 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1775 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1776 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1777 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1778 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1779 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1780 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1781 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1782 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1783 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1784 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1785 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1786 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1787 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1788 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1789 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
2657c663 1790#if 0
151b2986 1791 VMSTATE_UINT16(status, EEPRO100State),
2657c663 1792#endif
151b2986
JQ		 1793 /* Configuration bytes. */
1794 VMSTATE_BUFFER(configuration, EEPRO100State),
1795 VMSTATE_END_OF_LIST()
aac443e6 1796 }
151b2986 1797};
663e8e51 1798
e00e365e 1799static void nic_cleanup(VLANClientState *nc)
b946a153 1800{
e00e365e 1801 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 1802
e00e365e 1803 s->nic = NULL;
b946a153
AL		 1804}
1805
c4c270e2 1806static int pci_nic_uninit(PCIDevice *pci_dev)
b946a153 1807{
c4c270e2 1808 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
b946a153
AL		 1809
1810 cpu_unregister_io_memory(s->mmio_index);
151b2986 1811 vmstate_unregister(s->vmstate, s);
508ef936 1812 eeprom93xx_free(s->eeprom);
e00e365e 1813 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 1814 return 0;
1815}
1816
e00e365e
MM		 1817static NetClientInfo net_eepro100_info = {
1818 .type = NET_CLIENT_TYPE_NIC,
1819 .size = sizeof(NICState),
1820 .can_receive = nic_can_receive,
1821 .receive = nic_receive,
1822 .cleanup = nic_cleanup,
1823};
1824
81a322d4 1825static int nic_init(PCIDevice *pci_dev, uint32_t device)
663e8e51 1826{
273a2142 1827 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
663e8e51 1828
aac443e6 1829 TRACE(OTHER, logout("\n"));
663e8e51 1830
663e8e51 1831 s->device = device;
663e8e51
TS		 1832
1833 pci_reset(s);
1834
1835 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1836 * i82559 and later support 64 or 256 word EEPROM. */
1837 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1838
1839 /* Handler for memory-mapped I/O */
273a2142 1840 s->mmio_index =
1eed09cb 1841 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
663e8e51 1842
273a2142 1843 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
0392a017
IY		 1844 PCI_BASE_ADDRESS_SPACE_MEMORY |
1845 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1846 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
663e8e51 1847 pci_map);
0392a017 1848 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
663e8e51
TS		 1849 pci_mmio_map);
1850
508ef936 1851 qemu_macaddr_default_if_unset(&s->conf.macaddr);
663e8e51
TS		 1852 logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));
1853 assert(s->region[1] == 0);
1854
1855 nic_reset(s);
1856
e00e365e
MM		 1857 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1858 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
663e8e51 1859
e00e365e
MM		 1860 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1861 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
663e8e51 1862
a08d4367 1863 qemu_register_reset(nic_reset, s);
663e8e51 1864
151b2986
JQ		 1865 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1866 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
e00e365e 1867 s->vmstate->name = s->nic->nc.model;
151b2986 1868 vmstate_register(-1, s->vmstate, s);
4e9df06a 1869
81a322d4 1870 return 0;
663e8e51
TS		 1871}
1872
c4c270e2
SW		 1873static int pci_i82550_init(PCIDevice *pci_dev)
1874{
1875 return nic_init(pci_dev, i82550);
1876}
1877
1878static int pci_i82551_init(PCIDevice *pci_dev)
1879{
1880 return nic_init(pci_dev, i82551);
1881}
1882
1883static int pci_i82557a_init(PCIDevice *pci_dev)
1884{
1885 return nic_init(pci_dev, i82557A);
1886}
1887
1888static int pci_i82557b_init(PCIDevice *pci_dev)
1889{
1890 return nic_init(pci_dev, i82557B);
1891}
1892
1893static int pci_i82557c_init(PCIDevice *pci_dev)
1894{
1895 return nic_init(pci_dev, i82557C);
1896}
1897
1898static int pci_i82558a_init(PCIDevice *pci_dev)
1899{
1900 return nic_init(pci_dev, i82558A);
1901}
1902
1903static int pci_i82558b_init(PCIDevice *pci_dev)
1904{
1905 return nic_init(pci_dev, i82558B);
1906}
1907
1908static int pci_i82559a_init(PCIDevice *pci_dev)
1909{
1910 return nic_init(pci_dev, i82559A);
1911}
1912
1913static int pci_i82559b_init(PCIDevice *pci_dev)
1914{
1915 return nic_init(pci_dev, i82559B);
1916}
1917
1918static int pci_i82559c_init(PCIDevice *pci_dev)
9d07d757 1919{
c4c270e2 1920 return nic_init(pci_dev, i82559C);
9d07d757
PB		 1921}
1922
c4c270e2 1923static int pci_i82559er_init(PCIDevice *pci_dev)
663e8e51 1924{
c4c270e2 1925 return nic_init(pci_dev, i82559ER);
663e8e51
TS		 1926}
1927
c4c270e2 1928static int pci_i82562_init(PCIDevice *pci_dev)
663e8e51 1929{
c4c270e2 1930 return nic_init(pci_dev, i82562);
663e8e51
TS		 1931}
1932
0aab0d3a
GH		 1933static PCIDeviceInfo eepro100_info[] = {
1934 {
c4c270e2
SW		 1935 .qdev.name = "i82550",
1936 .qdev.size = sizeof(EEPRO100State),
1937 .init = pci_i82550_init,
6a90e308 1938 .exit = pci_nic_uninit,
508ef936
GH		 1939 .qdev.props = (Property[]) {
1940 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1941 DEFINE_PROP_END_OF_LIST(),
1942 },
c4c270e2 1943 },{
0aab0d3a 1944 .qdev.name = "i82551",
273a2142 1945 .qdev.size = sizeof(EEPRO100State),
0aab0d3a 1946 .init = pci_i82551_init,
e3936fa5 1947 .exit = pci_nic_uninit,
508ef936
GH		 1948 .qdev.props = (Property[]) {
1949 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1950 DEFINE_PROP_END_OF_LIST(),
1951 },
c4c270e2
SW		 1952 },{
1953 .qdev.name = "i82557a",
1954 .qdev.size = sizeof(EEPRO100State),
1955 .init = pci_i82557a_init,
6a90e308 1956 .exit = pci_nic_uninit,
508ef936
GH		 1957 .qdev.props = (Property[]) {
1958 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1959 DEFINE_PROP_END_OF_LIST(),
1960 },
0aab0d3a
GH		 1961 },{
1962 .qdev.name = "i82557b",
273a2142 1963 .qdev.size = sizeof(EEPRO100State),
0aab0d3a 1964 .init = pci_i82557b_init,
e3936fa5 1965 .exit = pci_nic_uninit,
508ef936
GH		 1966 .qdev.props = (Property[]) {
1967 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1968 DEFINE_PROP_END_OF_LIST(),
1969 },
c4c270e2
SW		 1970 },{
1971 .qdev.name = "i82557c",
1972 .qdev.size = sizeof(EEPRO100State),
1973 .init = pci_i82557c_init,
6a90e308 1974 .exit = pci_nic_uninit,
508ef936
GH		 1975 .qdev.props = (Property[]) {
1976 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1977 DEFINE_PROP_END_OF_LIST(),
1978 },
c4c270e2
SW		 1979 },{
1980 .qdev.name = "i82558a",
1981 .qdev.size = sizeof(EEPRO100State),
1982 .init = pci_i82558a_init,
6a90e308 1983 .exit = pci_nic_uninit,
508ef936
GH		 1984 .qdev.props = (Property[]) {
1985 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1986 DEFINE_PROP_END_OF_LIST(),
1987 },
c4c270e2
SW		 1988 },{
1989 .qdev.name = "i82558b",
1990 .qdev.size = sizeof(EEPRO100State),
1991 .init = pci_i82558b_init,
6a90e308 1992 .exit = pci_nic_uninit,
508ef936
GH		 1993 .qdev.props = (Property[]) {
1994 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1995 DEFINE_PROP_END_OF_LIST(),
1996 },
c4c270e2
SW		 1997 },{
1998 .qdev.name = "i82559a",
1999 .qdev.size = sizeof(EEPRO100State),
2000 .init = pci_i82559a_init,
6a90e308 2001 .exit = pci_nic_uninit,
508ef936
GH		 2002 .qdev.props = (Property[]) {
2003 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2004 DEFINE_PROP_END_OF_LIST(),
2005 },
c4c270e2
SW		 2006 },{
2007 .qdev.name = "i82559b",
2008 .qdev.size = sizeof(EEPRO100State),
2009 .init = pci_i82559b_init,
6a90e308 2010 .exit = pci_nic_uninit,
508ef936
GH		 2011 .qdev.props = (Property[]) {
2012 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2013 DEFINE_PROP_END_OF_LIST(),
2014 },
c4c270e2
SW		 2015 },{
2016 .qdev.name = "i82559c",
2017 .qdev.size = sizeof(EEPRO100State),
2018 .init = pci_i82559c_init,
6a90e308 2019 .exit = pci_nic_uninit,
508ef936
GH		 2020 .qdev.props = (Property[]) {
2021 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2022 DEFINE_PROP_END_OF_LIST(),
2023 },
0aab0d3a
GH		 2024 },{
2025 .qdev.name = "i82559er",
273a2142 2026 .qdev.size = sizeof(EEPRO100State),
0aab0d3a 2027 .init = pci_i82559er_init,
e3936fa5 2028 .exit = pci_nic_uninit,
938a6324 2029 .romfile = "pxe-i82559er.bin",
508ef936
GH		 2030 .qdev.props = (Property[]) {
2031 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2032 DEFINE_PROP_END_OF_LIST(),
2033 },
c4c270e2
SW		 2034 },{
2035 .qdev.name = "i82562",
2036 .qdev.size = sizeof(EEPRO100State),
2037 .init = pci_i82562_init,
6a90e308 2038 .exit = pci_nic_uninit,
508ef936
GH		 2039 .qdev.props = (Property[]) {
2040 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2041 DEFINE_PROP_END_OF_LIST(),
2042 },
0aab0d3a
GH		 2043 },{
2044 /* end of list */
2045 }
2046};
2047
9d07d757 2048static void eepro100_register_devices(void)
663e8e51 2049{
0aab0d3a 2050 pci_qdev_register_many(eepro100_info);
663e8e51
TS		 2051}
2052
9d07d757 2053device_init(eepro100_register_devices)
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