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FB		 1/*
2 * QEMU ES1370 emulation
3 *
4 * Copyright (c) 2005 Vassili Karpov (malc)
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25/* #define DEBUG_ES1370 */
26/* #define VERBOSE_ES1370 */
27#define SILENT_ES1370
28
29#include "vl.h"
30
31/* Missing stuff:
32 SCTRL_P[12](END|ST)INC
33 SCTRL_P1SCTRLD
34 SCTRL_P2DACSEN
35 CTRL_DAC_SYNC
36 MIDI
37 non looped mode
38 surely more
39*/
40
41/*
42 Following macros and samplerate array were copied verbatim from
43 Linux kernel 2.4.30: drivers/sound/es1370.c
44
45 Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
46*/
47
48/* Start blatant GPL violation */
49
50#define ES1370_REG_CONTROL 0x00
51#define ES1370_REG_STATUS 0x04
52#define ES1370_REG_UART_DATA 0x08
53#define ES1370_REG_UART_STATUS 0x09
54#define ES1370_REG_UART_CONTROL 0x09
55#define ES1370_REG_UART_TEST 0x0a
56#define ES1370_REG_MEMPAGE 0x0c
57#define ES1370_REG_CODEC 0x10
58#define ES1370_REG_SERIAL_CONTROL 0x20
59#define ES1370_REG_DAC1_SCOUNT 0x24
60#define ES1370_REG_DAC2_SCOUNT 0x28
61#define ES1370_REG_ADC_SCOUNT 0x2c
62
63#define ES1370_REG_DAC1_FRAMEADR 0xc30
64#define ES1370_REG_DAC1_FRAMECNT 0xc34
65#define ES1370_REG_DAC2_FRAMEADR 0xc38
66#define ES1370_REG_DAC2_FRAMECNT 0xc3c
67#define ES1370_REG_ADC_FRAMEADR 0xd30
68#define ES1370_REG_ADC_FRAMECNT 0xd34
69#define ES1370_REG_PHANTOM_FRAMEADR 0xd38
70#define ES1370_REG_PHANTOM_FRAMECNT 0xd3c
71
72static const unsigned dac1_samplerate[] = { 5512, 11025, 22050, 44100 };
73
74#define DAC2_SRTODIV(x) (((1411200+(x)/2)/(x))-2)
75#define DAC2_DIVTOSR(x) (1411200/((x)+2))
76
77#define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */
78#define CTRL_XCTL1 0x40000000 /* electret mic bias */
79#define CTRL_OPEN 0x20000000 /* no function, can be read and written */
80#define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */
81#define CTRL_SH_PCLKDIV 16
82#define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
83#define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */
84#define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025, 2=22050, 3=44100 */
85#define CTRL_SH_WTSRSEL 12
86#define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */
87#define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
88#define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 = MPEG */
89#define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */
90#define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
91#define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
92#define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
93#define CTRL_ADC_EN 0x00000010 /* enable ADC */
94#define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
95#define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably at address 0x200) */
96#define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */
97#define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */
98
99#define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
100#define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in progress */
101#define STAT_CBUSY 0x00000200 /* 1 = codec busy */
102#define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */
103#define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
104#define STAT_SH_VC 5
105#define STAT_MCCB 0x00000010 /* CCB int pending */
106#define STAT_UART 0x00000008 /* UART int pending */
107#define STAT_DAC1 0x00000004 /* DAC1 int pending */
108#define STAT_DAC2 0x00000002 /* DAC2 int pending */
109#define STAT_ADC 0x00000001 /* ADC int pending */
110
111#define USTAT_RXINT 0x80 /* UART rx int pending */
112#define USTAT_TXINT 0x04 /* UART tx int pending */
113#define USTAT_TXRDY 0x02 /* UART tx ready */
114#define USTAT_RXRDY 0x01 /* UART rx ready */
115
116#define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
117#define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
118#define UCTRL_ENA_TXINT 0x20 /* enable TX int */
119#define UCTRL_CNTRL 0x03 /* control field */
120#define UCTRL_CNTRL_SWR 0x03 /* software reset command */
121
122#define SCTRL_P2ENDINC 0x00380000 /* */
123#define SCTRL_SH_P2ENDINC 19
124#define SCTRL_P2STINC 0x00070000 /* */
125#define SCTRL_SH_P2STINC 16
126#define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
127#define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
128#define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
129#define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
130#define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
131#define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
132#define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
133#define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
134#define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
135#define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
136#define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
137#define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
138#define SCTRL_R1FMT 0x00000030 /* format mask */
139#define SCTRL_SH_R1FMT 4
140#define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
141#define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
142#define SCTRL_P2FMT 0x0000000c /* format mask */
143#define SCTRL_SH_P2FMT 2
144#define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
145#define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
146#define SCTRL_P1FMT 0x00000003 /* format mask */
147#define SCTRL_SH_P1FMT 0
148
149/* End blatant GPL violation */
150
151#define NB_CHANNELS 3
152#define DAC1_CHANNEL 0
153#define DAC2_CHANNEL 1
154#define ADC_CHANNEL 2
155
156#define IO_READ_PROTO(n) \
157static uint32_t n (void *opaque, uint32_t addr)
158#define IO_WRITE_PROTO(n) \
159static void n (void *opaque, uint32_t addr, uint32_t val)
160
161static void es1370_dac1_callback (void *opaque, int free);
162static void es1370_dac2_callback (void *opaque, int free);
163static void es1370_adc_callback (void *opaque, int avail);
164
165#ifdef DEBUG_ES1370
166
167#define ldebug(...) AUD_log ("es1370", __VA_ARGS__)
168
169static void print_ctl (uint32_t val)
170{
171 char buf[1024];
172
173 buf[0] = '\0';
174#define a(n) if (val & CTRL_##n) strcat (buf, " "#n)
175 a (ADC_STOP);
176 a (XCTL1);
177 a (OPEN);
178 a (MSFMTSEL);
179 a (M_SBB);
180 a (DAC_SYNC);
181 a (CCB_INTRM);
182 a (M_CB);
183 a (XCTL0);
184 a (BREQ);
185 a (DAC1_EN);
186 a (DAC2_EN);
187 a (ADC_EN);
188 a (UART_EN);
189 a (JYSTK_EN);
190 a (CDC_EN);
191 a (SERR_DIS);
192#undef a
193 AUD_log ("es1370", "ctl - PCLKDIV %d(DAC2 freq %d), freq %d,%s\n",
194 (val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV,
195 DAC2_DIVTOSR ((val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV),
196 dac1_samplerate[(val & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL],
197 buf);
198}
199
200static void print_sctl (uint32_t val)
201{
202 static const char *fmt_names[] = {"8M", "8S", "16M", "16S"};
203 char buf[1024];
204
205 buf[0] = '\0';
206
207#define a(n) if (val & SCTRL_##n) strcat (buf, " "#n)
208#define b(n) if (!(val & SCTRL_##n)) strcat (buf, " "#n)
209 b (R1LOOPSEL);
210 b (P2LOOPSEL);
211 b (P1LOOPSEL);
212 a (P2PAUSE);
213 a (P1PAUSE);
214 a (R1INTEN);
215 a (P2INTEN);
216 a (P1INTEN);
217 a (P1SCTRLD);
218 a (P2DACSEN);
219 if (buf[0]) {
220 strcat (buf, "\n ");
221 }
222 else {
223 buf[0] = ' ';
224 buf[1] = '\0';
225 }
226#undef b
227#undef a
228 AUD_log ("es1370",
229 "%s"
230 "p2_end_inc %d, p2_st_inc %d, r1_fmt %s, p2_fmt %s, p1_fmt %s\n",
231 buf,
232 (val & SCTRL_P2ENDINC) >> SCTRL_SH_P2ENDINC,
233 (val & SCTRL_P2STINC) >> SCTRL_SH_P2STINC,
234 fmt_names [(val >> SCTRL_SH_R1FMT) & 3],
235 fmt_names [(val >> SCTRL_SH_P2FMT) & 3],
236 fmt_names [(val >> SCTRL_SH_P1FMT) & 3]
237 );
238}
239#else
240#define ldebug(...)
241#define print_ctl(...)
242#define print_sctl(...)
243#endif
244
245#ifdef VERBOSE_ES1370
246#define dolog(...) AUD_log ("es1370", __VA_ARGS__)
247#else
248#define dolog(...)
249#endif
250
251#ifndef SILENT_ES1370
252#define lwarn(...) AUD_log ("es1370: warning:", __VA_ARGS__)
253#else
254#define lwarn(...)
255#endif
256
257struct chan {
258 uint32_t shift;
259 uint32_t leftover;
260 uint32_t scount;
261 uint32_t frame_addr;
262 uint32_t frame_cnt;
263};
264
265typedef struct ES1370State {
266 PCIDevice *pci_dev;
267
268 struct chan chan[NB_CHANNELS];
269 SWVoiceOut *dac_voice[2];
270 SWVoiceIn *adc_voice;
271
272 uint32_t ctl;
273 uint32_t status;
274 uint32_t mempage;
275 uint32_t codec;
276 uint32_t sctl;
277} ES1370State;
278
279typedef struct PCIES1370State {
280 PCIDevice dev;
281 ES1370State es1370;
282} PCIES1370State;
283
284struct chan_bits {
285 uint32_t ctl_en;
286 uint32_t stat_int;
287 uint32_t sctl_pause;
288 uint32_t sctl_inten;
289 uint32_t sctl_fmt;
290 uint32_t sctl_sh_fmt;
291 uint32_t sctl_loopsel;
292 void (*calc_freq) (ES1370State *s, uint32_t ctl,
293 uint32_t *old_freq, uint32_t *new_freq);
294};
295
296static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
297 uint32_t *old_freq, uint32_t *new_freq);
298static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
299 uint32_t *old_freq,
300 uint32_t *new_freq);
301
302static const struct chan_bits es1370_chan_bits[] = {
303 {CTRL_DAC1_EN, STAT_DAC1, SCTRL_P1PAUSE, SCTRL_P1INTEN,
304 SCTRL_P1FMT, SCTRL_SH_P1FMT, SCTRL_P1LOOPSEL,
305 es1370_dac1_calc_freq},
306
307 {CTRL_DAC2_EN, STAT_DAC2, SCTRL_P2PAUSE, SCTRL_P2INTEN,
308 SCTRL_P2FMT, SCTRL_SH_P2FMT, SCTRL_P2LOOPSEL,
309 es1370_dac2_and_adc_calc_freq},
310
311 {CTRL_ADC_EN, STAT_ADC, 0, SCTRL_R1INTEN,
312 SCTRL_R1FMT, SCTRL_SH_R1FMT, SCTRL_R1LOOPSEL,
313 es1370_dac2_and_adc_calc_freq}
314};
315
316static void es1370_update_status (ES1370State *s, uint32_t new_status)
317{
318 uint32_t level = new_status & (STAT_DAC1 | STAT_DAC2 | STAT_ADC);
319
320 if (level) {
321 s->status = new_status | STAT_INTR;
322 }
323 else {
324 s->status = new_status & ~STAT_INTR;
325 }
326 pci_set_irq (s->pci_dev, 0, !!level);
327}
328
329static void es1370_reset (ES1370State *s)
330{
331 size_t i;
332
333 s->ctl = 1;
334 s->status = 0x60;
335 s->mempage = 0;
336 s->codec = 0;
337 s->sctl = 0;
338
339 for (i = 0; i < NB_CHANNELS; ++i) {
340 struct chan *d = &s->chan[i];
341 d->scount = 0;
342 d->leftover = 0;
343 if (i == ADC_CHANNEL) {
344 AUD_close_in (s->adc_voice);
345 s->adc_voice = NULL;
346 }
347 else {
348 AUD_close_out (s->dac_voice[i]);
349 s->dac_voice[i] = NULL;
350 }
351 }
352 pci_set_irq (s->pci_dev, 0, 0);
353}
354
355static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl)
356{
357 uint32_t new_status = s->status;
358
359 if (!(sctl & SCTRL_P1INTEN) && (s->sctl & SCTRL_P1INTEN)) {
360 new_status &= ~STAT_DAC1;
361 }
362
363 if (!(sctl & SCTRL_P2INTEN) && (s->sctl & SCTRL_P2INTEN)) {
364 new_status &= ~STAT_DAC2;
365 }
366
367 if (!(sctl & SCTRL_R1INTEN) && (s->sctl & SCTRL_R1INTEN)) {
368 new_status &= ~STAT_ADC;
369 }
370
371 if (new_status != s->status) {
372 es1370_update_status (s, new_status);
373 }
374}
375
376static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
377 uint32_t *old_freq, uint32_t *new_freq)
378
379{
380 *old_freq = dac1_samplerate[(s->ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
381 *new_freq = dac1_samplerate[(ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
382}
383
384static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
385 uint32_t *old_freq,
386 uint32_t *new_freq)
387
388{
389 uint32_t old_pclkdiv, new_pclkdiv;
390
391 new_pclkdiv = (ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
392 old_pclkdiv = (s->ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
393 *new_freq = DAC2_DIVTOSR (new_pclkdiv);
394 *old_freq = DAC2_DIVTOSR (old_pclkdiv);
395}
396
397static void es1370_update_voices (ES1370State *s, uint32_t ctl, uint32_t sctl)
398{
399 size_t i;
400 uint32_t old_freq, new_freq, old_fmt, new_fmt;
401
402 for (i = 0; i < NB_CHANNELS; ++i) {
403 struct chan *d = &s->chan[i];
404 const struct chan_bits *b = &es1370_chan_bits[i];
405
406 new_fmt = (sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
407 old_fmt = (s->sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
408
409 b->calc_freq (s, ctl, &old_freq, &new_freq);
410
411 if ((old_fmt != new_fmt) || (old_freq != new_freq)) {
412 d->shift = (new_fmt & 1) + (new_fmt >> 1);
413 ldebug ("channel %d, freq = %d, nchannels %d, fmt %d, shift %d\n",
414 i,
415 new_freq,
416 1 << (new_fmt & 1),
417 (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8,
418 d->shift);
419 if (new_freq) {
420 if (i == ADC_CHANNEL) {
421 s->adc_voice =
422 AUD_open_in (
423 s->adc_voice,
424 "es1370.adc",
425 s,
426 es1370_adc_callback,
427 new_freq,
428 1 << (new_fmt & 1),
429 (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8
430 );
431 }
432 else {
433 s->dac_voice[i] =
434 AUD_open_out (
435 s->dac_voice[i],
436 i ? "es1370.dac2" : "es1370.dac1",
437 s,
438 i ? es1370_dac2_callback : es1370_dac1_callback,
439 new_freq,
440 1 << (new_fmt & 1),
441 (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8
442 );
443 }
444 }
445 }
446
447 if (((ctl ^ s->ctl) & b->ctl_en)
448 || ((sctl ^ s->sctl) & b->sctl_pause)) {
449 int on = (ctl & b->ctl_en) && !(sctl & b->sctl_pause);
450
451 if (i == ADC_CHANNEL) {
452 AUD_set_active_in (s->adc_voice, on);
453 }
454 else {
455 AUD_set_active_out (s->dac_voice[i], on);
456 }
457 }
458 }
459
460 s->ctl = ctl;
461 s->sctl = sctl;
462}
463
464static inline uint32_t es1370_fixup (ES1370State *s, uint32_t addr)
465{
466 addr &= 0xff;
467 if (addr >= 0x30 && addr <= 0x3f)
468 addr |= s->mempage << 8;
469 return addr;
470}
471
472IO_WRITE_PROTO (es1370_writeb)
473{
474 ES1370State *s = opaque;
475 addr = es1370_fixup (s, addr);
476 uint32_t shift, mask;
477
478 switch (addr) {
479 case ES1370_REG_CONTROL:
480 case ES1370_REG_CONTROL + 1:
481 case ES1370_REG_CONTROL + 2:
482 case ES1370_REG_CONTROL + 3:
483 shift = (addr - ES1370_REG_CONTROL) << 3;
484 mask = 0xff << shift;
485 val = (s->ctl & ~mask) | ((val & 0xff) << shift);
486 es1370_update_voices (s, val, s->sctl);
487 print_ctl (val);
488 break;
489 case ES1370_REG_MEMPAGE:
490 s->mempage = val;
491 break;
492 case ES1370_REG_SERIAL_CONTROL:
493 case ES1370_REG_SERIAL_CONTROL + 1:
494 case ES1370_REG_SERIAL_CONTROL + 2:
495 case ES1370_REG_SERIAL_CONTROL + 3:
496 shift = (addr - ES1370_REG_SERIAL_CONTROL) << 3;
497 mask = 0xff << shift;
498 val = (s->sctl & ~mask) | ((val & 0xff) << shift);
499 es1370_maybe_lower_irq (s, val);
500 es1370_update_voices (s, s->ctl, val);
501 print_sctl (val);
502 break;
503 default:
504 lwarn ("writeb %#x <- %#x\n", addr, val);
505 break;
506 }
507}
508
509IO_WRITE_PROTO (es1370_writew)
510{
511 ES1370State *s = opaque;
512 addr = es1370_fixup (s, addr);
513 uint32_t shift, mask;
514 struct chan *d = &s->chan[0];
515
516 switch (addr) {
517 case ES1370_REG_CODEC:
518 dolog ("ignored codec write address %#x, data %#x\n",
519 (val >> 8) & 0xff, val & 0xff);
520 s->codec = val;
521 break;
522
523 case ES1370_REG_CONTROL:
524 case ES1370_REG_CONTROL + 2:
525 shift = (addr != ES1370_REG_CONTROL) << 4;
526 mask = 0xffff << shift;
527 val = (s->ctl & ~mask) | ((val & 0xffff) << shift);
528 es1370_update_voices (s, val, s->sctl);
529 print_ctl (val);
530 break;
531
532 case ES1370_REG_ADC_SCOUNT:
533 d++;
534 case ES1370_REG_DAC2_SCOUNT:
535 d++;
536 case ES1370_REG_DAC1_SCOUNT:
537 d->scount = (d->scount & ~0xffff) | (val & 0xffff);
538 break;
539
540 default:
541 lwarn ("writew %#x <- %#x\n", addr, val);
542 break;
543 }
544}
545
546IO_WRITE_PROTO (es1370_writel)
547{
548 ES1370State *s = opaque;
549 struct chan *d = &s->chan[0];
550
551 addr = es1370_fixup (s, addr);
552
553 switch (addr) {
554 case ES1370_REG_CONTROL:
555 es1370_update_voices (s, val, s->sctl);
556 print_ctl (val);
557 break;
558
559 case ES1370_REG_MEMPAGE:
560 s->mempage = val & 0xf;
561 break;
562
563 case ES1370_REG_SERIAL_CONTROL:
564 es1370_maybe_lower_irq (s, val);
565 es1370_update_voices (s, s->ctl, val);
566 print_sctl (val);
567 break;
568
569 case ES1370_REG_ADC_SCOUNT:
570 d++;
571 case ES1370_REG_DAC2_SCOUNT:
572 d++;
573 case ES1370_REG_DAC1_SCOUNT:
574 d->scount = (val & 0xffff) | (d->scount & ~0xffff);
575 ldebug ("chan %d CURR_SAMP_CT %d, SAMP_CT %d\n",
576 d - &s->chan[0], val >> 16, (val & 0xffff));
577 break;
578
579 case ES1370_REG_ADC_FRAMEADR:
580 d++;
581 case ES1370_REG_DAC2_FRAMEADR:
582 d++;
583 case ES1370_REG_DAC1_FRAMEADR:
584 d->frame_addr = val;
585 ldebug ("chan %d frame address %#x\n", d - &s->chan[0], val);
586 break;
587
588 case ES1370_REG_ADC_FRAMECNT:
589 d++;
590 case ES1370_REG_DAC2_FRAMECNT:
591 d++;
592 case ES1370_REG_DAC1_FRAMECNT:
593 d->frame_cnt = val;
594 d->leftover = 0;
595 ldebug ("chan %d frame count %d, buffer size %d\n",
596 d - &s->chan[0], val >> 16, val & 0xffff);
597 break;
598
599 default:
600 lwarn ("writel %#x <- %#x\n", addr, val);
601 break;
602 }
603}
604
605IO_READ_PROTO (es1370_readb)
606{
607 ES1370State *s = opaque;
608 uint32_t val;
609
610 addr = es1370_fixup (s, addr);
611
612 switch (addr) {
613 case 0x1b: /* Legacy */
614 lwarn ("Attempt to read from legacy register\n");
615 val = 5;
616 break;
617 case ES1370_REG_MEMPAGE:
618 val = s->mempage;
619 break;
620 case ES1370_REG_CONTROL + 0:
621 case ES1370_REG_CONTROL + 1:
622 case ES1370_REG_CONTROL + 2:
623 case ES1370_REG_CONTROL + 3:
624 val = s->ctl >> ((addr - ES1370_REG_CONTROL) << 3);
625 break;
626 case ES1370_REG_STATUS + 0:
627 case ES1370_REG_STATUS + 1:
628 case ES1370_REG_STATUS + 2:
629 case ES1370_REG_STATUS + 3:
630 val = s->status >> ((addr - ES1370_REG_STATUS) << 3);
631 break;
632 default:
633 val = ~0;
634 lwarn ("readb %#x -> %#x\n", addr, val);
635 break;
636 }
637 return val;
638}
639
640IO_READ_PROTO (es1370_readw)
641{
642 ES1370State *s = opaque;
643 struct chan *d = &s->chan[0];
644 uint32_t val;
645
646 addr = es1370_fixup (s, addr);
647
648 switch (addr) {
649 case ES1370_REG_ADC_SCOUNT + 2:
650 d++;
651 case ES1370_REG_DAC2_SCOUNT + 2:
652 d++;
653 case ES1370_REG_DAC1_SCOUNT + 2:
654 val = d->scount >> 16;
655 break;
656
657 default:
658 val = ~0;
659 lwarn ("readw %#x -> %#x\n", addr, val);
660 break;
661 }
662
663 return val;
664}
665
666IO_READ_PROTO (es1370_readl)
667{
668 ES1370State *s = opaque;
669 uint32_t val;
670 struct chan *d = &s->chan[0];
671
672 addr = es1370_fixup (s, addr);
673
674 switch (addr) {
675 case ES1370_REG_CONTROL:
676 val = s->ctl;
677 break;
678 case ES1370_REG_STATUS:
679 val = s->status;
680 break;
681 case ES1370_REG_MEMPAGE:
682 val = s->mempage;
683 break;
684 case ES1370_REG_CODEC:
685 val = s->codec;
686 break;
687 case ES1370_REG_SERIAL_CONTROL:
688 val = s->sctl;
689 break;
690
691 case ES1370_REG_ADC_SCOUNT:
692 d++;
693 case ES1370_REG_DAC2_SCOUNT:
694 d++;
695 case ES1370_REG_DAC1_SCOUNT:
696 val = d->scount;
697#ifdef DEBUG_ES1370
698 {
699 uint32_t curr_count = d->scount >> 16;
700 uint32_t count = d->scount & 0xffff;
701
702 curr_count <<= d->shift;
703 count <<= d->shift;
704 dolog ("read scount curr %d, total %d\n", curr_count, count);
705 }
706#endif
707 break;
708
709 case ES1370_REG_ADC_FRAMECNT:
710 d++;
711 case ES1370_REG_DAC2_FRAMECNT:
712 d++;
713 case ES1370_REG_DAC1_FRAMECNT:
714 val = d->frame_cnt;
715#ifdef DEBUG_ES1370
716 {
717 uint32_t size = ((d->frame_cnt & 0xffff) + 1) << 2;
718 uint32_t curr = ((d->frame_cnt >> 16) + 1) << 2;
719 if (curr > size)
720 dolog ("read framecnt curr %d, size %d %d\n", curr, size,
721 curr > size);
722 }
723#endif
724 break;
725
726 case ES1370_REG_ADC_FRAMEADR:
727 d++;
728 case ES1370_REG_DAC2_FRAMEADR:
729 d++;
730 case ES1370_REG_DAC1_FRAMEADR:
731 val = d->frame_addr;
732 break;
733
734 default:
735 val = ~0U;
736 lwarn ("readl %#x -> %#x\n", addr, val);
737 break;
738 }
739 return val;
740}
741
742
743static void es1370_transfer_audio (ES1370State *s, struct chan *d, int loop_sel,
744 int max, int *irq)
745{
746 uint8_t tmpbuf[4096];
747 uint32_t addr = d->frame_addr;
748 int sc = d->scount & 0xffff;
749 int csc = d->scount >> 16;
750 int csc_bytes = (csc + 1) << d->shift;
751 int cnt = d->frame_cnt >> 16;
752 int size = d->frame_cnt & 0xffff;
753 int left = ((size - cnt + 1) << 2) + d->leftover;
754 int transfered = 0;
755 int temp = audio_MIN (max, audio_MIN (left, csc_bytes));
756 int index = d - &s->chan[0];
757
758 addr += (cnt << 2) + d->leftover;
759
760 if (index == ADC_CHANNEL) {
761 while (temp) {
762 int acquired, to_copy;
763
764 to_copy = audio_MIN (temp, sizeof (tmpbuf));
765 acquired = AUD_read (s->adc_voice, tmpbuf, to_copy);
766 if (!acquired)
767 break;
768
769 cpu_physical_memory_write (addr, tmpbuf, acquired);
770
771 temp -= acquired;
772 addr += acquired;
773 transfered += acquired;
774 }
775 }
776 else {
777 SWVoiceOut *voice = s->dac_voice[index];
778
779 while (temp) {
780 int copied, to_copy;
781
782 to_copy = audio_MIN (temp, sizeof (tmpbuf));
783 cpu_physical_memory_read (addr, tmpbuf, to_copy);
784 copied = AUD_write (voice, tmpbuf, to_copy);
785 if (!copied)
786 break;
787 temp -= copied;
788 addr += copied;
789 transfered += copied;
790 }
791 }
792
793 if (csc_bytes == transfered) {
794 *irq = 1;
795 d->scount = sc | (sc << 16);
796 ldebug ("sc = %d, rate = %f\n",
797 (sc + 1) << d->shift,
798 (sc + 1) / (double) 44100);
799 }
800 else {
801 *irq = 0;
802 d->scount = sc | (((csc_bytes - transfered - 1) >> d->shift) << 16);
803 }
804
805 cnt += (transfered + d->leftover) >> 2;
806
807 if (s->sctl & loop_sel) {
808 /* Bah, how stupid is that having a 0 represent true value?
809 i just spent few hours on this shit */
810 lwarn ("whoops non looping mode\n");
811 }
812 else {
813 d->frame_cnt = size;
814
815 if (cnt <= d->frame_cnt)
816 d->frame_cnt |= cnt << 16;
817 }
818
819 d->leftover = (transfered + d->leftover) & 3;
820}
821
822static void es1370_run_channel (ES1370State *s, size_t chan, int free_or_avail)
823{
824 uint32_t new_status = s->status;
825 int max_bytes, irq;
826 struct chan *d = &s->chan[chan];
827 const struct chan_bits *b = &es1370_chan_bits[chan];
828
829 if (!(s->ctl & b->ctl_en) || (s->sctl & b->sctl_pause)) {
830 return;
831 }
832
833 max_bytes = free_or_avail;
834 max_bytes &= ~((1 << d->shift) - 1);
835 if (!max_bytes) {
836 return;
837 }
838
839 es1370_transfer_audio (s, d, b->sctl_loopsel, max_bytes, &irq);
840
841 if (irq) {
842 if (s->sctl & b->sctl_inten) {
843 new_status |= b->stat_int;
844 }
845 }
846
847 if (new_status != s->status) {
848 es1370_update_status (s, new_status);
849 }
850}
851
852static void es1370_dac1_callback (void *opaque, int free)
853{
854 ES1370State *s = opaque;
855
856 es1370_run_channel (s, DAC1_CHANNEL, free);
857}
858
859static void es1370_dac2_callback (void *opaque, int free)
860{
861 ES1370State *s = opaque;
862
863 es1370_run_channel (s, DAC2_CHANNEL, free);
864}
865
866static void es1370_adc_callback (void *opaque, int avail)
867{
868 ES1370State *s = opaque;
869
870 es1370_run_channel (s, ADC_CHANNEL, avail);
871}
872
873static void es1370_map (PCIDevice *pci_dev, int region_num,
874 uint32_t addr, uint32_t size, int type)
875{
876 PCIES1370State *d = (PCIES1370State *) pci_dev;
877 ES1370State *s = &d->es1370;
878
879 register_ioport_write (addr, 0x40 * 4, 1, es1370_writeb, s);
880 register_ioport_write (addr, 0x40 * 2, 2, es1370_writew, s);
881 register_ioport_write (addr, 0x40, 4, es1370_writel, s);
882
883 register_ioport_read (addr, 0x40 * 4, 1, es1370_readb, s);
884 register_ioport_read (addr, 0x40 * 2, 2, es1370_readw, s);
885 register_ioport_read (addr, 0x40, 4, es1370_readl, s);
886}
887
888static void es1370_save (QEMUFile *f, void *opaque)
889{
890 ES1370State *s = opaque;
891 size_t i;
892
893 for (i = 0; i < NB_CHANNELS; ++i) {
894 struct chan *d = &s->chan[i];
895 qemu_put_be32s (f, &d->shift);
896 qemu_put_be32s (f, &d->leftover);
897 qemu_put_be32s (f, &d->scount);
898 qemu_put_be32s (f, &d->frame_addr);
899 qemu_put_be32s (f, &d->frame_cnt);
900 }
901 qemu_put_be32s (f, &s->ctl);
902 qemu_put_be32s (f, &s->status);
903 qemu_put_be32s (f, &s->mempage);
904 qemu_put_be32s (f, &s->codec);
905 qemu_put_be32s (f, &s->sctl);
906}
907
908static int es1370_load (QEMUFile *f, void *opaque, int version_id)
909{
910 uint32_t ctl, sctl;
911 ES1370State *s = opaque;
912 size_t i;
913
914 if (version_id != 1)
915 return -EINVAL;
916
917 for (i = 0; i < NB_CHANNELS; ++i) {
918 struct chan *d = &s->chan[i];
919 qemu_get_be32s (f, &d->shift);
920 qemu_get_be32s (f, &d->leftover);
921 qemu_get_be32s (f, &d->scount);
922 qemu_get_be32s (f, &d->frame_addr);
923 qemu_get_be32s (f, &d->frame_cnt);
924 if (i == ADC_CHANNEL) {
925 if (s->adc_voice) {
926 AUD_close_in (s->adc_voice);
927 s->adc_voice = NULL;
928 }
929 }
930 else {
931 if (s->dac_voice[i]) {
932 AUD_close_out (s->dac_voice[i]);
933 s->dac_voice[i] = NULL;
934 }
935 }
936 }
937
938 qemu_get_be32s (f, &ctl);
939 qemu_get_be32s (f, &s->status);
940 qemu_get_be32s (f, &s->mempage);
941 qemu_get_be32s (f, &s->codec);
942 qemu_get_be32s (f, &sctl);
943
944 s->ctl = 0;
945 s->sctl = 0;
946 es1370_update_voices (s, ctl, sctl);
947 return 0;
948}
949
950static void es1370_on_reset (void *opaque)
951{
952 ES1370State *s = opaque;
953 es1370_reset (s);
954}
955
956int es1370_init (PCIBus *bus)
957{
958 PCIES1370State *d;
959 ES1370State *s;
960 uint8_t *c;
961
962 d = (PCIES1370State *) pci_register_device (bus, "ES1370",
963 sizeof (PCIES1370State),
964 -1, NULL, NULL);
965
966 if (!d) {
967 fprintf (stderr, "Failed to register PCI device for ES1370\n");
968 return -1;
969 }
970
971 c = d->dev.config;
972 c[0x00] = 0x74;
973 c[0x01] = 0x12;
974 c[0x02] = 0x00;
975 c[0x03] = 0x50;
976 c[0x07] = 2 << 1;
977 c[0x0a] = 0x01;
978 c[0x0b] = 0x04;
979
980#if 1
981 c[0x2c] = 0x42;
982 c[0x2d] = 0x49;
983 c[0x2e] = 0x4c;
984 c[0x2f] = 0x4c;
985#else
986 c[0x2c] = 0x74;
987 c[0x2d] = 0x12;
988 c[0x2e] = 0x71;
989 c[0x2f] = 0x13;
990 c[0x34] = 0xdc;
991 c[0x3c] = 10;
992 c[0xdc] = 0x00;
993#endif
994
995 c[0x3d] = 1;
996 c[0x3e] = 0x0c;
997 c[0x3f] = 0x80;
998
999 s = &d->es1370;
1000 s->pci_dev = &d->dev;
1001
1002 pci_register_io_region (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map);
1003 register_savevm ("es1370", 0, 1, es1370_save, es1370_load, s);
1004 qemu_register_reset (es1370_on_reset, s);
1005 es1370_reset (s);
1006 return 0;
1007}
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