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Commit | Line | Data |
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6f7e9aec | 1 | /* |
67e999be | 2 | * QEMU ESP/NCR53C9x emulation |
5fafdf24 | 3 | * |
4e9aec74 | 4 | * Copyright (c) 2005-2006 Fabrice Bellard |
5fafdf24 | 5 | * |
6f7e9aec FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
5d20fa6b | 24 | |
cfb9de9c | 25 | #include "sysbus.h" |
87ecb68b | 26 | #include "scsi-disk.h" |
8b17de88 | 27 | #include "scsi.h" |
6f7e9aec FB |
28 | |
29 | /* debug ESP card */ | |
2f275b8f | 30 | //#define DEBUG_ESP |
6f7e9aec | 31 | |
67e999be | 32 | /* |
5ad6bb97 BS |
33 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), |
34 | * also produced as NCR89C100. See | |
67e999be FB |
35 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt |
36 | * and | |
37 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt | |
38 | */ | |
39 | ||
6f7e9aec | 40 | #ifdef DEBUG_ESP |
001faf32 BS |
41 | #define DPRINTF(fmt, ...) \ |
42 | do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0) | |
6f7e9aec | 43 | #else |
001faf32 | 44 | #define DPRINTF(fmt, ...) do {} while (0) |
6f7e9aec FB |
45 | #endif |
46 | ||
001faf32 BS |
47 | #define ESP_ERROR(fmt, ...) \ |
48 | do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) | |
8dea1dd4 | 49 | |
5aca8c3b | 50 | #define ESP_REGS 16 |
8dea1dd4 | 51 | #define TI_BUFSZ 16 |
67e999be | 52 | |
4e9aec74 | 53 | typedef struct ESPState ESPState; |
6f7e9aec | 54 | |
4e9aec74 | 55 | struct ESPState { |
cfb9de9c | 56 | SysBusDevice busdev; |
5d20fa6b | 57 | uint32_t it_shift; |
70c0de96 | 58 | qemu_irq irq; |
5aca8c3b BS |
59 | uint8_t rregs[ESP_REGS]; |
60 | uint8_t wregs[ESP_REGS]; | |
67e999be | 61 | int32_t ti_size; |
4f6200f0 | 62 | uint32_t ti_rptr, ti_wptr; |
4f6200f0 | 63 | uint8_t ti_buf[TI_BUFSZ]; |
22548760 BS |
64 | uint32_t sense; |
65 | uint32_t dma; | |
e4bcb14c | 66 | SCSIDevice *scsi_dev[ESP_MAX_DEVS]; |
2e5d83bb | 67 | SCSIDevice *current_dev; |
9f149aa9 | 68 | uint8_t cmdbuf[TI_BUFSZ]; |
22548760 BS |
69 | uint32_t cmdlen; |
70 | uint32_t do_cmd; | |
4d611c9a | 71 | |
6787f5fa | 72 | /* The amount of data left in the current DMA transfer. */ |
4d611c9a | 73 | uint32_t dma_left; |
6787f5fa PB |
74 | /* The size of the current DMA transfer. Zero if no transfer is in |
75 | progress. */ | |
76 | uint32_t dma_counter; | |
a917d384 | 77 | uint8_t *async_buf; |
4d611c9a | 78 | uint32_t async_len; |
8b17de88 BS |
79 | |
80 | espdma_memory_read_write dma_memory_read; | |
81 | espdma_memory_read_write dma_memory_write; | |
67e999be | 82 | void *dma_opaque; |
4e9aec74 | 83 | }; |
6f7e9aec | 84 | |
5ad6bb97 BS |
85 | #define ESP_TCLO 0x0 |
86 | #define ESP_TCMID 0x1 | |
87 | #define ESP_FIFO 0x2 | |
88 | #define ESP_CMD 0x3 | |
89 | #define ESP_RSTAT 0x4 | |
90 | #define ESP_WBUSID 0x4 | |
91 | #define ESP_RINTR 0x5 | |
92 | #define ESP_WSEL 0x5 | |
93 | #define ESP_RSEQ 0x6 | |
94 | #define ESP_WSYNTP 0x6 | |
95 | #define ESP_RFLAGS 0x7 | |
96 | #define ESP_WSYNO 0x7 | |
97 | #define ESP_CFG1 0x8 | |
98 | #define ESP_RRES1 0x9 | |
99 | #define ESP_WCCF 0x9 | |
100 | #define ESP_RRES2 0xa | |
101 | #define ESP_WTEST 0xa | |
102 | #define ESP_CFG2 0xb | |
103 | #define ESP_CFG3 0xc | |
104 | #define ESP_RES3 0xd | |
105 | #define ESP_TCHI 0xe | |
106 | #define ESP_RES4 0xf | |
107 | ||
108 | #define CMD_DMA 0x80 | |
109 | #define CMD_CMD 0x7f | |
110 | ||
111 | #define CMD_NOP 0x00 | |
112 | #define CMD_FLUSH 0x01 | |
113 | #define CMD_RESET 0x02 | |
114 | #define CMD_BUSRESET 0x03 | |
115 | #define CMD_TI 0x10 | |
116 | #define CMD_ICCS 0x11 | |
117 | #define CMD_MSGACC 0x12 | |
0fd0eb21 | 118 | #define CMD_PAD 0x18 |
5ad6bb97 | 119 | #define CMD_SATN 0x1a |
5e1e0a3b | 120 | #define CMD_SEL 0x41 |
5ad6bb97 BS |
121 | #define CMD_SELATN 0x42 |
122 | #define CMD_SELATNS 0x43 | |
123 | #define CMD_ENSEL 0x44 | |
124 | ||
2f275b8f FB |
125 | #define STAT_DO 0x00 |
126 | #define STAT_DI 0x01 | |
127 | #define STAT_CD 0x02 | |
128 | #define STAT_ST 0x03 | |
8dea1dd4 BS |
129 | #define STAT_MO 0x06 |
130 | #define STAT_MI 0x07 | |
5ad6bb97 | 131 | #define STAT_PIO_MASK 0x06 |
2f275b8f FB |
132 | |
133 | #define STAT_TC 0x10 | |
4d611c9a PB |
134 | #define STAT_PE 0x20 |
135 | #define STAT_GE 0x40 | |
c73f96fd | 136 | #define STAT_INT 0x80 |
2f275b8f | 137 | |
8dea1dd4 BS |
138 | #define BUSID_DID 0x07 |
139 | ||
2f275b8f FB |
140 | #define INTR_FC 0x08 |
141 | #define INTR_BS 0x10 | |
142 | #define INTR_DC 0x20 | |
9e61bde5 | 143 | #define INTR_RST 0x80 |
2f275b8f FB |
144 | |
145 | #define SEQ_0 0x0 | |
146 | #define SEQ_CD 0x4 | |
147 | ||
5ad6bb97 BS |
148 | #define CFG1_RESREPT 0x40 |
149 | ||
5ad6bb97 BS |
150 | #define TCHI_FAS100A 0x4 |
151 | ||
c73f96fd BS |
152 | static void esp_raise_irq(ESPState *s) |
153 | { | |
154 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { | |
155 | s->rregs[ESP_RSTAT] |= STAT_INT; | |
156 | qemu_irq_raise(s->irq); | |
157 | } | |
158 | } | |
159 | ||
160 | static void esp_lower_irq(ESPState *s) | |
161 | { | |
162 | if (s->rregs[ESP_RSTAT] & STAT_INT) { | |
163 | s->rregs[ESP_RSTAT] &= ~STAT_INT; | |
164 | qemu_irq_lower(s->irq); | |
165 | } | |
166 | } | |
167 | ||
22548760 | 168 | static uint32_t get_cmd(ESPState *s, uint8_t *buf) |
2f275b8f | 169 | { |
a917d384 | 170 | uint32_t dmalen; |
2f275b8f FB |
171 | int target; |
172 | ||
8dea1dd4 | 173 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
4f6200f0 | 174 | if (s->dma) { |
fc4d65da | 175 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); |
8b17de88 | 176 | s->dma_memory_read(s->dma_opaque, buf, dmalen); |
4f6200f0 | 177 | } else { |
fc4d65da BS |
178 | dmalen = s->ti_size; |
179 | memcpy(buf, s->ti_buf, dmalen); | |
f930d07e | 180 | buf[0] = 0; |
4f6200f0 | 181 | } |
fc4d65da | 182 | DPRINTF("get_cmd: len %d target %d\n", dmalen, target); |
2e5d83bb | 183 | |
2f275b8f | 184 | s->ti_size = 0; |
4f6200f0 FB |
185 | s->ti_rptr = 0; |
186 | s->ti_wptr = 0; | |
2f275b8f | 187 | |
a917d384 PB |
188 | if (s->current_dev) { |
189 | /* Started a new command before the old one finished. Cancel it. */ | |
8ccc2ace | 190 | s->current_dev->cancel_io(s->current_dev, 0); |
a917d384 PB |
191 | s->async_len = 0; |
192 | } | |
193 | ||
e4bcb14c | 194 | if (target >= ESP_MAX_DEVS || !s->scsi_dev[target]) { |
2e5d83bb | 195 | // No such drive |
c73f96fd | 196 | s->rregs[ESP_RSTAT] = 0; |
5ad6bb97 BS |
197 | s->rregs[ESP_RINTR] = INTR_DC; |
198 | s->rregs[ESP_RSEQ] = SEQ_0; | |
c73f96fd | 199 | esp_raise_irq(s); |
f930d07e | 200 | return 0; |
2f275b8f | 201 | } |
2e5d83bb | 202 | s->current_dev = s->scsi_dev[target]; |
9f149aa9 PB |
203 | return dmalen; |
204 | } | |
205 | ||
206 | static void do_cmd(ESPState *s, uint8_t *buf) | |
207 | { | |
208 | int32_t datalen; | |
209 | int lun; | |
210 | ||
211 | DPRINTF("do_cmd: busid 0x%x\n", buf[0]); | |
212 | lun = buf[0] & 7; | |
8ccc2ace | 213 | datalen = s->current_dev->send_command(s->current_dev, 0, &buf[1], lun); |
67e999be FB |
214 | s->ti_size = datalen; |
215 | if (datalen != 0) { | |
c73f96fd | 216 | s->rregs[ESP_RSTAT] = STAT_TC; |
a917d384 | 217 | s->dma_left = 0; |
6787f5fa | 218 | s->dma_counter = 0; |
2e5d83bb | 219 | if (datalen > 0) { |
5ad6bb97 | 220 | s->rregs[ESP_RSTAT] |= STAT_DI; |
8ccc2ace | 221 | s->current_dev->read_data(s->current_dev, 0); |
2e5d83bb | 222 | } else { |
5ad6bb97 | 223 | s->rregs[ESP_RSTAT] |= STAT_DO; |
8ccc2ace | 224 | s->current_dev->write_data(s->current_dev, 0); |
b9788fc4 | 225 | } |
2f275b8f | 226 | } |
5ad6bb97 BS |
227 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
228 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 229 | esp_raise_irq(s); |
2f275b8f FB |
230 | } |
231 | ||
9f149aa9 PB |
232 | static void handle_satn(ESPState *s) |
233 | { | |
234 | uint8_t buf[32]; | |
235 | int len; | |
236 | ||
237 | len = get_cmd(s, buf); | |
238 | if (len) | |
239 | do_cmd(s, buf); | |
240 | } | |
241 | ||
242 | static void handle_satn_stop(ESPState *s) | |
243 | { | |
244 | s->cmdlen = get_cmd(s, s->cmdbuf); | |
245 | if (s->cmdlen) { | |
246 | DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen); | |
247 | s->do_cmd = 1; | |
c73f96fd | 248 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
5ad6bb97 BS |
249 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
250 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 251 | esp_raise_irq(s); |
9f149aa9 PB |
252 | } |
253 | } | |
254 | ||
0fc5c15a | 255 | static void write_response(ESPState *s) |
2f275b8f | 256 | { |
0fc5c15a PB |
257 | DPRINTF("Transfer status (sense=%d)\n", s->sense); |
258 | s->ti_buf[0] = s->sense; | |
259 | s->ti_buf[1] = 0; | |
4f6200f0 | 260 | if (s->dma) { |
8b17de88 | 261 | s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); |
c73f96fd | 262 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
5ad6bb97 BS |
263 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
264 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
4f6200f0 | 265 | } else { |
f930d07e BS |
266 | s->ti_size = 2; |
267 | s->ti_rptr = 0; | |
268 | s->ti_wptr = 0; | |
5ad6bb97 | 269 | s->rregs[ESP_RFLAGS] = 2; |
4f6200f0 | 270 | } |
c73f96fd | 271 | esp_raise_irq(s); |
2f275b8f | 272 | } |
4f6200f0 | 273 | |
a917d384 PB |
274 | static void esp_dma_done(ESPState *s) |
275 | { | |
c73f96fd | 276 | s->rregs[ESP_RSTAT] |= STAT_TC; |
5ad6bb97 BS |
277 | s->rregs[ESP_RINTR] = INTR_BS; |
278 | s->rregs[ESP_RSEQ] = 0; | |
279 | s->rregs[ESP_RFLAGS] = 0; | |
280 | s->rregs[ESP_TCLO] = 0; | |
281 | s->rregs[ESP_TCMID] = 0; | |
c73f96fd | 282 | esp_raise_irq(s); |
a917d384 PB |
283 | } |
284 | ||
4d611c9a PB |
285 | static void esp_do_dma(ESPState *s) |
286 | { | |
67e999be | 287 | uint32_t len; |
4d611c9a | 288 | int to_device; |
a917d384 | 289 | |
67e999be | 290 | to_device = (s->ti_size < 0); |
a917d384 | 291 | len = s->dma_left; |
4d611c9a | 292 | if (s->do_cmd) { |
4d611c9a | 293 | DPRINTF("command len %d + %d\n", s->cmdlen, len); |
8b17de88 | 294 | s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
4d611c9a PB |
295 | s->ti_size = 0; |
296 | s->cmdlen = 0; | |
297 | s->do_cmd = 0; | |
298 | do_cmd(s, s->cmdbuf); | |
299 | return; | |
a917d384 PB |
300 | } |
301 | if (s->async_len == 0) { | |
302 | /* Defer until data is available. */ | |
303 | return; | |
304 | } | |
305 | if (len > s->async_len) { | |
306 | len = s->async_len; | |
307 | } | |
308 | if (to_device) { | |
8b17de88 | 309 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
4d611c9a | 310 | } else { |
8b17de88 | 311 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
a917d384 | 312 | } |
a917d384 PB |
313 | s->dma_left -= len; |
314 | s->async_buf += len; | |
315 | s->async_len -= len; | |
6787f5fa PB |
316 | if (to_device) |
317 | s->ti_size += len; | |
318 | else | |
319 | s->ti_size -= len; | |
a917d384 | 320 | if (s->async_len == 0) { |
4d611c9a | 321 | if (to_device) { |
67e999be | 322 | // ti_size is negative |
8ccc2ace | 323 | s->current_dev->write_data(s->current_dev, 0); |
4d611c9a | 324 | } else { |
8ccc2ace | 325 | s->current_dev->read_data(s->current_dev, 0); |
6787f5fa | 326 | /* If there is still data to be read from the device then |
8dea1dd4 | 327 | complete the DMA operation immediately. Otherwise defer |
6787f5fa PB |
328 | until the scsi layer has completed. */ |
329 | if (s->dma_left == 0 && s->ti_size > 0) { | |
330 | esp_dma_done(s); | |
331 | } | |
4d611c9a | 332 | } |
6787f5fa PB |
333 | } else { |
334 | /* Partially filled a scsi buffer. Complete immediately. */ | |
a917d384 PB |
335 | esp_dma_done(s); |
336 | } | |
4d611c9a PB |
337 | } |
338 | ||
a917d384 PB |
339 | static void esp_command_complete(void *opaque, int reason, uint32_t tag, |
340 | uint32_t arg) | |
2e5d83bb PB |
341 | { |
342 | ESPState *s = (ESPState *)opaque; | |
343 | ||
4d611c9a PB |
344 | if (reason == SCSI_REASON_DONE) { |
345 | DPRINTF("SCSI Command complete\n"); | |
346 | if (s->ti_size != 0) | |
347 | DPRINTF("SCSI command completed unexpectedly\n"); | |
348 | s->ti_size = 0; | |
a917d384 PB |
349 | s->dma_left = 0; |
350 | s->async_len = 0; | |
351 | if (arg) | |
4d611c9a | 352 | DPRINTF("Command failed\n"); |
a917d384 | 353 | s->sense = arg; |
5ad6bb97 | 354 | s->rregs[ESP_RSTAT] = STAT_ST; |
a917d384 PB |
355 | esp_dma_done(s); |
356 | s->current_dev = NULL; | |
4d611c9a PB |
357 | } else { |
358 | DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size); | |
a917d384 | 359 | s->async_len = arg; |
8ccc2ace | 360 | s->async_buf = s->current_dev->get_buf(s->current_dev, 0); |
6787f5fa | 361 | if (s->dma_left) { |
a917d384 | 362 | esp_do_dma(s); |
6787f5fa PB |
363 | } else if (s->dma_counter != 0 && s->ti_size <= 0) { |
364 | /* If this was the last part of a DMA transfer then the | |
365 | completion interrupt is deferred to here. */ | |
366 | esp_dma_done(s); | |
367 | } | |
4d611c9a | 368 | } |
2e5d83bb PB |
369 | } |
370 | ||
2f275b8f FB |
371 | static void handle_ti(ESPState *s) |
372 | { | |
4d611c9a | 373 | uint32_t dmalen, minlen; |
2f275b8f | 374 | |
5ad6bb97 | 375 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); |
db59203d PB |
376 | if (dmalen==0) { |
377 | dmalen=0x10000; | |
378 | } | |
6787f5fa | 379 | s->dma_counter = dmalen; |
db59203d | 380 | |
9f149aa9 PB |
381 | if (s->do_cmd) |
382 | minlen = (dmalen < 32) ? dmalen : 32; | |
67e999be FB |
383 | else if (s->ti_size < 0) |
384 | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; | |
9f149aa9 PB |
385 | else |
386 | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; | |
db59203d | 387 | DPRINTF("Transfer Information len %d\n", minlen); |
4f6200f0 | 388 | if (s->dma) { |
4d611c9a | 389 | s->dma_left = minlen; |
5ad6bb97 | 390 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
4d611c9a | 391 | esp_do_dma(s); |
9f149aa9 PB |
392 | } else if (s->do_cmd) { |
393 | DPRINTF("command len %d\n", s->cmdlen); | |
394 | s->ti_size = 0; | |
395 | s->cmdlen = 0; | |
396 | s->do_cmd = 0; | |
397 | do_cmd(s, s->cmdbuf); | |
398 | return; | |
399 | } | |
2f275b8f FB |
400 | } |
401 | ||
5aca8c3b | 402 | static void esp_reset(void *opaque) |
6f7e9aec FB |
403 | { |
404 | ESPState *s = opaque; | |
67e999be | 405 | |
5aca8c3b BS |
406 | memset(s->rregs, 0, ESP_REGS); |
407 | memset(s->wregs, 0, ESP_REGS); | |
5ad6bb97 | 408 | s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a |
4e9aec74 PB |
409 | s->ti_size = 0; |
410 | s->ti_rptr = 0; | |
411 | s->ti_wptr = 0; | |
4e9aec74 | 412 | s->dma = 0; |
9f149aa9 | 413 | s->do_cmd = 0; |
8dea1dd4 BS |
414 | |
415 | s->rregs[ESP_CFG1] = 7; | |
6f7e9aec FB |
416 | } |
417 | ||
2d069bab BS |
418 | static void parent_esp_reset(void *opaque, int irq, int level) |
419 | { | |
420 | if (level) | |
421 | esp_reset(opaque); | |
422 | } | |
423 | ||
6f7e9aec FB |
424 | static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
425 | { | |
426 | ESPState *s = opaque; | |
2814df28 | 427 | uint32_t saddr, old_val; |
6f7e9aec | 428 | |
e64d7d59 | 429 | saddr = addr >> s->it_shift; |
9e61bde5 | 430 | DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]); |
6f7e9aec | 431 | switch (saddr) { |
5ad6bb97 | 432 | case ESP_FIFO: |
f930d07e BS |
433 | if (s->ti_size > 0) { |
434 | s->ti_size--; | |
5ad6bb97 | 435 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
8dea1dd4 BS |
436 | /* Data out. */ |
437 | ESP_ERROR("PIO data read not implemented\n"); | |
5ad6bb97 | 438 | s->rregs[ESP_FIFO] = 0; |
2e5d83bb | 439 | } else { |
5ad6bb97 | 440 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
2e5d83bb | 441 | } |
c73f96fd | 442 | esp_raise_irq(s); |
f930d07e BS |
443 | } |
444 | if (s->ti_size == 0) { | |
4f6200f0 FB |
445 | s->ti_rptr = 0; |
446 | s->ti_wptr = 0; | |
447 | } | |
f930d07e | 448 | break; |
5ad6bb97 | 449 | case ESP_RINTR: |
2814df28 BS |
450 | /* Clear sequence step, interrupt register and all status bits |
451 | except TC */ | |
452 | old_val = s->rregs[ESP_RINTR]; | |
453 | s->rregs[ESP_RINTR] = 0; | |
454 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
455 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 456 | esp_lower_irq(s); |
2814df28 BS |
457 | |
458 | return old_val; | |
6f7e9aec | 459 | default: |
f930d07e | 460 | break; |
6f7e9aec | 461 | } |
2f275b8f | 462 | return s->rregs[saddr]; |
6f7e9aec FB |
463 | } |
464 | ||
465 | static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | |
466 | { | |
467 | ESPState *s = opaque; | |
468 | uint32_t saddr; | |
469 | ||
e64d7d59 | 470 | saddr = addr >> s->it_shift; |
5ad6bb97 BS |
471 | DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], |
472 | val); | |
6f7e9aec | 473 | switch (saddr) { |
5ad6bb97 BS |
474 | case ESP_TCLO: |
475 | case ESP_TCMID: | |
476 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
4f6200f0 | 477 | break; |
5ad6bb97 | 478 | case ESP_FIFO: |
9f149aa9 PB |
479 | if (s->do_cmd) { |
480 | s->cmdbuf[s->cmdlen++] = val & 0xff; | |
8dea1dd4 BS |
481 | } else if (s->ti_size == TI_BUFSZ - 1) { |
482 | ESP_ERROR("fifo overrun\n"); | |
2e5d83bb PB |
483 | } else { |
484 | s->ti_size++; | |
485 | s->ti_buf[s->ti_wptr++] = val & 0xff; | |
486 | } | |
f930d07e | 487 | break; |
5ad6bb97 | 488 | case ESP_CMD: |
4f6200f0 | 489 | s->rregs[saddr] = val; |
5ad6bb97 | 490 | if (val & CMD_DMA) { |
f930d07e | 491 | s->dma = 1; |
6787f5fa | 492 | /* Reload DMA counter. */ |
5ad6bb97 BS |
493 | s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
494 | s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; | |
f930d07e BS |
495 | } else { |
496 | s->dma = 0; | |
497 | } | |
5ad6bb97 BS |
498 | switch(val & CMD_CMD) { |
499 | case CMD_NOP: | |
f930d07e BS |
500 | DPRINTF("NOP (%2.2x)\n", val); |
501 | break; | |
5ad6bb97 | 502 | case CMD_FLUSH: |
f930d07e | 503 | DPRINTF("Flush FIFO (%2.2x)\n", val); |
9e61bde5 | 504 | //s->ti_size = 0; |
5ad6bb97 BS |
505 | s->rregs[ESP_RINTR] = INTR_FC; |
506 | s->rregs[ESP_RSEQ] = 0; | |
a214c598 | 507 | s->rregs[ESP_RFLAGS] = 0; |
f930d07e | 508 | break; |
5ad6bb97 | 509 | case CMD_RESET: |
f930d07e BS |
510 | DPRINTF("Chip reset (%2.2x)\n", val); |
511 | esp_reset(s); | |
512 | break; | |
5ad6bb97 | 513 | case CMD_BUSRESET: |
f930d07e | 514 | DPRINTF("Bus reset (%2.2x)\n", val); |
5ad6bb97 BS |
515 | s->rregs[ESP_RINTR] = INTR_RST; |
516 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { | |
c73f96fd | 517 | esp_raise_irq(s); |
9e61bde5 | 518 | } |
f930d07e | 519 | break; |
5ad6bb97 | 520 | case CMD_TI: |
f930d07e BS |
521 | handle_ti(s); |
522 | break; | |
5ad6bb97 | 523 | case CMD_ICCS: |
f930d07e BS |
524 | DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val); |
525 | write_response(s); | |
4bf5801d BS |
526 | s->rregs[ESP_RINTR] = INTR_FC; |
527 | s->rregs[ESP_RSTAT] |= STAT_MI; | |
f930d07e | 528 | break; |
5ad6bb97 | 529 | case CMD_MSGACC: |
f930d07e BS |
530 | DPRINTF("Message Accepted (%2.2x)\n", val); |
531 | write_response(s); | |
5ad6bb97 BS |
532 | s->rregs[ESP_RINTR] = INTR_DC; |
533 | s->rregs[ESP_RSEQ] = 0; | |
f930d07e | 534 | break; |
0fd0eb21 BS |
535 | case CMD_PAD: |
536 | DPRINTF("Transfer padding (%2.2x)\n", val); | |
537 | s->rregs[ESP_RSTAT] = STAT_TC; | |
538 | s->rregs[ESP_RINTR] = INTR_FC; | |
539 | s->rregs[ESP_RSEQ] = 0; | |
540 | break; | |
5ad6bb97 | 541 | case CMD_SATN: |
f930d07e BS |
542 | DPRINTF("Set ATN (%2.2x)\n", val); |
543 | break; | |
5e1e0a3b BS |
544 | case CMD_SEL: |
545 | DPRINTF("Select without ATN (%2.2x)\n", val); | |
546 | handle_satn(s); | |
547 | break; | |
5ad6bb97 | 548 | case CMD_SELATN: |
5e1e0a3b | 549 | DPRINTF("Select with ATN (%2.2x)\n", val); |
f930d07e BS |
550 | handle_satn(s); |
551 | break; | |
5ad6bb97 | 552 | case CMD_SELATNS: |
5e1e0a3b | 553 | DPRINTF("Select with ATN & stop (%2.2x)\n", val); |
f930d07e BS |
554 | handle_satn_stop(s); |
555 | break; | |
5ad6bb97 | 556 | case CMD_ENSEL: |
74ec6048 | 557 | DPRINTF("Enable selection (%2.2x)\n", val); |
e3926838 | 558 | s->rregs[ESP_RINTR] = 0; |
74ec6048 | 559 | break; |
f930d07e | 560 | default: |
8dea1dd4 | 561 | ESP_ERROR("Unhandled ESP command (%2.2x)\n", val); |
f930d07e BS |
562 | break; |
563 | } | |
564 | break; | |
5ad6bb97 | 565 | case ESP_WBUSID ... ESP_WSYNO: |
f930d07e | 566 | break; |
5ad6bb97 | 567 | case ESP_CFG1: |
4f6200f0 FB |
568 | s->rregs[saddr] = val; |
569 | break; | |
5ad6bb97 | 570 | case ESP_WCCF ... ESP_WTEST: |
4f6200f0 | 571 | break; |
b44c08fa | 572 | case ESP_CFG2 ... ESP_RES4: |
4f6200f0 FB |
573 | s->rregs[saddr] = val; |
574 | break; | |
6f7e9aec | 575 | default: |
8dea1dd4 BS |
576 | ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr); |
577 | return; | |
6f7e9aec | 578 | } |
2f275b8f | 579 | s->wregs[saddr] = val; |
6f7e9aec FB |
580 | } |
581 | ||
d60efc6b | 582 | static CPUReadMemoryFunc * const esp_mem_read[3] = { |
6f7e9aec | 583 | esp_mem_readb, |
7c560456 BS |
584 | NULL, |
585 | NULL, | |
6f7e9aec FB |
586 | }; |
587 | ||
d60efc6b | 588 | static CPUWriteMemoryFunc * const esp_mem_write[3] = { |
6f7e9aec | 589 | esp_mem_writeb, |
7c560456 | 590 | NULL, |
daa41b00 | 591 | esp_mem_writeb, |
6f7e9aec FB |
592 | }; |
593 | ||
6f7e9aec FB |
594 | static void esp_save(QEMUFile *f, void *opaque) |
595 | { | |
596 | ESPState *s = opaque; | |
2f275b8f | 597 | |
5aca8c3b BS |
598 | qemu_put_buffer(f, s->rregs, ESP_REGS); |
599 | qemu_put_buffer(f, s->wregs, ESP_REGS); | |
b6c4f71f | 600 | qemu_put_sbe32s(f, &s->ti_size); |
4f6200f0 FB |
601 | qemu_put_be32s(f, &s->ti_rptr); |
602 | qemu_put_be32s(f, &s->ti_wptr); | |
4f6200f0 | 603 | qemu_put_buffer(f, s->ti_buf, TI_BUFSZ); |
5425a216 | 604 | qemu_put_be32s(f, &s->sense); |
4f6200f0 | 605 | qemu_put_be32s(f, &s->dma); |
5425a216 BS |
606 | qemu_put_buffer(f, s->cmdbuf, TI_BUFSZ); |
607 | qemu_put_be32s(f, &s->cmdlen); | |
608 | qemu_put_be32s(f, &s->do_cmd); | |
609 | qemu_put_be32s(f, &s->dma_left); | |
610 | // There should be no transfers in progress, so dma_counter is not saved | |
6f7e9aec FB |
611 | } |
612 | ||
613 | static int esp_load(QEMUFile *f, void *opaque, int version_id) | |
614 | { | |
615 | ESPState *s = opaque; | |
3b46e624 | 616 | |
5425a216 BS |
617 | if (version_id != 3) |
618 | return -EINVAL; // Cannot emulate 2 | |
6f7e9aec | 619 | |
5aca8c3b BS |
620 | qemu_get_buffer(f, s->rregs, ESP_REGS); |
621 | qemu_get_buffer(f, s->wregs, ESP_REGS); | |
b6c4f71f | 622 | qemu_get_sbe32s(f, &s->ti_size); |
4f6200f0 FB |
623 | qemu_get_be32s(f, &s->ti_rptr); |
624 | qemu_get_be32s(f, &s->ti_wptr); | |
4f6200f0 | 625 | qemu_get_buffer(f, s->ti_buf, TI_BUFSZ); |
5425a216 | 626 | qemu_get_be32s(f, &s->sense); |
4f6200f0 | 627 | qemu_get_be32s(f, &s->dma); |
5425a216 BS |
628 | qemu_get_buffer(f, s->cmdbuf, TI_BUFSZ); |
629 | qemu_get_be32s(f, &s->cmdlen); | |
630 | qemu_get_be32s(f, &s->do_cmd); | |
631 | qemu_get_be32s(f, &s->dma_left); | |
2f275b8f | 632 | |
6f7e9aec FB |
633 | return 0; |
634 | } | |
635 | ||
cfb9de9c | 636 | static void esp_scsi_attach(DeviceState *host, BlockDriverState *bd, int id) |
fa1fb14c | 637 | { |
cfb9de9c | 638 | ESPState *s = FROM_SYSBUS(ESPState, sysbus_from_qdev(host)); |
fa1fb14c TS |
639 | |
640 | if (id < 0) { | |
641 | for (id = 0; id < ESP_MAX_DEVS; id++) { | |
8dea1dd4 BS |
642 | if (id == (s->rregs[ESP_CFG1] & 0x7)) |
643 | continue; | |
fa1fb14c TS |
644 | if (s->scsi_dev[id] == NULL) |
645 | break; | |
646 | } | |
647 | } | |
648 | if (id >= ESP_MAX_DEVS) { | |
649 | DPRINTF("Bad Device ID %d\n", id); | |
650 | return; | |
651 | } | |
652 | if (s->scsi_dev[id]) { | |
653 | DPRINTF("Destroying device %d\n", id); | |
8ccc2ace | 654 | s->scsi_dev[id]->destroy(s->scsi_dev[id]); |
fa1fb14c TS |
655 | } |
656 | DPRINTF("Attaching block device %d\n", id); | |
657 | /* Command queueing is not implemented. */ | |
985a03b0 TS |
658 | s->scsi_dev[id] = scsi_generic_init(bd, 0, esp_command_complete, s); |
659 | if (s->scsi_dev[id] == NULL) | |
660 | s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s); | |
fa1fb14c TS |
661 | } |
662 | ||
cfb9de9c PB |
663 | void esp_init(target_phys_addr_t espaddr, int it_shift, |
664 | espdma_memory_read_write dma_memory_read, | |
665 | espdma_memory_read_write dma_memory_write, | |
666 | void *dma_opaque, qemu_irq irq, qemu_irq *reset) | |
6f7e9aec | 667 | { |
cfb9de9c PB |
668 | DeviceState *dev; |
669 | SysBusDevice *s; | |
ee6847d1 | 670 | ESPState *esp; |
cfb9de9c PB |
671 | |
672 | dev = qdev_create(NULL, "esp"); | |
ee6847d1 GH |
673 | esp = DO_UPCAST(ESPState, busdev.qdev, dev); |
674 | esp->dma_memory_read = dma_memory_read; | |
675 | esp->dma_memory_write = dma_memory_write; | |
676 | esp->dma_opaque = dma_opaque; | |
677 | esp->it_shift = it_shift; | |
cfb9de9c PB |
678 | qdev_init(dev); |
679 | s = sysbus_from_qdev(dev); | |
680 | sysbus_connect_irq(s, 0, irq); | |
681 | sysbus_mmio_map(s, 0, espaddr); | |
74ff8d90 | 682 | *reset = qdev_get_gpio_in(dev, 0); |
cfb9de9c | 683 | } |
6f7e9aec | 684 | |
81a322d4 | 685 | static int esp_init1(SysBusDevice *dev) |
cfb9de9c PB |
686 | { |
687 | ESPState *s = FROM_SYSBUS(ESPState, dev); | |
688 | int esp_io_memory; | |
6f7e9aec | 689 | |
cfb9de9c | 690 | sysbus_init_irq(dev, &s->irq); |
cfb9de9c | 691 | assert(s->it_shift != -1); |
6f7e9aec | 692 | |
1eed09cb | 693 | esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s); |
cfb9de9c | 694 | sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); |
6f7e9aec | 695 | |
6f7e9aec FB |
696 | esp_reset(s); |
697 | ||
cfb9de9c | 698 | register_savevm("esp", -1, 3, esp_save, esp_load, s); |
a08d4367 | 699 | qemu_register_reset(esp_reset, s); |
6f7e9aec | 700 | |
067a3ddc | 701 | qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1); |
2d069bab | 702 | |
cfb9de9c | 703 | scsi_bus_new(&dev->qdev, esp_scsi_attach); |
81a322d4 | 704 | return 0; |
67e999be | 705 | } |
cfb9de9c PB |
706 | |
707 | static void esp_register_devices(void) | |
708 | { | |
709 | sysbus_register_dev("esp", sizeof(ESPState), esp_init1); | |
710 | } | |
711 | ||
712 | device_init(esp_register_devices) |