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1ba13a5d EI |
1 | /* |
2 | * QEMU ETRAX DMA Controller. | |
3 | * | |
4 | * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include <stdio.h> | |
25 | #include <sys/time.h> | |
26 | #include "hw.h" | |
492c30af AL |
27 | #include "qemu-common.h" |
28 | #include "sysemu.h" | |
1ba13a5d EI |
29 | |
30 | #include "etraxfs_dma.h" | |
31 | ||
32 | #define D(x) | |
33 | ||
34 | #define RW_DATA 0x0 | |
35 | #define RW_SAVED_DATA 0x58 | |
36 | #define RW_SAVED_DATA_BUF 0x5c | |
37 | #define RW_GROUP 0x60 | |
38 | #define RW_GROUP_DOWN 0x7c | |
39 | #define RW_CMD 0x80 | |
40 | #define RW_CFG 0x84 | |
41 | #define RW_STAT 0x88 | |
42 | #define RW_INTR_MASK 0x8c | |
43 | #define RW_ACK_INTR 0x90 | |
44 | #define R_INTR 0x94 | |
45 | #define R_MASKED_INTR 0x98 | |
46 | #define RW_STREAM_CMD 0x9c | |
47 | ||
48 | #define DMA_REG_MAX 0x100 | |
49 | ||
50 | /* descriptors */ | |
51 | ||
52 | // ------------------------------------------------------------ dma_descr_group | |
53 | typedef struct dma_descr_group { | |
54 | struct dma_descr_group *next; | |
55 | unsigned eol : 1; | |
56 | unsigned tol : 1; | |
57 | unsigned bol : 1; | |
58 | unsigned : 1; | |
59 | unsigned intr : 1; | |
60 | unsigned : 2; | |
61 | unsigned en : 1; | |
62 | unsigned : 7; | |
63 | unsigned dis : 1; | |
64 | unsigned md : 16; | |
65 | struct dma_descr_group *up; | |
66 | union { | |
67 | struct dma_descr_context *context; | |
68 | struct dma_descr_group *group; | |
69 | } down; | |
70 | } dma_descr_group; | |
71 | ||
72 | // ---------------------------------------------------------- dma_descr_context | |
73 | typedef struct dma_descr_context { | |
74 | struct dma_descr_context *next; | |
75 | unsigned eol : 1; | |
76 | unsigned : 3; | |
77 | unsigned intr : 1; | |
78 | unsigned : 1; | |
79 | unsigned store_mode : 1; | |
80 | unsigned en : 1; | |
81 | unsigned : 7; | |
82 | unsigned dis : 1; | |
83 | unsigned md0 : 16; | |
84 | unsigned md1; | |
85 | unsigned md2; | |
86 | unsigned md3; | |
87 | unsigned md4; | |
88 | struct dma_descr_data *saved_data; | |
89 | char *saved_data_buf; | |
90 | } dma_descr_context; | |
91 | ||
92 | // ------------------------------------------------------------- dma_descr_data | |
93 | typedef struct dma_descr_data { | |
94 | struct dma_descr_data *next; | |
95 | char *buf; | |
96 | unsigned eol : 1; | |
97 | unsigned : 2; | |
98 | unsigned out_eop : 1; | |
99 | unsigned intr : 1; | |
100 | unsigned wait : 1; | |
101 | unsigned : 2; | |
102 | unsigned : 3; | |
103 | unsigned in_eop : 1; | |
104 | unsigned : 4; | |
105 | unsigned md : 16; | |
106 | char *after; | |
107 | } dma_descr_data; | |
108 | ||
109 | /* Constants */ | |
110 | enum { | |
111 | regk_dma_ack_pkt = 0x00000100, | |
112 | regk_dma_anytime = 0x00000001, | |
113 | regk_dma_array = 0x00000008, | |
114 | regk_dma_burst = 0x00000020, | |
115 | regk_dma_client = 0x00000002, | |
116 | regk_dma_copy_next = 0x00000010, | |
117 | regk_dma_copy_up = 0x00000020, | |
118 | regk_dma_data_at_eol = 0x00000001, | |
119 | regk_dma_dis_c = 0x00000010, | |
120 | regk_dma_dis_g = 0x00000020, | |
121 | regk_dma_idle = 0x00000001, | |
122 | regk_dma_intern = 0x00000004, | |
123 | regk_dma_load_c = 0x00000200, | |
124 | regk_dma_load_c_n = 0x00000280, | |
125 | regk_dma_load_c_next = 0x00000240, | |
126 | regk_dma_load_d = 0x00000140, | |
127 | regk_dma_load_g = 0x00000300, | |
128 | regk_dma_load_g_down = 0x000003c0, | |
129 | regk_dma_load_g_next = 0x00000340, | |
130 | regk_dma_load_g_up = 0x00000380, | |
131 | regk_dma_next_en = 0x00000010, | |
132 | regk_dma_next_pkt = 0x00000010, | |
133 | regk_dma_no = 0x00000000, | |
134 | regk_dma_only_at_wait = 0x00000000, | |
135 | regk_dma_restore = 0x00000020, | |
136 | regk_dma_rst = 0x00000001, | |
137 | regk_dma_running = 0x00000004, | |
138 | regk_dma_rw_cfg_default = 0x00000000, | |
139 | regk_dma_rw_cmd_default = 0x00000000, | |
140 | regk_dma_rw_intr_mask_default = 0x00000000, | |
141 | regk_dma_rw_stat_default = 0x00000101, | |
142 | regk_dma_rw_stream_cmd_default = 0x00000000, | |
143 | regk_dma_save_down = 0x00000020, | |
144 | regk_dma_save_up = 0x00000020, | |
145 | regk_dma_set_reg = 0x00000050, | |
146 | regk_dma_set_w_size1 = 0x00000190, | |
147 | regk_dma_set_w_size2 = 0x000001a0, | |
148 | regk_dma_set_w_size4 = 0x000001c0, | |
149 | regk_dma_stopped = 0x00000002, | |
150 | regk_dma_store_c = 0x00000002, | |
151 | regk_dma_store_descr = 0x00000000, | |
152 | regk_dma_store_g = 0x00000004, | |
153 | regk_dma_store_md = 0x00000001, | |
154 | regk_dma_sw = 0x00000008, | |
155 | regk_dma_update_down = 0x00000020, | |
156 | regk_dma_yes = 0x00000001 | |
157 | }; | |
158 | ||
159 | enum dma_ch_state | |
160 | { | |
4487fd34 | 161 | RST = 1, |
1ba13a5d EI |
162 | STOPPED = 2, |
163 | RUNNING = 4 | |
164 | }; | |
165 | ||
166 | struct fs_dma_channel | |
167 | { | |
168 | int regmap; | |
169 | qemu_irq *irq; | |
170 | struct etraxfs_dma_client *client; | |
171 | ||
172 | ||
173 | /* Internal status. */ | |
174 | int stream_cmd_src; | |
175 | enum dma_ch_state state; | |
176 | ||
177 | unsigned int input : 1; | |
178 | unsigned int eol : 1; | |
179 | ||
180 | struct dma_descr_group current_g; | |
181 | struct dma_descr_context current_c; | |
182 | struct dma_descr_data current_d; | |
183 | ||
184 | /* Controll registers. */ | |
185 | uint32_t regs[DMA_REG_MAX]; | |
186 | }; | |
187 | ||
188 | struct fs_dma_ctrl | |
189 | { | |
190 | CPUState *env; | |
191 | target_phys_addr_t base; | |
192 | ||
193 | int nr_channels; | |
194 | struct fs_dma_channel *channels; | |
492c30af AL |
195 | |
196 | QEMUBH *bh; | |
1ba13a5d EI |
197 | }; |
198 | ||
199 | static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg) | |
200 | { | |
201 | return ctrl->channels[c].regs[reg]; | |
202 | } | |
203 | ||
204 | static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c) | |
205 | { | |
206 | return channel_reg(ctrl, c, RW_CFG) & 2; | |
207 | } | |
208 | ||
209 | static inline int channel_en(struct fs_dma_ctrl *ctrl, int c) | |
210 | { | |
211 | return (channel_reg(ctrl, c, RW_CFG) & 1) | |
212 | && ctrl->channels[c].client; | |
213 | } | |
214 | ||
215 | static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr) | |
216 | { | |
217 | /* Every channel has a 0x2000 ctrl register map. */ | |
218 | return (addr - base) >> 13; | |
219 | } | |
220 | ||
d297f464 | 221 | #ifdef USE_THIS_DEAD_CODE |
1ba13a5d EI |
222 | static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) |
223 | { | |
224 | target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP); | |
225 | ||
226 | /* Load and decode. FIXME: handle endianness. */ | |
227 | cpu_physical_memory_read (addr, | |
228 | (void *) &ctrl->channels[c].current_g, | |
229 | sizeof ctrl->channels[c].current_g); | |
230 | } | |
231 | ||
232 | static void dump_c(int ch, struct dma_descr_context *c) | |
233 | { | |
234 | printf("%s ch=%d\n", __func__, ch); | |
d297f464 EI |
235 | printf("next=%p\n", c->next); |
236 | printf("saved_data=%p\n", c->saved_data); | |
237 | printf("saved_data_buf=%p\n", c->saved_data_buf); | |
1ba13a5d EI |
238 | printf("eol=%x\n", (uint32_t) c->eol); |
239 | } | |
240 | ||
241 | static void dump_d(int ch, struct dma_descr_data *d) | |
242 | { | |
243 | printf("%s ch=%d\n", __func__, ch); | |
d297f464 EI |
244 | printf("next=%p\n", d->next); |
245 | printf("buf=%p\n", d->buf); | |
246 | printf("after=%p\n", d->after); | |
1ba13a5d EI |
247 | printf("intr=%x\n", (uint32_t) d->intr); |
248 | printf("out_eop=%x\n", (uint32_t) d->out_eop); | |
249 | printf("in_eop=%x\n", (uint32_t) d->in_eop); | |
250 | printf("eol=%x\n", (uint32_t) d->eol); | |
251 | } | |
d297f464 | 252 | #endif |
1ba13a5d EI |
253 | |
254 | static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) | |
255 | { | |
256 | target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); | |
257 | ||
258 | /* Load and decode. FIXME: handle endianness. */ | |
259 | cpu_physical_memory_read (addr, | |
260 | (void *) &ctrl->channels[c].current_c, | |
261 | sizeof ctrl->channels[c].current_c); | |
262 | ||
263 | D(dump_c(c, &ctrl->channels[c].current_c)); | |
264 | /* I guess this should update the current pos. */ | |
d297f464 EI |
265 | ctrl->channels[c].regs[RW_SAVED_DATA] = |
266 | (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data; | |
1ba13a5d | 267 | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
d297f464 | 268 | (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf; |
1ba13a5d EI |
269 | } |
270 | ||
271 | static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) | |
272 | { | |
273 | target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); | |
274 | ||
275 | /* Load and decode. FIXME: handle endianness. */ | |
a8303d18 | 276 | D(printf("%s ch=%d addr=%x\n", __func__, c, addr)); |
1ba13a5d EI |
277 | cpu_physical_memory_read (addr, |
278 | (void *) &ctrl->channels[c].current_d, | |
279 | sizeof ctrl->channels[c].current_d); | |
280 | ||
281 | D(dump_d(c, &ctrl->channels[c].current_d)); | |
fa1bdde4 | 282 | ctrl->channels[c].regs[RW_DATA] = addr; |
a8303d18 EI |
283 | } |
284 | ||
285 | static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) | |
286 | { | |
287 | target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); | |
288 | ||
289 | /* Encode and store. FIXME: handle endianness. */ | |
290 | D(printf("%s ch=%d addr=%x\n", __func__, c, addr)); | |
291 | D(dump_d(c, &ctrl->channels[c].current_d)); | |
292 | cpu_physical_memory_write (addr, | |
293 | (void *) &ctrl->channels[c].current_c, | |
294 | sizeof ctrl->channels[c].current_c); | |
1ba13a5d EI |
295 | } |
296 | ||
297 | static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) | |
298 | { | |
299 | target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); | |
300 | ||
a8303d18 EI |
301 | /* Encode and store. FIXME: handle endianness. */ |
302 | D(printf("%s ch=%d addr=%x\n", __func__, c, addr)); | |
1ba13a5d EI |
303 | cpu_physical_memory_write (addr, |
304 | (void *) &ctrl->channels[c].current_d, | |
305 | sizeof ctrl->channels[c].current_d); | |
306 | } | |
307 | ||
308 | static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) | |
309 | { | |
310 | /* FIXME: */ | |
311 | } | |
312 | ||
313 | static inline void channel_start(struct fs_dma_ctrl *ctrl, int c) | |
314 | { | |
315 | if (ctrl->channels[c].client) | |
316 | { | |
317 | ctrl->channels[c].eol = 0; | |
318 | ctrl->channels[c].state = RUNNING; | |
319 | } else | |
320 | printf("WARNING: starting DMA ch %d with no client\n", c); | |
321 | } | |
322 | ||
323 | static void channel_continue(struct fs_dma_ctrl *ctrl, int c) | |
324 | { | |
325 | if (!channel_en(ctrl, c) | |
326 | || channel_stopped(ctrl, c) | |
327 | || ctrl->channels[c].state != RUNNING | |
328 | /* Only reload the current data descriptor if it has eol set. */ | |
329 | || !ctrl->channels[c].current_d.eol) { | |
330 | D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n", | |
331 | c, ctrl->channels[c].state, | |
332 | channel_stopped(ctrl, c), | |
333 | channel_en(ctrl,c), | |
334 | ctrl->channels[c].eol)); | |
335 | D(dump_d(c, &ctrl->channels[c].current_d)); | |
336 | return; | |
337 | } | |
338 | ||
339 | /* Reload the current descriptor. */ | |
340 | channel_load_d(ctrl, c); | |
341 | ||
342 | /* If the current descriptor cleared the eol flag and we had already | |
343 | reached eol state, do the continue. */ | |
344 | if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) { | |
a8303d18 | 345 | D(printf("continue %d ok %p\n", c, |
1ba13a5d EI |
346 | ctrl->channels[c].current_d.next)); |
347 | ctrl->channels[c].regs[RW_SAVED_DATA] = | |
d297f464 | 348 | (uint32_t)(unsigned long)ctrl->channels[c].current_d.next; |
1ba13a5d EI |
349 | channel_load_d(ctrl, c); |
350 | channel_start(ctrl, c); | |
351 | } | |
a8303d18 | 352 | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
d297f464 | 353 | (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; |
1ba13a5d EI |
354 | } |
355 | ||
356 | static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v) | |
357 | { | |
358 | unsigned int cmd = v & ((1 << 10) - 1); | |
359 | ||
d27b2e50 EI |
360 | D(printf("%s ch=%d cmd=%x\n", |
361 | __func__, c, cmd)); | |
1ba13a5d EI |
362 | if (cmd & regk_dma_load_d) { |
363 | channel_load_d(ctrl, c); | |
364 | if (cmd & regk_dma_burst) | |
365 | channel_start(ctrl, c); | |
366 | } | |
367 | ||
368 | if (cmd & regk_dma_load_c) { | |
369 | channel_load_c(ctrl, c); | |
a8303d18 | 370 | channel_start(ctrl, c); |
1ba13a5d EI |
371 | } |
372 | } | |
373 | ||
374 | static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c) | |
375 | { | |
376 | D(printf("%s %d\n", __func__, c)); | |
377 | ctrl->channels[c].regs[R_INTR] &= | |
378 | ~(ctrl->channels[c].regs[RW_ACK_INTR]); | |
379 | ||
380 | ctrl->channels[c].regs[R_MASKED_INTR] = | |
381 | ctrl->channels[c].regs[R_INTR] | |
382 | & ctrl->channels[c].regs[RW_INTR_MASK]; | |
383 | ||
384 | D(printf("%s: chan=%d masked_intr=%x\n", __func__, | |
385 | c, | |
386 | ctrl->channels[c].regs[R_MASKED_INTR])); | |
387 | ||
388 | if (ctrl->channels[c].regs[R_MASKED_INTR]) | |
389 | qemu_irq_raise(ctrl->channels[c].irq[0]); | |
390 | else | |
391 | qemu_irq_lower(ctrl->channels[c].irq[0]); | |
392 | } | |
393 | ||
394 | static void channel_out_run(struct fs_dma_ctrl *ctrl, int c) | |
395 | { | |
396 | uint32_t len; | |
397 | uint32_t saved_data_buf; | |
398 | unsigned char buf[2 * 1024]; | |
399 | ||
c968ef8d EI |
400 | while (ctrl->channels[c].eol != 1) { |
401 | saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); | |
402 | ||
403 | D(printf("ch=%d buf=%x after=%x saved_data_buf=%x\n", | |
404 | c, | |
405 | (uint32_t)ctrl->channels[c].current_d.buf, | |
406 | (uint32_t)ctrl->channels[c].current_d.after, | |
407 | saved_data_buf)); | |
408 | ||
ea0f49a7 EI |
409 | len = (uint32_t)(unsigned long) |
410 | ctrl->channels[c].current_d.after; | |
c968ef8d EI |
411 | len -= saved_data_buf; |
412 | ||
413 | if (len > sizeof buf) | |
414 | len = sizeof buf; | |
415 | cpu_physical_memory_read (saved_data_buf, buf, len); | |
416 | ||
417 | D(printf("channel %d pushes %x %u bytes\n", c, | |
418 | saved_data_buf, len)); | |
419 | ||
420 | if (ctrl->channels[c].client->client.push) | |
421 | ctrl->channels[c].client->client.push( | |
422 | ctrl->channels[c].client->client.opaque, | |
423 | buf, len); | |
424 | else | |
425 | printf("WARNING: DMA ch%d dataloss," | |
426 | " no attached client.\n", c); | |
427 | ||
428 | saved_data_buf += len; | |
429 | ||
ea0f49a7 EI |
430 | if (saved_data_buf == (uint32_t)(unsigned long) |
431 | ctrl->channels[c].current_d.after) { | |
c968ef8d EI |
432 | /* Done. Step to next. */ |
433 | if (ctrl->channels[c].current_d.out_eop) { | |
434 | /* TODO: signal eop to the client. */ | |
435 | D(printf("signal eop\n")); | |
436 | } | |
437 | if (ctrl->channels[c].current_d.intr) { | |
438 | /* TODO: signal eop to the client. */ | |
439 | /* data intr. */ | |
440 | D(printf("signal intr\n")); | |
441 | ctrl->channels[c].regs[R_INTR] |= (1 << 2); | |
442 | channel_update_irq(ctrl, c); | |
443 | } | |
444 | if (ctrl->channels[c].current_d.eol) { | |
445 | D(printf("channel %d EOL\n", c)); | |
446 | ctrl->channels[c].eol = 1; | |
447 | ||
448 | /* Mark the context as disabled. */ | |
449 | ctrl->channels[c].current_c.dis = 1; | |
450 | channel_store_c(ctrl, c); | |
451 | ||
452 | channel_stop(ctrl, c); | |
453 | } else { | |
454 | ctrl->channels[c].regs[RW_SAVED_DATA] = | |
ea0f49a7 EI |
455 | (uint32_t)(unsigned long)ctrl-> |
456 | channels[c].current_d.next; | |
c968ef8d EI |
457 | /* Load new descriptor. */ |
458 | channel_load_d(ctrl, c); | |
459 | saved_data_buf = (uint32_t)(unsigned long) | |
460 | ctrl->channels[c].current_d.buf; | |
461 | } | |
462 | ||
463 | channel_store_d(ctrl, c); | |
464 | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = | |
465 | saved_data_buf; | |
466 | D(dump_d(c, &ctrl->channels[c].current_d)); | |
1ba13a5d | 467 | } |
a8303d18 | 468 | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
1ba13a5d | 469 | } |
1ba13a5d EI |
470 | } |
471 | ||
472 | static int channel_in_process(struct fs_dma_ctrl *ctrl, int c, | |
473 | unsigned char *buf, int buflen, int eop) | |
474 | { | |
475 | uint32_t len; | |
476 | uint32_t saved_data_buf; | |
477 | ||
478 | if (ctrl->channels[c].eol == 1) | |
479 | return 0; | |
480 | ||
481 | saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); | |
ea0f49a7 | 482 | len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after; |
1ba13a5d EI |
483 | len -= saved_data_buf; |
484 | ||
485 | if (len > buflen) | |
486 | len = buflen; | |
487 | ||
488 | cpu_physical_memory_write (saved_data_buf, buf, len); | |
489 | saved_data_buf += len; | |
490 | ||
d297f464 | 491 | if (saved_data_buf == |
ea0f49a7 | 492 | (uint32_t)(unsigned long)ctrl->channels[c].current_d.after |
1ba13a5d EI |
493 | || eop) { |
494 | uint32_t r_intr = ctrl->channels[c].regs[R_INTR]; | |
495 | ||
496 | D(printf("in dscr end len=%d\n", | |
497 | ctrl->channels[c].current_d.after | |
498 | - ctrl->channels[c].current_d.buf)); | |
499 | ctrl->channels[c].current_d.after = | |
d297f464 | 500 | (void *)(unsigned long) saved_data_buf; |
1ba13a5d EI |
501 | |
502 | /* Done. Step to next. */ | |
503 | if (ctrl->channels[c].current_d.intr) { | |
504 | /* TODO: signal eop to the client. */ | |
505 | /* data intr. */ | |
506 | ctrl->channels[c].regs[R_INTR] |= 3; | |
507 | } | |
508 | if (eop) { | |
509 | ctrl->channels[c].current_d.in_eop = 1; | |
510 | ctrl->channels[c].regs[R_INTR] |= 8; | |
511 | } | |
512 | if (r_intr != ctrl->channels[c].regs[R_INTR]) | |
513 | channel_update_irq(ctrl, c); | |
514 | ||
515 | channel_store_d(ctrl, c); | |
516 | D(dump_d(c, &ctrl->channels[c].current_d)); | |
517 | ||
518 | if (ctrl->channels[c].current_d.eol) { | |
519 | D(printf("channel %d EOL\n", c)); | |
520 | ctrl->channels[c].eol = 1; | |
a8303d18 EI |
521 | |
522 | /* Mark the context as disabled. */ | |
523 | ctrl->channels[c].current_c.dis = 1; | |
524 | channel_store_c(ctrl, c); | |
525 | ||
1ba13a5d EI |
526 | channel_stop(ctrl, c); |
527 | } else { | |
528 | ctrl->channels[c].regs[RW_SAVED_DATA] = | |
ea0f49a7 EI |
529 | (uint32_t)(unsigned long)ctrl-> |
530 | channels[c].current_d.next; | |
1ba13a5d EI |
531 | /* Load new descriptor. */ |
532 | channel_load_d(ctrl, c); | |
ea0f49a7 | 533 | saved_data_buf = (uint32_t)(unsigned long) |
a8303d18 | 534 | ctrl->channels[c].current_d.buf; |
1ba13a5d EI |
535 | } |
536 | } | |
537 | ||
538 | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; | |
539 | return len; | |
540 | } | |
541 | ||
542 | static inline void channel_in_run(struct fs_dma_ctrl *ctrl, int c) | |
543 | { | |
544 | if (ctrl->channels[c].client->client.pull) | |
545 | ctrl->channels[c].client->client.pull( | |
546 | ctrl->channels[c].client->client.opaque); | |
547 | } | |
548 | ||
549 | static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr) | |
550 | { | |
551 | struct fs_dma_ctrl *ctrl = opaque; | |
552 | CPUState *env = ctrl->env; | |
d27b2e50 EI |
553 | cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
554 | addr); | |
1ba13a5d EI |
555 | return 0; |
556 | } | |
557 | ||
558 | static uint32_t | |
559 | dma_readl (void *opaque, target_phys_addr_t addr) | |
560 | { | |
561 | struct fs_dma_ctrl *ctrl = opaque; | |
562 | int c; | |
563 | uint32_t r = 0; | |
564 | ||
565 | /* Make addr relative to this instances base. */ | |
566 | c = fs_channel(ctrl->base, addr); | |
a8303d18 | 567 | addr &= 0x1fff; |
1ba13a5d | 568 | switch (addr) |
a8303d18 | 569 | { |
1ba13a5d EI |
570 | case RW_STAT: |
571 | r = ctrl->channels[c].state & 7; | |
572 | r |= ctrl->channels[c].eol << 5; | |
573 | r |= ctrl->channels[c].stream_cmd_src << 8; | |
574 | break; | |
575 | ||
a8303d18 | 576 | default: |
1ba13a5d | 577 | r = ctrl->channels[c].regs[addr]; |
d27b2e50 EI |
578 | D(printf ("%s c=%d addr=%x\n", |
579 | __func__, c, addr)); | |
a8303d18 EI |
580 | break; |
581 | } | |
1ba13a5d EI |
582 | return r; |
583 | } | |
584 | ||
585 | static void | |
586 | dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value) | |
587 | { | |
588 | struct fs_dma_ctrl *ctrl = opaque; | |
589 | CPUState *env = ctrl->env; | |
d27b2e50 EI |
590 | cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
591 | addr); | |
1ba13a5d EI |
592 | } |
593 | ||
4487fd34 EI |
594 | static void |
595 | dma_update_state(struct fs_dma_ctrl *ctrl, int c) | |
596 | { | |
597 | if ((ctrl->channels[c].regs[RW_CFG] & 1) != 3) { | |
598 | if (ctrl->channels[c].regs[RW_CFG] & 2) | |
599 | ctrl->channels[c].state = STOPPED; | |
600 | if (!(ctrl->channels[c].regs[RW_CFG] & 1)) | |
601 | ctrl->channels[c].state = RST; | |
602 | } | |
603 | } | |
604 | ||
1ba13a5d EI |
605 | static void |
606 | dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value) | |
607 | { | |
608 | struct fs_dma_ctrl *ctrl = opaque; | |
609 | int c; | |
610 | ||
611 | /* Make addr relative to this instances base. */ | |
612 | c = fs_channel(ctrl->base, addr); | |
613 | addr &= 0x1fff; | |
614 | switch (addr) | |
a8303d18 | 615 | { |
1ba13a5d | 616 | case RW_DATA: |
fa1bdde4 | 617 | ctrl->channels[c].regs[addr] = value; |
1ba13a5d EI |
618 | break; |
619 | ||
620 | case RW_CFG: | |
621 | ctrl->channels[c].regs[addr] = value; | |
4487fd34 | 622 | dma_update_state(ctrl, c); |
1ba13a5d EI |
623 | break; |
624 | case RW_CMD: | |
625 | /* continue. */ | |
4487fd34 EI |
626 | if (value & ~1) |
627 | printf("Invalid store to ch=%d RW_CMD %x\n", | |
628 | c, value); | |
1ba13a5d EI |
629 | ctrl->channels[c].regs[addr] = value; |
630 | channel_continue(ctrl, c); | |
631 | break; | |
632 | ||
633 | case RW_SAVED_DATA: | |
634 | case RW_SAVED_DATA_BUF: | |
635 | case RW_GROUP: | |
636 | case RW_GROUP_DOWN: | |
637 | ctrl->channels[c].regs[addr] = value; | |
638 | break; | |
639 | ||
640 | case RW_ACK_INTR: | |
641 | case RW_INTR_MASK: | |
642 | ctrl->channels[c].regs[addr] = value; | |
643 | channel_update_irq(ctrl, c); | |
644 | if (addr == RW_ACK_INTR) | |
645 | ctrl->channels[c].regs[RW_ACK_INTR] = 0; | |
646 | break; | |
647 | ||
648 | case RW_STREAM_CMD: | |
4487fd34 EI |
649 | if (value & ~1023) |
650 | printf("Invalid store to ch=%d " | |
651 | "RW_STREAMCMD %x\n", | |
652 | c, value); | |
1ba13a5d | 653 | ctrl->channels[c].regs[addr] = value; |
d27b2e50 | 654 | D(printf("stream_cmd ch=%d\n", c)); |
1ba13a5d EI |
655 | channel_stream_cmd(ctrl, c, value); |
656 | break; | |
657 | ||
a8303d18 | 658 | default: |
d27b2e50 | 659 | D(printf ("%s c=%d %x %x\n", __func__, c, addr)); |
a8303d18 | 660 | break; |
1ba13a5d EI |
661 | } |
662 | } | |
663 | ||
664 | static CPUReadMemoryFunc *dma_read[] = { | |
665 | &dma_rinvalid, | |
666 | &dma_rinvalid, | |
667 | &dma_readl, | |
668 | }; | |
669 | ||
670 | static CPUWriteMemoryFunc *dma_write[] = { | |
671 | &dma_winvalid, | |
672 | &dma_winvalid, | |
673 | &dma_writel, | |
674 | }; | |
675 | ||
2c99f725 | 676 | static void etraxfs_dmac_run(void *opaque) |
1ba13a5d EI |
677 | { |
678 | struct fs_dma_ctrl *ctrl = opaque; | |
679 | int i; | |
680 | int p = 0; | |
681 | ||
682 | for (i = 0; | |
683 | i < ctrl->nr_channels; | |
684 | i++) | |
685 | { | |
686 | if (ctrl->channels[i].state == RUNNING) | |
687 | { | |
688 | p++; | |
689 | if (ctrl->channels[i].input) | |
690 | channel_in_run(ctrl, i); | |
691 | else | |
692 | channel_out_run(ctrl, i); | |
693 | } | |
694 | } | |
695 | } | |
696 | ||
697 | int etraxfs_dmac_input(struct etraxfs_dma_client *client, | |
698 | void *buf, int len, int eop) | |
699 | { | |
700 | return channel_in_process(client->ctrl, client->channel, | |
701 | buf, len, eop); | |
702 | } | |
703 | ||
704 | /* Connect an IRQ line with a channel. */ | |
705 | void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input) | |
706 | { | |
707 | struct fs_dma_ctrl *ctrl = opaque; | |
708 | ctrl->channels[c].irq = line; | |
709 | ctrl->channels[c].input = input; | |
710 | } | |
711 | ||
712 | void etraxfs_dmac_connect_client(void *opaque, int c, | |
713 | struct etraxfs_dma_client *cl) | |
714 | { | |
715 | struct fs_dma_ctrl *ctrl = opaque; | |
716 | cl->ctrl = ctrl; | |
717 | cl->channel = c; | |
718 | ctrl->channels[c].client = cl; | |
719 | } | |
720 | ||
721 | ||
492c30af | 722 | static void DMA_run(void *opaque) |
fa1bdde4 | 723 | { |
492c30af AL |
724 | struct fs_dma_ctrl *etraxfs_dmac = opaque; |
725 | if (vm_running) | |
726 | etraxfs_dmac_run(etraxfs_dmac); | |
727 | qemu_bh_schedule_idle(etraxfs_dmac->bh); | |
fa1bdde4 EI |
728 | } |
729 | ||
1ba13a5d EI |
730 | void *etraxfs_dmac_init(CPUState *env, |
731 | target_phys_addr_t base, int nr_channels) | |
732 | { | |
733 | struct fs_dma_ctrl *ctrl = NULL; | |
734 | int i; | |
735 | ||
736 | ctrl = qemu_mallocz(sizeof *ctrl); | |
737 | if (!ctrl) | |
738 | return NULL; | |
739 | ||
492c30af AL |
740 | ctrl->bh = qemu_bh_new(DMA_run, ctrl); |
741 | qemu_bh_schedule_idle(ctrl->bh); | |
742 | ||
1ba13a5d EI |
743 | ctrl->base = base; |
744 | ctrl->env = env; | |
745 | ctrl->nr_channels = nr_channels; | |
746 | ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels); | |
747 | if (!ctrl->channels) | |
748 | goto err; | |
749 | ||
750 | for (i = 0; i < nr_channels; i++) | |
751 | { | |
752 | ctrl->channels[i].regmap = cpu_register_io_memory(0, | |
753 | dma_read, | |
754 | dma_write, | |
755 | ctrl); | |
756 | cpu_register_physical_memory (base + i * 0x2000, | |
757 | sizeof ctrl->channels[i].regs, | |
758 | ctrl->channels[i].regmap); | |
759 | } | |
760 | ||
761 | return ctrl; | |
762 | err: | |
763 | qemu_free(ctrl->channels); | |
764 | qemu_free(ctrl); | |
765 | return NULL; | |
766 | } |