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e62b5b13 EI |
1 | /* |
2 | * QEMU ETRAX Interrupt Controller. | |
3 | * | |
4 | * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include <stdio.h> | |
26 | #include "hw.h" | |
27 | ||
28 | #define D(x) | |
29 | ||
30 | struct fs_pic_state_t | |
31 | { | |
32 | CPUState *env; | |
ca87d03b | 33 | target_phys_addr_t base; |
e62b5b13 EI |
34 | |
35 | uint32_t rw_mask; | |
36 | /* Active interrupt lines. */ | |
37 | uint32_t r_vect; | |
38 | /* Active lines, gated through the mask. */ | |
39 | uint32_t r_masked_vect; | |
40 | uint32_t r_nmi; | |
41 | uint32_t r_guru; | |
42 | }; | |
43 | ||
44 | static uint32_t pic_readb (void *opaque, target_phys_addr_t addr) | |
45 | { | |
46 | return 0; | |
47 | } | |
48 | static uint32_t pic_readw (void *opaque, target_phys_addr_t addr) | |
49 | { | |
50 | return 0; | |
51 | } | |
52 | ||
53 | static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) | |
54 | { | |
55 | struct fs_pic_state_t *fs = opaque; | |
56 | uint32_t rval; | |
57 | ||
58 | /* Transform this to a relative addr. */ | |
59 | addr -= fs->base; | |
60 | switch (addr) | |
61 | { | |
62 | case 0x0: | |
63 | rval = fs->rw_mask; | |
64 | break; | |
65 | case 0x4: | |
66 | rval = fs->r_vect; | |
67 | break; | |
68 | case 0x8: | |
69 | rval = fs->r_masked_vect; | |
70 | break; | |
71 | case 0xc: | |
72 | rval = fs->r_nmi; | |
73 | break; | |
74 | case 0x10: | |
75 | rval = fs->r_guru; | |
76 | break; | |
77 | default: | |
78 | cpu_abort(fs->env, "invalid PIC register.\n"); | |
79 | break; | |
80 | ||
81 | } | |
82 | D(printf("%s %x=%x\n", __func__, addr, rval)); | |
83 | return rval; | |
84 | } | |
85 | ||
86 | static void | |
87 | pic_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) | |
88 | { | |
89 | } | |
90 | ||
91 | static void | |
92 | pic_writew (void *opaque, target_phys_addr_t addr, uint32_t value) | |
93 | { | |
94 | } | |
95 | ||
96 | static void | |
97 | pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) | |
98 | { | |
99 | struct fs_pic_state_t *fs = opaque; | |
100 | D(printf("%s addr=%x val=%x\n", __func__, addr, value)); | |
101 | /* Transform this to a relative addr. */ | |
102 | addr -= fs->base; | |
103 | switch (addr) | |
104 | { | |
105 | case 0x0: | |
106 | fs->rw_mask = value; | |
107 | break; | |
108 | case 0x4: | |
109 | fs->r_vect = value; | |
110 | break; | |
111 | case 0x8: | |
112 | fs->r_masked_vect = value; | |
113 | break; | |
114 | case 0xc: | |
115 | fs->r_nmi = value; | |
116 | break; | |
117 | case 0x10: | |
118 | fs->r_guru = value; | |
119 | break; | |
120 | default: | |
121 | cpu_abort(fs->env, "invalid PIC register.\n"); | |
122 | break; | |
123 | } | |
124 | } | |
125 | ||
126 | static CPUReadMemoryFunc *pic_read[] = { | |
127 | &pic_readb, | |
128 | &pic_readw, | |
129 | &pic_readl, | |
130 | }; | |
131 | ||
132 | static CPUWriteMemoryFunc *pic_write[] = { | |
133 | &pic_writeb, | |
134 | &pic_writew, | |
135 | &pic_writel, | |
136 | }; | |
137 | ||
138 | void pic_info(void) | |
139 | { | |
140 | } | |
141 | ||
142 | void irq_info(void) | |
143 | { | |
144 | } | |
145 | ||
146 | static void etraxfs_pic_handler(void *opaque, int irq, int level) | |
147 | { | |
148 | struct fs_pic_state_t *fs = (void *)opaque; | |
149 | CPUState *env = fs->env; | |
150 | int i; | |
151 | uint32_t vector = 0; | |
152 | ||
153 | D(printf("%s irq=%d level=%d mask=%x v=%x mv=%x\n", | |
154 | __func__, irq, level, | |
155 | fs->rw_mask, fs->r_vect, fs->r_masked_vect)); | |
156 | ||
157 | fs->r_vect &= ~(1 << irq); | |
158 | fs->r_vect |= (!!level << irq); | |
159 | fs->r_masked_vect = fs->r_vect & fs->rw_mask; | |
160 | ||
161 | /* The ETRAX interrupt controller signals interrupts to teh core | |
162 | through an interrupt request wire and an irq vector bus. If | |
163 | multiple interrupts are simultaneously active it chooses vector | |
164 | 0x30 and lets the sw choose the priorities. */ | |
165 | if (fs->r_masked_vect) { | |
166 | uint32_t mv = fs->r_masked_vect; | |
167 | for (i = 0; i < 31; i++) { | |
168 | if (mv & 1) { | |
169 | vector = 0x31 + i; | |
170 | /* Check for multiple interrupts. */ | |
171 | if (mv > 1) | |
172 | vector = 0x30; | |
173 | break; | |
174 | } | |
175 | mv >>= 1; | |
176 | } | |
177 | if (vector) { | |
178 | env->interrupt_vector = vector; | |
179 | D(printf("%s vector=%x\n", __func__, vector)); | |
180 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
181 | } | |
182 | } else { | |
183 | env->interrupt_vector = 0; | |
184 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
185 | D(printf("%s reset irqs\n", __func__)); | |
186 | } | |
187 | } | |
188 | ||
ca87d03b | 189 | qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base) |
e62b5b13 EI |
190 | { |
191 | struct fs_pic_state_t *fs; | |
192 | qemu_irq *pic; | |
193 | int intr_vect_regs; | |
194 | ||
195 | fs = qemu_mallocz(sizeof *fs); | |
196 | if (!fs) | |
197 | return NULL; | |
198 | fs->env = env; | |
199 | ||
200 | pic = qemu_allocate_irqs(etraxfs_pic_handler, fs, 30); | |
201 | ||
202 | intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs); | |
203 | cpu_register_physical_memory(base, 0x14, intr_vect_regs); | |
204 | fs->base = base; | |
205 | ||
206 | return pic; | |
207 | } |