[mirror_qemu.git] / hw / etraxfs_ser.c

/*
 * QEMU ETRAX System Emulator
 *
 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "qemu-char.h"
#include "qemu-log.h"

#define D(x)

#define RW_TR_CTRL     (0x00 / 4)
#define RW_TR_DMA_EN   (0x04 / 4)
#define RW_REC_CTRL    (0x08 / 4)
#define RW_DOUT        (0x1c / 4)
#define RS_STAT_DIN    (0x20 / 4)
#define R_STAT_DIN     (0x24 / 4)
#define RW_INTR_MASK   (0x2c / 4)
#define RW_ACK_INTR    (0x30 / 4)
#define R_INTR         (0x34 / 4)
#define R_MASKED_INTR  (0x38 / 4)
#define R_MAX          (0x3c / 4)

#define STAT_DAV     16
#define STAT_TR_IDLE 22
#define STAT_TR_RDY  24

struct etrax_serial
{
    SysBusDevice busdev;
    CharDriverState *chr;
    qemu_irq irq;

    int pending_tx;

    uint8_t rx_fifo[16];
    unsigned int rx_fifo_pos;
    unsigned int rx_fifo_len;

    /* Control registers.  */
    uint32_t regs[R_MAX];
};

static void ser_update_irq(struct etrax_serial *s)
{

    if (s->rx_fifo_len) {
        s->regs[R_INTR] |= 8;
    } else {
        s->regs[R_INTR] &= ~8;
    }

    s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
    qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
}

static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
{
    struct etrax_serial *s = opaque;
    D(CPUState *env = s->env);
    uint32_t r = 0;

    addr >>= 2;
    switch (addr)
    {
        case R_STAT_DIN:
            r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
            if (s->rx_fifo_len) {
                r |= 1 << STAT_DAV;
            }
            r |= 1 << STAT_TR_RDY;
            r |= 1 << STAT_TR_IDLE;
            break;
        case RS_STAT_DIN:
            r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
            if (s->rx_fifo_len) {
                r |= 1 << STAT_DAV;
                s->rx_fifo_len--;
            }
            r |= 1 << STAT_TR_RDY;
            r |= 1 << STAT_TR_IDLE;
            break;
        default:
            r = s->regs[addr];
            D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
            break;
    }
    return r;
}

static void
ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    struct etrax_serial *s = opaque;
    unsigned char ch = value;
    D(CPUState *env = s->env);

    D(qemu_log("%s " TARGET_FMT_plx "=%x\n",  __func__, addr, value));
    addr >>= 2;
    switch (addr)
    {
        case RW_DOUT:
            qemu_chr_fe_write(s->chr, &ch, 1);
            s->regs[R_INTR] |= 3;
            s->pending_tx = 1;
            s->regs[addr] = value;
            break;
        case RW_ACK_INTR:
            if (s->pending_tx) {
                value &= ~1;
                s->pending_tx = 0;
                D(qemu_log("fixedup value=%x r_intr=%x\n",
                           value, s->regs[R_INTR]));
            }
            s->regs[addr] = value;
            s->regs[R_INTR] &= ~value;
            D(printf("r_intr=%x\n", s->regs[R_INTR]));
            break;
        default:
            s->regs[addr] = value;
            break;
    }
    ser_update_irq(s);
}

static CPUReadMemoryFunc * const ser_read[] = {
    NULL, NULL,
    &ser_readl,
};

static CPUWriteMemoryFunc * const ser_write[] = {
    NULL, NULL,
    &ser_writel,
};

static void serial_receive(void *opaque, const uint8_t *buf, int size)
{
    struct etrax_serial *s = opaque;
    int i;

    /* Got a byte.  */
    if (s->rx_fifo_len >= 16) {
        qemu_log("WARNING: UART dropped char.\n");
        return;
    }

    for (i = 0; i < size; i++) { 
        s->rx_fifo[s->rx_fifo_pos] = buf[i];
        s->rx_fifo_pos++;
        s->rx_fifo_pos &= 15;
        s->rx_fifo_len++;
    }

    ser_update_irq(s);
}

static int serial_can_receive(void *opaque)
{
    struct etrax_serial *s = opaque;
    int r;

    /* Is the receiver enabled?  */
    if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
        return 0;
    }

    r = sizeof(s->rx_fifo) - s->rx_fifo_len;
    return r;
}

static void serial_event(void *opaque, int event)
{

}

static void etraxfs_ser_reset(DeviceState *d)
{
    struct etrax_serial *s = container_of(d, typeof(*s), busdev.qdev);

    /* transmitter begins ready and idle.  */
    s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
    s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);

    s->regs[RW_REC_CTRL] = 0x10000;

}

static int etraxfs_ser_init(SysBusDevice *dev)
{
    struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
    int ser_regs;

    sysbus_init_irq(dev, &s->irq);
    ser_regs = cpu_register_io_memory(ser_read, ser_write, s,
                                      DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, R_MAX * 4, ser_regs);
    s->chr = qdev_init_chardev(&dev->qdev);
    if (s->chr)
        qemu_chr_add_handlers(s->chr,
                      serial_can_receive, serial_receive,
                      serial_event, s);
    return 0;
}

static SysBusDeviceInfo etraxfs_ser_info = {
    .init = etraxfs_ser_init,
    .qdev.name  = "etraxfs,serial",
    .qdev.size  = sizeof(struct etrax_serial),
    .qdev.reset = etraxfs_ser_reset,
};

static void etraxfs_serial_register(void)
{
    sysbus_register_withprop(&etraxfs_ser_info);
}

device_init(etraxfs_serial_register)
Commit	Line	Data
83fa1010 TS	1	/*
	2	* QEMU ETRAX System Emulator
	3	*
	4	* Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
4b816985	25	#include "sysbus.h"
f062058f	26	#include "qemu-char.h"
8cc7c395	27	#include "qemu-log.h"
83fa1010	28
bbaf29c7 EI	29	#define D(x)
bbaf29c7 EI	30
72af9170 EI	31	#define RW_TR_CTRL (0x00 / 4)
	32	#define RW_TR_DMA_EN (0x04 / 4)
	33	#define RW_REC_CTRL (0x08 / 4)
	34	#define RW_DOUT (0x1c / 4)
	35	#define RS_STAT_DIN (0x20 / 4)
	36	#define R_STAT_DIN (0x24 / 4)
	37	#define RW_INTR_MASK (0x2c / 4)
	38	#define RW_ACK_INTR (0x30 / 4)
	39	#define R_INTR (0x34 / 4)
	40	#define R_MASKED_INTR (0x38 / 4)
	41	#define R_MAX (0x3c / 4)
83fa1010	42
f062058f EI	43	#define STAT_DAV 16
	44	#define STAT_TR_IDLE 22
	45	#define STAT_TR_RDY 24
	46
f2964260	47	struct etrax_serial
83fa1010	48	{
2a9859e7 EI	49	SysBusDevice busdev;
	50	CharDriverState *chr;
	51	qemu_irq irq;
f062058f	52
2a9859e7	53	int pending_tx;
f062058f	54
f2fcffbb EI	55	uint8_t rx_fifo[16];
	56	unsigned int rx_fifo_pos;
	57	unsigned int rx_fifo_len;
	58
2a9859e7 EI	59	/* Control registers. */
2a9859e7 EI	60	uint32_t regs[R_MAX];
f062058f EI	61	};
f062058f EI	62
f2964260	63	static void ser_update_irq(struct etrax_serial *s)
f062058f	64	{
72af9170	65
f2fcffbb EI	66	if (s->rx_fifo_len) {
	67	s->regs[R_INTR] \|= 8;
	68	} else {
	69	s->regs[R_INTR] &= ~8;
	70	}
	71
	72	s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
2a9859e7	73	qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
83fa1010	74	}
f062058f	75
c227f099	76	static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
83fa1010	77	{
2a9859e7 EI	78	struct etrax_serial *s = opaque;
	79	D(CPUState *env = s->env);
	80	uint32_t r = 0;
	81
	82	addr >>= 2;
	83	switch (addr)
	84	{
	85	case R_STAT_DIN:
f2fcffbb EI	86	r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
	87	if (s->rx_fifo_len) {
	88	r \|= 1 << STAT_DAV;
	89	}
	90	r \|= 1 << STAT_TR_RDY;
	91	r \|= 1 << STAT_TR_IDLE;
2a9859e7 EI	92	break;
2a9859e7 EI	93	case RS_STAT_DIN:
f2fcffbb EI	94	r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
	95	if (s->rx_fifo_len) {
	96	r \|= 1 << STAT_DAV;
	97	s->rx_fifo_len--;
	98	}
	99	r \|= 1 << STAT_TR_RDY;
	100	r \|= 1 << STAT_TR_IDLE;
2a9859e7 EI	101	break;
	102	default:
	103	r = s->regs[addr];
8cc7c395	104	D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
2a9859e7 EI	105	break;
	106	}
	107	return r;
83fa1010 TS	108	}
83fa1010 TS	109
83fa1010	110	static void
c227f099	111	ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
83fa1010	112	{
2a9859e7 EI	113	struct etrax_serial *s = opaque;
	114	unsigned char ch = value;
	115	D(CPUState *env = s->env);
	116
8cc7c395	117	D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value));
2a9859e7 EI	118	addr >>= 2;
	119	switch (addr)
	120	{
	121	case RW_DOUT:
2cc6e0a1	122	qemu_chr_fe_write(s->chr, &ch, 1);
f2fcffbb	123	s->regs[R_INTR] \|= 3;
2a9859e7 EI	124	s->pending_tx = 1;
	125	s->regs[addr] = value;
	126	break;
	127	case RW_ACK_INTR:
f2fcffbb EI	128	if (s->pending_tx) {
f2fcffbb EI	129	value &= ~1;
2a9859e7	130	s->pending_tx = 0;
8cc7c395 EI	131	D(qemu_log("fixedup value=%x r_intr=%x\n",
8cc7c395 EI	132	value, s->regs[R_INTR]));
2a9859e7	133	}
f2fcffbb EI	134	s->regs[addr] = value;
	135	s->regs[R_INTR] &= ~value;
	136	D(printf("r_intr=%x\n", s->regs[R_INTR]));
2a9859e7 EI	137	break;
	138	default:
	139	s->regs[addr] = value;
	140	break;
	141	}
	142	ser_update_irq(s);
83fa1010 TS	143	}
83fa1010 TS	144
d60efc6b	145	static CPUReadMemoryFunc * const ser_read[] = {
2a9859e7 EI	146	NULL, NULL,
2a9859e7 EI	147	&ser_readl,
83fa1010 TS	148	};
83fa1010 TS	149
d60efc6b	150	static CPUWriteMemoryFunc * const ser_write[] = {
2a9859e7 EI	151	NULL, NULL,
2a9859e7 EI	152	&ser_writel,
83fa1010 TS	153	};
83fa1010 TS	154
f062058f	155	static void serial_receive(void opaque, const uint8_t buf, int size)
83fa1010	156	{
2a9859e7	157	struct etrax_serial *s = opaque;
f2fcffbb EI	158	int i;
	159
	160	/* Got a byte. */
	161	if (s->rx_fifo_len >= 16) {
8cc7c395	162	qemu_log("WARNING: UART dropped char.\n");
f2fcffbb EI	163	return;
	164	}
	165
	166	for (i = 0; i < size; i++) {
	167	s->rx_fifo[s->rx_fifo_pos] = buf[i];
	168	s->rx_fifo_pos++;
	169	s->rx_fifo_pos &= 15;
	170	s->rx_fifo_len++;
	171	}
f062058f	172
2a9859e7	173	ser_update_irq(s);
f062058f EI	174	}
	175
	176	static int serial_can_receive(void *opaque)
	177	{
2a9859e7 EI	178	struct etrax_serial *s = opaque;
2a9859e7 EI	179	int r;
f062058f	180
2a9859e7	181	/* Is the receiver enabled? */
f2fcffbb EI	182	if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
	183	return 0;
	184	}
f062058f	185
f2fcffbb	186	r = sizeof(s->rx_fifo) - s->rx_fifo_len;
2a9859e7	187	return r;
f062058f EI	188	}
	189
	190	static void serial_event(void *opaque, int event)
	191	{
	192
	193	}
	194
20be39de	195	static void etraxfs_ser_reset(DeviceState *d)
f062058f	196	{
20be39de	197	struct etrax_serial s = container_of(d, typeof(s), busdev.qdev);
2a9859e7 EI	198
	199	/* transmitter begins ready and idle. */
	200	s->regs[RS_STAT_DIN] \|= (1 << STAT_TR_RDY);
	201	s->regs[RS_STAT_DIN] \|= (1 << STAT_TR_IDLE);
	202
20be39de EI	203	s->regs[RW_REC_CTRL] = 0x10000;
	204
	205	}
	206
	207	static int etraxfs_ser_init(SysBusDevice *dev)
	208	{
	209	struct etrax_serial s = FROM_SYSBUS(typeof (s), dev);
	210	int ser_regs;
	211
2a9859e7	212	sysbus_init_irq(dev, &s->irq);
2507c12a AG	213	ser_regs = cpu_register_io_memory(ser_read, ser_write, s,
2507c12a AG	214	DEVICE_NATIVE_ENDIAN);
2a9859e7 EI	215	sysbus_init_mmio(dev, R_MAX * 4, ser_regs);
	216	s->chr = qdev_init_chardev(&dev->qdev);
	217	if (s->chr)
	218	qemu_chr_add_handlers(s->chr,
	219	serial_can_receive, serial_receive,
	220	serial_event, s);
81a322d4	221	return 0;
83fa1010	222	}
4b816985	223
20be39de EI	224	static SysBusDeviceInfo etraxfs_ser_info = {
	225	.init = etraxfs_ser_init,
	226	.qdev.name = "etraxfs,serial",
	227	.qdev.size = sizeof(struct etrax_serial),
	228	.qdev.reset = etraxfs_ser_reset,
	229	};
	230
4b816985 EI	231	static void etraxfs_serial_register(void)
4b816985 EI	232	{
20be39de	233	sysbus_register_withprop(&etraxfs_ser_info);
4b816985 EI	234	}
	235
	236	device_init(etraxfs_serial_register)