[mirror_qemu.git] / hw / etraxfs_timer.c

/*
 * QEMU ETRAX Timers
 *
 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <stdio.h>
#include <sys/time.h>
#include "hw.h"
#include "qemu-timer.h"

#define D(x)

#define RW_TMR0_DIV   0x00
#define R_TMR0_DATA   0x04
#define RW_TMR0_CTRL  0x08
#define RW_TMR1_DIV   0x10
#define R_TMR1_DATA   0x14
#define RW_TMR1_CTRL  0x18
#define R_TIME        0x38
#define RW_WD_CTRL    0x40
#define RW_INTR_MASK  0x48
#define RW_ACK_INTR   0x4c
#define R_INTR        0x50
#define R_MASKED_INTR 0x54

struct fs_timer_t {
	CPUState *env;
	qemu_irq *irq;
	target_phys_addr_t base;

	QEMUBH *bh;
	ptimer_state *ptimer;
	unsigned int limit;
	int scale;
	uint32_t mask;
	struct timeval last;

	uint32_t rw_intr_mask;
	uint32_t rw_ack_intr;
	uint32_t r_intr;
};

/* diff two timevals.  Return a single int in us. */
int diff_timeval_us(struct timeval *a, struct timeval *b)
{
        int diff;

        /* assume these values are signed.  */
        diff = (a->tv_sec - b->tv_sec) * 1000 * 1000;
        diff += (a->tv_usec - b->tv_usec);
        return diff;
}

static uint32_t timer_rinvalid (void *opaque, target_phys_addr_t addr)
{
	struct fs_timer_t *t = opaque;
	CPUState *env = t->env;
	cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n", 
		  addr, env->pc);
	return 0;
}

static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
{
	struct fs_timer_t *t = opaque;
	D(CPUState *env = t->env);
	uint32_t r = 0;

	/* Make addr relative to this instances base.  */
	addr -= t->base;
	switch (addr) {
	case R_TMR0_DATA:
		break;
	case R_TMR1_DATA:
		D(printf ("R_TMR1_DATA\n"));
		break;
	case R_TIME:
	{
		struct timeval now;
		gettimeofday(&now, NULL);
		if (!(t->last.tv_sec == 0 
		      && t->last.tv_usec == 0)) {
			r = diff_timeval_us(&now, &t->last);
			r *= 1000; /* convert to ns.  */
			r++; /* make sure we increase for each call.  */
		}
		t->last = now;
		break;
	}

	case RW_INTR_MASK:
		r = t->rw_intr_mask;
		break;
	case R_MASKED_INTR:
		r = t->r_intr & t->rw_intr_mask;
		break;
	default:
		D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
		break;
	}
	return r;
}

static void
timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
{
	struct fs_timer_t *t = opaque;
	CPUState *env = t->env;
	cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n", 
		  addr, env->pc);
}

static void write_ctrl(struct fs_timer_t *t, uint32_t v)
{
	int op;
	int freq;
	int freq_hz;

	op = v & 3;
	freq = v >> 2;
	freq_hz = 32000000;

	switch (freq)
	{
	case 0:
	case 1:
		D(printf ("extern or disabled timer clock?\n"));
		break;
	case 4: freq_hz =  29493000; break;
	case 5: freq_hz =  32000000; break;
	case 6: freq_hz =  32768000; break;
	case 7: freq_hz = 100000000; break;
	default:
		abort();
		break;
	}

	D(printf ("freq_hz=%d limit=%d\n", freq_hz, t->limit));
	t->scale = 0;
	if (t->limit > 2048)
	{
		t->scale = 2048;
		ptimer_set_period(t->ptimer, freq_hz / t->scale);
	}

	switch (op)
	{
		case 0:
			D(printf ("limit=%d %d\n", 
				  t->limit, t->limit/t->scale));
			ptimer_set_limit(t->ptimer, t->limit / t->scale, 1);
			break;
		case 1:
			ptimer_stop(t->ptimer);
			break;
		case 2:
			ptimer_run(t->ptimer, 0);
			break;
		default:
			abort();
			break;
	}
}

static void timer_ack_irq(struct fs_timer_t *t)
{
	if (!(t->r_intr & t->mask & t->rw_intr_mask))
		qemu_irq_lower(t->irq[0]);
}

static void
timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
	struct fs_timer_t *t = opaque;
	CPUState *env = t->env;

	D(printf ("%s %x %x pc=%x\n",
		__func__, addr, value, env->pc));
	/* Make addr relative to this instances base.  */
	addr -= t->base;
	switch (addr)
	{
		case RW_TMR0_DIV:
			D(printf ("RW_TMR0_DIV=%x\n", value));
			t->limit = value;
			break;
		case RW_TMR0_CTRL:
			D(printf ("RW_TMR0_CTRL=%x\n", value));
			write_ctrl(t, value);
			break;
		case RW_TMR1_DIV:
			D(printf ("RW_TMR1_DIV=%x\n", value));
			break;
		case RW_TMR1_CTRL:
			D(printf ("RW_TMR1_CTRL=%x\n", value));
			break;
		case RW_INTR_MASK:
			D(printf ("RW_INTR_MASK=%x\n", value));
			t->rw_intr_mask = value;
			break;
		case RW_WD_CTRL:
			D(printf ("RW_WD_CTRL=%x\n", value));
			break;
		case RW_ACK_INTR:
			t->r_intr &= ~value;
			timer_ack_irq(t);
			break;
		default:
			printf ("%s %x %x pc=%x\n",
				__func__, addr, value, env->pc);
			break;
	}
}

static CPUReadMemoryFunc *timer_read[] = {
    &timer_rinvalid,
    &timer_rinvalid,
    &timer_readl,
};

static CPUWriteMemoryFunc *timer_write[] = {
    &timer_winvalid,
    &timer_winvalid,
    &timer_writel,
};

static void timer_irq(void *opaque)
{
	struct fs_timer_t *t = opaque;
	t->r_intr |= t->mask;
	if (t->mask & t->rw_intr_mask) {
		D(printf("%s raise\n", __func__));
		qemu_irq_raise(t->irq[0]);
	}
}

void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, 
			target_phys_addr_t base)
{
	static struct fs_timer_t *t;
	int timer_regs;

	t = qemu_mallocz(sizeof *t);
	if (!t)
		return;

	t->bh = qemu_bh_new(timer_irq, t);
	t->ptimer = ptimer_init(t->bh);
	t->irq = irqs + 26;
	t->mask = 1;
	t->env = env;
	t->base = base;

	timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
	cpu_register_physical_memory (base, 0x5c, timer_regs);
}
Commit	Line	Data
83fa1010	1	/*
e62b5b13	2	* QEMU ETRAX Timers
83fa1010 TS	3	*
	4	* Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include <stdio.h>
	25	#include <sys/time.h>
87ecb68b PB	26	#include "hw.h"
87ecb68b PB	27	#include "qemu-timer.h"
83fa1010	28
bbaf29c7 EI	29	#define D(x)
bbaf29c7 EI	30
ca87d03b EI	31	#define RW_TMR0_DIV 0x00
	32	#define R_TMR0_DATA 0x04
	33	#define RW_TMR0_CTRL 0x08
	34	#define RW_TMR1_DIV 0x10
	35	#define R_TMR1_DATA 0x14
	36	#define RW_TMR1_CTRL 0x18
	37	#define R_TIME 0x38
	38	#define RW_WD_CTRL 0x40
	39	#define RW_INTR_MASK 0x48
	40	#define RW_ACK_INTR 0x4c
	41	#define R_INTR 0x50
	42	#define R_MASKED_INTR 0x54
83fa1010	43
83fa1010	44	struct fs_timer_t {
ca87d03b EI	45	CPUState *env;
	46	qemu_irq *irq;
	47	target_phys_addr_t base;
	48
83fa1010	49	QEMUBH *bh;
ca87d03b	50	ptimer_state *ptimer;
83fa1010 TS	51	unsigned int limit;
83fa1010 TS	52	int scale;
83fa1010	53	uint32_t mask;
bbaf29c7	54	struct timeval last;
e62b5b13 EI	55
	56	uint32_t rw_intr_mask;
	57	uint32_t rw_ack_intr;
	58	uint32_t r_intr;
83fa1010 TS	59	};
83fa1010 TS	60
83fa1010 TS	61	/* diff two timevals. Return a single int in us. */
	62	int diff_timeval_us(struct timeval a, struct timeval b)
	63	{
	64	int diff;
	65
	66	/* assume these values are signed. */
	67	diff = (a->tv_sec - b->tv_sec) * 1000 * 1000;
	68	diff += (a->tv_usec - b->tv_usec);
	69	return diff;
	70	}
	71
ca87d03b	72	static uint32_t timer_rinvalid (void *opaque, target_phys_addr_t addr)
83fa1010	73	{
ca87d03b EI	74	struct fs_timer_t *t = opaque;
	75	CPUState *env = t->env;
	76	cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
	77	addr, env->pc);
	78	return 0;
83fa1010 TS	79	}
	80
	81	static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
	82	{
ca87d03b EI	83	struct fs_timer_t *t = opaque;
ca87d03b EI	84	D(CPUState *env = t->env);
83fa1010 TS	85	uint32_t r = 0;
83fa1010 TS	86
ca87d03b EI	87	/* Make addr relative to this instances base. */
ca87d03b EI	88	addr -= t->base;
83fa1010 TS	89	switch (addr) {
	90	case R_TMR0_DATA:
	91	break;
	92	case R_TMR1_DATA:
bbaf29c7	93	D(printf ("R_TMR1_DATA\n"));
83fa1010 TS	94	break;
	95	case R_TIME:
	96	{
83fa1010 TS	97	struct timeval now;
83fa1010 TS	98	gettimeofday(&now, NULL);
ca87d03b EI	99	if (!(t->last.tv_sec == 0
	100	&& t->last.tv_usec == 0)) {
	101	r = diff_timeval_us(&now, &t->last);
83fa1010 TS	102	r = 1000; / convert to ns. */
	103	r++; /* make sure we increase for each call. */
	104	}
ca87d03b	105	t->last = now;
83fa1010 TS	106	break;
	107	}
	108
	109	case RW_INTR_MASK:
ca87d03b	110	r = t->rw_intr_mask;
83fa1010 TS	111	break;
83fa1010 TS	112	case R_MASKED_INTR:
ca87d03b	113	r = t->r_intr & t->rw_intr_mask;
83fa1010 TS	114	break;
83fa1010 TS	115	default:
e62b5b13	116	D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
83fa1010 TS	117	break;
	118	}
	119	return r;
	120	}
	121
	122	static void
ca87d03b	123	timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
83fa1010	124	{
ca87d03b EI	125	struct fs_timer_t *t = opaque;
	126	CPUState *env = t->env;
	127	cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
	128	addr, env->pc);
83fa1010 TS	129	}
	130
	131	static void write_ctrl(struct fs_timer_t *t, uint32_t v)
	132	{
	133	int op;
	134	int freq;
	135	int freq_hz;
	136
	137	op = v & 3;
	138	freq = v >> 2;
	139	freq_hz = 32000000;
	140
	141	switch (freq)
	142	{
	143	case 0:
	144	case 1:
e62b5b13	145	D(printf ("extern or disabled timer clock?\n"));
83fa1010 TS	146	break;
	147	case 4: freq_hz = 29493000; break;
	148	case 5: freq_hz = 32000000; break;
	149	case 6: freq_hz = 32768000; break;
	150	case 7: freq_hz = 100000000; break;
	151	default:
	152	abort();
	153	break;
	154	}
	155
e62b5b13	156	D(printf ("freq_hz=%d limit=%d\n", freq_hz, t->limit));
83fa1010 TS	157	t->scale = 0;
	158	if (t->limit > 2048)
	159	{
	160	t->scale = 2048;
bbaf29c7	161	ptimer_set_period(t->ptimer, freq_hz / t->scale);
83fa1010 TS	162	}
83fa1010 TS	163
83fa1010 TS	164	switch (op)
	165	{
	166	case 0:
e62b5b13 EI	167	D(printf ("limit=%d %d\n",
e62b5b13 EI	168	t->limit, t->limit/t->scale));
83fa1010 TS	169	ptimer_set_limit(t->ptimer, t->limit / t->scale, 1);
	170	break;
	171	case 1:
	172	ptimer_stop(t->ptimer);
	173	break;
	174	case 2:
	175	ptimer_run(t->ptimer, 0);
	176	break;
	177	default:
	178	abort();
	179	break;
	180	}
	181	}
	182
bbaf29c7	183	static void timer_ack_irq(struct fs_timer_t *t)
83fa1010	184	{
e62b5b13	185	if (!(t->r_intr & t->mask & t->rw_intr_mask))
bbaf29c7	186	qemu_irq_lower(t->irq[0]);
83fa1010 TS	187	}
	188
	189	static void
	190	timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	191	{
ca87d03b EI	192	struct fs_timer_t *t = opaque;
ca87d03b EI	193	CPUState *env = t->env;
bbaf29c7 EI	194
	195	D(printf ("%s %x %x pc=%x\n",
	196	__func__, addr, value, env->pc));
ca87d03b EI	197	/* Make addr relative to this instances base. */
ca87d03b EI	198	addr -= t->base;
83fa1010 TS	199	switch (addr)
	200	{
	201	case RW_TMR0_DIV:
bbaf29c7	202	D(printf ("RW_TMR0_DIV=%x\n", value));
ca87d03b	203	t->limit = value;
83fa1010 TS	204	break;
83fa1010 TS	205	case RW_TMR0_CTRL:
bbaf29c7	206	D(printf ("RW_TMR0_CTRL=%x\n", value));
ca87d03b	207	write_ctrl(t, value);
83fa1010 TS	208	break;
83fa1010 TS	209	case RW_TMR1_DIV:
bbaf29c7	210	D(printf ("RW_TMR1_DIV=%x\n", value));
83fa1010 TS	211	break;
83fa1010 TS	212	case RW_TMR1_CTRL:
bbaf29c7	213	D(printf ("RW_TMR1_CTRL=%x\n", value));
83fa1010 TS	214	break;
83fa1010 TS	215	case RW_INTR_MASK:
bbaf29c7	216	D(printf ("RW_INTR_MASK=%x\n", value));
ca87d03b	217	t->rw_intr_mask = value;
e62b5b13 EI	218	break;
	219	case RW_WD_CTRL:
	220	D(printf ("RW_WD_CTRL=%x\n", value));
83fa1010 TS	221	break;
83fa1010 TS	222	case RW_ACK_INTR:
ca87d03b EI	223	t->r_intr &= ~value;
ca87d03b EI	224	timer_ack_irq(t);
83fa1010 TS	225	break;
	226	default:
	227	printf ("%s %x %x pc=%x\n",
	228	__func__, addr, value, env->pc);
	229	break;
	230	}
	231	}
	232
	233	static CPUReadMemoryFunc *timer_read[] = {
ca87d03b EI	234	&timer_rinvalid,
ca87d03b EI	235	&timer_rinvalid,
83fa1010 TS	236	&timer_readl,
	237	};
	238
	239	static CPUWriteMemoryFunc *timer_write[] = {
ca87d03b EI	240	&timer_winvalid,
ca87d03b EI	241	&timer_winvalid,
83fa1010 TS	242	&timer_writel,
	243	};
	244
	245	static void timer_irq(void *opaque)
	246	{
	247	struct fs_timer_t *t = opaque;
e62b5b13 EI	248	t->r_intr \|= t->mask;
	249	if (t->mask & t->rw_intr_mask) {
	250	D(printf("%s raise\n", __func__));
83fa1010 TS	251	qemu_irq_raise(t->irq[0]);
	252	}
	253	}
	254
ca87d03b EI	255	void etraxfs_timer_init(CPUState env, qemu_irq irqs,
ca87d03b EI	256	target_phys_addr_t base)
83fa1010	257	{
ca87d03b	258	static struct fs_timer_t *t;
83fa1010 TS	259	int timer_regs;
83fa1010 TS	260
ca87d03b EI	261	t = qemu_mallocz(sizeof *t);
	262	if (!t)
	263	return;
bbaf29c7	264
ca87d03b EI	265	t->bh = qemu_bh_new(timer_irq, t);
	266	t->ptimer = ptimer_init(t->bh);
	267	t->irq = irqs + 26;
	268	t->mask = 1;
	269	t->env = env;
	270	t->base = base;
83fa1010	271
ca87d03b EI	272	timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
ca87d03b EI	273	cpu_register_physical_memory (base, 0x5c, timer_regs);
83fa1010	274	}