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1/*
2 * QEMU Firmware configuration device emulation
3 *
4 * Copyright (c) 2008 Gleb Natapov
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include "hw.h"
084a197a 25#include "sysemu.h"
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26#include "isa.h"
27#include "fw_cfg.h"
28
29/* debug firmware config */
30//#define DEBUG_FW_CFG
31
32#ifdef DEBUG_FW_CFG
001faf32
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33#define FW_CFG_DPRINTF(fmt, ...) \
34 do { printf("FW_CFG: " fmt , ## __VA_ARGS__); } while (0)
3cce6243 35#else
001faf32 36#define FW_CFG_DPRINTF(fmt, ...)
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37#endif
38
39#define FW_CFG_SIZE 2
40
41typedef struct _FWCfgEntry {
ff06108b 42 uint32_t len;
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43 uint8_t *data;
44 void *callback_opaque;
45 FWCfgCallback callback;
46} FWCfgEntry;
47
48typedef struct _FWCfgState {
49 FWCfgEntry entries[2][FW_CFG_MAX_ENTRY];
50 uint16_t cur_entry;
ff06108b 51 uint32_t cur_offset;
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52} FWCfgState;
53
54static void fw_cfg_write(FWCfgState *s, uint8_t value)
55{
56 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
57 FWCfgEntry *e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
58
59 FW_CFG_DPRINTF("write %d\n", value);
60
61 if (s->cur_entry & FW_CFG_WRITE_CHANNEL && s->cur_offset < e->len) {
62 e->data[s->cur_offset++] = value;
63 if (s->cur_offset == e->len) {
64 e->callback(e->callback_opaque, e->data);
65 s->cur_offset = 0;
66 }
67 }
68}
69
70static int fw_cfg_select(FWCfgState *s, uint16_t key)
71{
72 int ret;
73
74 s->cur_offset = 0;
75 if ((key & FW_CFG_ENTRY_MASK) >= FW_CFG_MAX_ENTRY) {
76 s->cur_entry = FW_CFG_INVALID;
77 ret = 0;
78 } else {
79 s->cur_entry = key;
80 ret = 1;
81 }
82
83 FW_CFG_DPRINTF("select key %d (%sfound)\n", key, ret ? "" : "not ");
84
85 return ret;
86}
87
88static uint8_t fw_cfg_read(FWCfgState *s)
89{
90 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
91 FWCfgEntry *e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
92 uint8_t ret;
93
94 if (s->cur_entry == FW_CFG_INVALID || !e->data || s->cur_offset >= e->len)
95 ret = 0;
96 else
97 ret = e->data[s->cur_offset++];
98
99 FW_CFG_DPRINTF("read %d\n", ret);
100
101 return ret;
102}
103
104static uint32_t fw_cfg_io_readb(void *opaque, uint32_t addr)
105{
106 return fw_cfg_read(opaque);
107}
108
109static void fw_cfg_io_writeb(void *opaque, uint32_t addr, uint32_t value)
110{
7442511c 111 fw_cfg_write(opaque, (uint8_t)value);
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112}
113
114static void fw_cfg_io_writew(void *opaque, uint32_t addr, uint32_t value)
115{
116 fw_cfg_select(opaque, (uint16_t)value);
117}
118
c227f099 119static uint32_t fw_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
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120{
121 return fw_cfg_read(opaque);
122}
123
c227f099 124static void fw_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
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125 uint32_t value)
126{
7442511c 127 fw_cfg_write(opaque, (uint8_t)value);
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128}
129
c227f099 130static void fw_cfg_mem_writew(void *opaque, target_phys_addr_t addr,
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131 uint32_t value)
132{
133 fw_cfg_select(opaque, (uint16_t)value);
134}
135
d60efc6b 136static CPUReadMemoryFunc * const fw_cfg_ctl_mem_read[3] = {
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137 NULL,
138 NULL,
139 NULL,
140};
141
d60efc6b 142static CPUWriteMemoryFunc * const fw_cfg_ctl_mem_write[3] = {
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143 NULL,
144 fw_cfg_mem_writew,
145 NULL,
146};
147
d60efc6b 148static CPUReadMemoryFunc * const fw_cfg_data_mem_read[3] = {
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149 fw_cfg_mem_readb,
150 NULL,
151 NULL,
152};
153
d60efc6b 154static CPUWriteMemoryFunc * const fw_cfg_data_mem_write[3] = {
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155 fw_cfg_mem_writeb,
156 NULL,
157 NULL,
158};
159
160static void fw_cfg_reset(void *opaque)
161{
162 FWCfgState *s = opaque;
163
164 fw_cfg_select(s, 0);
165}
166
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167/* Save restore 32 bit int as uint16_t
168 This is a Big hack, but it is how the old state did it.
169 Or we broke compatibility in the state, or we can't use struct tm
170 */
171
172static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size)
173{
174 uint32_t *v = pv;
175 *v = qemu_get_be16(f);
176 return 0;
177}
178
179static void put_unused(QEMUFile *f, void *pv, size_t size)
180{
181 fprintf(stderr, "uint32_as_uint16 is only used for backward compatibilty.\n");
182 fprintf(stderr, "This functions shouldn't be called.\n");
183}
184
d05ac8fa 185static const VMStateInfo vmstate_hack_uint32_as_uint16 = {
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186 .name = "int32_as_uint16",
187 .get = get_uint32_as_uint16,
188 .put = put_unused,
189};
190
191#define VMSTATE_UINT16_HACK(_f, _s, _t) \
192 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
193
194
195static bool is_version_1(void *opaque, int version_id)
196{
197 return version_id == 1;
198}
199
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200static const VMStateDescription vmstate_fw_cfg = {
201 .name = "fw_cfg",
ff06108b 202 .version_id = 2,
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203 .minimum_version_id = 1,
204 .minimum_version_id_old = 1,
205 .fields = (VMStateField []) {
206 VMSTATE_UINT16(cur_entry, FWCfgState),
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207 VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
208 VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
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209 VMSTATE_END_OF_LIST()
210 }
211};
3cce6243 212
ff06108b 213int fw_cfg_add_bytes(void *opaque, uint16_t key, uint8_t *data, uint32_t len)
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214{
215 FWCfgState *s = opaque;
216 int arch = !!(key & FW_CFG_ARCH_LOCAL);
217
218 key &= FW_CFG_ENTRY_MASK;
219
220 if (key >= FW_CFG_MAX_ENTRY)
221 return 0;
222
223 s->entries[arch][key].data = data;
224 s->entries[arch][key].len = len;
225
226 return 1;
227}
228
229int fw_cfg_add_i16(void *opaque, uint16_t key, uint16_t value)
230{
231 uint16_t *copy;
232
233 copy = qemu_malloc(sizeof(value));
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234 *copy = cpu_to_le16(value);
235 return fw_cfg_add_bytes(opaque, key, (uint8_t *)copy, sizeof(value));
236}
237
238int fw_cfg_add_i32(void *opaque, uint16_t key, uint32_t value)
239{
240 uint32_t *copy;
241
242 copy = qemu_malloc(sizeof(value));
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243 *copy = cpu_to_le32(value);
244 return fw_cfg_add_bytes(opaque, key, (uint8_t *)copy, sizeof(value));
245}
246
247int fw_cfg_add_i64(void *opaque, uint16_t key, uint64_t value)
248{
249 uint64_t *copy;
250
251 copy = qemu_malloc(sizeof(value));
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252 *copy = cpu_to_le64(value);
253 return fw_cfg_add_bytes(opaque, key, (uint8_t *)copy, sizeof(value));
254}
255
256int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback,
257 void *callback_opaque, uint8_t *data, size_t len)
258{
259 FWCfgState *s = opaque;
260 int arch = !!(key & FW_CFG_ARCH_LOCAL);
261
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262 if (!(key & FW_CFG_WRITE_CHANNEL))
263 return 0;
264
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265 key &= FW_CFG_ENTRY_MASK;
266
85df0de4 267 if (key >= FW_CFG_MAX_ENTRY || len > 65535)
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268 return 0;
269
270 s->entries[arch][key].data = data;
271 s->entries[arch][key].len = len;
272 s->entries[arch][key].callback_opaque = callback_opaque;
273 s->entries[arch][key].callback = callback;
274
275 return 1;
276}
277
278void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
c227f099 279 target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
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280{
281 FWCfgState *s;
282 int io_ctl_memory, io_data_memory;
283
284 s = qemu_mallocz(sizeof(FWCfgState));
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285
286 if (ctl_port) {
287 register_ioport_write(ctl_port, 2, 2, fw_cfg_io_writew, s);
288 }
289 if (data_port) {
290 register_ioport_read(data_port, 1, 1, fw_cfg_io_readb, s);
291 register_ioport_write(data_port, 1, 1, fw_cfg_io_writeb, s);
292 }
293 if (ctl_addr) {
1eed09cb 294 io_ctl_memory = cpu_register_io_memory(fw_cfg_ctl_mem_read,
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295 fw_cfg_ctl_mem_write, s);
296 cpu_register_physical_memory(ctl_addr, FW_CFG_SIZE, io_ctl_memory);
297 }
298 if (data_addr) {
1eed09cb 299 io_data_memory = cpu_register_io_memory(fw_cfg_data_mem_read,
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300 fw_cfg_data_mem_write, s);
301 cpu_register_physical_memory(data_addr, FW_CFG_SIZE, io_data_memory);
302 }
303 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (uint8_t *)"QEMU", 4);
084a197a 304 fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16);
993fbfdb 305 fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)(display_type == DT_NOGRAPHIC));
905fdcb5 306 fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
6be68d7e 307 fw_cfg_add_i16(s, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
95387491 308 fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
905fdcb5 309
7d2edd40 310 vmstate_register(-1, &vmstate_fw_cfg, s);
a08d4367 311 qemu_register_reset(fw_cfg_reset, s);
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312
313 return s;
314}