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Commit | Line | Data |
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9ee6e8bb PB |
1 | /* |
2 | * Arm PrimeCell PL061 General Purpose IO with additional | |
3 | * Luminary Micro Stellaris bits. | |
4 | * | |
5 | * Copyright (c) 2007 CodeSourcery. | |
6 | * Written by Paul Brook | |
7 | * | |
8e31bf38 | 8 | * This code is licensed under the GPL. |
9ee6e8bb PB |
9 | */ |
10 | ||
83c9f4ca | 11 | #include "hw/sysbus.h" |
9ee6e8bb PB |
12 | |
13 | //#define DEBUG_PL061 1 | |
14 | ||
15 | #ifdef DEBUG_PL061 | |
001faf32 BS |
16 | #define DPRINTF(fmt, ...) \ |
17 | do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) | |
18 | #define BADF(fmt, ...) \ | |
19 | do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) | |
9ee6e8bb | 20 | #else |
001faf32 BS |
21 | #define DPRINTF(fmt, ...) do {} while(0) |
22 | #define BADF(fmt, ...) \ | |
23 | do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) | |
9ee6e8bb PB |
24 | #endif |
25 | ||
26 | static const uint8_t pl061_id[12] = | |
7063f49f PM |
27 | { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
28 | static const uint8_t pl061_id_luminary[12] = | |
9ee6e8bb PB |
29 | { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; |
30 | ||
692a76d1 AF |
31 | #define TYPE_PL061 "pl061" |
32 | #define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061) | |
33 | ||
ee663e96 | 34 | typedef struct PL061State { |
692a76d1 AF |
35 | SysBusDevice parent_obj; |
36 | ||
3cf89f8a | 37 | MemoryRegion iomem; |
a35faa94 PM |
38 | uint32_t locked; |
39 | uint32_t data; | |
bfb27e60 CL |
40 | uint32_t old_out_data; |
41 | uint32_t old_in_data; | |
a35faa94 PM |
42 | uint32_t dir; |
43 | uint32_t isense; | |
44 | uint32_t ibe; | |
45 | uint32_t iev; | |
46 | uint32_t im; | |
47 | uint32_t istate; | |
48 | uint32_t afsel; | |
49 | uint32_t dr2r; | |
50 | uint32_t dr4r; | |
51 | uint32_t dr8r; | |
52 | uint32_t odr; | |
53 | uint32_t pur; | |
54 | uint32_t pdr; | |
55 | uint32_t slr; | |
56 | uint32_t den; | |
57 | uint32_t cr; | |
58 | uint32_t float_high; | |
b3aaff11 | 59 | uint32_t amsel; |
9ee6e8bb PB |
60 | qemu_irq irq; |
61 | qemu_irq out[8]; | |
7063f49f | 62 | const unsigned char *id; |
ee663e96 | 63 | } PL061State; |
9ee6e8bb | 64 | |
a35faa94 PM |
65 | static const VMStateDescription vmstate_pl061 = { |
66 | .name = "pl061", | |
bfb27e60 CL |
67 | .version_id = 3, |
68 | .minimum_version_id = 3, | |
a35faa94 | 69 | .fields = (VMStateField[]) { |
ee663e96 AF |
70 | VMSTATE_UINT32(locked, PL061State), |
71 | VMSTATE_UINT32(data, PL061State), | |
bfb27e60 CL |
72 | VMSTATE_UINT32(old_out_data, PL061State), |
73 | VMSTATE_UINT32(old_in_data, PL061State), | |
ee663e96 AF |
74 | VMSTATE_UINT32(dir, PL061State), |
75 | VMSTATE_UINT32(isense, PL061State), | |
76 | VMSTATE_UINT32(ibe, PL061State), | |
77 | VMSTATE_UINT32(iev, PL061State), | |
78 | VMSTATE_UINT32(im, PL061State), | |
79 | VMSTATE_UINT32(istate, PL061State), | |
80 | VMSTATE_UINT32(afsel, PL061State), | |
81 | VMSTATE_UINT32(dr2r, PL061State), | |
82 | VMSTATE_UINT32(dr4r, PL061State), | |
83 | VMSTATE_UINT32(dr8r, PL061State), | |
84 | VMSTATE_UINT32(odr, PL061State), | |
85 | VMSTATE_UINT32(pur, PL061State), | |
86 | VMSTATE_UINT32(pdr, PL061State), | |
87 | VMSTATE_UINT32(slr, PL061State), | |
88 | VMSTATE_UINT32(den, PL061State), | |
89 | VMSTATE_UINT32(cr, PL061State), | |
90 | VMSTATE_UINT32(float_high, PL061State), | |
91 | VMSTATE_UINT32_V(amsel, PL061State, 2), | |
a35faa94 PM |
92 | VMSTATE_END_OF_LIST() |
93 | } | |
94 | }; | |
95 | ||
ee663e96 | 96 | static void pl061_update(PL061State *s) |
9ee6e8bb PB |
97 | { |
98 | uint8_t changed; | |
99 | uint8_t mask; | |
775616c3 | 100 | uint8_t out; |
9ee6e8bb PB |
101 | int i; |
102 | ||
bfb27e60 CL |
103 | DPRINTF("dir = %d, data = %d\n", s->dir, s->data); |
104 | ||
775616c3 PB |
105 | /* Outputs float high. */ |
106 | /* FIXME: This is board dependent. */ | |
107 | out = (s->data & s->dir) | ~s->dir; | |
bfb27e60 CL |
108 | changed = s->old_out_data ^ out; |
109 | if (changed) { | |
110 | s->old_out_data = out; | |
111 | for (i = 0; i < 8; i++) { | |
112 | mask = 1 << i; | |
113 | if (changed & mask) { | |
114 | DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); | |
115 | qemu_set_irq(s->out[i], (out & mask) != 0); | |
116 | } | |
9ee6e8bb PB |
117 | } |
118 | } | |
119 | ||
bfb27e60 CL |
120 | /* Inputs */ |
121 | changed = (s->old_in_data ^ s->data) & ~s->dir; | |
122 | if (changed) { | |
123 | s->old_in_data = s->data; | |
124 | for (i = 0; i < 8; i++) { | |
125 | mask = 1 << i; | |
126 | if (changed & mask) { | |
127 | DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0); | |
128 | ||
129 | if (!(s->isense & mask)) { | |
130 | /* Edge interrupt */ | |
131 | if (s->ibe & mask) { | |
132 | /* Any edge triggers the interrupt */ | |
133 | s->istate |= mask; | |
134 | } else { | |
135 | /* Edge is selected by IEV */ | |
136 | s->istate |= ~(s->data ^ s->iev) & mask; | |
137 | } | |
138 | } | |
139 | } | |
140 | } | |
141 | } | |
142 | ||
143 | /* Level interrupt */ | |
144 | s->istate |= ~(s->data ^ s->iev) & s->isense; | |
145 | ||
146 | DPRINTF("istate = %02X\n", s->istate); | |
147 | ||
148 | qemu_set_irq(s->irq, (s->istate & s->im) != 0); | |
9ee6e8bb PB |
149 | } |
150 | ||
a8170e5e | 151 | static uint64_t pl061_read(void *opaque, hwaddr offset, |
3cf89f8a | 152 | unsigned size) |
9ee6e8bb | 153 | { |
ee663e96 | 154 | PL061State *s = (PL061State *)opaque; |
9ee6e8bb | 155 | |
9ee6e8bb | 156 | if (offset >= 0xfd0 && offset < 0x1000) { |
7063f49f | 157 | return s->id[(offset - 0xfd0) >> 2]; |
9ee6e8bb PB |
158 | } |
159 | if (offset < 0x400) { | |
160 | return s->data & (offset >> 2); | |
161 | } | |
162 | switch (offset) { | |
163 | case 0x400: /* Direction */ | |
164 | return s->dir; | |
165 | case 0x404: /* Interrupt sense */ | |
166 | return s->isense; | |
167 | case 0x408: /* Interrupt both edges */ | |
168 | return s->ibe; | |
ff2712ba | 169 | case 0x40c: /* Interrupt event */ |
9ee6e8bb PB |
170 | return s->iev; |
171 | case 0x410: /* Interrupt mask */ | |
172 | return s->im; | |
173 | case 0x414: /* Raw interrupt status */ | |
174 | return s->istate; | |
175 | case 0x418: /* Masked interrupt status */ | |
176 | return s->istate | s->im; | |
177 | case 0x420: /* Alternate function select */ | |
178 | return s->afsel; | |
179 | case 0x500: /* 2mA drive */ | |
180 | return s->dr2r; | |
181 | case 0x504: /* 4mA drive */ | |
182 | return s->dr4r; | |
183 | case 0x508: /* 8mA drive */ | |
184 | return s->dr8r; | |
185 | case 0x50c: /* Open drain */ | |
186 | return s->odr; | |
187 | case 0x510: /* Pull-up */ | |
188 | return s->pur; | |
189 | case 0x514: /* Pull-down */ | |
190 | return s->pdr; | |
191 | case 0x518: /* Slew rate control */ | |
192 | return s->slr; | |
193 | case 0x51c: /* Digital enable */ | |
194 | return s->den; | |
195 | case 0x520: /* Lock */ | |
196 | return s->locked; | |
197 | case 0x524: /* Commit */ | |
198 | return s->cr; | |
b3aaff11 PM |
199 | case 0x528: /* Analog mode select */ |
200 | return s->amsel; | |
9ee6e8bb | 201 | default: |
abff909c PM |
202 | qemu_log_mask(LOG_GUEST_ERROR, |
203 | "pl061_read: Bad offset %x\n", (int)offset); | |
9ee6e8bb PB |
204 | return 0; |
205 | } | |
206 | } | |
207 | ||
a8170e5e | 208 | static void pl061_write(void *opaque, hwaddr offset, |
3cf89f8a | 209 | uint64_t value, unsigned size) |
9ee6e8bb | 210 | { |
ee663e96 | 211 | PL061State *s = (PL061State *)opaque; |
9ee6e8bb PB |
212 | uint8_t mask; |
213 | ||
9ee6e8bb PB |
214 | if (offset < 0x400) { |
215 | mask = (offset >> 2) & s->dir; | |
216 | s->data = (s->data & ~mask) | (value & mask); | |
217 | pl061_update(s); | |
218 | return; | |
219 | } | |
220 | switch (offset) { | |
221 | case 0x400: /* Direction */ | |
a35faa94 | 222 | s->dir = value & 0xff; |
9ee6e8bb PB |
223 | break; |
224 | case 0x404: /* Interrupt sense */ | |
a35faa94 | 225 | s->isense = value & 0xff; |
9ee6e8bb PB |
226 | break; |
227 | case 0x408: /* Interrupt both edges */ | |
a35faa94 | 228 | s->ibe = value & 0xff; |
9ee6e8bb | 229 | break; |
ff2712ba | 230 | case 0x40c: /* Interrupt event */ |
a35faa94 | 231 | s->iev = value & 0xff; |
9ee6e8bb PB |
232 | break; |
233 | case 0x410: /* Interrupt mask */ | |
a35faa94 | 234 | s->im = value & 0xff; |
9ee6e8bb PB |
235 | break; |
236 | case 0x41c: /* Interrupt clear */ | |
237 | s->istate &= ~value; | |
238 | break; | |
239 | case 0x420: /* Alternate function select */ | |
240 | mask = s->cr; | |
241 | s->afsel = (s->afsel & ~mask) | (value & mask); | |
242 | break; | |
243 | case 0x500: /* 2mA drive */ | |
a35faa94 | 244 | s->dr2r = value & 0xff; |
9ee6e8bb PB |
245 | break; |
246 | case 0x504: /* 4mA drive */ | |
a35faa94 | 247 | s->dr4r = value & 0xff; |
9ee6e8bb PB |
248 | break; |
249 | case 0x508: /* 8mA drive */ | |
a35faa94 | 250 | s->dr8r = value & 0xff; |
9ee6e8bb PB |
251 | break; |
252 | case 0x50c: /* Open drain */ | |
a35faa94 | 253 | s->odr = value & 0xff; |
9ee6e8bb PB |
254 | break; |
255 | case 0x510: /* Pull-up */ | |
a35faa94 | 256 | s->pur = value & 0xff; |
9ee6e8bb PB |
257 | break; |
258 | case 0x514: /* Pull-down */ | |
a35faa94 | 259 | s->pdr = value & 0xff; |
9ee6e8bb PB |
260 | break; |
261 | case 0x518: /* Slew rate control */ | |
a35faa94 | 262 | s->slr = value & 0xff; |
9ee6e8bb PB |
263 | break; |
264 | case 0x51c: /* Digital enable */ | |
a35faa94 | 265 | s->den = value & 0xff; |
9ee6e8bb PB |
266 | break; |
267 | case 0x520: /* Lock */ | |
268 | s->locked = (value != 0xacce551); | |
269 | break; | |
270 | case 0x524: /* Commit */ | |
271 | if (!s->locked) | |
a35faa94 | 272 | s->cr = value & 0xff; |
9ee6e8bb | 273 | break; |
b3aaff11 PM |
274 | case 0x528: |
275 | s->amsel = value & 0xff; | |
276 | break; | |
9ee6e8bb | 277 | default: |
abff909c PM |
278 | qemu_log_mask(LOG_GUEST_ERROR, |
279 | "pl061_write: Bad offset %x\n", (int)offset); | |
9ee6e8bb PB |
280 | } |
281 | pl061_update(s); | |
282 | } | |
283 | ||
ee663e96 | 284 | static void pl061_reset(PL061State *s) |
9ee6e8bb PB |
285 | { |
286 | s->locked = 1; | |
287 | s->cr = 0xff; | |
288 | } | |
289 | ||
9596ebb7 | 290 | static void pl061_set_irq(void * opaque, int irq, int level) |
9ee6e8bb | 291 | { |
ee663e96 | 292 | PL061State *s = (PL061State *)opaque; |
9ee6e8bb PB |
293 | uint8_t mask; |
294 | ||
295 | mask = 1 << irq; | |
296 | if ((s->dir & mask) == 0) { | |
297 | s->data &= ~mask; | |
298 | if (level) | |
299 | s->data |= mask; | |
300 | pl061_update(s); | |
301 | } | |
302 | } | |
303 | ||
3cf89f8a AK |
304 | static const MemoryRegionOps pl061_ops = { |
305 | .read = pl061_read, | |
306 | .write = pl061_write, | |
307 | .endianness = DEVICE_NATIVE_ENDIAN, | |
9ee6e8bb PB |
308 | }; |
309 | ||
692a76d1 | 310 | static int pl061_initfn(SysBusDevice *sbd) |
9ee6e8bb | 311 | { |
692a76d1 AF |
312 | DeviceState *dev = DEVICE(sbd); |
313 | PL061State *s = PL061(dev); | |
314 | ||
b7163687 | 315 | memory_region_init_io(&s->iomem, OBJECT(s), &pl061_ops, s, "pl061", 0x1000); |
692a76d1 AF |
316 | sysbus_init_mmio(sbd, &s->iomem); |
317 | sysbus_init_irq(sbd, &s->irq); | |
318 | qdev_init_gpio_in(dev, pl061_set_irq, 8); | |
319 | qdev_init_gpio_out(dev, s->out, 8); | |
9ee6e8bb | 320 | pl061_reset(s); |
81a322d4 | 321 | return 0; |
9ee6e8bb | 322 | } |
40905a6a | 323 | |
692a76d1 | 324 | static void pl061_luminary_init(Object *obj) |
7063f49f | 325 | { |
692a76d1 AF |
326 | PL061State *s = PL061(obj); |
327 | ||
328 | s->id = pl061_id_luminary; | |
7063f49f PM |
329 | } |
330 | ||
692a76d1 | 331 | static void pl061_init(Object *obj) |
7063f49f | 332 | { |
692a76d1 AF |
333 | PL061State *s = PL061(obj); |
334 | ||
335 | s->id = pl061_id; | |
7063f49f PM |
336 | } |
337 | ||
999e12bb AL |
338 | static void pl061_class_init(ObjectClass *klass, void *data) |
339 | { | |
39bffca2 | 340 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
341 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
342 | ||
692a76d1 | 343 | k->init = pl061_initfn; |
39bffca2 | 344 | dc->vmsd = &vmstate_pl061; |
999e12bb AL |
345 | } |
346 | ||
8c43a6f0 | 347 | static const TypeInfo pl061_info = { |
692a76d1 | 348 | .name = TYPE_PL061, |
39bffca2 | 349 | .parent = TYPE_SYS_BUS_DEVICE, |
ee663e96 | 350 | .instance_size = sizeof(PL061State), |
692a76d1 | 351 | .instance_init = pl061_init, |
39bffca2 | 352 | .class_init = pl061_class_init, |
a35faa94 PM |
353 | }; |
354 | ||
8c43a6f0 | 355 | static const TypeInfo pl061_luminary_info = { |
39bffca2 | 356 | .name = "pl061_luminary", |
692a76d1 AF |
357 | .parent = TYPE_PL061, |
358 | .instance_init = pl061_luminary_init, | |
a35faa94 PM |
359 | }; |
360 | ||
83f7d43a | 361 | static void pl061_register_types(void) |
40905a6a | 362 | { |
39bffca2 AL |
363 | type_register_static(&pl061_info); |
364 | type_register_static(&pl061_luminary_info); | |
40905a6a PB |
365 | } |
366 | ||
83f7d43a | 367 | type_init(pl061_register_types) |