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a89d01c1 GX |
1 | /* |
2 | * GPIO device simulation in PKUnity SoC | |
3 | * | |
4 | * Copyright (C) 2010-2012 Guan Xuetao | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation, or any later version. | |
9 | * See the COPYING file in the top-level directory. | |
10 | */ | |
0b8fa32f | 11 | |
5af98cc5 | 12 | #include "qemu/osdep.h" |
83c9f4ca | 13 | #include "hw/sysbus.h" |
db1015e9 | 14 | #include "qom/object.h" |
a89d01c1 GX |
15 | |
16 | #undef DEBUG_PUV3 | |
0d09e41a | 17 | #include "hw/unicore32/puv3.h" |
0b8fa32f | 18 | #include "qemu/module.h" |
3b34ee67 | 19 | #include "qemu/log.h" |
a89d01c1 | 20 | |
1ed09e2f | 21 | #define TYPE_PUV3_GPIO "puv3_gpio" |
db1015e9 | 22 | typedef struct PUV3GPIOState PUV3GPIOState; |
8110fa1d EH |
23 | DECLARE_INSTANCE_CHECKER(PUV3GPIOState, PUV3_GPIO, |
24 | TYPE_PUV3_GPIO) | |
1ed09e2f | 25 | |
db1015e9 | 26 | struct PUV3GPIOState { |
1ed09e2f AF |
27 | SysBusDevice parent_obj; |
28 | ||
a89d01c1 GX |
29 | MemoryRegion iomem; |
30 | qemu_irq irq[9]; | |
31 | ||
32 | uint32_t reg_GPLR; | |
33 | uint32_t reg_GPDR; | |
34 | uint32_t reg_GPIR; | |
db1015e9 | 35 | }; |
a89d01c1 | 36 | |
a8170e5e | 37 | static uint64_t puv3_gpio_read(void *opaque, hwaddr offset, |
a89d01c1 GX |
38 | unsigned size) |
39 | { | |
40 | PUV3GPIOState *s = opaque; | |
41 | uint32_t ret = 0; | |
42 | ||
43 | switch (offset) { | |
44 | case 0x00: | |
45 | ret = s->reg_GPLR; | |
46 | break; | |
47 | case 0x04: | |
48 | ret = s->reg_GPDR; | |
49 | break; | |
50 | case 0x20: | |
51 | ret = s->reg_GPIR; | |
52 | break; | |
53 | default: | |
3b34ee67 PMD |
54 | qemu_log_mask(LOG_GUEST_ERROR, |
55 | "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | |
56 | __func__, offset); | |
a89d01c1 GX |
57 | } |
58 | DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); | |
59 | ||
60 | return ret; | |
61 | } | |
62 | ||
a8170e5e | 63 | static void puv3_gpio_write(void *opaque, hwaddr offset, |
a89d01c1 GX |
64 | uint64_t value, unsigned size) |
65 | { | |
66 | PUV3GPIOState *s = opaque; | |
67 | ||
68 | DPRINTF("offset 0x%x, value 0x%x\n", offset, value); | |
69 | switch (offset) { | |
70 | case 0x04: | |
71 | s->reg_GPDR = value; | |
72 | break; | |
73 | case 0x08: | |
74 | if (s->reg_GPDR & value) { | |
75 | s->reg_GPLR |= value; | |
76 | } else { | |
3b34ee67 PMD |
77 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n", |
78 | __func__); | |
a89d01c1 GX |
79 | } |
80 | break; | |
81 | case 0x0c: | |
82 | if (s->reg_GPDR & value) { | |
83 | s->reg_GPLR &= ~value; | |
84 | } else { | |
3b34ee67 PMD |
85 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n", |
86 | __func__); | |
a89d01c1 GX |
87 | } |
88 | break; | |
89 | case 0x10: /* GRER */ | |
90 | case 0x14: /* GFER */ | |
91 | case 0x18: /* GEDR */ | |
92 | break; | |
93 | case 0x20: /* GPIR */ | |
94 | s->reg_GPIR = value; | |
95 | break; | |
96 | default: | |
3b34ee67 PMD |
97 | qemu_log_mask(LOG_GUEST_ERROR, |
98 | "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | |
99 | __func__, offset); | |
a89d01c1 GX |
100 | } |
101 | } | |
102 | ||
103 | static const MemoryRegionOps puv3_gpio_ops = { | |
104 | .read = puv3_gpio_read, | |
105 | .write = puv3_gpio_write, | |
106 | .impl = { | |
107 | .min_access_size = 4, | |
108 | .max_access_size = 4, | |
109 | }, | |
110 | .endianness = DEVICE_NATIVE_ENDIAN, | |
111 | }; | |
112 | ||
671872b6 | 113 | static void puv3_gpio_realize(DeviceState *dev, Error **errp) |
a89d01c1 | 114 | { |
1ed09e2f | 115 | PUV3GPIOState *s = PUV3_GPIO(dev); |
671872b6 | 116 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
a89d01c1 GX |
117 | |
118 | s->reg_GPLR = 0; | |
119 | s->reg_GPDR = 0; | |
120 | ||
121 | /* FIXME: these irqs not handled yet */ | |
671872b6 MZ |
122 | sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW0]); |
123 | sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW1]); | |
124 | sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW2]); | |
125 | sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW3]); | |
126 | sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW4]); | |
127 | sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW5]); | |
128 | sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW6]); | |
129 | sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW7]); | |
130 | sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOHIGH]); | |
a89d01c1 | 131 | |
b7163687 | 132 | memory_region_init_io(&s->iomem, OBJECT(s), &puv3_gpio_ops, s, "puv3_gpio", |
a89d01c1 | 133 | PUV3_REGS_OFFSET); |
671872b6 | 134 | sysbus_init_mmio(sbd, &s->iomem); |
a89d01c1 GX |
135 | } |
136 | ||
137 | static void puv3_gpio_class_init(ObjectClass *klass, void *data) | |
138 | { | |
671872b6 | 139 | DeviceClass *dc = DEVICE_CLASS(klass); |
a89d01c1 | 140 | |
671872b6 | 141 | dc->realize = puv3_gpio_realize; |
a89d01c1 GX |
142 | } |
143 | ||
144 | static const TypeInfo puv3_gpio_info = { | |
1ed09e2f | 145 | .name = TYPE_PUV3_GPIO, |
a89d01c1 GX |
146 | .parent = TYPE_SYS_BUS_DEVICE, |
147 | .instance_size = sizeof(PUV3GPIOState), | |
148 | .class_init = puv3_gpio_class_init, | |
149 | }; | |
150 | ||
151 | static void puv3_gpio_register_type(void) | |
152 | { | |
153 | type_register_static(&puv3_gpio_info); | |
154 | } | |
155 | ||
156 | type_init(puv3_gpio_register_type) |