projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| d0fb9657 | 1 | # See docs/devel/tracing.rst for syntax documentation. |
| 805f61bb | 2 | |
| 526dbbe0 HS |
3 | # npcm7xx_gpio.c |
| 4 | npcm7xx_gpio_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 | |
| 5 | npcm7xx_gpio_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 | |
| 6 | npcm7xx_gpio_set_input(const char *id, int32_t line, int32_t level) "%s line: %" PRIi32 " level: %" PRIi32 | |
| 7 | npcm7xx_gpio_set_output(const char *id, int32_t line, int32_t level) "%s line: %" PRIi32 " level: %" PRIi32 | |
| 8 | npcm7xx_gpio_update_events(const char *id, uint32_t evst, uint32_t even) "%s evst: 0x%08" PRIx32 " even: 0x%08" PRIx32 | |
| 9 | ||
| 500016e5 | 10 | # nrf51_gpio.c |
| 805f61bb SG |
11 | nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 |
| 12 | nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 | |
| 13 | nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 | |
| 77606363 | 14 | nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 |
| 4921a0ce | 15 | |
| 6328d8ff CLG |
16 | # pca9552.c |
| 17 | pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]" | |
| 18 | pca955x_gpio_change(const char *description, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u -> %u" | |
| 19 | ||
| 102d7d1f | 20 | # pl061.c |
| ad06d56f | 21 | pl061_update(const char *id, uint32_t dir, uint32_t data, uint32_t pullups, uint32_t floating) "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0x%x" |
| 102d7d1f PM |
22 | pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d" |
| 23 | pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d" | |
| 24 | pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" | |
| 74d359b5 PM |
25 | pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64 |
| 26 | pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64 | |
| ef4989b0 | 27 | pl061_reset(const char *id) "%s reset" |
| 102d7d1f | 28 | |
| 4921a0ce BM |
29 | # sifive_gpio.c |
| 30 | sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 | |
| 31 | sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 | |
| 32 | sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 | |
| 33 | sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 | |
| 7b1d21a8 JL |
34 | |
| 35 | # aspeed_gpio.c | |
| 36 | aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64 | |
| 37 | aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64 | |
| 1cdcfb6e IV |
38 | |
| 39 | # stm32l4x5_gpio.c | |
| 40 | stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " " | |
| 41 | stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" | |
| 42 | stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) "GPIO%s from: 0x%x to: 0x%x" | |
| 43 | stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x%x levels: 0x%x" |