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e33d8cdb AZ |
1 | /* |
2 | * Copyright (c) 2006-2008 Openedhand Ltd. | |
3 | * Written by Andrzej Zaborowski <balrog@zabor.org> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 or | |
8 | * (at your option) version 3 of the License. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
fad6cb1a | 15 | * You should have received a copy of the GNU General Public License along |
8167ee88 | 16 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
e33d8cdb | 17 | */ |
0b8fa32f | 18 | |
17b7f2db | 19 | #include "qemu/osdep.h" |
83c9f4ca | 20 | #include "hw/hw.h" |
0d09e41a | 21 | #include "hw/arm/sharpsl.h" |
83c9f4ca | 22 | #include "hw/sysbus.h" |
0b8fa32f | 23 | #include "qemu/module.h" |
e33d8cdb | 24 | |
e33d8cdb | 25 | #undef REG_FMT |
e33d8cdb | 26 | #define REG_FMT "0x%02lx" |
e33d8cdb AZ |
27 | |
28 | /* SCOOP devices */ | |
29 | ||
a009de46 AF |
30 | #define TYPE_SCOOP "scoop" |
31 | #define SCOOP(obj) OBJECT_CHECK(ScoopInfo, (obj), TYPE_SCOOP) | |
32 | ||
383d01c6 | 33 | typedef struct ScoopInfo ScoopInfo; |
bc24a225 | 34 | struct ScoopInfo { |
a009de46 AF |
35 | SysBusDevice parent_obj; |
36 | ||
e33d8cdb | 37 | qemu_irq handler[16]; |
e71ceafc | 38 | MemoryRegion iomem; |
e33d8cdb AZ |
39 | uint16_t status; |
40 | uint16_t power; | |
41 | uint32_t gpio_level; | |
42 | uint32_t gpio_dir; | |
43 | uint32_t prev_level; | |
44 | ||
45 | uint16_t mcr; | |
46 | uint16_t cdr; | |
47 | uint16_t ccr; | |
48 | uint16_t irr; | |
49 | uint16_t imr; | |
50 | uint16_t isr; | |
e33d8cdb AZ |
51 | }; |
52 | ||
53 | #define SCOOP_MCR 0x00 | |
54 | #define SCOOP_CDR 0x04 | |
55 | #define SCOOP_CSR 0x08 | |
56 | #define SCOOP_CPR 0x0c | |
57 | #define SCOOP_CCR 0x10 | |
58 | #define SCOOP_IRR_IRM 0x14 | |
59 | #define SCOOP_IMR 0x18 | |
60 | #define SCOOP_ISR 0x1c | |
61 | #define SCOOP_GPCR 0x20 | |
62 | #define SCOOP_GPWR 0x24 | |
63 | #define SCOOP_GPRR 0x28 | |
64 | ||
bc24a225 | 65 | static inline void scoop_gpio_handler_update(ScoopInfo *s) { |
e33d8cdb AZ |
66 | uint32_t level, diff; |
67 | int bit; | |
68 | level = s->gpio_level & s->gpio_dir; | |
69 | ||
70 | for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { | |
786a4ea8 | 71 | bit = ctz32(diff); |
e33d8cdb AZ |
72 | qemu_set_irq(s->handler[bit], (level >> bit) & 1); |
73 | } | |
74 | ||
75 | s->prev_level = level; | |
76 | } | |
77 | ||
a8170e5e | 78 | static uint64_t scoop_read(void *opaque, hwaddr addr, |
e71ceafc | 79 | unsigned size) |
e33d8cdb | 80 | { |
bc24a225 | 81 | ScoopInfo *s = (ScoopInfo *) opaque; |
e33d8cdb | 82 | |
aa9438d9 | 83 | switch (addr & 0x3f) { |
e33d8cdb AZ |
84 | case SCOOP_MCR: |
85 | return s->mcr; | |
86 | case SCOOP_CDR: | |
87 | return s->cdr; | |
88 | case SCOOP_CSR: | |
89 | return s->status; | |
90 | case SCOOP_CPR: | |
91 | return s->power; | |
92 | case SCOOP_CCR: | |
93 | return s->ccr; | |
94 | case SCOOP_IRR_IRM: | |
95 | return s->irr; | |
96 | case SCOOP_IMR: | |
97 | return s->imr; | |
98 | case SCOOP_ISR: | |
99 | return s->isr; | |
100 | case SCOOP_GPCR: | |
101 | return s->gpio_dir; | |
102 | case SCOOP_GPWR: | |
e33d8cdb | 103 | case SCOOP_GPRR: |
1f163b14 | 104 | return s->gpio_level; |
e33d8cdb | 105 | default: |
a8b7063b | 106 | zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); |
e33d8cdb AZ |
107 | } |
108 | ||
109 | return 0; | |
110 | } | |
111 | ||
a8170e5e | 112 | static void scoop_write(void *opaque, hwaddr addr, |
e71ceafc | 113 | uint64_t value, unsigned size) |
e33d8cdb | 114 | { |
bc24a225 | 115 | ScoopInfo *s = (ScoopInfo *) opaque; |
e33d8cdb AZ |
116 | value &= 0xffff; |
117 | ||
aa9438d9 | 118 | switch (addr & 0x3f) { |
e33d8cdb AZ |
119 | case SCOOP_MCR: |
120 | s->mcr = value; | |
121 | break; | |
122 | case SCOOP_CDR: | |
123 | s->cdr = value; | |
124 | break; | |
125 | case SCOOP_CPR: | |
126 | s->power = value; | |
127 | if (value & 0x80) | |
128 | s->power |= 0x8040; | |
129 | break; | |
130 | case SCOOP_CCR: | |
131 | s->ccr = value; | |
132 | break; | |
133 | case SCOOP_IRR_IRM: | |
134 | s->irr = value; | |
135 | break; | |
136 | case SCOOP_IMR: | |
137 | s->imr = value; | |
138 | break; | |
139 | case SCOOP_ISR: | |
140 | s->isr = value; | |
141 | break; | |
142 | case SCOOP_GPCR: | |
143 | s->gpio_dir = value; | |
144 | scoop_gpio_handler_update(s); | |
145 | break; | |
146 | case SCOOP_GPWR: | |
1f163b14 | 147 | case SCOOP_GPRR: /* GPRR is probably R/O in real HW */ |
e33d8cdb AZ |
148 | s->gpio_level = value & s->gpio_dir; |
149 | scoop_gpio_handler_update(s); | |
150 | break; | |
e33d8cdb | 151 | default: |
a8b7063b | 152 | zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); |
e33d8cdb AZ |
153 | } |
154 | } | |
155 | ||
e71ceafc AK |
156 | static const MemoryRegionOps scoop_ops = { |
157 | .read = scoop_read, | |
158 | .write = scoop_write, | |
159 | .endianness = DEVICE_NATIVE_ENDIAN, | |
e33d8cdb AZ |
160 | }; |
161 | ||
383d01c6 | 162 | static void scoop_gpio_set(void *opaque, int line, int level) |
e33d8cdb | 163 | { |
8d30b794 | 164 | ScoopInfo *s = (ScoopInfo *) opaque; |
e33d8cdb AZ |
165 | |
166 | if (level) | |
167 | s->gpio_level |= (1 << line); | |
168 | else | |
169 | s->gpio_level &= ~(1 << line); | |
170 | } | |
171 | ||
53677667 | 172 | static void scoop_init(Object *obj) |
e33d8cdb | 173 | { |
53677667 XZ |
174 | DeviceState *dev = DEVICE(obj); |
175 | ScoopInfo *s = SCOOP(obj); | |
176 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
e33d8cdb | 177 | |
383d01c6 | 178 | s->status = 0x02; |
a009de46 AF |
179 | qdev_init_gpio_out(dev, s->handler, 16); |
180 | qdev_init_gpio_in(dev, scoop_gpio_set, 16); | |
53677667 | 181 | memory_region_init_io(&s->iomem, obj, &scoop_ops, s, "scoop", 0x1000); |
e33d8cdb | 182 | |
a009de46 | 183 | sysbus_init_mmio(sbd, &s->iomem); |
e33d8cdb AZ |
184 | } |
185 | ||
7fe63a17 DES |
186 | static int scoop_post_load(void *opaque, int version_id) |
187 | { | |
188 | ScoopInfo *s = (ScoopInfo *) opaque; | |
189 | int i; | |
190 | uint32_t level; | |
191 | ||
192 | level = s->gpio_level & s->gpio_dir; | |
193 | ||
194 | for (i = 0; i < 16; i++) { | |
195 | qemu_set_irq(s->handler[i], (level >> i) & 1); | |
196 | } | |
197 | ||
198 | s->prev_level = level; | |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
383d01c6 | 203 | static bool is_version_0 (void *opaque, int version_id) |
e33d8cdb | 204 | { |
383d01c6 | 205 | return version_id == 0; |
e33d8cdb AZ |
206 | } |
207 | ||
52f91c37 MT |
208 | static bool vmstate_scoop_validate(void *opaque, int version_id) |
209 | { | |
210 | ScoopInfo *s = opaque; | |
211 | ||
212 | return !(s->prev_level & 0xffff0000) && | |
213 | !(s->gpio_level & 0xffff0000) && | |
214 | !(s->gpio_dir & 0xffff0000); | |
215 | } | |
216 | ||
383d01c6 DES |
217 | static const VMStateDescription vmstate_scoop_regs = { |
218 | .name = "scoop", | |
219 | .version_id = 1, | |
220 | .minimum_version_id = 0, | |
7fe63a17 | 221 | .post_load = scoop_post_load, |
8f1e884b | 222 | .fields = (VMStateField[]) { |
383d01c6 DES |
223 | VMSTATE_UINT16(status, ScoopInfo), |
224 | VMSTATE_UINT16(power, ScoopInfo), | |
225 | VMSTATE_UINT32(gpio_level, ScoopInfo), | |
226 | VMSTATE_UINT32(gpio_dir, ScoopInfo), | |
227 | VMSTATE_UINT32(prev_level, ScoopInfo), | |
52f91c37 | 228 | VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate), |
383d01c6 DES |
229 | VMSTATE_UINT16(mcr, ScoopInfo), |
230 | VMSTATE_UINT16(cdr, ScoopInfo), | |
231 | VMSTATE_UINT16(ccr, ScoopInfo), | |
232 | VMSTATE_UINT16(irr, ScoopInfo), | |
233 | VMSTATE_UINT16(imr, ScoopInfo), | |
234 | VMSTATE_UINT16(isr, ScoopInfo), | |
235 | VMSTATE_UNUSED_TEST(is_version_0, 2), | |
236 | VMSTATE_END_OF_LIST(), | |
237 | }, | |
238 | }; | |
e33d8cdb | 239 | |
999e12bb AL |
240 | static void scoop_sysbus_class_init(ObjectClass *klass, void *data) |
241 | { | |
39bffca2 | 242 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 243 | |
39bffca2 AL |
244 | dc->desc = "Scoop2 Sharp custom ASIC"; |
245 | dc->vmsd = &vmstate_scoop_regs; | |
999e12bb AL |
246 | } |
247 | ||
8c43a6f0 | 248 | static const TypeInfo scoop_sysbus_info = { |
a009de46 | 249 | .name = TYPE_SCOOP, |
39bffca2 AL |
250 | .parent = TYPE_SYS_BUS_DEVICE, |
251 | .instance_size = sizeof(ScoopInfo), | |
53677667 | 252 | .instance_init = scoop_init, |
39bffca2 | 253 | .class_init = scoop_sysbus_class_init, |
383d01c6 | 254 | }; |
e33d8cdb | 255 | |
83f7d43a | 256 | static void scoop_register_types(void) |
383d01c6 | 257 | { |
39bffca2 | 258 | type_register_static(&scoop_sysbus_info); |
e33d8cdb | 259 | } |
83f7d43a AF |
260 | |
261 | type_init(scoop_register_types) | |
e33d8cdb AZ |
262 | |
263 | /* Write the bootloader parameters memory area. */ | |
264 | ||
265 | #define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a) | |
266 | ||
541dc0d4 | 267 | static struct QEMU_PACKED sl_param_info { |
e33d8cdb AZ |
268 | uint32_t comadj_keyword; |
269 | int32_t comadj; | |
270 | ||
271 | uint32_t uuid_keyword; | |
272 | char uuid[16]; | |
273 | ||
274 | uint32_t touch_keyword; | |
275 | int32_t touch_xp; | |
276 | int32_t touch_yp; | |
277 | int32_t touch_xd; | |
278 | int32_t touch_yd; | |
279 | ||
280 | uint32_t adadj_keyword; | |
281 | int32_t adadj; | |
282 | ||
283 | uint32_t phad_keyword; | |
284 | int32_t phadadj; | |
285 | } zaurus_bootparam = { | |
286 | .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'), | |
287 | .comadj = 125, | |
288 | .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'), | |
289 | .uuid = { -1 }, | |
290 | .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'), | |
291 | .touch_xp = -1, | |
292 | .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'), | |
293 | .adadj = -1, | |
294 | .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'), | |
295 | .phadadj = 0x01, | |
296 | }; | |
297 | ||
a8170e5e | 298 | void sl_bootparam_write(hwaddr ptr) |
e33d8cdb | 299 | { |
e1fe50dc | 300 | cpu_physical_memory_write(ptr, &zaurus_bootparam, |
f78630ab | 301 | sizeof(struct sl_param_info)); |
e33d8cdb | 302 | } |