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fde7d5bd TS |
1 | /* |
2 | * QEMU GT64120 PCI host | |
3 | * | |
4de9b249 | 4 | * Copyright (c) 2006,2007 Aurelien Jarno |
fde7d5bd TS |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "vl.h" | |
05b4ff43 | 26 | |
fde7d5bd TS |
27 | typedef target_phys_addr_t pci_addr_t; |
28 | #include "pci_host.h" | |
29 | ||
05b4ff43 TS |
30 | //#define DEBUG |
31 | ||
32 | #ifdef DEBUG | |
33 | #define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) | |
34 | #else | |
35 | #define dprintf(fmt, ...) | |
36 | #endif | |
37 | ||
fde7d5bd TS |
38 | #define GT_REGS (0x1000 >> 2) |
39 | ||
40 | /* CPU Configuration */ | |
41 | #define GT_CPU (0x000 >> 2) | |
42 | #define GT_MULTI (0x120 >> 2) | |
43 | ||
44 | /* CPU Address Decode */ | |
45 | #define GT_SCS10LD (0x008 >> 2) | |
46 | #define GT_SCS10HD (0x010 >> 2) | |
47 | #define GT_SCS32LD (0x018 >> 2) | |
48 | #define GT_SCS32HD (0x020 >> 2) | |
49 | #define GT_CS20LD (0x028 >> 2) | |
50 | #define GT_CS20HD (0x030 >> 2) | |
51 | #define GT_CS3BOOTLD (0x038 >> 2) | |
52 | #define GT_CS3BOOTHD (0x040 >> 2) | |
53 | #define GT_PCI0IOLD (0x048 >> 2) | |
54 | #define GT_PCI0IOHD (0x050 >> 2) | |
55 | #define GT_PCI0M0LD (0x058 >> 2) | |
56 | #define GT_PCI0M0HD (0x060 >> 2) | |
fde7d5bd TS |
57 | #define GT_PCI0M1LD (0x080 >> 2) |
58 | #define GT_PCI0M1HD (0x088 >> 2) | |
59 | #define GT_PCI1IOLD (0x090 >> 2) | |
60 | #define GT_PCI1IOHD (0x098 >> 2) | |
61 | #define GT_PCI1M0LD (0x0a0 >> 2) | |
62 | #define GT_PCI1M0HD (0x0a8 >> 2) | |
63 | #define GT_PCI1M1LD (0x0b0 >> 2) | |
64 | #define GT_PCI1M1HD (0x0b8 >> 2) | |
05b4ff43 | 65 | #define GT_ISD (0x068 >> 2) |
fde7d5bd TS |
66 | |
67 | #define GT_SCS10AR (0x0d0 >> 2) | |
68 | #define GT_SCS32AR (0x0d8 >> 2) | |
69 | #define GT_CS20R (0x0e0 >> 2) | |
70 | #define GT_CS3BOOTR (0x0e8 >> 2) | |
71 | ||
72 | #define GT_PCI0IOREMAP (0x0f0 >> 2) | |
73 | #define GT_PCI0M0REMAP (0x0f8 >> 2) | |
74 | #define GT_PCI0M1REMAP (0x100 >> 2) | |
75 | #define GT_PCI1IOREMAP (0x108 >> 2) | |
76 | #define GT_PCI1M0REMAP (0x110 >> 2) | |
77 | #define GT_PCI1M1REMAP (0x118 >> 2) | |
78 | ||
79 | /* CPU Error Report */ | |
80 | #define GT_CPUERR_ADDRLO (0x070 >> 2) | |
81 | #define GT_CPUERR_ADDRHI (0x078 >> 2) | |
82 | #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ | |
83 | #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ | |
84 | #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ | |
85 | ||
86 | /* CPU Sync Barrier */ | |
87 | #define GT_PCI0SYNC (0x0c0 >> 2) | |
88 | #define GT_PCI1SYNC (0x0c8 >> 2) | |
89 | ||
90 | /* SDRAM and Device Address Decode */ | |
91 | #define GT_SCS0LD (0x400 >> 2) | |
92 | #define GT_SCS0HD (0x404 >> 2) | |
93 | #define GT_SCS1LD (0x408 >> 2) | |
94 | #define GT_SCS1HD (0x40c >> 2) | |
95 | #define GT_SCS2LD (0x410 >> 2) | |
96 | #define GT_SCS2HD (0x414 >> 2) | |
97 | #define GT_SCS3LD (0x418 >> 2) | |
98 | #define GT_SCS3HD (0x41c >> 2) | |
99 | #define GT_CS0LD (0x420 >> 2) | |
100 | #define GT_CS0HD (0x424 >> 2) | |
101 | #define GT_CS1LD (0x428 >> 2) | |
102 | #define GT_CS1HD (0x42c >> 2) | |
103 | #define GT_CS2LD (0x430 >> 2) | |
104 | #define GT_CS2HD (0x434 >> 2) | |
105 | #define GT_CS3LD (0x438 >> 2) | |
106 | #define GT_CS3HD (0x43c >> 2) | |
107 | #define GT_BOOTLD (0x440 >> 2) | |
108 | #define GT_BOOTHD (0x444 >> 2) | |
109 | #define GT_ADERR (0x470 >> 2) | |
110 | ||
111 | /* SDRAM Configuration */ | |
112 | #define GT_SDRAM_CFG (0x448 >> 2) | |
113 | #define GT_SDRAM_OPMODE (0x474 >> 2) | |
114 | #define GT_SDRAM_BM (0x478 >> 2) | |
115 | #define GT_SDRAM_ADDRDECODE (0x47c >> 2) | |
116 | ||
117 | /* SDRAM Parameters */ | |
118 | #define GT_SDRAM_B0 (0x44c >> 2) | |
119 | #define GT_SDRAM_B1 (0x450 >> 2) | |
120 | #define GT_SDRAM_B2 (0x454 >> 2) | |
121 | #define GT_SDRAM_B3 (0x458 >> 2) | |
122 | ||
123 | /* Device Parameters */ | |
124 | #define GT_DEV_B0 (0x45c >> 2) | |
125 | #define GT_DEV_B1 (0x460 >> 2) | |
126 | #define GT_DEV_B2 (0x464 >> 2) | |
127 | #define GT_DEV_B3 (0x468 >> 2) | |
128 | #define GT_DEV_BOOT (0x46c >> 2) | |
129 | ||
130 | /* ECC */ | |
131 | #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ | |
132 | #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ | |
133 | #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ | |
134 | #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ | |
135 | #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ | |
136 | ||
137 | /* DMA Record */ | |
138 | #define GT_DMA0_CNT (0x800 >> 2) | |
139 | #define GT_DMA1_CNT (0x804 >> 2) | |
140 | #define GT_DMA2_CNT (0x808 >> 2) | |
141 | #define GT_DMA3_CNT (0x80c >> 2) | |
142 | #define GT_DMA0_SA (0x810 >> 2) | |
143 | #define GT_DMA1_SA (0x814 >> 2) | |
144 | #define GT_DMA2_SA (0x818 >> 2) | |
145 | #define GT_DMA3_SA (0x81c >> 2) | |
146 | #define GT_DMA0_DA (0x820 >> 2) | |
147 | #define GT_DMA1_DA (0x824 >> 2) | |
148 | #define GT_DMA2_DA (0x828 >> 2) | |
149 | #define GT_DMA3_DA (0x82c >> 2) | |
150 | #define GT_DMA0_NEXT (0x830 >> 2) | |
151 | #define GT_DMA1_NEXT (0x834 >> 2) | |
152 | #define GT_DMA2_NEXT (0x838 >> 2) | |
153 | #define GT_DMA3_NEXT (0x83c >> 2) | |
154 | #define GT_DMA0_CUR (0x870 >> 2) | |
155 | #define GT_DMA1_CUR (0x874 >> 2) | |
156 | #define GT_DMA2_CUR (0x878 >> 2) | |
157 | #define GT_DMA3_CUR (0x87c >> 2) | |
158 | ||
159 | /* DMA Channel Control */ | |
160 | #define GT_DMA0_CTRL (0x840 >> 2) | |
161 | #define GT_DMA1_CTRL (0x844 >> 2) | |
162 | #define GT_DMA2_CTRL (0x848 >> 2) | |
163 | #define GT_DMA3_CTRL (0x84c >> 2) | |
164 | ||
165 | /* DMA Arbiter */ | |
166 | #define GT_DMA_ARB (0x860 >> 2) | |
167 | ||
168 | /* Timer/Counter */ | |
169 | #define GT_TC0 (0x850 >> 2) | |
170 | #define GT_TC1 (0x854 >> 2) | |
171 | #define GT_TC2 (0x858 >> 2) | |
172 | #define GT_TC3 (0x85c >> 2) | |
173 | #define GT_TC_CONTROL (0x864 >> 2) | |
174 | ||
175 | /* PCI Internal */ | |
176 | #define GT_PCI0_CMD (0xc00 >> 2) | |
177 | #define GT_PCI0_TOR (0xc04 >> 2) | |
178 | #define GT_PCI0_BS_SCS10 (0xc08 >> 2) | |
179 | #define GT_PCI0_BS_SCS32 (0xc0c >> 2) | |
180 | #define GT_PCI0_BS_CS20 (0xc10 >> 2) | |
181 | #define GT_PCI0_BS_CS3BT (0xc14 >> 2) | |
182 | #define GT_PCI1_IACK (0xc30 >> 2) | |
183 | #define GT_PCI0_IACK (0xc34 >> 2) | |
184 | #define GT_PCI0_BARE (0xc3c >> 2) | |
185 | #define GT_PCI0_PREFMBR (0xc40 >> 2) | |
186 | #define GT_PCI0_SCS10_BAR (0xc48 >> 2) | |
187 | #define GT_PCI0_SCS32_BAR (0xc4c >> 2) | |
188 | #define GT_PCI0_CS20_BAR (0xc50 >> 2) | |
189 | #define GT_PCI0_CS3BT_BAR (0xc54 >> 2) | |
190 | #define GT_PCI0_SSCS10_BAR (0xc58 >> 2) | |
191 | #define GT_PCI0_SSCS32_BAR (0xc5c >> 2) | |
192 | #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) | |
193 | #define GT_PCI1_CMD (0xc80 >> 2) | |
194 | #define GT_PCI1_TOR (0xc84 >> 2) | |
195 | #define GT_PCI1_BS_SCS10 (0xc88 >> 2) | |
196 | #define GT_PCI1_BS_SCS32 (0xc8c >> 2) | |
197 | #define GT_PCI1_BS_CS20 (0xc90 >> 2) | |
198 | #define GT_PCI1_BS_CS3BT (0xc94 >> 2) | |
199 | #define GT_PCI1_BARE (0xcbc >> 2) | |
200 | #define GT_PCI1_PREFMBR (0xcc0 >> 2) | |
201 | #define GT_PCI1_SCS10_BAR (0xcc8 >> 2) | |
202 | #define GT_PCI1_SCS32_BAR (0xccc >> 2) | |
203 | #define GT_PCI1_CS20_BAR (0xcd0 >> 2) | |
204 | #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) | |
205 | #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) | |
206 | #define GT_PCI1_SSCS32_BAR (0xcdc >> 2) | |
207 | #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) | |
208 | #define GT_PCI1_CFGADDR (0xcf0 >> 2) | |
209 | #define GT_PCI1_CFGDATA (0xcf4 >> 2) | |
210 | #define GT_PCI0_CFGADDR (0xcf8 >> 2) | |
211 | #define GT_PCI0_CFGDATA (0xcfc >> 2) | |
212 | ||
213 | /* Interrupts */ | |
214 | #define GT_INTRCAUSE (0xc18 >> 2) | |
215 | #define GT_INTRMASK (0xc1c >> 2) | |
216 | #define GT_PCI0_ICMASK (0xc24 >> 2) | |
217 | #define GT_PCI0_SERR0MASK (0xc28 >> 2) | |
218 | #define GT_CPU_INTSEL (0xc70 >> 2) | |
219 | #define GT_PCI0_INTSEL (0xc74 >> 2) | |
220 | #define GT_HINTRCAUSE (0xc98 >> 2) | |
221 | #define GT_HINTRMASK (0xc9c >> 2) | |
222 | #define GT_PCI0_HICMASK (0xca4 >> 2) | |
223 | #define GT_PCI1_SERR1MASK (0xca8 >> 2) | |
224 | ||
225 | ||
226 | typedef PCIHostState GT64120PCIState; | |
227 | ||
a0a8793e TS |
228 | #define PCI_MAPPING_ENTRY(regname) \ |
229 | target_phys_addr_t regname ##_start; \ | |
230 | target_phys_addr_t regname ##_length; \ | |
231 | int regname ##_handle | |
232 | ||
fde7d5bd TS |
233 | typedef struct GT64120State { |
234 | GT64120PCIState *pci; | |
235 | uint32_t regs[GT_REGS]; | |
a0a8793e TS |
236 | PCI_MAPPING_ENTRY(PCI0IO); |
237 | PCI_MAPPING_ENTRY(ISD); | |
fde7d5bd TS |
238 | } GT64120State; |
239 | ||
a0a8793e TS |
240 | /* Adjust range to avoid touching space which isn't mappable via PCI */ |
241 | /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 | |
242 | 0x1fc00000 - 0x1fd00000 */ | |
243 | static void check_reserved_space (target_phys_addr_t *start, | |
244 | target_phys_addr_t *length) | |
245 | { | |
246 | target_phys_addr_t begin = *start; | |
247 | target_phys_addr_t end = *start + *length; | |
248 | ||
249 | if (end >= 0x1e000000LL && end < 0x1f100000LL) | |
250 | end = 0x1e000000LL; | |
251 | if (begin >= 0x1e000000LL && begin < 0x1f100000LL) | |
252 | begin = 0x1f100000LL; | |
253 | if (end >= 0x1fc00000LL && end < 0x1fd00000LL) | |
254 | end = 0x1fc00000LL; | |
255 | if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) | |
256 | begin = 0x1fd00000LL; | |
257 | /* XXX: This is broken when a reserved range splits the requested range */ | |
258 | if (end >= 0x1f100000LL && begin < 0x1e000000LL) | |
259 | end = 0x1e000000LL; | |
260 | if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) | |
261 | end = 0x1fc00000LL; | |
262 | ||
263 | *start = begin; | |
264 | *length = end - begin; | |
265 | } | |
266 | ||
267 | static void gt64120_isd_mapping(GT64120State *s) | |
268 | { | |
269 | target_phys_addr_t start = s->regs[GT_ISD] << 21; | |
270 | target_phys_addr_t length = 0x1000; | |
271 | ||
272 | if (s->ISD_length) | |
273 | cpu_register_physical_memory(s->ISD_start, s->ISD_length, | |
274 | IO_MEM_UNASSIGNED); | |
275 | check_reserved_space(&start, &length); | |
276 | length = 0x1000; | |
277 | /* Map new address */ | |
278 | dprintf("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start, | |
279 | length, start, s->ISD_handle); | |
280 | s->ISD_start = start; | |
281 | s->ISD_length = length; | |
282 | cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle); | |
283 | } | |
284 | ||
9414cc6f | 285 | static void gt64120_pci_mapping(GT64120State *s) |
2a1086d9 | 286 | { |
9414cc6f TS |
287 | /* Update IO mapping */ |
288 | if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) | |
289 | { | |
290 | /* Unmap old IO address */ | |
291 | if (s->PCI0IO_length) | |
292 | { | |
293 | cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED); | |
294 | } | |
295 | /* Map new IO address */ | |
296 | s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; | |
297 | s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; | |
298 | isa_mem_base = s->PCI0IO_start; | |
299 | isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length); | |
300 | } | |
2a1086d9 TS |
301 | } |
302 | ||
fde7d5bd TS |
303 | static void gt64120_writel (void *opaque, target_phys_addr_t addr, |
304 | uint32_t val) | |
305 | { | |
306 | GT64120State *s = opaque; | |
307 | uint32_t saddr; | |
308 | ||
0da75eb1 TS |
309 | #ifdef TARGET_WORDS_BIGENDIAN |
310 | val = bswap32(val); | |
311 | #endif | |
312 | ||
fde7d5bd TS |
313 | saddr = (addr & 0xfff) >> 2; |
314 | switch (saddr) { | |
0da75eb1 TS |
315 | |
316 | /* CPU Configuration */ | |
fde7d5bd TS |
317 | case GT_CPU: |
318 | s->regs[GT_CPU] = val; | |
fde7d5bd TS |
319 | break; |
320 | case GT_MULTI: | |
0da75eb1 | 321 | /* Read-only register as only one GT64xxx is present on the CPU bus */ |
fde7d5bd TS |
322 | break; |
323 | ||
324 | /* CPU Address Decode */ | |
325 | case GT_PCI0IOLD: | |
326 | s->regs[GT_PCI0IOLD] = val & 0x00007fff; | |
327 | s->regs[GT_PCI0IOREMAP] = val & 0x000007ff; | |
9414cc6f | 328 | gt64120_pci_mapping(s); |
fde7d5bd TS |
329 | break; |
330 | case GT_PCI0M0LD: | |
331 | s->regs[GT_PCI0M0LD] = val & 0x00007fff; | |
332 | s->regs[GT_PCI0M0REMAP] = val & 0x000007ff; | |
9414cc6f | 333 | gt64120_pci_mapping(s); |
fde7d5bd TS |
334 | break; |
335 | case GT_PCI0M1LD: | |
336 | s->regs[GT_PCI0M1LD] = val & 0x00007fff; | |
337 | s->regs[GT_PCI0M1REMAP] = val & 0x000007ff; | |
9414cc6f | 338 | gt64120_pci_mapping(s); |
fde7d5bd TS |
339 | break; |
340 | case GT_PCI1IOLD: | |
341 | s->regs[GT_PCI1IOLD] = val & 0x00007fff; | |
342 | s->regs[GT_PCI1IOREMAP] = val & 0x000007ff; | |
9414cc6f | 343 | gt64120_pci_mapping(s); |
fde7d5bd TS |
344 | break; |
345 | case GT_PCI1M0LD: | |
346 | s->regs[GT_PCI1M0LD] = val & 0x00007fff; | |
347 | s->regs[GT_PCI1M0REMAP] = val & 0x000007ff; | |
9414cc6f | 348 | gt64120_pci_mapping(s); |
fde7d5bd TS |
349 | break; |
350 | case GT_PCI1M1LD: | |
351 | s->regs[GT_PCI1M1LD] = val & 0x00007fff; | |
352 | s->regs[GT_PCI1M1REMAP] = val & 0x000007ff; | |
9414cc6f | 353 | gt64120_pci_mapping(s); |
fde7d5bd TS |
354 | break; |
355 | case GT_PCI0IOHD: | |
356 | case GT_PCI0M0HD: | |
357 | case GT_PCI0M1HD: | |
358 | case GT_PCI1IOHD: | |
359 | case GT_PCI1M0HD: | |
360 | case GT_PCI1M1HD: | |
361 | s->regs[saddr] = val & 0x0000007f; | |
9414cc6f | 362 | gt64120_pci_mapping(s); |
fde7d5bd | 363 | break; |
a0a8793e TS |
364 | case GT_ISD: |
365 | s->regs[saddr] = val & 0x00007fff; | |
366 | gt64120_isd_mapping(s); | |
367 | break; | |
368 | ||
fde7d5bd TS |
369 | case GT_PCI0IOREMAP: |
370 | case GT_PCI0M0REMAP: | |
371 | case GT_PCI0M1REMAP: | |
372 | case GT_PCI1IOREMAP: | |
373 | case GT_PCI1M0REMAP: | |
374 | case GT_PCI1M1REMAP: | |
375 | s->regs[saddr] = val & 0x000007ff; | |
9414cc6f | 376 | gt64120_pci_mapping(s); |
fde7d5bd TS |
377 | break; |
378 | ||
379 | /* CPU Error Report */ | |
380 | case GT_CPUERR_ADDRLO: | |
381 | case GT_CPUERR_ADDRHI: | |
382 | case GT_CPUERR_DATALO: | |
383 | case GT_CPUERR_DATAHI: | |
384 | case GT_CPUERR_PARITY: | |
0da75eb1 TS |
385 | /* Read-only registers, do nothing */ |
386 | break; | |
387 | ||
388 | /* CPU Sync Barrier */ | |
389 | case GT_PCI0SYNC: | |
390 | case GT_PCI1SYNC: | |
391 | /* Read-only registers, do nothing */ | |
fde7d5bd TS |
392 | break; |
393 | ||
05b4ff43 TS |
394 | /* SDRAM and Device Address Decode */ |
395 | case GT_SCS0LD: | |
396 | case GT_SCS0HD: | |
397 | case GT_SCS1LD: | |
398 | case GT_SCS1HD: | |
399 | case GT_SCS2LD: | |
400 | case GT_SCS2HD: | |
401 | case GT_SCS3LD: | |
402 | case GT_SCS3HD: | |
403 | case GT_CS0LD: | |
404 | case GT_CS0HD: | |
405 | case GT_CS1LD: | |
406 | case GT_CS1HD: | |
407 | case GT_CS2LD: | |
408 | case GT_CS2HD: | |
409 | case GT_CS3LD: | |
410 | case GT_CS3HD: | |
411 | case GT_BOOTLD: | |
412 | case GT_BOOTHD: | |
413 | case GT_ADERR: | |
414 | /* SDRAM Configuration */ | |
415 | case GT_SDRAM_CFG: | |
416 | case GT_SDRAM_OPMODE: | |
417 | case GT_SDRAM_BM: | |
418 | case GT_SDRAM_ADDRDECODE: | |
419 | /* Accept and ignore SDRAM interleave configuration */ | |
420 | s->regs[saddr] = val; | |
421 | break; | |
422 | ||
423 | /* Device Parameters */ | |
424 | case GT_DEV_B0: | |
425 | case GT_DEV_B1: | |
426 | case GT_DEV_B2: | |
427 | case GT_DEV_B3: | |
428 | case GT_DEV_BOOT: | |
429 | /* Not implemented */ | |
430 | dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2); | |
431 | break; | |
432 | ||
fde7d5bd TS |
433 | /* ECC */ |
434 | case GT_ECC_ERRDATALO: | |
435 | case GT_ECC_ERRDATAHI: | |
436 | case GT_ECC_MEM: | |
437 | case GT_ECC_CALC: | |
438 | case GT_ECC_ERRADDR: | |
0da75eb1 | 439 | /* Read-only registers, do nothing */ |
fde7d5bd TS |
440 | break; |
441 | ||
05b4ff43 TS |
442 | /* DMA Record */ |
443 | case GT_DMA0_CNT: | |
444 | case GT_DMA1_CNT: | |
445 | case GT_DMA2_CNT: | |
446 | case GT_DMA3_CNT: | |
447 | case GT_DMA0_SA: | |
448 | case GT_DMA1_SA: | |
449 | case GT_DMA2_SA: | |
450 | case GT_DMA3_SA: | |
451 | case GT_DMA0_DA: | |
452 | case GT_DMA1_DA: | |
453 | case GT_DMA2_DA: | |
454 | case GT_DMA3_DA: | |
455 | case GT_DMA0_NEXT: | |
456 | case GT_DMA1_NEXT: | |
457 | case GT_DMA2_NEXT: | |
458 | case GT_DMA3_NEXT: | |
459 | case GT_DMA0_CUR: | |
460 | case GT_DMA1_CUR: | |
461 | case GT_DMA2_CUR: | |
462 | case GT_DMA3_CUR: | |
463 | /* Not implemented */ | |
464 | dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2); | |
465 | break; | |
466 | ||
467 | /* DMA Channel Control */ | |
468 | case GT_DMA0_CTRL: | |
469 | case GT_DMA1_CTRL: | |
470 | case GT_DMA2_CTRL: | |
471 | case GT_DMA3_CTRL: | |
472 | /* Not implemented */ | |
473 | dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2); | |
474 | break; | |
475 | ||
476 | /* DMA Arbiter */ | |
477 | case GT_DMA_ARB: | |
478 | /* Not implemented */ | |
479 | dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2); | |
480 | break; | |
481 | ||
482 | /* Timer/Counter */ | |
483 | case GT_TC0: | |
484 | case GT_TC1: | |
485 | case GT_TC2: | |
486 | case GT_TC3: | |
487 | case GT_TC_CONTROL: | |
488 | /* Not implemented */ | |
489 | dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2); | |
490 | break; | |
491 | ||
fde7d5bd TS |
492 | /* PCI Internal */ |
493 | case GT_PCI0_CMD: | |
494 | case GT_PCI1_CMD: | |
495 | s->regs[saddr] = val & 0x0401fc0f; | |
496 | break; | |
05b4ff43 TS |
497 | case GT_PCI0_TOR: |
498 | case GT_PCI0_BS_SCS10: | |
499 | case GT_PCI0_BS_SCS32: | |
500 | case GT_PCI0_BS_CS20: | |
501 | case GT_PCI0_BS_CS3BT: | |
502 | case GT_PCI1_IACK: | |
503 | case GT_PCI0_IACK: | |
504 | case GT_PCI0_BARE: | |
505 | case GT_PCI0_PREFMBR: | |
506 | case GT_PCI0_SCS10_BAR: | |
507 | case GT_PCI0_SCS32_BAR: | |
508 | case GT_PCI0_CS20_BAR: | |
509 | case GT_PCI0_CS3BT_BAR: | |
510 | case GT_PCI0_SSCS10_BAR: | |
511 | case GT_PCI0_SSCS32_BAR: | |
512 | case GT_PCI0_SCS3BT_BAR: | |
513 | case GT_PCI1_TOR: | |
514 | case GT_PCI1_BS_SCS10: | |
515 | case GT_PCI1_BS_SCS32: | |
516 | case GT_PCI1_BS_CS20: | |
517 | case GT_PCI1_BS_CS3BT: | |
518 | case GT_PCI1_BARE: | |
519 | case GT_PCI1_PREFMBR: | |
520 | case GT_PCI1_SCS10_BAR: | |
521 | case GT_PCI1_SCS32_BAR: | |
522 | case GT_PCI1_CS20_BAR: | |
523 | case GT_PCI1_CS3BT_BAR: | |
524 | case GT_PCI1_SSCS10_BAR: | |
525 | case GT_PCI1_SSCS32_BAR: | |
526 | case GT_PCI1_SCS3BT_BAR: | |
527 | case GT_PCI1_CFGADDR: | |
528 | case GT_PCI1_CFGDATA: | |
529 | /* not implemented */ | |
530 | break; | |
fde7d5bd TS |
531 | case GT_PCI0_CFGADDR: |
532 | s->pci->config_reg = val & 0x80fffffc; | |
533 | break; | |
534 | case GT_PCI0_CFGDATA: | |
05b4ff43 TS |
535 | if (s->pci->config_reg & (1u << 31)) |
536 | pci_host_data_writel(s->pci, 0, val); | |
537 | break; | |
538 | ||
539 | /* Interrupts */ | |
540 | case GT_INTRCAUSE: | |
541 | /* not really implemented */ | |
542 | s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); | |
543 | s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); | |
544 | dprintf("INTRCAUSE %x\n", val); | |
545 | break; | |
546 | case GT_INTRMASK: | |
547 | s->regs[saddr] = val & 0x3c3ffffe; | |
548 | dprintf("INTRMASK %x\n", val); | |
549 | break; | |
550 | case GT_PCI0_ICMASK: | |
551 | s->regs[saddr] = val & 0x03fffffe; | |
552 | dprintf("ICMASK %x\n", val); | |
553 | break; | |
554 | case GT_PCI0_SERR0MASK: | |
555 | s->regs[saddr] = val & 0x0000003f; | |
556 | dprintf("SERR0MASK %x\n", val); | |
557 | break; | |
558 | ||
559 | /* Reserved when only PCI_0 is configured. */ | |
560 | case GT_HINTRCAUSE: | |
561 | case GT_CPU_INTSEL: | |
562 | case GT_PCI0_INTSEL: | |
563 | case GT_HINTRMASK: | |
564 | case GT_PCI0_HICMASK: | |
565 | case GT_PCI1_SERR1MASK: | |
566 | /* not implemented */ | |
fde7d5bd TS |
567 | break; |
568 | ||
0da75eb1 TS |
569 | /* SDRAM Parameters */ |
570 | case GT_SDRAM_B0: | |
571 | case GT_SDRAM_B1: | |
572 | case GT_SDRAM_B2: | |
573 | case GT_SDRAM_B3: | |
574 | /* We don't simulate electrical parameters of the SDRAM. | |
575 | Accept, but ignore the values. */ | |
576 | s->regs[saddr] = val; | |
577 | break; | |
578 | ||
fde7d5bd | 579 | default: |
05b4ff43 | 580 | dprintf ("Bad register offset 0x%x\n", (int)addr); |
fde7d5bd TS |
581 | break; |
582 | } | |
583 | } | |
584 | ||
585 | static uint32_t gt64120_readl (void *opaque, | |
586 | target_phys_addr_t addr) | |
587 | { | |
588 | GT64120State *s = opaque; | |
589 | uint32_t val; | |
590 | uint32_t saddr; | |
591 | ||
592 | val = 0; | |
593 | saddr = (addr & 0xfff) >> 2; | |
594 | ||
595 | switch (saddr) { | |
596 | ||
0da75eb1 TS |
597 | /* CPU Configuration */ |
598 | case GT_MULTI: | |
599 | /* Only one GT64xxx is present on the CPU bus, return | |
600 | the initial value */ | |
601 | val = s->regs[saddr]; | |
602 | break; | |
603 | ||
fde7d5bd TS |
604 | /* CPU Error Report */ |
605 | case GT_CPUERR_ADDRLO: | |
606 | case GT_CPUERR_ADDRHI: | |
607 | case GT_CPUERR_DATALO: | |
608 | case GT_CPUERR_DATAHI: | |
609 | case GT_CPUERR_PARITY: | |
0da75eb1 TS |
610 | /* Emulated memory has no error, always return the initial |
611 | values */ | |
612 | val = s->regs[saddr]; | |
613 | break; | |
614 | ||
615 | /* CPU Sync Barrier */ | |
616 | case GT_PCI0SYNC: | |
617 | case GT_PCI1SYNC: | |
618 | /* Reading those register should empty all FIFO on the PCI | |
619 | bus, which are not emulated. The return value should be | |
620 | a random value that should be ignored. */ | |
621 | val = 0xc000ffee; | |
fde7d5bd TS |
622 | break; |
623 | ||
624 | /* ECC */ | |
625 | case GT_ECC_ERRDATALO: | |
626 | case GT_ECC_ERRDATAHI: | |
627 | case GT_ECC_MEM: | |
628 | case GT_ECC_CALC: | |
629 | case GT_ECC_ERRADDR: | |
0da75eb1 TS |
630 | /* Emulated memory has no error, always return the initial |
631 | values */ | |
632 | val = s->regs[saddr]; | |
fde7d5bd TS |
633 | break; |
634 | ||
635 | case GT_CPU: | |
05b4ff43 TS |
636 | case GT_SCS10LD: |
637 | case GT_SCS10HD: | |
638 | case GT_SCS32LD: | |
639 | case GT_SCS32HD: | |
640 | case GT_CS20LD: | |
641 | case GT_CS20HD: | |
642 | case GT_CS3BOOTLD: | |
643 | case GT_CS3BOOTHD: | |
644 | case GT_SCS10AR: | |
645 | case GT_SCS32AR: | |
646 | case GT_CS20R: | |
647 | case GT_CS3BOOTR: | |
fde7d5bd TS |
648 | case GT_PCI0IOLD: |
649 | case GT_PCI0M0LD: | |
650 | case GT_PCI0M1LD: | |
651 | case GT_PCI1IOLD: | |
652 | case GT_PCI1M0LD: | |
653 | case GT_PCI1M1LD: | |
654 | case GT_PCI0IOHD: | |
655 | case GT_PCI0M0HD: | |
656 | case GT_PCI0M1HD: | |
657 | case GT_PCI1IOHD: | |
658 | case GT_PCI1M0HD: | |
659 | case GT_PCI1M1HD: | |
fde7d5bd TS |
660 | case GT_PCI0IOREMAP: |
661 | case GT_PCI0M0REMAP: | |
662 | case GT_PCI0M1REMAP: | |
663 | case GT_PCI1IOREMAP: | |
664 | case GT_PCI1M0REMAP: | |
665 | case GT_PCI1M1REMAP: | |
05b4ff43 | 666 | case GT_ISD: |
fde7d5bd TS |
667 | val = s->regs[saddr]; |
668 | break; | |
669 | case GT_PCI0_IACK: | |
4de9b249 TS |
670 | /* Read the IRQ number */ |
671 | val = pic_read_irq(isa_pic); | |
fde7d5bd TS |
672 | break; |
673 | ||
05b4ff43 TS |
674 | /* SDRAM and Device Address Decode */ |
675 | case GT_SCS0LD: | |
676 | case GT_SCS0HD: | |
677 | case GT_SCS1LD: | |
678 | case GT_SCS1HD: | |
679 | case GT_SCS2LD: | |
680 | case GT_SCS2HD: | |
681 | case GT_SCS3LD: | |
682 | case GT_SCS3HD: | |
683 | case GT_CS0LD: | |
684 | case GT_CS0HD: | |
685 | case GT_CS1LD: | |
686 | case GT_CS1HD: | |
687 | case GT_CS2LD: | |
688 | case GT_CS2HD: | |
689 | case GT_CS3LD: | |
690 | case GT_CS3HD: | |
691 | case GT_BOOTLD: | |
692 | case GT_BOOTHD: | |
693 | case GT_ADERR: | |
694 | val = s->regs[saddr]; | |
695 | break; | |
696 | ||
697 | /* SDRAM Configuration */ | |
698 | case GT_SDRAM_CFG: | |
699 | case GT_SDRAM_OPMODE: | |
700 | case GT_SDRAM_BM: | |
701 | case GT_SDRAM_ADDRDECODE: | |
702 | val = s->regs[saddr]; | |
703 | break; | |
704 | ||
0da75eb1 TS |
705 | /* SDRAM Parameters */ |
706 | case GT_SDRAM_B0: | |
707 | case GT_SDRAM_B1: | |
708 | case GT_SDRAM_B2: | |
709 | case GT_SDRAM_B3: | |
710 | /* We don't simulate electrical parameters of the SDRAM. | |
711 | Just return the last written value. */ | |
712 | val = s->regs[saddr]; | |
713 | break; | |
714 | ||
05b4ff43 TS |
715 | /* Device Parameters */ |
716 | case GT_DEV_B0: | |
717 | case GT_DEV_B1: | |
718 | case GT_DEV_B2: | |
719 | case GT_DEV_B3: | |
720 | case GT_DEV_BOOT: | |
721 | val = s->regs[saddr]; | |
722 | break; | |
723 | ||
724 | /* DMA Record */ | |
725 | case GT_DMA0_CNT: | |
726 | case GT_DMA1_CNT: | |
727 | case GT_DMA2_CNT: | |
728 | case GT_DMA3_CNT: | |
729 | case GT_DMA0_SA: | |
730 | case GT_DMA1_SA: | |
731 | case GT_DMA2_SA: | |
732 | case GT_DMA3_SA: | |
733 | case GT_DMA0_DA: | |
734 | case GT_DMA1_DA: | |
735 | case GT_DMA2_DA: | |
736 | case GT_DMA3_DA: | |
737 | case GT_DMA0_NEXT: | |
738 | case GT_DMA1_NEXT: | |
739 | case GT_DMA2_NEXT: | |
740 | case GT_DMA3_NEXT: | |
741 | case GT_DMA0_CUR: | |
742 | case GT_DMA1_CUR: | |
743 | case GT_DMA2_CUR: | |
744 | case GT_DMA3_CUR: | |
745 | val = s->regs[saddr]; | |
746 | break; | |
747 | ||
748 | /* DMA Channel Control */ | |
749 | case GT_DMA0_CTRL: | |
750 | case GT_DMA1_CTRL: | |
751 | case GT_DMA2_CTRL: | |
752 | case GT_DMA3_CTRL: | |
753 | val = s->regs[saddr]; | |
754 | break; | |
755 | ||
756 | /* DMA Arbiter */ | |
757 | case GT_DMA_ARB: | |
758 | val = s->regs[saddr]; | |
759 | break; | |
760 | ||
761 | /* Timer/Counter */ | |
762 | case GT_TC0: | |
763 | case GT_TC1: | |
764 | case GT_TC2: | |
765 | case GT_TC3: | |
766 | case GT_TC_CONTROL: | |
767 | val = s->regs[saddr]; | |
768 | break; | |
769 | ||
fde7d5bd TS |
770 | /* PCI Internal */ |
771 | case GT_PCI0_CFGADDR: | |
772 | val = s->pci->config_reg; | |
773 | break; | |
774 | case GT_PCI0_CFGDATA: | |
05b4ff43 TS |
775 | if (!(s->pci->config_reg & (1u << 31))) |
776 | val = 0xffffffff; | |
777 | else | |
f00cb701 | 778 | val = pci_host_data_readl(s->pci, 0); |
05b4ff43 TS |
779 | break; |
780 | ||
781 | case GT_PCI0_CMD: | |
782 | case GT_PCI0_TOR: | |
783 | case GT_PCI0_BS_SCS10: | |
784 | case GT_PCI0_BS_SCS32: | |
785 | case GT_PCI0_BS_CS20: | |
786 | case GT_PCI0_BS_CS3BT: | |
787 | case GT_PCI1_IACK: | |
788 | case GT_PCI0_BARE: | |
789 | case GT_PCI0_PREFMBR: | |
790 | case GT_PCI0_SCS10_BAR: | |
791 | case GT_PCI0_SCS32_BAR: | |
792 | case GT_PCI0_CS20_BAR: | |
793 | case GT_PCI0_CS3BT_BAR: | |
794 | case GT_PCI0_SSCS10_BAR: | |
795 | case GT_PCI0_SSCS32_BAR: | |
796 | case GT_PCI0_SCS3BT_BAR: | |
797 | case GT_PCI1_CMD: | |
798 | case GT_PCI1_TOR: | |
799 | case GT_PCI1_BS_SCS10: | |
800 | case GT_PCI1_BS_SCS32: | |
801 | case GT_PCI1_BS_CS20: | |
802 | case GT_PCI1_BS_CS3BT: | |
803 | case GT_PCI1_BARE: | |
804 | case GT_PCI1_PREFMBR: | |
805 | case GT_PCI1_SCS10_BAR: | |
806 | case GT_PCI1_SCS32_BAR: | |
807 | case GT_PCI1_CS20_BAR: | |
808 | case GT_PCI1_CS3BT_BAR: | |
809 | case GT_PCI1_SSCS10_BAR: | |
810 | case GT_PCI1_SSCS32_BAR: | |
811 | case GT_PCI1_SCS3BT_BAR: | |
812 | case GT_PCI1_CFGADDR: | |
813 | case GT_PCI1_CFGDATA: | |
814 | val = s->regs[saddr]; | |
815 | break; | |
816 | ||
817 | /* Interrupts */ | |
818 | case GT_INTRCAUSE: | |
819 | val = s->regs[saddr]; | |
820 | dprintf("INTRCAUSE %x\n", val); | |
821 | break; | |
822 | case GT_INTRMASK: | |
823 | val = s->regs[saddr]; | |
824 | dprintf("INTRMASK %x\n", val); | |
825 | break; | |
826 | case GT_PCI0_ICMASK: | |
827 | val = s->regs[saddr]; | |
828 | dprintf("ICMASK %x\n", val); | |
829 | break; | |
830 | case GT_PCI0_SERR0MASK: | |
831 | val = s->regs[saddr]; | |
832 | dprintf("SERR0MASK %x\n", val); | |
833 | break; | |
834 | ||
835 | /* Reserved when only PCI_0 is configured. */ | |
836 | case GT_HINTRCAUSE: | |
837 | case GT_CPU_INTSEL: | |
838 | case GT_PCI0_INTSEL: | |
839 | case GT_HINTRMASK: | |
840 | case GT_PCI0_HICMASK: | |
841 | case GT_PCI1_SERR1MASK: | |
842 | val = s->regs[saddr]; | |
fde7d5bd TS |
843 | break; |
844 | ||
845 | default: | |
846 | val = s->regs[saddr]; | |
05b4ff43 | 847 | dprintf ("Bad register offset 0x%x\n", (int)addr); |
fde7d5bd TS |
848 | break; |
849 | } | |
850 | ||
0da75eb1 | 851 | #ifdef TARGET_WORDS_BIGENDIAN |
05b4ff43 | 852 | val = bswap32(val); |
0da75eb1 | 853 | #endif |
05b4ff43 | 854 | return val; |
fde7d5bd TS |
855 | } |
856 | ||
857 | static CPUWriteMemoryFunc *gt64120_write[] = { | |
858 | >64120_writel, | |
859 | >64120_writel, | |
860 | >64120_writel, | |
861 | }; | |
862 | ||
863 | static CPUReadMemoryFunc *gt64120_read[] = { | |
864 | >64120_readl, | |
865 | >64120_readl, | |
866 | >64120_readl, | |
867 | }; | |
868 | ||
869 | static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num) | |
870 | { | |
871 | int slot; | |
872 | ||
873 | slot = (pci_dev->devfn >> 3); | |
874 | ||
875 | switch (slot) { | |
876 | /* PIIX4 USB */ | |
877 | case 10: | |
878 | return 3; | |
879 | /* AMD 79C973 Ethernet */ | |
880 | case 11: | |
d4a4d056 | 881 | return 1; |
fde7d5bd TS |
882 | /* Crystal 4281 Sound */ |
883 | case 12: | |
d4a4d056 | 884 | return 2; |
fde7d5bd TS |
885 | /* PCI slot 1 to 4 */ |
886 | case 18 ... 21: | |
887 | return ((slot - 18) + irq_num) & 0x03; | |
888 | /* Unknown device, don't do any translation */ | |
889 | default: | |
890 | return irq_num; | |
891 | } | |
892 | } | |
893 | ||
894 | extern PCIDevice *piix4_dev; | |
895 | static int pci_irq_levels[4]; | |
896 | ||
d537cf6c | 897 | static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level) |
fde7d5bd TS |
898 | { |
899 | int i, pic_irq, pic_level; | |
900 | ||
901 | pci_irq_levels[irq_num] = level; | |
902 | ||
903 | /* now we change the pic irq level according to the piix irq mappings */ | |
904 | /* XXX: optimize */ | |
905 | pic_irq = piix4_dev->config[0x60 + irq_num]; | |
906 | if (pic_irq < 16) { | |
907 | /* The pic level is the logical OR of all the PCI irqs mapped | |
908 | to it */ | |
909 | pic_level = 0; | |
910 | for (i = 0; i < 4; i++) { | |
911 | if (pic_irq == piix4_dev->config[0x60 + i]) | |
912 | pic_level |= pci_irq_levels[i]; | |
913 | } | |
d537cf6c | 914 | qemu_set_irq(pic[pic_irq], pic_level); |
fde7d5bd TS |
915 | } |
916 | } | |
917 | ||
918 | ||
919 | void gt64120_reset(void *opaque) | |
920 | { | |
921 | GT64120State *s = opaque; | |
922 | ||
30b6f3a8 TS |
923 | /* FIXME: Malta specific hw assumptions ahead */ |
924 | ||
fde7d5bd TS |
925 | /* CPU Configuration */ |
926 | #ifdef TARGET_WORDS_BIGENDIAN | |
927 | s->regs[GT_CPU] = 0x00000000; | |
928 | #else | |
bc687ec9 | 929 | s->regs[GT_CPU] = 0x00001000; |
fde7d5bd | 930 | #endif |
30b6f3a8 TS |
931 | s->regs[GT_MULTI] = 0x00000003; |
932 | ||
933 | /* CPU Address decode */ | |
934 | s->regs[GT_SCS10LD] = 0x00000000; | |
935 | s->regs[GT_SCS10HD] = 0x00000007; | |
936 | s->regs[GT_SCS32LD] = 0x00000008; | |
937 | s->regs[GT_SCS32HD] = 0x0000000f; | |
938 | s->regs[GT_CS20LD] = 0x000000e0; | |
939 | s->regs[GT_CS20HD] = 0x00000070; | |
940 | s->regs[GT_CS3BOOTLD] = 0x000000f8; | |
941 | s->regs[GT_CS3BOOTHD] = 0x0000007f; | |
fde7d5bd | 942 | |
fde7d5bd TS |
943 | s->regs[GT_PCI0IOLD] = 0x00000080; |
944 | s->regs[GT_PCI0IOHD] = 0x0000000f; | |
945 | s->regs[GT_PCI0M0LD] = 0x00000090; | |
946 | s->regs[GT_PCI0M0HD] = 0x0000001f; | |
30b6f3a8 | 947 | s->regs[GT_ISD] = 0x000000a0; |
fde7d5bd TS |
948 | s->regs[GT_PCI0M1LD] = 0x00000790; |
949 | s->regs[GT_PCI0M1HD] = 0x0000001f; | |
950 | s->regs[GT_PCI1IOLD] = 0x00000100; | |
951 | s->regs[GT_PCI1IOHD] = 0x0000000f; | |
952 | s->regs[GT_PCI1M0LD] = 0x00000110; | |
953 | s->regs[GT_PCI1M0HD] = 0x0000001f; | |
954 | s->regs[GT_PCI1M1LD] = 0x00000120; | |
955 | s->regs[GT_PCI1M1HD] = 0x0000002f; | |
30b6f3a8 TS |
956 | |
957 | s->regs[GT_SCS10AR] = 0x00000000; | |
958 | s->regs[GT_SCS32AR] = 0x00000008; | |
959 | s->regs[GT_CS20R] = 0x000000e0; | |
960 | s->regs[GT_CS3BOOTR] = 0x000000f8; | |
961 | ||
fde7d5bd TS |
962 | s->regs[GT_PCI0IOREMAP] = 0x00000080; |
963 | s->regs[GT_PCI0M0REMAP] = 0x00000090; | |
964 | s->regs[GT_PCI0M1REMAP] = 0x00000790; | |
965 | s->regs[GT_PCI1IOREMAP] = 0x00000100; | |
966 | s->regs[GT_PCI1M0REMAP] = 0x00000110; | |
967 | s->regs[GT_PCI1M1REMAP] = 0x00000120; | |
968 | ||
969 | /* CPU Error Report */ | |
970 | s->regs[GT_CPUERR_ADDRLO] = 0x00000000; | |
971 | s->regs[GT_CPUERR_ADDRHI] = 0x00000000; | |
972 | s->regs[GT_CPUERR_DATALO] = 0xffffffff; | |
973 | s->regs[GT_CPUERR_DATAHI] = 0xffffffff; | |
974 | s->regs[GT_CPUERR_PARITY] = 0x000000ff; | |
975 | ||
30b6f3a8 TS |
976 | /* CPU Sync Barrier */ |
977 | s->regs[GT_PCI0SYNC] = 0x00000000; | |
978 | s->regs[GT_PCI1SYNC] = 0x00000000; | |
979 | ||
980 | /* SDRAM and Device Address Decode */ | |
981 | s->regs[GT_SCS0LD] = 0x00000000; | |
982 | s->regs[GT_SCS0HD] = 0x00000007; | |
983 | s->regs[GT_SCS1LD] = 0x00000008; | |
984 | s->regs[GT_SCS1HD] = 0x0000000f; | |
985 | s->regs[GT_SCS2LD] = 0x00000010; | |
986 | s->regs[GT_SCS2HD] = 0x00000017; | |
987 | s->regs[GT_SCS3LD] = 0x00000018; | |
988 | s->regs[GT_SCS3HD] = 0x0000001f; | |
989 | s->regs[GT_CS0LD] = 0x000000c0; | |
990 | s->regs[GT_CS0HD] = 0x000000c7; | |
991 | s->regs[GT_CS1LD] = 0x000000c8; | |
992 | s->regs[GT_CS1HD] = 0x000000cf; | |
993 | s->regs[GT_CS2LD] = 0x000000d0; | |
994 | s->regs[GT_CS2HD] = 0x000000df; | |
995 | s->regs[GT_CS3LD] = 0x000000f0; | |
996 | s->regs[GT_CS3HD] = 0x000000fb; | |
997 | s->regs[GT_BOOTLD] = 0x000000fc; | |
998 | s->regs[GT_BOOTHD] = 0x000000ff; | |
999 | s->regs[GT_ADERR] = 0xffffffff; | |
1000 | ||
1001 | /* SDRAM Configuration */ | |
1002 | s->regs[GT_SDRAM_CFG] = 0x00000200; | |
1003 | s->regs[GT_SDRAM_OPMODE] = 0x00000000; | |
1004 | s->regs[GT_SDRAM_BM] = 0x00000007; | |
1005 | s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002; | |
1006 | ||
1007 | /* SDRAM Parameters */ | |
1008 | s->regs[GT_SDRAM_B0] = 0x00000005; | |
1009 | s->regs[GT_SDRAM_B1] = 0x00000005; | |
1010 | s->regs[GT_SDRAM_B2] = 0x00000005; | |
1011 | s->regs[GT_SDRAM_B3] = 0x00000005; | |
1012 | ||
fde7d5bd TS |
1013 | /* ECC */ |
1014 | s->regs[GT_ECC_ERRDATALO] = 0x00000000; | |
1015 | s->regs[GT_ECC_ERRDATAHI] = 0x00000000; | |
1016 | s->regs[GT_ECC_MEM] = 0x00000000; | |
1017 | s->regs[GT_ECC_CALC] = 0x00000000; | |
1018 | s->regs[GT_ECC_ERRADDR] = 0x00000000; | |
1019 | ||
30b6f3a8 TS |
1020 | /* Device Parameters */ |
1021 | s->regs[GT_DEV_B0] = 0x386fffff; | |
1022 | s->regs[GT_DEV_B1] = 0x386fffff; | |
1023 | s->regs[GT_DEV_B2] = 0x386fffff; | |
1024 | s->regs[GT_DEV_B3] = 0x386fffff; | |
1025 | s->regs[GT_DEV_BOOT] = 0x146fffff; | |
0da75eb1 | 1026 | |
30b6f3a8 TS |
1027 | /* DMA registers are all zeroed at reset */ |
1028 | ||
1029 | /* Timer/Counter */ | |
1030 | s->regs[GT_TC0] = 0xffffffff; | |
1031 | s->regs[GT_TC1] = 0x00ffffff; | |
1032 | s->regs[GT_TC2] = 0x00ffffff; | |
1033 | s->regs[GT_TC3] = 0x00ffffff; | |
1034 | s->regs[GT_TC_CONTROL] = 0x00000000; | |
1035 | ||
1036 | /* PCI Internal */ | |
fde7d5bd TS |
1037 | #ifdef TARGET_WORDS_BIGENDIAN |
1038 | s->regs[GT_PCI0_CMD] = 0x00000000; | |
fde7d5bd TS |
1039 | #else |
1040 | s->regs[GT_PCI0_CMD] = 0x00010001; | |
fde7d5bd | 1041 | #endif |
30b6f3a8 TS |
1042 | s->regs[GT_PCI0_TOR] = 0x0000070f; |
1043 | s->regs[GT_PCI0_BS_SCS10] = 0x00fff000; | |
1044 | s->regs[GT_PCI0_BS_SCS32] = 0x00fff000; | |
1045 | s->regs[GT_PCI0_BS_CS20] = 0x01fff000; | |
1046 | s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000; | |
fde7d5bd | 1047 | s->regs[GT_PCI1_IACK] = 0x00000000; |
30b6f3a8 TS |
1048 | s->regs[GT_PCI0_IACK] = 0x00000000; |
1049 | s->regs[GT_PCI0_BARE] = 0x0000000f; | |
1050 | s->regs[GT_PCI0_PREFMBR] = 0x00000040; | |
1051 | s->regs[GT_PCI0_SCS10_BAR] = 0x00000000; | |
1052 | s->regs[GT_PCI0_SCS32_BAR] = 0x01000000; | |
1053 | s->regs[GT_PCI0_CS20_BAR] = 0x1c000000; | |
1054 | s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000; | |
1055 | s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000; | |
1056 | s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000; | |
1057 | s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000; | |
1058 | #ifdef TARGET_WORDS_BIGENDIAN | |
1059 | s->regs[GT_PCI1_CMD] = 0x00000000; | |
1060 | #else | |
1061 | s->regs[GT_PCI1_CMD] = 0x00010001; | |
1062 | #endif | |
1063 | s->regs[GT_PCI1_TOR] = 0x0000070f; | |
1064 | s->regs[GT_PCI1_BS_SCS10] = 0x00fff000; | |
1065 | s->regs[GT_PCI1_BS_SCS32] = 0x00fff000; | |
1066 | s->regs[GT_PCI1_BS_CS20] = 0x01fff000; | |
1067 | s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000; | |
1068 | s->regs[GT_PCI1_BARE] = 0x0000000f; | |
1069 | s->regs[GT_PCI1_PREFMBR] = 0x00000040; | |
1070 | s->regs[GT_PCI1_SCS10_BAR] = 0x00000000; | |
1071 | s->regs[GT_PCI1_SCS32_BAR] = 0x01000000; | |
1072 | s->regs[GT_PCI1_CS20_BAR] = 0x1c000000; | |
1073 | s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000; | |
1074 | s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000; | |
1075 | s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000; | |
1076 | s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000; | |
1077 | s->regs[GT_PCI1_CFGADDR] = 0x00000000; | |
1078 | s->regs[GT_PCI1_CFGDATA] = 0x00000000; | |
1079 | s->regs[GT_PCI0_CFGADDR] = 0x00000000; | |
1080 | s->regs[GT_PCI0_CFGDATA] = 0x00000000; | |
1081 | ||
1082 | /* Interrupt registers are all zeroed at reset */ | |
fde7d5bd | 1083 | |
a0a8793e | 1084 | gt64120_isd_mapping(s); |
9414cc6f | 1085 | gt64120_pci_mapping(s); |
fde7d5bd TS |
1086 | } |
1087 | ||
bc687ec9 TS |
1088 | static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len) |
1089 | { | |
1090 | uint32_t val = pci_default_read_config(d, address, len); | |
1091 | #ifdef TARGET_WORDS_BIGENDIAN | |
1092 | val = bswap32(val); | |
1093 | #endif | |
1094 | return val; | |
1095 | } | |
1096 | ||
1097 | static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val, | |
1098 | int len) | |
1099 | { | |
1100 | #ifdef TARGET_WORDS_BIGENDIAN | |
1101 | val = bswap32(val); | |
1102 | #endif | |
1103 | pci_default_write_config(d, address, val, len); | |
1104 | } | |
1105 | ||
1823082c TS |
1106 | static void gt64120_save(QEMUFile* f, void *opaque) |
1107 | { | |
1108 | PCIDevice *d = opaque; | |
1109 | pci_device_save(d, f); | |
1110 | } | |
1111 | ||
1112 | static int gt64120_load(QEMUFile* f, void *opaque, int version_id) | |
1113 | { | |
1114 | PCIDevice *d = opaque; | |
1115 | int ret; | |
1116 | ||
1117 | if (version_id != 1) | |
1118 | return -EINVAL; | |
1119 | ret = pci_device_load(d, f); | |
1120 | if (ret < 0) | |
1121 | return ret; | |
1122 | return 0; | |
1123 | } | |
1124 | ||
d537cf6c | 1125 | PCIBus *pci_gt64120_init(qemu_irq *pic) |
fde7d5bd TS |
1126 | { |
1127 | GT64120State *s; | |
1128 | PCIDevice *d; | |
fde7d5bd TS |
1129 | |
1130 | s = qemu_mallocz(sizeof(GT64120State)); | |
1131 | s->pci = qemu_mallocz(sizeof(GT64120PCIState)); | |
9414cc6f | 1132 | |
fde7d5bd TS |
1133 | s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq, |
1134 | pic, 144, 4); | |
a0a8793e | 1135 | s->ISD_handle = cpu_register_io_memory(0, gt64120_read, gt64120_write, s); |
fde7d5bd | 1136 | d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice), |
bc687ec9 | 1137 | 0, gt64120_read_config, gt64120_write_config); |
fde7d5bd | 1138 | |
0f78cf0c TS |
1139 | /* FIXME: Malta specific hw assumptions ahead */ |
1140 | ||
a0a8793e | 1141 | d->config[0x00] = 0xab; /* vendor_id */ |
fde7d5bd | 1142 | d->config[0x01] = 0x11; |
a0a8793e | 1143 | d->config[0x02] = 0x20; /* device_id */ |
bc687ec9 | 1144 | d->config[0x03] = 0x46; |
0f78cf0c TS |
1145 | |
1146 | d->config[0x04] = 0x00; | |
fde7d5bd TS |
1147 | d->config[0x05] = 0x00; |
1148 | d->config[0x06] = 0x80; | |
0f78cf0c TS |
1149 | d->config[0x07] = 0x02; |
1150 | ||
fde7d5bd TS |
1151 | d->config[0x08] = 0x10; |
1152 | d->config[0x09] = 0x00; | |
0f78cf0c TS |
1153 | d->config[0x0A] = 0x00; |
1154 | d->config[0x0B] = 0x06; | |
1155 | ||
1156 | d->config[0x10] = 0x08; | |
1157 | d->config[0x14] = 0x08; | |
1158 | d->config[0x17] = 0x01; | |
fde7d5bd TS |
1159 | d->config[0x1B] = 0x1c; |
1160 | d->config[0x1F] = 0x1f; | |
1161 | d->config[0x23] = 0x14; | |
0f78cf0c | 1162 | d->config[0x24] = 0x01; |
fde7d5bd TS |
1163 | d->config[0x27] = 0x14; |
1164 | d->config[0x3D] = 0x01; | |
1165 | ||
a0a8793e TS |
1166 | gt64120_reset(s); |
1167 | ||
1823082c TS |
1168 | register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save, gt64120_load, d); |
1169 | ||
fde7d5bd TS |
1170 | return s->pci->bus; |
1171 | } |