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a72bd606 HD |
1 | /* |
2 | * HP-PARISC Dino PCI chipset emulation. | |
3 | * | |
4 | * (C) 2017 by Helge Deller <deller@gmx.de> | |
5 | * | |
6 | * This work is licensed under the GNU GPL license version 2 or later. | |
7 | * | |
8 | * Documentation available at: | |
9 | * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf | |
10 | * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
14 | #include "qapi/error.h" | |
15 | #include "cpu.h" | |
16 | #include "hw/hw.h" | |
17 | #include "hw/devices.h" | |
18 | #include "sysemu/sysemu.h" | |
19 | #include "hw/pci/pci.h" | |
20 | #include "hw/pci/pci_bus.h" | |
21 | #include "hppa_sys.h" | |
22 | #include "exec/address-spaces.h" | |
23 | ||
24 | ||
25 | #define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost" | |
26 | ||
27 | #define DINO_IAR0 0x004 | |
28 | #define DINO_IODC 0x008 | |
29 | #define DINO_IRR0 0x00C /* RO */ | |
30 | #define DINO_IAR1 0x010 | |
31 | #define DINO_IRR1 0x014 /* RO */ | |
32 | #define DINO_IMR 0x018 | |
33 | #define DINO_IPR 0x01C | |
34 | #define DINO_TOC_ADDR 0x020 | |
35 | #define DINO_ICR 0x024 | |
36 | #define DINO_ILR 0x028 /* RO */ | |
37 | #define DINO_IO_COMMAND 0x030 /* WO */ | |
38 | #define DINO_IO_STATUS 0x034 /* RO */ | |
39 | #define DINO_IO_CONTROL 0x038 | |
40 | #define DINO_IO_GSC_ERR_RESP 0x040 /* RO */ | |
41 | #define DINO_IO_ERR_INFO 0x044 /* RO */ | |
42 | #define DINO_IO_PCI_ERR_RESP 0x048 /* RO */ | |
43 | #define DINO_IO_FBB_EN 0x05c | |
44 | #define DINO_IO_ADDR_EN 0x060 | |
45 | #define DINO_PCI_CONFIG_ADDR 0x064 | |
46 | #define DINO_PCI_CONFIG_DATA 0x068 | |
47 | #define DINO_PCI_IO_DATA 0x06c | |
48 | #define DINO_PCI_MEM_DATA 0x070 /* Dino 3.x only */ | |
49 | #define DINO_GSC2X_CONFIG 0x7b4 /* RO */ | |
50 | #define DINO_GMASK 0x800 | |
51 | #define DINO_PAMR 0x804 | |
52 | #define DINO_PAPR 0x808 | |
53 | #define DINO_DAMODE 0x80c | |
54 | #define DINO_PCICMD 0x810 | |
55 | #define DINO_PCISTS 0x814 /* R/WC */ | |
56 | #define DINO_MLTIM 0x81c | |
57 | #define DINO_BRDG_FEAT 0x820 | |
58 | #define DINO_PCIROR 0x824 | |
59 | #define DINO_PCIWOR 0x828 | |
60 | #define DINO_TLTIM 0x830 | |
61 | ||
62 | #define DINO_IRQS 11 /* bits 0-10 are architected */ | |
63 | #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ | |
64 | #define DINO_LOCAL_IRQS (DINO_IRQS + 1) | |
65 | #define DINO_MASK_IRQ(x) (1 << (x)) | |
66 | ||
67 | #define PCIINTA 0x001 | |
68 | #define PCIINTB 0x002 | |
69 | #define PCIINTC 0x004 | |
70 | #define PCIINTD 0x008 | |
71 | #define PCIINTE 0x010 | |
72 | #define PCIINTF 0x020 | |
73 | #define GSCEXTINT 0x040 | |
74 | /* #define xxx 0x080 - bit 7 is "default" */ | |
75 | /* #define xxx 0x100 - bit 8 not used */ | |
76 | /* #define xxx 0x200 - bit 9 not used */ | |
77 | #define RS232INT 0x400 | |
78 | ||
79 | #define DINO_MEM_CHUNK_SIZE (8 * 1024 * 1024) /* 8MB */ | |
80 | ||
81 | #define DINO_PCI_HOST_BRIDGE(obj) \ | |
82 | OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE) | |
83 | ||
84 | typedef struct DinoState { | |
85 | PCIHostState parent_obj; | |
86 | ||
87 | /* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops, | |
88 | so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. */ | |
89 | ||
90 | uint32_t iar0; | |
91 | uint32_t iar1; | |
92 | uint32_t imr; | |
93 | uint32_t ipr; | |
94 | uint32_t icr; | |
95 | uint32_t ilr; | |
96 | uint32_t io_addr_en; | |
97 | uint32_t io_control; | |
98 | ||
99 | MemoryRegion this_mem; | |
100 | MemoryRegion pci_mem; | |
101 | MemoryRegion pci_mem_alias[32]; | |
102 | ||
103 | AddressSpace bm_as; | |
104 | MemoryRegion bm; | |
105 | MemoryRegion bm_ram_alias; | |
106 | MemoryRegion bm_pci_alias; | |
107 | ||
108 | MemoryRegion cpu0_eir_mem; | |
109 | } DinoState; | |
110 | ||
111 | /* | |
112 | * Dino can forward memory accesses from the CPU in the range between | |
113 | * 0xf0800000 and 0xff000000 to the PCI bus. | |
114 | */ | |
115 | static void gsc_to_pci_forwarding(DinoState *s) | |
116 | { | |
117 | uint32_t io_addr_en, tmp; | |
118 | int enabled, i; | |
119 | ||
120 | tmp = extract32(s->io_control, 7, 2); | |
121 | enabled = (tmp == 0x01); | |
122 | io_addr_en = s->io_addr_en; | |
123 | ||
124 | memory_region_transaction_begin(); | |
125 | for (i = 1; i < 31; i++) { | |
126 | MemoryRegion *mem = &s->pci_mem_alias[i]; | |
127 | if (enabled && (io_addr_en & (1U << i))) { | |
128 | if (!memory_region_is_mapped(mem)) { | |
129 | uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE; | |
130 | memory_region_add_subregion(get_system_memory(), addr, mem); | |
131 | } | |
132 | } else if (memory_region_is_mapped(mem)) { | |
133 | memory_region_del_subregion(get_system_memory(), mem); | |
134 | } | |
135 | } | |
136 | memory_region_transaction_commit(); | |
137 | } | |
138 | ||
139 | static bool dino_chip_mem_valid(void *opaque, hwaddr addr, | |
8372d383 PM |
140 | unsigned size, bool is_write, |
141 | MemTxAttrs attrs) | |
a72bd606 HD |
142 | { |
143 | switch (addr) { | |
144 | case DINO_IAR0: | |
145 | case DINO_IAR1: | |
146 | case DINO_IRR0: | |
147 | case DINO_IRR1: | |
148 | case DINO_IMR: | |
149 | case DINO_IPR: | |
150 | case DINO_ICR: | |
151 | case DINO_ILR: | |
152 | case DINO_IO_CONTROL: | |
153 | case DINO_IO_ADDR_EN: | |
154 | case DINO_PCI_IO_DATA: | |
155 | return true; | |
156 | case DINO_PCI_IO_DATA + 2: | |
157 | return size <= 2; | |
158 | case DINO_PCI_IO_DATA + 1: | |
159 | case DINO_PCI_IO_DATA + 3: | |
160 | return size == 1; | |
161 | } | |
162 | return false; | |
163 | } | |
164 | ||
165 | static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr, | |
166 | uint64_t *data, unsigned size, | |
167 | MemTxAttrs attrs) | |
168 | { | |
169 | DinoState *s = opaque; | |
170 | MemTxResult ret = MEMTX_OK; | |
171 | AddressSpace *io; | |
172 | uint16_t ioaddr; | |
173 | uint32_t val; | |
174 | ||
175 | switch (addr) { | |
176 | case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3: | |
177 | /* Read from PCI IO space. */ | |
178 | io = &address_space_io; | |
179 | ioaddr = s->parent_obj.config_reg; | |
180 | switch (size) { | |
181 | case 1: | |
182 | val = address_space_ldub(io, ioaddr, attrs, &ret); | |
183 | break; | |
184 | case 2: | |
185 | val = address_space_lduw_be(io, ioaddr, attrs, &ret); | |
186 | break; | |
187 | case 4: | |
188 | val = address_space_ldl_be(io, ioaddr, attrs, &ret); | |
189 | break; | |
190 | default: | |
191 | g_assert_not_reached(); | |
192 | } | |
193 | break; | |
194 | ||
195 | case DINO_IO_ADDR_EN: | |
196 | val = s->io_addr_en; | |
197 | break; | |
198 | case DINO_IO_CONTROL: | |
199 | val = s->io_control; | |
200 | break; | |
201 | ||
202 | case DINO_IAR0: | |
203 | val = s->iar0; | |
204 | break; | |
205 | case DINO_IAR1: | |
206 | val = s->iar1; | |
207 | break; | |
208 | case DINO_IMR: | |
209 | val = s->imr; | |
210 | break; | |
211 | case DINO_ICR: | |
212 | val = s->icr; | |
213 | break; | |
214 | case DINO_IPR: | |
215 | val = s->ipr; | |
216 | /* Any read to IPR clears the register. */ | |
217 | s->ipr = 0; | |
218 | break; | |
219 | case DINO_ILR: | |
220 | val = s->ilr; | |
221 | break; | |
222 | case DINO_IRR0: | |
223 | val = s->ilr & s->imr & ~s->icr; | |
224 | break; | |
225 | case DINO_IRR1: | |
226 | val = s->ilr & s->imr & s->icr; | |
227 | break; | |
228 | ||
229 | default: | |
230 | /* Controlled by dino_chip_mem_valid above. */ | |
231 | g_assert_not_reached(); | |
232 | } | |
233 | ||
234 | *data = val; | |
235 | return ret; | |
236 | } | |
237 | ||
238 | static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr, | |
239 | uint64_t val, unsigned size, | |
240 | MemTxAttrs attrs) | |
241 | { | |
242 | DinoState *s = opaque; | |
243 | AddressSpace *io; | |
244 | MemTxResult ret; | |
245 | uint16_t ioaddr; | |
246 | ||
247 | switch (addr) { | |
248 | case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3: | |
249 | /* Write into PCI IO space. */ | |
250 | io = &address_space_io; | |
251 | ioaddr = s->parent_obj.config_reg; | |
252 | switch (size) { | |
253 | case 1: | |
254 | address_space_stb(io, ioaddr, val, attrs, &ret); | |
255 | break; | |
256 | case 2: | |
257 | address_space_stw_be(io, ioaddr, val, attrs, &ret); | |
258 | break; | |
259 | case 4: | |
260 | address_space_stl_be(io, ioaddr, val, attrs, &ret); | |
261 | break; | |
262 | default: | |
263 | g_assert_not_reached(); | |
264 | } | |
265 | return ret; | |
266 | ||
267 | case DINO_IO_ADDR_EN: | |
268 | /* Never allow first (=firmware) and last (=Dino) areas. */ | |
269 | s->io_addr_en = val & 0x7ffffffe; | |
270 | gsc_to_pci_forwarding(s); | |
271 | break; | |
272 | case DINO_IO_CONTROL: | |
273 | s->io_control = val; | |
274 | gsc_to_pci_forwarding(s); | |
275 | break; | |
276 | ||
277 | case DINO_IAR0: | |
278 | s->iar0 = val; | |
279 | break; | |
280 | case DINO_IAR1: | |
281 | s->iar1 = val; | |
282 | break; | |
283 | case DINO_IMR: | |
284 | s->imr = val; | |
285 | break; | |
286 | case DINO_ICR: | |
287 | s->icr = val; | |
288 | break; | |
289 | case DINO_IPR: | |
290 | /* Any write to IPR clears the register. */ | |
291 | s->ipr = 0; | |
292 | break; | |
293 | ||
294 | case DINO_ILR: | |
295 | case DINO_IRR0: | |
296 | case DINO_IRR1: | |
297 | /* These registers are read-only. */ | |
298 | break; | |
299 | ||
300 | default: | |
301 | /* Controlled by dino_chip_mem_valid above. */ | |
302 | g_assert_not_reached(); | |
303 | } | |
304 | return MEMTX_OK; | |
305 | } | |
306 | ||
307 | static const MemoryRegionOps dino_chip_ops = { | |
308 | .read_with_attrs = dino_chip_read_with_attrs, | |
309 | .write_with_attrs = dino_chip_write_with_attrs, | |
310 | .endianness = DEVICE_BIG_ENDIAN, | |
311 | .valid = { | |
312 | .min_access_size = 1, | |
313 | .max_access_size = 4, | |
314 | .accepts = dino_chip_mem_valid, | |
315 | }, | |
316 | .impl = { | |
317 | .min_access_size = 1, | |
318 | .max_access_size = 4, | |
319 | }, | |
320 | }; | |
321 | ||
322 | static const VMStateDescription vmstate_dino = { | |
323 | .name = "Dino", | |
324 | .version_id = 1, | |
325 | .minimum_version_id = 1, | |
326 | .fields = (VMStateField[]) { | |
327 | VMSTATE_UINT32(iar0, DinoState), | |
328 | VMSTATE_UINT32(iar1, DinoState), | |
329 | VMSTATE_UINT32(imr, DinoState), | |
330 | VMSTATE_UINT32(ipr, DinoState), | |
331 | VMSTATE_UINT32(icr, DinoState), | |
332 | VMSTATE_UINT32(ilr, DinoState), | |
333 | VMSTATE_UINT32(io_addr_en, DinoState), | |
334 | VMSTATE_UINT32(io_control, DinoState), | |
335 | VMSTATE_END_OF_LIST() | |
336 | } | |
337 | }; | |
338 | ||
339 | ||
340 | /* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. */ | |
341 | ||
342 | static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len) | |
343 | { | |
344 | PCIHostState *s = opaque; | |
345 | return pci_data_read(s->bus, s->config_reg | (addr & 3), len); | |
346 | } | |
347 | ||
348 | static void dino_config_data_write(void *opaque, hwaddr addr, | |
349 | uint64_t val, unsigned len) | |
350 | { | |
351 | PCIHostState *s = opaque; | |
352 | pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); | |
353 | } | |
354 | ||
355 | static const MemoryRegionOps dino_config_data_ops = { | |
356 | .read = dino_config_data_read, | |
357 | .write = dino_config_data_write, | |
358 | .endianness = DEVICE_LITTLE_ENDIAN, | |
359 | }; | |
360 | ||
361 | static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque, | |
362 | int devfn) | |
363 | { | |
364 | DinoState *s = opaque; | |
365 | ||
366 | return &s->bm_as; | |
367 | } | |
368 | ||
369 | /* | |
370 | * Dino interrupts are connected as shown on Page 78, Table 23 | |
371 | * (Little-endian bit numbers) | |
372 | * 0 PCI INTA | |
373 | * 1 PCI INTB | |
374 | * 2 PCI INTC | |
375 | * 3 PCI INTD | |
376 | * 4 PCI INTE | |
377 | * 5 PCI INTF | |
378 | * 6 GSC External Interrupt | |
379 | * 7 Bus Error for "less than fatal" mode | |
380 | * 8 PS2 | |
381 | * 9 Unused | |
382 | * 10 RS232 | |
383 | */ | |
384 | ||
385 | static void dino_set_irq(void *opaque, int irq, int level) | |
386 | { | |
387 | DinoState *s = opaque; | |
388 | uint32_t bit = 1u << irq; | |
389 | uint32_t old_ilr = s->ilr; | |
390 | ||
391 | if (level) { | |
392 | uint32_t ena = bit & ~old_ilr; | |
393 | s->ipr |= ena; | |
394 | s->ilr = old_ilr | bit; | |
395 | if (ena & s->imr) { | |
396 | uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0); | |
397 | stl_be_phys(&address_space_memory, iar & -32, iar & 31); | |
398 | } | |
399 | } else { | |
400 | s->ilr = old_ilr & ~bit; | |
401 | } | |
402 | } | |
403 | ||
404 | static int dino_pci_map_irq(PCIDevice *d, int irq_num) | |
405 | { | |
406 | int slot = d->devfn >> 3; | |
a72bd606 HD |
407 | |
408 | assert(irq_num >= 0 && irq_num <= 3); | |
409 | ||
4a4ff4c5 | 410 | return slot & 0x03; |
a72bd606 HD |
411 | } |
412 | ||
413 | static void dino_set_timer_irq(void *opaque, int irq, int level) | |
414 | { | |
415 | /* ??? Not connected. */ | |
416 | } | |
417 | ||
418 | static void dino_set_serial_irq(void *opaque, int irq, int level) | |
419 | { | |
420 | dino_set_irq(opaque, 10, level); | |
421 | } | |
422 | ||
423 | PCIBus *dino_init(MemoryRegion *addr_space, | |
424 | qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq) | |
425 | { | |
426 | DeviceState *dev; | |
427 | DinoState *s; | |
428 | PCIBus *b; | |
429 | int i; | |
430 | ||
431 | dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE); | |
432 | s = DINO_PCI_HOST_BRIDGE(dev); | |
433 | ||
434 | /* Dino PCI access from main memory. */ | |
435 | memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops, | |
436 | s, "dino", 4096); | |
437 | memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem); | |
438 | ||
439 | /* Dino PCI config. */ | |
440 | memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj), | |
441 | &pci_host_conf_be_ops, dev, "pci-conf-idx", 4); | |
442 | memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj), | |
443 | &dino_config_data_ops, dev, "pci-conf-data", 4); | |
444 | memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR, | |
445 | &s->parent_obj.conf_mem); | |
446 | memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA, | |
447 | &s->parent_obj.data_mem); | |
448 | ||
449 | /* Dino PCI bus memory. */ | |
450 | memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 1ull << 32); | |
451 | ||
452 | b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s, | |
453 | &s->pci_mem, get_system_io(), | |
454 | PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS); | |
455 | s->parent_obj.bus = b; | |
456 | qdev_init_nofail(dev); | |
457 | ||
458 | /* Set up windows into PCI bus memory. */ | |
459 | for (i = 1; i < 31; i++) { | |
460 | uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE; | |
461 | char *name = g_strdup_printf("PCI Outbound Window %d", i); | |
462 | memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s), | |
463 | name, &s->pci_mem, addr, | |
464 | DINO_MEM_CHUNK_SIZE); | |
465 | } | |
466 | ||
467 | /* Set up PCI view of memory: Bus master address space. */ | |
468 | memory_region_init(&s->bm, OBJECT(s), "bm-dino", 1ull << 32); | |
469 | memory_region_init_alias(&s->bm_ram_alias, OBJECT(s), | |
470 | "bm-system", addr_space, 0, | |
471 | 0xf0000000 + DINO_MEM_CHUNK_SIZE); | |
472 | memory_region_init_alias(&s->bm_pci_alias, OBJECT(s), | |
473 | "bm-pci", &s->pci_mem, | |
474 | 0xf0000000 + DINO_MEM_CHUNK_SIZE, | |
475 | 31 * DINO_MEM_CHUNK_SIZE); | |
476 | memory_region_add_subregion(&s->bm, 0, | |
477 | &s->bm_ram_alias); | |
478 | memory_region_add_subregion(&s->bm, | |
479 | 0xf0000000 + DINO_MEM_CHUNK_SIZE, | |
480 | &s->bm_pci_alias); | |
481 | address_space_init(&s->bm_as, &s->bm, "pci-bm"); | |
482 | pci_setup_iommu(b, dino_pcihost_set_iommu, s); | |
483 | ||
484 | *p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0); | |
485 | *p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0); | |
486 | ||
487 | return b; | |
488 | } | |
489 | ||
490 | static int dino_pcihost_init(SysBusDevice *dev) | |
491 | { | |
492 | return 0; | |
493 | } | |
494 | ||
495 | static void dino_pcihost_class_init(ObjectClass *klass, void *data) | |
496 | { | |
497 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
498 | DeviceClass *dc = DEVICE_CLASS(klass); | |
499 | ||
500 | k->init = dino_pcihost_init; | |
501 | dc->vmsd = &vmstate_dino; | |
502 | } | |
503 | ||
504 | static const TypeInfo dino_pcihost_info = { | |
505 | .name = TYPE_DINO_PCI_HOST_BRIDGE, | |
506 | .parent = TYPE_PCI_HOST_BRIDGE, | |
507 | .instance_size = sizeof(DinoState), | |
508 | .class_init = dino_pcihost_class_init, | |
509 | }; | |
510 | ||
511 | static void dino_register_types(void) | |
512 | { | |
513 | type_register_static(&dino_pcihost_info); | |
514 | } | |
515 | ||
516 | type_init(dino_register_types) |