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376b8519 HD |
1 | /* |
2 | * HP-PARISC Lasi chipset emulation. | |
3 | * | |
4 | * (C) 2019 by Helge Deller <deller@gmx.de> | |
5 | * | |
6 | * This work is licensed under the GNU GPL license version 2 or later. | |
7 | * | |
8 | * Documentation available at: | |
9 | * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf | |
10 | */ | |
11 | ||
12 | #include "qemu/osdep.h" | |
13 | #include "qemu/units.h" | |
14 | #include "qapi/error.h" | |
15 | #include "cpu.h" | |
16 | #include "trace.h" | |
17 | #include "hw/hw.h" | |
18 | #include "hw/irq.h" | |
19 | #include "sysemu/sysemu.h" | |
20 | #include "sysemu/runstate.h" | |
21 | #include "hppa_sys.h" | |
22 | #include "hw/net/lasi_82596.h" | |
23 | #include "hw/char/parallel.h" | |
24 | #include "hw/char/serial.h" | |
2a6505b0 | 25 | #include "hw/input/lasips2.h" |
376b8519 HD |
26 | #include "exec/address-spaces.h" |
27 | #include "migration/vmstate.h" | |
28 | ||
29 | #define TYPE_LASI_CHIP "lasi-chip" | |
30 | ||
31 | #define LASI_IRR 0x00 /* RO */ | |
32 | #define LASI_IMR 0x04 | |
33 | #define LASI_IPR 0x08 | |
34 | #define LASI_ICR 0x0c | |
35 | #define LASI_IAR 0x10 | |
36 | ||
37 | #define LASI_PCR 0x0C000 /* LASI Power Control register */ | |
38 | #define LASI_ERRLOG 0x0C004 /* LASI Error Logging register */ | |
39 | #define LASI_VER 0x0C008 /* LASI Version Control register */ | |
40 | #define LASI_IORESET 0x0C00C /* LASI I/O Reset register */ | |
41 | #define LASI_AMR 0x0C010 /* LASI Arbitration Mask register */ | |
42 | #define LASI_IO_CONF 0x7FFFE /* LASI primary configuration register */ | |
43 | #define LASI_IO_CONF2 0x7FFFF /* LASI secondary configuration register */ | |
44 | ||
45 | #define LASI_BIT(x) (1ul << (x)) | |
46 | #define LASI_IRQ_BITS (LASI_BIT(5) | LASI_BIT(7) | LASI_BIT(8) | LASI_BIT(9) \ | |
47 | | LASI_BIT(13) | LASI_BIT(14) | LASI_BIT(16) | LASI_BIT(17) \ | |
48 | | LASI_BIT(18) | LASI_BIT(19) | LASI_BIT(20) | LASI_BIT(21) \ | |
49 | | LASI_BIT(26)) | |
50 | ||
51 | #define ICR_BUS_ERROR_BIT LASI_BIT(8) /* bit 8 in ICR */ | |
52 | #define ICR_TOC_BIT LASI_BIT(1) /* bit 1 in ICR */ | |
53 | ||
54 | #define LASI_CHIP(obj) \ | |
55 | OBJECT_CHECK(LasiState, (obj), TYPE_LASI_CHIP) | |
56 | ||
376b8519 HD |
57 | typedef struct LasiState { |
58 | PCIHostState parent_obj; | |
59 | ||
60 | uint32_t irr; | |
61 | uint32_t imr; | |
62 | uint32_t ipr; | |
63 | uint32_t icr; | |
64 | uint32_t iar; | |
65 | ||
66 | uint32_t errlog; | |
67 | uint32_t amr; | |
68 | uint32_t rtc; | |
69 | time_t rtc_ref; | |
70 | ||
71 | MemoryRegion this_mem; | |
72 | } LasiState; | |
73 | ||
74 | static bool lasi_chip_mem_valid(void *opaque, hwaddr addr, | |
75 | unsigned size, bool is_write, | |
76 | MemTxAttrs attrs) | |
77 | { | |
78 | bool ret = false; | |
79 | ||
80 | switch (addr) { | |
81 | case LASI_IRR: | |
82 | case LASI_IMR: | |
83 | case LASI_IPR: | |
84 | case LASI_ICR: | |
85 | case LASI_IAR: | |
86 | ||
87 | case (LASI_LAN_HPA - LASI_HPA): | |
88 | case (LASI_LPT_HPA - LASI_HPA): | |
89 | case (LASI_UART_HPA - LASI_HPA): | |
90 | case (LASI_RTC_HPA - LASI_HPA): | |
91 | ||
92 | case LASI_PCR ... LASI_AMR: | |
93 | ret = true; | |
94 | } | |
95 | ||
96 | trace_lasi_chip_mem_valid(addr, ret); | |
97 | return ret; | |
98 | } | |
99 | ||
100 | static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr, | |
101 | uint64_t *data, unsigned size, | |
102 | MemTxAttrs attrs) | |
103 | { | |
104 | LasiState *s = opaque; | |
105 | MemTxResult ret = MEMTX_OK; | |
106 | uint32_t val; | |
107 | ||
108 | switch (addr) { | |
109 | case LASI_IRR: | |
110 | val = s->irr; | |
111 | break; | |
112 | case LASI_IMR: | |
113 | val = s->imr; | |
114 | break; | |
115 | case LASI_IPR: | |
116 | val = s->ipr; | |
117 | /* Any read to IPR clears the register. */ | |
118 | s->ipr = 0; | |
119 | break; | |
120 | case LASI_ICR: | |
121 | val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */ | |
122 | break; | |
123 | case LASI_IAR: | |
124 | val = s->iar; | |
125 | break; | |
126 | ||
127 | case (LASI_LAN_HPA - LASI_HPA): | |
128 | case (LASI_LPT_HPA - LASI_HPA): | |
129 | case (LASI_UART_HPA - LASI_HPA): | |
130 | val = 0; | |
131 | break; | |
132 | case (LASI_RTC_HPA - LASI_HPA): | |
133 | val = time(NULL); | |
134 | val += s->rtc_ref; | |
135 | break; | |
136 | ||
137 | case LASI_PCR: | |
138 | case LASI_VER: /* only version 0 existed. */ | |
139 | case LASI_IORESET: | |
140 | val = 0; | |
141 | break; | |
142 | case LASI_ERRLOG: | |
143 | val = s->errlog; | |
144 | break; | |
145 | case LASI_AMR: | |
146 | val = s->amr; | |
147 | break; | |
148 | ||
149 | default: | |
150 | /* Controlled by lasi_chip_mem_valid above. */ | |
151 | g_assert_not_reached(); | |
152 | } | |
153 | ||
154 | trace_lasi_chip_read(addr, val); | |
155 | ||
156 | *data = val; | |
157 | return ret; | |
158 | } | |
159 | ||
160 | static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr, | |
161 | uint64_t val, unsigned size, | |
162 | MemTxAttrs attrs) | |
163 | { | |
164 | LasiState *s = opaque; | |
165 | ||
166 | trace_lasi_chip_write(addr, val); | |
167 | ||
168 | switch (addr) { | |
169 | case LASI_IRR: | |
170 | /* read-only. */ | |
171 | break; | |
172 | case LASI_IMR: | |
173 | s->imr = val; /* 0x20 ?? */ | |
174 | assert((val & LASI_IRQ_BITS) == val); | |
175 | break; | |
176 | case LASI_IPR: | |
177 | /* Any write to IPR clears the register. */ | |
178 | s->ipr = 0; | |
179 | break; | |
180 | case LASI_ICR: | |
181 | s->icr = val; | |
182 | /* if (val & ICR_TOC_BIT) issue_toc(); */ | |
183 | break; | |
184 | case LASI_IAR: | |
185 | s->iar = val; | |
186 | break; | |
187 | ||
188 | case (LASI_LAN_HPA - LASI_HPA): | |
189 | /* XXX: reset LAN card */ | |
190 | break; | |
191 | case (LASI_LPT_HPA - LASI_HPA): | |
192 | /* XXX: reset parallel port */ | |
193 | break; | |
194 | case (LASI_UART_HPA - LASI_HPA): | |
195 | /* XXX: reset serial port */ | |
196 | break; | |
197 | case (LASI_RTC_HPA - LASI_HPA): | |
198 | s->rtc_ref = val - time(NULL); | |
199 | break; | |
200 | ||
201 | case LASI_PCR: | |
202 | if (val == 0x02) /* immediately power off */ | |
203 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | |
204 | break; | |
205 | case LASI_ERRLOG: | |
206 | s->errlog = val; | |
207 | break; | |
208 | case LASI_VER: | |
209 | /* read-only. */ | |
210 | break; | |
211 | case LASI_IORESET: | |
212 | break; /* XXX: TODO: Reset various devices. */ | |
213 | case LASI_AMR: | |
214 | s->amr = val; | |
215 | break; | |
216 | ||
217 | default: | |
218 | /* Controlled by lasi_chip_mem_valid above. */ | |
219 | g_assert_not_reached(); | |
220 | } | |
221 | return MEMTX_OK; | |
222 | } | |
223 | ||
224 | static const MemoryRegionOps lasi_chip_ops = { | |
225 | .read_with_attrs = lasi_chip_read_with_attrs, | |
226 | .write_with_attrs = lasi_chip_write_with_attrs, | |
227 | .endianness = DEVICE_BIG_ENDIAN, | |
228 | .valid = { | |
229 | .min_access_size = 1, | |
230 | .max_access_size = 4, | |
231 | .accepts = lasi_chip_mem_valid, | |
232 | }, | |
233 | .impl = { | |
234 | .min_access_size = 1, | |
235 | .max_access_size = 4, | |
236 | }, | |
237 | }; | |
238 | ||
239 | static const VMStateDescription vmstate_lasi = { | |
240 | .name = "Lasi", | |
241 | .version_id = 1, | |
242 | .minimum_version_id = 1, | |
243 | .fields = (VMStateField[]) { | |
244 | VMSTATE_UINT32(irr, LasiState), | |
245 | VMSTATE_UINT32(imr, LasiState), | |
246 | VMSTATE_UINT32(ipr, LasiState), | |
247 | VMSTATE_UINT32(icr, LasiState), | |
248 | VMSTATE_UINT32(iar, LasiState), | |
249 | VMSTATE_UINT32(errlog, LasiState), | |
250 | VMSTATE_UINT32(amr, LasiState), | |
251 | VMSTATE_END_OF_LIST() | |
252 | } | |
253 | }; | |
254 | ||
255 | ||
256 | static void lasi_set_irq(void *opaque, int irq, int level) | |
257 | { | |
258 | LasiState *s = opaque; | |
259 | uint32_t bit = 1u << irq; | |
260 | ||
261 | if (level) { | |
262 | s->ipr |= bit; | |
263 | if (bit & s->imr) { | |
264 | uint32_t iar = s->iar; | |
265 | s->irr |= bit; | |
266 | if ((s->icr & ICR_BUS_ERROR_BIT) == 0) { | |
267 | stl_be_phys(&address_space_memory, iar & -32, iar & 31); | |
268 | } | |
269 | } | |
270 | } | |
271 | } | |
272 | ||
273 | static int lasi_get_irq(unsigned long hpa) | |
274 | { | |
275 | switch (hpa) { | |
276 | case LASI_HPA: | |
277 | return 14; | |
278 | case LASI_UART_HPA: | |
279 | return 5; | |
280 | case LASI_LPT_HPA: | |
281 | return 7; | |
282 | case LASI_LAN_HPA: | |
283 | return 8; | |
284 | case LASI_SCSI_HPA: | |
285 | return 9; | |
286 | case LASI_AUDIO_HPA: | |
287 | return 13; | |
288 | case LASI_PS2KBD_HPA: | |
289 | case LASI_PS2MOU_HPA: | |
290 | return 26; | |
291 | default: | |
292 | g_assert_not_reached(); | |
293 | } | |
294 | } | |
295 | ||
296 | DeviceState *lasi_init(MemoryRegion *address_space) | |
297 | { | |
298 | DeviceState *dev; | |
299 | LasiState *s; | |
300 | ||
3e80f690 | 301 | dev = qdev_new(TYPE_LASI_CHIP); |
376b8519 HD |
302 | s = LASI_CHIP(dev); |
303 | s->iar = CPU_HPA + 3; | |
304 | ||
305 | /* Lasi access from main memory. */ | |
306 | memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops, | |
307 | s, "lasi", 0x100000); | |
308 | memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem); | |
309 | ||
3c6ef471 | 310 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
376b8519 HD |
311 | |
312 | /* LAN */ | |
313 | if (enable_lasi_lan()) { | |
314 | qemu_irq lan_irq = qemu_allocate_irq(lasi_set_irq, s, | |
315 | lasi_get_irq(LASI_LAN_HPA)); | |
316 | lasi_82596_init(address_space, LASI_LAN_HPA, lan_irq); | |
317 | } | |
318 | ||
319 | /* Parallel port */ | |
320 | qemu_irq lpt_irq = qemu_allocate_irq(lasi_set_irq, s, | |
321 | lasi_get_irq(LASI_LPT_HPA)); | |
322 | parallel_mm_init(address_space, LASI_LPT_HPA + 0x800, 0, | |
323 | lpt_irq, parallel_hds[0]); | |
324 | ||
325 | /* Real time clock (RTC), it's only one 32-bit counter @9000 */ | |
2a6505b0 | 326 | |
376b8519 HD |
327 | s->rtc = time(NULL); |
328 | s->rtc_ref = 0; | |
329 | ||
330 | if (serial_hd(1)) { | |
331 | /* Serial port */ | |
332 | qemu_irq serial_irq = qemu_allocate_irq(lasi_set_irq, s, | |
333 | lasi_get_irq(LASI_UART_HPA)); | |
334 | serial_mm_init(address_space, LASI_UART_HPA + 0x800, 0, | |
335 | serial_irq, 8000000 / 16, | |
2a6505b0 | 336 | serial_hd(0), DEVICE_NATIVE_ENDIAN); |
376b8519 | 337 | } |
2a6505b0 SS |
338 | |
339 | /* PS/2 Keyboard/Mouse */ | |
340 | qemu_irq ps2kbd_irq = qemu_allocate_irq(lasi_set_irq, s, | |
341 | lasi_get_irq(LASI_PS2KBD_HPA)); | |
342 | lasips2_init(address_space, LASI_PS2KBD_HPA, ps2kbd_irq); | |
343 | ||
376b8519 HD |
344 | return dev; |
345 | } | |
346 | ||
347 | static void lasi_class_init(ObjectClass *klass, void *data) | |
348 | { | |
349 | DeviceClass *dc = DEVICE_CLASS(klass); | |
350 | ||
351 | dc->vmsd = &vmstate_lasi; | |
352 | } | |
353 | ||
354 | static const TypeInfo lasi_pcihost_info = { | |
355 | .name = TYPE_LASI_CHIP, | |
356 | .parent = TYPE_SYS_BUS_DEVICE, | |
357 | .instance_size = sizeof(LasiState), | |
358 | .class_init = lasi_class_init, | |
359 | }; | |
360 | ||
361 | static void lasi_register_types(void) | |
362 | { | |
363 | type_register_static(&lasi_pcihost_info); | |
364 | } | |
365 | ||
366 | type_init(lasi_register_types) |