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Commit | Line | Data |
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813dff13 HD |
1 | /* |
2 | * QEMU HPPA hardware system emulator. | |
3 | * Copyright 2018 Helge Deller <deller@gmx.de> | |
4 | */ | |
5 | ||
6 | #include "qemu/osdep.h" | |
7 | #include "qemu-common.h" | |
8 | #include "cpu.h" | |
813dff13 HD |
9 | #include "elf.h" |
10 | #include "hw/loader.h" | |
11 | #include "hw/boards.h" | |
12 | #include "qemu/error-report.h" | |
71e8a915 | 13 | #include "sysemu/reset.h" |
813dff13 | 14 | #include "sysemu/sysemu.h" |
bcdb9064 | 15 | #include "hw/rtc/mc146818rtc.h" |
813dff13 HD |
16 | #include "hw/timer/i8254.h" |
17 | #include "hw/char/serial.h" | |
376b8519 | 18 | #include "hw/net/lasi_82596.h" |
070e9a1e | 19 | #include "hppa_sys.h" |
c108cc59 | 20 | #include "qemu/units.h" |
813dff13 | 21 | #include "qapi/error.h" |
852c27e2 | 22 | #include "net/net.h" |
691cbbad | 23 | #include "qemu/log.h" |
e07c4f44 | 24 | #include "net/net.h" |
813dff13 | 25 | |
a72bd606 HD |
26 | #define MAX_IDE_BUS 2 |
27 | ||
28b71a2e HD |
28 | #define MIN_SEABIOS_HPPA_VERSION 1 /* require at least this fw version */ |
29 | ||
a72bd606 HD |
30 | static ISABus *hppa_isa_bus(void) |
31 | { | |
32 | ISABus *isa_bus; | |
33 | qemu_irq *isa_irqs; | |
34 | MemoryRegion *isa_region; | |
35 | ||
36 | isa_region = g_new(MemoryRegion, 1); | |
37 | memory_region_init_io(isa_region, NULL, &hppa_pci_ignore_ops, | |
38 | NULL, "isa-io", 0x800); | |
39 | memory_region_add_subregion(get_system_memory(), IDE_HPA, | |
40 | isa_region); | |
41 | ||
42 | isa_bus = isa_bus_new(NULL, get_system_memory(), isa_region, | |
43 | &error_abort); | |
44 | isa_irqs = i8259_init(isa_bus, | |
45 | /* qemu_allocate_irq(dino_set_isa_irq, s, 0)); */ | |
46 | NULL); | |
47 | isa_bus_irqs(isa_bus, isa_irqs); | |
48 | ||
49 | return isa_bus; | |
50 | } | |
51 | ||
52 | static uint64_t cpu_hppa_to_phys(void *opaque, uint64_t addr) | |
53 | { | |
54 | addr &= (0x10000000 - 1); | |
55 | return addr; | |
56 | } | |
57 | ||
58 | static HPPACPU *cpu[HPPA_MAX_CPUS]; | |
59 | static uint64_t firmware_entry; | |
813dff13 | 60 | |
32ff8bf2 HD |
61 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
62 | Error **errp) | |
63 | { | |
64 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
65 | } | |
66 | ||
28b71a2e HD |
67 | static FWCfgState *create_fw_cfg(MachineState *ms) |
68 | { | |
69 | FWCfgState *fw_cfg; | |
70 | uint64_t val; | |
71 | ||
24576007 | 72 | fw_cfg = fw_cfg_init_mem(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4); |
28b71a2e HD |
73 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, ms->smp.cpus); |
74 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, HPPA_MAX_CPUS); | |
75 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ram_size); | |
76 | ||
77 | val = cpu_to_le64(MIN_SEABIOS_HPPA_VERSION); | |
78 | fw_cfg_add_file(fw_cfg, "/etc/firmware-min-version", | |
79 | g_memdup(&val, sizeof(val)), sizeof(val)); | |
80 | ||
df5c6a50 HD |
81 | val = cpu_to_le64(HPPA_TLB_ENTRIES); |
82 | fw_cfg_add_file(fw_cfg, "/etc/cpu/tlb_entries", | |
83 | g_memdup(&val, sizeof(val)), sizeof(val)); | |
84 | ||
85 | val = cpu_to_le64(HPPA_BTLB_ENTRIES); | |
86 | fw_cfg_add_file(fw_cfg, "/etc/cpu/btlb_entries", | |
87 | g_memdup(&val, sizeof(val)), sizeof(val)); | |
88 | ||
32ff8bf2 HD |
89 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ms->boot_order[0]); |
90 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
91 | ||
28b71a2e HD |
92 | return fw_cfg; |
93 | } | |
94 | ||
813dff13 HD |
95 | static void machine_hppa_init(MachineState *machine) |
96 | { | |
a72bd606 HD |
97 | const char *kernel_filename = machine->kernel_filename; |
98 | const char *kernel_cmdline = machine->kernel_cmdline; | |
99 | const char *initrd_filename = machine->initrd_filename; | |
877eb21d | 100 | DeviceState *dev; |
a72bd606 HD |
101 | PCIBus *pci_bus; |
102 | ISABus *isa_bus; | |
103 | qemu_irq rtc_irq, serial_irq; | |
104 | char *firmware_filename; | |
105 | uint64_t firmware_low, firmware_high; | |
106 | long size; | |
107 | uint64_t kernel_entry = 0, kernel_low, kernel_high; | |
108 | MemoryRegion *addr_space = get_system_memory(); | |
109 | MemoryRegion *rom_region; | |
a72bd606 HD |
110 | MemoryRegion *cpu_region; |
111 | long i; | |
33decbd2 | 112 | unsigned int smp_cpus = machine->smp.cpus; |
4765384c | 113 | SysBusDevice *s; |
a72bd606 | 114 | |
a72bd606 HD |
115 | /* Create CPUs. */ |
116 | for (i = 0; i < smp_cpus; i++) { | |
266a880e | 117 | char *name = g_strdup_printf("cpu%ld-io-eir", i); |
a72bd606 HD |
118 | cpu[i] = HPPA_CPU(cpu_create(machine->cpu_type)); |
119 | ||
120 | cpu_region = g_new(MemoryRegion, 1); | |
121 | memory_region_init_io(cpu_region, OBJECT(cpu[i]), &hppa_io_eir_ops, | |
266a880e | 122 | cpu[i], name, 4); |
a72bd606 HD |
123 | memory_region_add_subregion(addr_space, CPU_HPA + i * 0x1000, |
124 | cpu_region); | |
266a880e | 125 | g_free(name); |
a72bd606 HD |
126 | } |
127 | ||
a72bd606 | 128 | /* Main memory region. */ |
b7746b11 PMD |
129 | if (machine->ram_size > 3 * GiB) { |
130 | error_report("RAM size is currently restricted to 3GB"); | |
131 | exit(EXIT_FAILURE); | |
132 | } | |
7c59c1e0 IM |
133 | memory_region_add_subregion_overlap(addr_space, 0, machine->ram, -1); |
134 | ||
a72bd606 | 135 | |
376b8519 HD |
136 | /* Init Lasi chip */ |
137 | lasi_init(addr_space); | |
138 | ||
a72bd606 HD |
139 | /* Init Dino (PCI host bus chip). */ |
140 | pci_bus = dino_init(addr_space, &rtc_irq, &serial_irq); | |
141 | assert(pci_bus); | |
142 | ||
143 | /* Create ISA bus. */ | |
144 | isa_bus = hppa_isa_bus(); | |
145 | assert(isa_bus); | |
146 | ||
147 | /* Realtime clock, used by firmware for PDC_TOD call. */ | |
148 | mc146818_rtc_init(isa_bus, 2000, rtc_irq); | |
149 | ||
150 | /* Serial code setup. */ | |
9bca0edb | 151 | if (serial_hd(0)) { |
a72bd606 HD |
152 | uint32_t addr = DINO_UART_HPA + 0x800; |
153 | serial_mm_init(addr_space, addr, 0, serial_irq, | |
9bca0edb | 154 | 115200, serial_hd(0), DEVICE_BIG_ENDIAN); |
a72bd606 HD |
155 | } |
156 | ||
28b71a2e HD |
157 | /* fw_cfg configuration interface */ |
158 | create_fw_cfg(machine); | |
159 | ||
a72bd606 | 160 | /* SCSI disk setup. */ |
877eb21d MCA |
161 | dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); |
162 | lsi53c8xx_handle_legacy_cmdline(dev); | |
a72bd606 | 163 | |
4765384c SS |
164 | /* Graphics setup. */ |
165 | if (machine->enable_graphics && vga_interface_type != VGA_NONE) { | |
3e80f690 | 166 | dev = qdev_new("artist"); |
4765384c | 167 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 168 | sysbus_realize_and_unref(s, &error_fatal); |
4765384c SS |
169 | sysbus_mmio_map(s, 0, LASI_GFX_HPA); |
170 | sysbus_mmio_map(s, 1, ARTIST_FB_ADDR); | |
171 | } | |
172 | ||
0e6de551 | 173 | /* Network setup. */ |
a72bd606 | 174 | for (i = 0; i < nb_nics; i++) { |
376b8519 | 175 | if (!enable_lasi_lan()) { |
0e6de551 | 176 | pci_nic_init_nofail(&nd_table[i], pci_bus, "tulip", NULL); |
376b8519 | 177 | } |
a72bd606 HD |
178 | } |
179 | ||
180 | /* Load firmware. Given that this is not "real" firmware, | |
181 | but one explicitly written for the emulation, we might as | |
182 | well load it directly from an ELF image. */ | |
183 | firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, | |
184 | bios_name ? bios_name : | |
185 | "hppa-firmware.img"); | |
186 | if (firmware_filename == NULL) { | |
187 | error_report("no firmware provided"); | |
188 | exit(1); | |
189 | } | |
190 | ||
4366e1db | 191 | size = load_elf(firmware_filename, NULL, NULL, NULL, |
6cdda0ff | 192 | &firmware_entry, &firmware_low, &firmware_high, NULL, |
a72bd606 HD |
193 | true, EM_PARISC, 0, 0); |
194 | ||
195 | /* Unfortunately, load_elf sign-extends reading elf32. */ | |
196 | firmware_entry = (target_ureg)firmware_entry; | |
197 | firmware_low = (target_ureg)firmware_low; | |
198 | firmware_high = (target_ureg)firmware_high; | |
199 | ||
200 | if (size < 0) { | |
201 | error_report("could not load firmware '%s'", firmware_filename); | |
202 | exit(1); | |
203 | } | |
691cbbad RH |
204 | qemu_log_mask(CPU_LOG_PAGE, "Firmware loaded at 0x%08" PRIx64 |
205 | "-0x%08" PRIx64 ", entry at 0x%08" PRIx64 ".\n", | |
206 | firmware_low, firmware_high, firmware_entry); | |
8262863d | 207 | if (firmware_low < FIRMWARE_START || firmware_high >= FIRMWARE_END) { |
a72bd606 HD |
208 | error_report("Firmware overlaps with memory or IO space"); |
209 | exit(1); | |
210 | } | |
211 | g_free(firmware_filename); | |
212 | ||
213 | rom_region = g_new(MemoryRegion, 1); | |
6a3a2e82 IM |
214 | memory_region_init_ram(rom_region, NULL, "firmware", |
215 | (FIRMWARE_END - FIRMWARE_START), &error_fatal); | |
a72bd606 HD |
216 | memory_region_add_subregion(addr_space, FIRMWARE_START, rom_region); |
217 | ||
218 | /* Load kernel */ | |
219 | if (kernel_filename) { | |
4366e1db | 220 | size = load_elf(kernel_filename, NULL, &cpu_hppa_to_phys, |
6cdda0ff | 221 | NULL, &kernel_entry, &kernel_low, &kernel_high, NULL, |
a72bd606 HD |
222 | true, EM_PARISC, 0, 0); |
223 | ||
224 | /* Unfortunately, load_elf sign-extends reading elf32. */ | |
225 | kernel_entry = (target_ureg) cpu_hppa_to_phys(NULL, kernel_entry); | |
226 | kernel_low = (target_ureg)kernel_low; | |
227 | kernel_high = (target_ureg)kernel_high; | |
228 | ||
229 | if (size < 0) { | |
230 | error_report("could not load kernel '%s'", kernel_filename); | |
231 | exit(1); | |
232 | } | |
691cbbad RH |
233 | qemu_log_mask(CPU_LOG_PAGE, "Kernel loaded at 0x%08" PRIx64 |
234 | "-0x%08" PRIx64 ", entry at 0x%08" PRIx64 | |
c108cc59 PMD |
235 | ", size %" PRIu64 " kB\n", |
236 | kernel_low, kernel_high, kernel_entry, size / KiB); | |
a72bd606 HD |
237 | |
238 | if (kernel_cmdline) { | |
239 | cpu[0]->env.gr[24] = 0x4000; | |
240 | pstrcpy_targphys("cmdline", cpu[0]->env.gr[24], | |
241 | TARGET_PAGE_SIZE, kernel_cmdline); | |
242 | } | |
243 | ||
244 | if (initrd_filename) { | |
245 | ram_addr_t initrd_base; | |
f3839fda | 246 | int64_t initrd_size; |
a72bd606 HD |
247 | |
248 | initrd_size = get_image_size(initrd_filename); | |
249 | if (initrd_size < 0) { | |
250 | error_report("could not load initial ram disk '%s'", | |
251 | initrd_filename); | |
252 | exit(1); | |
253 | } | |
254 | ||
255 | /* Load the initrd image high in memory. | |
256 | Mirror the algorithm used by palo: | |
257 | (1) Due to sign-extension problems and PDC, | |
258 | put the initrd no higher than 1G. | |
259 | (2) Reserve 64k for stack. */ | |
c108cc59 PMD |
260 | initrd_base = MIN(ram_size, 1 * GiB); |
261 | initrd_base = initrd_base - 64 * KiB; | |
a72bd606 HD |
262 | initrd_base = (initrd_base - initrd_size) & TARGET_PAGE_MASK; |
263 | ||
264 | if (initrd_base < kernel_high) { | |
265 | error_report("kernel and initial ram disk too large!"); | |
266 | exit(1); | |
267 | } | |
268 | ||
269 | load_image_targphys(initrd_filename, initrd_base, initrd_size); | |
270 | cpu[0]->env.gr[23] = initrd_base; | |
271 | cpu[0]->env.gr[22] = initrd_base + initrd_size; | |
272 | } | |
273 | } | |
274 | ||
275 | if (!kernel_entry) { | |
276 | /* When booting via firmware, tell firmware if we want interactive | |
277 | * mode (kernel_entry=1), and to boot from CD (gr[24]='d') | |
278 | * or hard disc * (gr[24]='c'). | |
279 | */ | |
280 | kernel_entry = boot_menu ? 1 : 0; | |
281 | cpu[0]->env.gr[24] = machine->boot_order[0]; | |
282 | } | |
283 | ||
284 | /* We jump to the firmware entry routine and pass the | |
285 | * various parameters in registers. After firmware initialization, | |
286 | * firmware will start the Linux kernel with ramdisk and cmdline. | |
287 | */ | |
288 | cpu[0]->env.gr[26] = ram_size; | |
289 | cpu[0]->env.gr[25] = kernel_entry; | |
290 | ||
291 | /* tell firmware how many SMP CPUs to present in inventory table */ | |
292 | cpu[0]->env.gr[21] = smp_cpus; | |
24576007 HD |
293 | |
294 | /* tell firmware fw_cfg port */ | |
295 | cpu[0]->env.gr[19] = FW_CFG_IO_BASE; | |
813dff13 HD |
296 | } |
297 | ||
a0628599 | 298 | static void hppa_machine_reset(MachineState *ms) |
a72bd606 | 299 | { |
33decbd2 | 300 | unsigned int smp_cpus = ms->smp.cpus; |
a72bd606 HD |
301 | int i; |
302 | ||
303 | qemu_devices_reset(); | |
304 | ||
305 | /* Start all CPUs at the firmware entry point. | |
306 | * Monarch CPU will initialize firmware, secondary CPUs | |
307 | * will enter a small idle look and wait for rendevouz. */ | |
308 | for (i = 0; i < smp_cpus; i++) { | |
309 | cpu_set_pc(CPU(cpu[i]), firmware_entry); | |
310 | cpu[i]->env.gr[5] = CPU_HPA + i * 0x1000; | |
311 | } | |
312 | ||
313 | /* already initialized by machine_hppa_init()? */ | |
314 | if (cpu[0]->env.gr[26] == ram_size) { | |
315 | return; | |
316 | } | |
317 | ||
318 | cpu[0]->env.gr[26] = ram_size; | |
319 | cpu[0]->env.gr[25] = 0; /* no firmware boot menu */ | |
320 | cpu[0]->env.gr[24] = 'c'; | |
321 | /* gr22/gr23 unused, no initrd while reboot. */ | |
322 | cpu[0]->env.gr[21] = smp_cpus; | |
24576007 HD |
323 | /* tell firmware fw_cfg port */ |
324 | cpu[0]->env.gr[19] = FW_CFG_IO_BASE; | |
a72bd606 HD |
325 | } |
326 | ||
327 | ||
813dff13 HD |
328 | static void machine_hppa_machine_init(MachineClass *mc) |
329 | { | |
330 | mc->desc = "HPPA generic machine"; | |
a72bd606 | 331 | mc->default_cpu_type = TYPE_HPPA_CPU; |
813dff13 | 332 | mc->init = machine_hppa_init; |
a72bd606 | 333 | mc->reset = hppa_machine_reset; |
813dff13 | 334 | mc->block_default_type = IF_SCSI; |
a72bd606 HD |
335 | mc->max_cpus = HPPA_MAX_CPUS; |
336 | mc->default_cpus = 1; | |
ea0ac7f6 | 337 | mc->is_default = true; |
d23b6caa | 338 | mc->default_ram_size = 512 * MiB; |
813dff13 | 339 | mc->default_boot_order = "cd"; |
7c59c1e0 | 340 | mc->default_ram_id = "ram"; |
813dff13 HD |
341 | } |
342 | ||
343 | DEFINE_MACHINE("hppa", machine_hppa_machine_init) |