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5fafdf24 1/*
0ff596d0
PB
2 * QEMU I2C bus interface.
3 *
4 * Copyright (c) 2007 CodeSourcery.
5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the LGPL.
0ff596d0
PB
8 */
9
0430891c 10#include "qemu/osdep.h"
0d09e41a 11#include "hw/i2c/i2c.h"
a27bd6c7 12#include "hw/qdev-properties.h"
d6454270 13#include "migration/vmstate.h"
3e80f690 14#include "qapi/error.h"
0b8fa32f 15#include "qemu/module.h"
37fa5ca4 16#include "qemu/main-loop.h"
08bb9b34 17#include "trace.h"
0ff596d0 18
71ae65e5
IM
19#define I2C_BROADCAST 0x00
20
3cb75a7c
PB
21static Property i2c_props[] = {
22 DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
23 DEFINE_PROP_END_OF_LIST(),
24};
25
0d936928
AL
26static const TypeInfo i2c_bus_info = {
27 .name = TYPE_I2C_BUS,
28 .parent = TYPE_BUS,
a5c82852 29 .instance_size = sizeof(I2CBus),
10c4c98a
GH
30};
31
44b1ff31 32static int i2c_bus_pre_save(void *opaque)
c701b35b 33{
a5c82852 34 I2CBus *bus = opaque;
c701b35b 35
2293c27f
FK
36 bus->saved_address = -1;
37 if (!QLIST_EMPTY(&bus->current_devs)) {
38 if (!bus->broadcast) {
39 bus->saved_address = QLIST_FIRST(&bus->current_devs)->elt->address;
71ae65e5
IM
40 } else {
41 bus->saved_address = I2C_BROADCAST;
2293c27f
FK
42 }
43 }
44b1ff31
DDAG
44
45 return 0;
c701b35b
PB
46}
47
8d0eb050
JQ
48static const VMStateDescription vmstate_i2c_bus = {
49 .name = "i2c_bus",
50 .version_id = 1,
51 .minimum_version_id = 1,
8d0eb050 52 .pre_save = i2c_bus_pre_save,
35d08458 53 .fields = (VMStateField[]) {
a5c82852 54 VMSTATE_UINT8(saved_address, I2CBus),
8d0eb050
JQ
55 VMSTATE_END_OF_LIST()
56 }
57};
58
0ff596d0 59/* Create a new I2C bus. */
a5c82852 60I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
0ff596d0 61{
a5c82852 62 I2CBus *bus;
0ff596d0 63
9388d170 64 bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name));
2293c27f 65 QLIST_INIT(&bus->current_devs);
37fa5ca4 66 QSIMPLEQ_INIT(&bus->pending_masters);
99b16e8e 67 vmstate_register_any(NULL, &vmstate_i2c_bus, bus);
0ff596d0
PB
68 return bus;
69}
70
c8665a59 71void i2c_slave_set_address(I2CSlave *dev, uint8_t address)
0ff596d0
PB
72{
73 dev->address = address;
74}
75
76/* Return nonzero if bus is busy. */
a5c82852 77int i2c_bus_busy(I2CBus *bus)
0ff596d0 78{
37fa5ca4 79 return !QLIST_EMPTY(&bus->current_devs) || bus->bh;
0ff596d0
PB
80}
81
3f9b3259
PV
82bool i2c_scan_bus(I2CBus *bus, uint8_t address, bool broadcast,
83 I2CNodeList *current_devs)
84{
85 BusChild *kid;
86
87 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
88 DeviceState *qdev = kid->child;
89 I2CSlave *candidate = I2C_SLAVE(qdev);
90 I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(candidate);
91
92 if (sc->match_and_add(candidate, address, broadcast, current_devs)) {
93 if (!broadcast) {
94 return true;
95 }
96 }
97 }
98
99 /*
100 * If broadcast was true, and the list was full or empty, return true. If
101 * broadcast was false, return false.
102 */
103 return broadcast;
104}
105
d307c28c 106/* TODO: Make this handle multiple masters. */
cc083d8a 107/*
d307c28c
CM
108 * Start or continue an i2c transaction. When this is called for the
109 * first time or after an i2c_end_transfer(), if it returns an error
110 * the bus transaction is terminated (or really never started). If
111 * this is called after another i2c_start_transfer() without an
112 * intervening i2c_end_transfer(), and it returns an error, the
113 * transaction will not be terminated. The caller must do it.
114 *
115 * This corresponds with the way real hardware works. The SMBus
116 * protocol uses a start transfer to switch from write to read mode
117 * without releasing the bus. If that fails, the bus is still
118 * in a transaction.
265caf45
PMD
119 *
120 * @event must be I2C_START_RECV or I2C_START_SEND.
cc083d8a 121 */
265caf45
PMD
122static int i2c_do_start_transfer(I2CBus *bus, uint8_t address,
123 enum i2c_event event)
0ff596d0 124{
b5ea9327 125 I2CSlaveClass *sc;
2293c27f 126 I2CNode *node;
d307c28c 127 bool bus_scanned = false;
2293c27f 128
71ae65e5 129 if (address == I2C_BROADCAST) {
2293c27f
FK
130 /*
131 * This is a broadcast, the current_devs will be all the devices of the
132 * bus.
133 */
134 bus->broadcast = true;
135 }
0ff596d0 136
0fa758c3
CM
137 /*
138 * If there are already devices in the list, that means we are in
139 * the middle of a transaction and we shouldn't rescan the bus.
140 *
141 * This happens with any SMBus transaction, even on a pure I2C
142 * device. The interface does a transaction start without
143 * terminating the previous transaction.
144 */
145 if (QLIST_EMPTY(&bus->current_devs)) {
3f9b3259
PV
146 /* Disregard whether devices were found. */
147 (void)i2c_scan_bus(bus, address, bus->broadcast, &bus->current_devs);
d307c28c 148 bus_scanned = true;
0ff596d0
PB
149 }
150
2293c27f 151 if (QLIST_EMPTY(&bus->current_devs)) {
0ff596d0 152 return 1;
b5ea9327 153 }
0ff596d0 154
2293c27f 155 QLIST_FOREACH(node, &bus->current_devs, next) {
08bb9b34 156 I2CSlave *s = node->elt;
d307c28c
CM
157 int rv;
158
08bb9b34 159 sc = I2C_SLAVE_GET_CLASS(s);
2293c27f
FK
160 /* If the bus is already busy, assume this is a repeated
161 start condition. */
d307c28c 162
2293c27f 163 if (sc->event) {
a78e9839
KJ
164 trace_i2c_event(event == I2C_START_SEND ? "start" : "start_async",
165 s->address);
265caf45 166 rv = sc->event(s, event);
d307c28c
CM
167 if (rv && !bus->broadcast) {
168 if (bus_scanned) {
169 /* First call, terminate the transfer. */
170 i2c_end_transfer(bus);
171 }
172 return rv;
173 }
2293c27f 174 }
b5ea9327 175 }
0ff596d0
PB
176 return 0;
177}
178
265caf45
PMD
179int i2c_start_transfer(I2CBus *bus, uint8_t address, bool is_recv)
180{
181 return i2c_do_start_transfer(bus, address, is_recv
182 ? I2C_START_RECV
183 : I2C_START_SEND);
90603c5b
PMD
184}
185
37fa5ca4
KJ
186void i2c_bus_master(I2CBus *bus, QEMUBH *bh)
187{
791cb95f
KJ
188 I2CPendingMaster *node = g_new(struct I2CPendingMaster, 1);
189 node->bh = bh;
190
191 QSIMPLEQ_INSERT_TAIL(&bus->pending_masters, node, entry);
192}
193
194void i2c_schedule_pending_master(I2CBus *bus)
195{
196 I2CPendingMaster *node;
37fa5ca4 197
791cb95f
KJ
198 if (i2c_bus_busy(bus)) {
199 /* someone is already controlling the bus; wait for it to release it */
200 return;
201 }
37fa5ca4 202
791cb95f 203 if (QSIMPLEQ_EMPTY(&bus->pending_masters)) {
37fa5ca4
KJ
204 return;
205 }
206
791cb95f
KJ
207 node = QSIMPLEQ_FIRST(&bus->pending_masters);
208 bus->bh = node->bh;
209
210 QSIMPLEQ_REMOVE_HEAD(&bus->pending_masters, entry);
211 g_free(node);
212
37fa5ca4
KJ
213 qemu_bh_schedule(bus->bh);
214}
215
216void i2c_bus_release(I2CBus *bus)
217{
218 bus->bh = NULL;
791cb95f
KJ
219
220 i2c_schedule_pending_master(bus);
37fa5ca4
KJ
221}
222
90603c5b
PMD
223int i2c_start_recv(I2CBus *bus, uint8_t address)
224{
225 return i2c_do_start_transfer(bus, address, I2C_START_RECV);
226}
227
228int i2c_start_send(I2CBus *bus, uint8_t address)
229{
230 return i2c_do_start_transfer(bus, address, I2C_START_SEND);
265caf45
PMD
231}
232
a78e9839
KJ
233int i2c_start_send_async(I2CBus *bus, uint8_t address)
234{
235 return i2c_do_start_transfer(bus, address, I2C_START_SEND_ASYNC);
236}
237
a5c82852 238void i2c_end_transfer(I2CBus *bus)
0ff596d0 239{
b5ea9327 240 I2CSlaveClass *sc;
2293c27f 241 I2CNode *node, *next;
0ff596d0 242
2293c27f 243 QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
08bb9b34
PMD
244 I2CSlave *s = node->elt;
245 sc = I2C_SLAVE_GET_CLASS(s);
2293c27f 246 if (sc->event) {
08bb9b34
PMD
247 trace_i2c_event("finish", s->address);
248 sc->event(s, I2C_FINISH);
2293c27f
FK
249 }
250 QLIST_REMOVE(node, next);
251 g_free(node);
b5ea9327 252 }
2293c27f 253 bus->broadcast = false;
0ff596d0
PB
254}
255
2038a290 256int i2c_send(I2CBus *bus, uint8_t data)
0ff596d0 257{
b5ea9327 258 I2CSlaveClass *sc;
08bb9b34 259 I2CSlave *s;
2293c27f
FK
260 I2CNode *node;
261 int ret = 0;
262
2038a290
PMD
263 QLIST_FOREACH(node, &bus->current_devs, next) {
264 s = node->elt;
265 sc = I2C_SLAVE_GET_CLASS(s);
266 if (sc->send) {
267 trace_i2c_send(s->address, data);
268 ret = ret || sc->send(s, data);
269 } else {
270 ret = -1;
056fca7b 271 }
b5ea9327 272 }
0ff596d0 273
2038a290 274 return ret ? -1 : 0;
056fca7b 275}
0ff596d0 276
a78e9839
KJ
277int i2c_send_async(I2CBus *bus, uint8_t data)
278{
279 I2CNode *node = QLIST_FIRST(&bus->current_devs);
280 I2CSlave *slave = node->elt;
281 I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(slave);
282
283 if (!sc->send_async) {
284 return -1;
285 }
286
287 trace_i2c_send_async(slave->address, data);
288
289 sc->send_async(slave, data);
290
291 return 0;
292}
293
2ac4c5f4 294uint8_t i2c_recv(I2CBus *bus)
056fca7b 295{
2ac4c5f4 296 uint8_t data = 0xff;
2038a290
PMD
297 I2CSlaveClass *sc;
298 I2CSlave *s;
299
300 if (!QLIST_EMPTY(&bus->current_devs) && !bus->broadcast) {
301 sc = I2C_SLAVE_GET_CLASS(QLIST_FIRST(&bus->current_devs)->elt);
302 if (sc->recv) {
303 s = QLIST_FIRST(&bus->current_devs)->elt;
304 data = sc->recv(s);
305 trace_i2c_recv(s->address, data);
306 }
307 }
b5ea9327 308
2ac4c5f4 309 return data;
0ff596d0
PB
310}
311
a5c82852 312void i2c_nack(I2CBus *bus)
0ff596d0 313{
b5ea9327 314 I2CSlaveClass *sc;
2293c27f 315 I2CNode *node;
0ff596d0 316
2293c27f 317 if (QLIST_EMPTY(&bus->current_devs)) {
0ff596d0 318 return;
b5ea9327 319 }
0ff596d0 320
2293c27f
FK
321 QLIST_FOREACH(node, &bus->current_devs, next) {
322 sc = I2C_SLAVE_GET_CLASS(node->elt);
323 if (sc->event) {
08bb9b34 324 trace_i2c_event("nack", node->elt->address);
2293c27f
FK
325 sc->event(node->elt, I2C_NACK);
326 }
b5ea9327 327 }
0ff596d0
PB
328}
329
a78e9839
KJ
330void i2c_ack(I2CBus *bus)
331{
332 if (!bus->bh) {
333 return;
334 }
335
336 trace_i2c_ack();
337
338 qemu_bh_schedule(bus->bh);
339}
340
bcbe8068 341static int i2c_slave_post_load(void *opaque, int version_id)
aa941b94 342{
9e07bdf8 343 I2CSlave *dev = opaque;
a5c82852 344 I2CBus *bus;
2293c27f
FK
345 I2CNode *node;
346
fef7fbc9 347 bus = I2C_BUS(qdev_get_parent_bus(DEVICE(dev)));
71ae65e5
IM
348 if ((bus->saved_address == dev->address) ||
349 (bus->saved_address == I2C_BROADCAST)) {
b21e2380 350 node = g_new(struct I2CNode, 1);
2293c27f
FK
351 node->elt = dev;
352 QLIST_INSERT_HEAD(&bus->current_devs, node, next);
fe8de492 353 }
bcbe8068
JQ
354 return 0;
355}
356
1894839f 357const VMStateDescription vmstate_i2c_slave = {
9e07bdf8 358 .name = "I2CSlave",
bcbe8068
JQ
359 .version_id = 1,
360 .minimum_version_id = 1,
bcbe8068 361 .post_load = i2c_slave_post_load,
35d08458 362 .fields = (VMStateField[]) {
9e07bdf8 363 VMSTATE_UINT8(address, I2CSlave),
bcbe8068
JQ
364 VMSTATE_END_OF_LIST()
365 }
366};
367
db437ca6 368I2CSlave *i2c_slave_new(const char *name, uint8_t addr)
fe8de492
PB
369{
370 DeviceState *dev;
371
3e80f690 372 dev = qdev_new(name);
5b7f5327 373 qdev_prop_set_uint8(dev, "address", addr);
db437ca6 374 return I2C_SLAVE(dev);
d88c42ff
PMD
375}
376
2616f572 377bool i2c_slave_realize_and_unref(I2CSlave *dev, I2CBus *bus, Error **errp)
d88c42ff 378{
2616f572 379 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp);
d88c42ff
PMD
380}
381
1373b15b 382I2CSlave *i2c_slave_create_simple(I2CBus *bus, const char *name, uint8_t addr)
d88c42ff 383{
db437ca6 384 I2CSlave *dev = i2c_slave_new(name, addr);
d88c42ff 385
1373b15b 386 i2c_slave_realize_and_unref(dev, bus, &error_abort);
d88c42ff 387
1373b15b 388 return dev;
aa941b94 389}
b5ea9327 390
513ca82d
PV
391static bool i2c_slave_match(I2CSlave *candidate, uint8_t address,
392 bool broadcast, I2CNodeList *current_devs)
393{
394 if ((candidate->address == address) || (broadcast)) {
b21e2380 395 I2CNode *node = g_new(struct I2CNode, 1);
513ca82d
PV
396 node->elt = candidate;
397 QLIST_INSERT_HEAD(current_devs, node, next);
398 return true;
399 }
400
401 /* Not found and not broadcast. */
402 return false;
403}
404
39bffca2
AL
405static void i2c_slave_class_init(ObjectClass *klass, void *data)
406{
407 DeviceClass *k = DEVICE_CLASS(klass);
513ca82d 408 I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
125ee0ed 409 set_bit(DEVICE_CATEGORY_MISC, k->categories);
0d936928 410 k->bus_type = TYPE_I2C_BUS;
4f67d30b 411 device_class_set_props(k, i2c_props);
513ca82d 412 sc->match_and_add = i2c_slave_match;
39bffca2
AL
413}
414
8c43a6f0 415static const TypeInfo i2c_slave_type_info = {
b5ea9327
AL
416 .name = TYPE_I2C_SLAVE,
417 .parent = TYPE_DEVICE,
418 .instance_size = sizeof(I2CSlave),
419 .abstract = true,
420 .class_size = sizeof(I2CSlaveClass),
39bffca2 421 .class_init = i2c_slave_class_init,
b5ea9327
AL
422};
423
83f7d43a 424static void i2c_slave_register_types(void)
b5ea9327 425{
0d936928 426 type_register_static(&i2c_bus_info);
b5ea9327
AL
427 type_register_static(&i2c_slave_type_info);
428}
429
83f7d43a 430type_init(i2c_slave_register_types)