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5fafdf24 1/*
0ff596d0
PB
2 * QEMU I2C bus interface.
3 *
4 * Copyright (c) 2007 CodeSourcery.
5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the LGPL.
0ff596d0
PB
8 */
9
0430891c 10#include "qemu/osdep.h"
0d09e41a 11#include "hw/i2c/i2c.h"
d6454270 12#include "migration/vmstate.h"
0b8fa32f 13#include "qemu/module.h"
08bb9b34 14#include "trace.h"
0ff596d0 15
71ae65e5
IM
16#define I2C_BROADCAST 0x00
17
3cb75a7c
PB
18static Property i2c_props[] = {
19 DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
20 DEFINE_PROP_END_OF_LIST(),
21};
22
0d936928
AL
23static const TypeInfo i2c_bus_info = {
24 .name = TYPE_I2C_BUS,
25 .parent = TYPE_BUS,
a5c82852 26 .instance_size = sizeof(I2CBus),
10c4c98a
GH
27};
28
44b1ff31 29static int i2c_bus_pre_save(void *opaque)
c701b35b 30{
a5c82852 31 I2CBus *bus = opaque;
c701b35b 32
2293c27f
FK
33 bus->saved_address = -1;
34 if (!QLIST_EMPTY(&bus->current_devs)) {
35 if (!bus->broadcast) {
36 bus->saved_address = QLIST_FIRST(&bus->current_devs)->elt->address;
71ae65e5
IM
37 } else {
38 bus->saved_address = I2C_BROADCAST;
2293c27f
FK
39 }
40 }
44b1ff31
DDAG
41
42 return 0;
c701b35b
PB
43}
44
8d0eb050
JQ
45static const VMStateDescription vmstate_i2c_bus = {
46 .name = "i2c_bus",
47 .version_id = 1,
48 .minimum_version_id = 1,
8d0eb050 49 .pre_save = i2c_bus_pre_save,
35d08458 50 .fields = (VMStateField[]) {
a5c82852 51 VMSTATE_UINT8(saved_address, I2CBus),
8d0eb050
JQ
52 VMSTATE_END_OF_LIST()
53 }
54};
55
0ff596d0 56/* Create a new I2C bus. */
a5c82852 57I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
0ff596d0 58{
a5c82852 59 I2CBus *bus;
0ff596d0 60
fef7fbc9 61 bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
2293c27f 62 QLIST_INIT(&bus->current_devs);
0be71e32 63 vmstate_register(NULL, -1, &vmstate_i2c_bus, bus);
0ff596d0
PB
64 return bus;
65}
66
9e07bdf8 67void i2c_set_slave_address(I2CSlave *dev, uint8_t address)
0ff596d0
PB
68{
69 dev->address = address;
70}
71
72/* Return nonzero if bus is busy. */
a5c82852 73int i2c_bus_busy(I2CBus *bus)
0ff596d0 74{
2293c27f 75 return !QLIST_EMPTY(&bus->current_devs);
0ff596d0
PB
76}
77
d307c28c 78/* TODO: Make this handle multiple masters. */
cc083d8a 79/*
d307c28c
CM
80 * Start or continue an i2c transaction. When this is called for the
81 * first time or after an i2c_end_transfer(), if it returns an error
82 * the bus transaction is terminated (or really never started). If
83 * this is called after another i2c_start_transfer() without an
84 * intervening i2c_end_transfer(), and it returns an error, the
85 * transaction will not be terminated. The caller must do it.
86 *
87 * This corresponds with the way real hardware works. The SMBus
88 * protocol uses a start transfer to switch from write to read mode
89 * without releasing the bus. If that fails, the bus is still
90 * in a transaction.
cc083d8a 91 */
a5c82852 92int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
0ff596d0 93{
0866aca1 94 BusChild *kid;
b5ea9327 95 I2CSlaveClass *sc;
2293c27f 96 I2CNode *node;
d307c28c 97 bool bus_scanned = false;
2293c27f 98
71ae65e5 99 if (address == I2C_BROADCAST) {
2293c27f
FK
100 /*
101 * This is a broadcast, the current_devs will be all the devices of the
102 * bus.
103 */
104 bus->broadcast = true;
105 }
0ff596d0 106
0fa758c3
CM
107 /*
108 * If there are already devices in the list, that means we are in
109 * the middle of a transaction and we shouldn't rescan the bus.
110 *
111 * This happens with any SMBus transaction, even on a pure I2C
112 * device. The interface does a transaction start without
113 * terminating the previous transaction.
114 */
115 if (QLIST_EMPTY(&bus->current_devs)) {
116 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
117 DeviceState *qdev = kid->child;
118 I2CSlave *candidate = I2C_SLAVE(qdev);
119 if ((candidate->address == address) || (bus->broadcast)) {
120 node = g_malloc(sizeof(struct I2CNode));
121 node->elt = candidate;
122 QLIST_INSERT_HEAD(&bus->current_devs, node, next);
123 if (!bus->broadcast) {
124 break;
125 }
2293c27f 126 }
b3a21988 127 }
d307c28c 128 bus_scanned = true;
0ff596d0
PB
129 }
130
2293c27f 131 if (QLIST_EMPTY(&bus->current_devs)) {
0ff596d0 132 return 1;
b5ea9327 133 }
0ff596d0 134
2293c27f 135 QLIST_FOREACH(node, &bus->current_devs, next) {
08bb9b34 136 I2CSlave *s = node->elt;
d307c28c
CM
137 int rv;
138
08bb9b34 139 sc = I2C_SLAVE_GET_CLASS(s);
2293c27f
FK
140 /* If the bus is already busy, assume this is a repeated
141 start condition. */
d307c28c 142
2293c27f 143 if (sc->event) {
08bb9b34
PMD
144 trace_i2c_event("start", s->address);
145 rv = sc->event(s, recv ? I2C_START_RECV : I2C_START_SEND);
d307c28c
CM
146 if (rv && !bus->broadcast) {
147 if (bus_scanned) {
148 /* First call, terminate the transfer. */
149 i2c_end_transfer(bus);
150 }
151 return rv;
152 }
2293c27f 153 }
b5ea9327 154 }
0ff596d0
PB
155 return 0;
156}
157
a5c82852 158void i2c_end_transfer(I2CBus *bus)
0ff596d0 159{
b5ea9327 160 I2CSlaveClass *sc;
2293c27f 161 I2CNode *node, *next;
0ff596d0 162
2293c27f 163 QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
08bb9b34
PMD
164 I2CSlave *s = node->elt;
165 sc = I2C_SLAVE_GET_CLASS(s);
2293c27f 166 if (sc->event) {
08bb9b34
PMD
167 trace_i2c_event("finish", s->address);
168 sc->event(s, I2C_FINISH);
2293c27f
FK
169 }
170 QLIST_REMOVE(node, next);
171 g_free(node);
b5ea9327 172 }
2293c27f 173 bus->broadcast = false;
0ff596d0
PB
174}
175
056fca7b 176int i2c_send_recv(I2CBus *bus, uint8_t *data, bool send)
0ff596d0 177{
b5ea9327 178 I2CSlaveClass *sc;
08bb9b34 179 I2CSlave *s;
2293c27f
FK
180 I2CNode *node;
181 int ret = 0;
182
056fca7b
PC
183 if (send) {
184 QLIST_FOREACH(node, &bus->current_devs, next) {
08bb9b34
PMD
185 s = node->elt;
186 sc = I2C_SLAVE_GET_CLASS(s);
056fca7b 187 if (sc->send) {
08bb9b34
PMD
188 trace_i2c_send(s->address, *data);
189 ret = ret || sc->send(s, *data);
056fca7b
PC
190 } else {
191 ret = -1;
192 }
193 }
194 return ret ? -1 : 0;
195 } else {
2ac4c5f4
CM
196 ret = 0xff;
197 if (!QLIST_EMPTY(&bus->current_devs) && !bus->broadcast) {
198 sc = I2C_SLAVE_GET_CLASS(QLIST_FIRST(&bus->current_devs)->elt);
199 if (sc->recv) {
200 s = QLIST_FIRST(&bus->current_devs)->elt;
201 ret = sc->recv(s);
202 trace_i2c_recv(s->address, ret);
056fca7b
PC
203 }
204 }
2ac4c5f4
CM
205 *data = ret;
206 return 0;
b5ea9327 207 }
0ff596d0
PB
208}
209
056fca7b 210int i2c_send(I2CBus *bus, uint8_t data)
0ff596d0 211{
056fca7b
PC
212 return i2c_send_recv(bus, &data, true);
213}
0ff596d0 214
2ac4c5f4 215uint8_t i2c_recv(I2CBus *bus)
056fca7b 216{
2ac4c5f4 217 uint8_t data = 0xff;
b5ea9327 218
2ac4c5f4
CM
219 i2c_send_recv(bus, &data, false);
220 return data;
0ff596d0
PB
221}
222
a5c82852 223void i2c_nack(I2CBus *bus)
0ff596d0 224{
b5ea9327 225 I2CSlaveClass *sc;
2293c27f 226 I2CNode *node;
0ff596d0 227
2293c27f 228 if (QLIST_EMPTY(&bus->current_devs)) {
0ff596d0 229 return;
b5ea9327 230 }
0ff596d0 231
2293c27f
FK
232 QLIST_FOREACH(node, &bus->current_devs, next) {
233 sc = I2C_SLAVE_GET_CLASS(node->elt);
234 if (sc->event) {
08bb9b34 235 trace_i2c_event("nack", node->elt->address);
2293c27f
FK
236 sc->event(node->elt, I2C_NACK);
237 }
b5ea9327 238 }
0ff596d0
PB
239}
240
bcbe8068 241static int i2c_slave_post_load(void *opaque, int version_id)
aa941b94 242{
9e07bdf8 243 I2CSlave *dev = opaque;
a5c82852 244 I2CBus *bus;
2293c27f
FK
245 I2CNode *node;
246
fef7fbc9 247 bus = I2C_BUS(qdev_get_parent_bus(DEVICE(dev)));
71ae65e5
IM
248 if ((bus->saved_address == dev->address) ||
249 (bus->saved_address == I2C_BROADCAST)) {
2293c27f
FK
250 node = g_malloc(sizeof(struct I2CNode));
251 node->elt = dev;
252 QLIST_INSERT_HEAD(&bus->current_devs, node, next);
fe8de492 253 }
bcbe8068
JQ
254 return 0;
255}
256
1894839f 257const VMStateDescription vmstate_i2c_slave = {
9e07bdf8 258 .name = "I2CSlave",
bcbe8068
JQ
259 .version_id = 1,
260 .minimum_version_id = 1,
bcbe8068 261 .post_load = i2c_slave_post_load,
35d08458 262 .fields = (VMStateField[]) {
9e07bdf8 263 VMSTATE_UINT8(address, I2CSlave),
bcbe8068
JQ
264 VMSTATE_END_OF_LIST()
265 }
266};
267
a5c82852 268DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr)
fe8de492
PB
269{
270 DeviceState *dev;
271
02e2da45 272 dev = qdev_create(&bus->qbus, name);
5b7f5327 273 qdev_prop_set_uint8(dev, "address", addr);
e23a1b33 274 qdev_init_nofail(dev);
fe8de492 275 return dev;
aa941b94 276}
b5ea9327 277
39bffca2
AL
278static void i2c_slave_class_init(ObjectClass *klass, void *data)
279{
280 DeviceClass *k = DEVICE_CLASS(klass);
125ee0ed 281 set_bit(DEVICE_CATEGORY_MISC, k->categories);
0d936928 282 k->bus_type = TYPE_I2C_BUS;
bce54474 283 k->props = i2c_props;
39bffca2
AL
284}
285
8c43a6f0 286static const TypeInfo i2c_slave_type_info = {
b5ea9327
AL
287 .name = TYPE_I2C_SLAVE,
288 .parent = TYPE_DEVICE,
289 .instance_size = sizeof(I2CSlave),
290 .abstract = true,
291 .class_size = sizeof(I2CSlaveClass),
39bffca2 292 .class_init = i2c_slave_class_init,
b5ea9327
AL
293};
294
83f7d43a 295static void i2c_slave_register_types(void)
b5ea9327 296{
0d936928 297 type_register_static(&i2c_bus_info);
b5ea9327
AL
298 type_register_static(&i2c_slave_type_info);
299}
300
83f7d43a 301type_init(i2c_slave_register_types)