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678e7b94 JB |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
6f918e40 JB |
5 | * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> |
6 | * VA Linux Systems Japan K.K. | |
7 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> | |
8 | * | |
9 | * This is based on acpi.c, but heavily rewritten. | |
678e7b94 JB |
10 | * |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License version 2 as published by the Free Software Foundation. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * Lesser General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU Lesser General Public | |
21 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
678e7b94 | 22 | * |
6f918e40 JB |
23 | * Contributions after 2012-01-13 are licensed under the terms of the |
24 | * GNU GPL, version 2 or (at your option) any later version. | |
25 | * | |
678e7b94 | 26 | */ |
b6a0aa05 | 27 | #include "qemu/osdep.h" |
83c9f4ca | 28 | #include "hw/hw.h" |
0d09e41a PB |
29 | #include "hw/i386/pc.h" |
30 | #include "hw/i2c/pm_smbus.h" | |
83c9f4ca | 31 | #include "hw/pci/pci.h" |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
0d09e41a PB |
33 | #include "hw/i2c/i2c.h" |
34 | #include "hw/i2c/smbus.h" | |
678e7b94 | 35 | |
0d09e41a | 36 | #include "hw/i386/ich9.h" |
678e7b94 | 37 | |
678e7b94 JB |
38 | #define ICH9_SMB_DEVICE(obj) \ |
39 | OBJECT_CHECK(ICH9SMBState, (obj), TYPE_ICH9_SMB_DEVICE) | |
40 | ||
41 | typedef struct ICH9SMBState { | |
42 | PCIDevice dev; | |
43 | ||
44 | PMSMBus smb; | |
678e7b94 JB |
45 | } ICH9SMBState; |
46 | ||
47 | static const VMStateDescription vmstate_ich9_smbus = { | |
48 | .name = "ich9_smb", | |
49 | .version_id = 1, | |
50 | .minimum_version_id = 1, | |
678e7b94 JB |
51 | .fields = (VMStateField[]) { |
52 | VMSTATE_PCI_DEVICE(dev, struct ICH9SMBState), | |
53 | VMSTATE_END_OF_LIST() | |
54 | } | |
55 | }; | |
56 | ||
798512e5 GH |
57 | static void ich9_smbus_write_config(PCIDevice *d, uint32_t address, |
58 | uint32_t val, int len) | |
678e7b94 | 59 | { |
798512e5 | 60 | ICH9SMBState *s = ICH9_SMB_DEVICE(d); |
678e7b94 | 61 | |
798512e5 GH |
62 | pci_default_write_config(d, address, val, len); |
63 | if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) { | |
64 | uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC]; | |
65 | if ((hostc & ICH9_SMB_HOSTC_HST_EN) && | |
66 | !(hostc & ICH9_SMB_HOSTC_I2C_EN)) { | |
67 | memory_region_set_enabled(&s->smb.io, true); | |
68 | } else { | |
69 | memory_region_set_enabled(&s->smb.io, false); | |
70 | } | |
678e7b94 JB |
71 | } |
72 | } | |
73 | ||
9af21dbe | 74 | static void ich9_smbus_realize(PCIDevice *d, Error **errp) |
678e7b94 JB |
75 | { |
76 | ICH9SMBState *s = ICH9_SMB_DEVICE(d); | |
77 | ||
78 | /* TODO? D31IP.SMIP in chipset configuration space */ | |
79 | pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */ | |
80 | ||
678e7b94 JB |
81 | pci_set_byte(d->config + ICH9_SMB_HOSTC, 0); |
82 | /* TODO bar0, bar1: 64bit BAR support*/ | |
83 | ||
678e7b94 | 84 | pm_smbus_init(&d->qdev, &s->smb); |
798512e5 GH |
85 | pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO, |
86 | &s->smb.io); | |
678e7b94 JB |
87 | } |
88 | ||
89 | static void ich9_smb_class_init(ObjectClass *klass, void *data) | |
90 | { | |
91 | DeviceClass *dc = DEVICE_CLASS(klass); | |
92 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
93 | ||
94 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
95 | k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6; | |
96 | k->revision = ICH9_A2_SMB_REVISION; | |
97 | k->class_id = PCI_CLASS_SERIAL_SMBUS; | |
678e7b94 JB |
98 | dc->vmsd = &vmstate_ich9_smbus; |
99 | dc->desc = "ICH9 SMBUS Bridge"; | |
9af21dbe | 100 | k->realize = ich9_smbus_realize; |
798512e5 | 101 | k->config_write = ich9_smbus_write_config; |
bfa6dfd0 MA |
102 | /* |
103 | * Reason: part of ICH9 southbridge, needs to be wired up by | |
104 | * pc_q35_init() | |
105 | */ | |
e90f2a8c | 106 | dc->user_creatable = false; |
678e7b94 JB |
107 | } |
108 | ||
a5c82852 | 109 | I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base) |
678e7b94 JB |
110 | { |
111 | PCIDevice *d = | |
112 | pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE); | |
113 | ICH9SMBState *s = ICH9_SMB_DEVICE(d); | |
114 | return s->smb.smbus; | |
115 | } | |
116 | ||
117 | static const TypeInfo ich9_smb_info = { | |
118 | .name = TYPE_ICH9_SMB_DEVICE, | |
119 | .parent = TYPE_PCI_DEVICE, | |
120 | .instance_size = sizeof(ICH9SMBState), | |
121 | .class_init = ich9_smb_class_init, | |
122 | }; | |
123 | ||
124 | static void ich9_smb_register(void) | |
125 | { | |
126 | type_register_static(&ich9_smb_info); | |
127 | } | |
128 | ||
129 | type_init(ich9_smb_register); |