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d1157ca4 1/*
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2 * ARM SBCon two-wire serial bus interface (I2C bitbang)
3 * a.k.a. ARM Versatile I2C controller
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4 *
5 * Copyright (c) 2006-2007 CodeSourcery.
6 * Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com>
7 *
8 * This file is derived from hw/realview.c by Paul Brook
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, see <http://www.gnu.org/licenses/>.
22 *
23 */
24
8ef94f0b 25#include "qemu/osdep.h"
f61c3fb5 26#include "hw/i2c/arm_sbcon_i2c.h"
faa1bdfa 27#include "hw/registerfields.h"
03dd024f 28#include "qemu/log.h"
0b8fa32f 29#include "qemu/module.h"
d1157ca4 30
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31#define VERSATILE_I2C(obj) \
32 OBJECT_CHECK(VersatileI2CState, (obj), TYPE_VERSATILE_I2C)
33
f61c3fb5 34typedef ArmSbconI2CState VersatileI2CState;
93e7f5f4 35
d1157ca4 36
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37REG32(CONTROL_GET, 0)
38REG32(CONTROL_SET, 0)
39REG32(CONTROL_CLR, 4)
40
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41#define SCL BIT(0)
42#define SDA BIT(1)
43
a8170e5e 44static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
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45 unsigned size)
46{
47 VersatileI2CState *s = (VersatileI2CState *)opaque;
48
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49 switch (offset) {
50 case A_CONTROL_SET:
d1157ca4 51 return (s->out & 1) | (s->in << 1);
faa1bdfa 52 default:
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53 qemu_log_mask(LOG_GUEST_ERROR,
54 "%s: Bad offset 0x%x\n", __func__, (int)offset);
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55 return -1;
56 }
57}
58
a8170e5e 59static void versatile_i2c_write(void *opaque, hwaddr offset,
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60 uint64_t value, unsigned size)
61{
62 VersatileI2CState *s = (VersatileI2CState *)opaque;
63
64 switch (offset) {
faa1bdfa 65 case A_CONTROL_SET:
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66 s->out |= value & 3;
67 break;
faa1bdfa 68 case A_CONTROL_CLR:
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69 s->out &= ~value;
70 break;
71 default:
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72 qemu_log_mask(LOG_GUEST_ERROR,
73 "%s: Bad offset 0x%x\n", __func__, (int)offset);
d1157ca4 74 }
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75 bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & SCL) != 0);
76 s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & SDA) != 0);
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77}
78
79static const MemoryRegionOps versatile_i2c_ops = {
80 .read = versatile_i2c_read,
81 .write = versatile_i2c_write,
82 .endianness = DEVICE_NATIVE_ENDIAN,
83};
84
8ce26fcd 85static void versatile_i2c_init(Object *obj)
d1157ca4 86{
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87 DeviceState *dev = DEVICE(obj);
88 VersatileI2CState *s = VERSATILE_I2C(obj);
89 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
a5c82852 90 I2CBus *bus;
d1157ca4 91
93e7f5f4 92 bus = i2c_init_bus(dev, "i2c");
41742927 93 bitbang_i2c_init(&s->bitbang, bus);
8ce26fcd 94 memory_region_init_io(&s->iomem, obj, &versatile_i2c_ops, s,
f61c3fb5 95 "arm_sbcon_i2c", 0x1000);
93e7f5f4 96 sysbus_init_mmio(sbd, &s->iomem);
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97}
98
99static const TypeInfo versatile_i2c_info = {
93e7f5f4 100 .name = TYPE_VERSATILE_I2C,
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101 .parent = TYPE_SYS_BUS_DEVICE,
102 .instance_size = sizeof(VersatileI2CState),
8ce26fcd 103 .instance_init = versatile_i2c_init,
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104};
105
106static void versatile_i2c_register_types(void)
107{
108 type_register_static(&versatile_i2c_info);
109}
110
111type_init(versatile_i2c_register_types)