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72c194f7 MT |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
4 | * Copyright (C) 2006 Fabrice Bellard | |
5 | * Copyright (C) 2013 Red Hat Inc | |
6 | * | |
7 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | ||
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | ||
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
b6a0aa05 | 23 | #include "qemu/osdep.h" |
da34e65c | 24 | #include "qapi/error.h" |
15280c36 | 25 | #include "qapi/qmp/qnum.h" |
72c194f7 | 26 | #include "acpi-build.h" |
eb66ffab | 27 | #include "acpi-common.h" |
72c194f7 | 28 | #include "qemu/bitmap.h" |
07fb6176 | 29 | #include "qemu/error-report.h" |
674b0a57 | 30 | #include "hw/pci/pci_bridge.h" |
6e4e3ae9 | 31 | #include "hw/cxl/cxl.h" |
2e5b09fd | 32 | #include "hw/core/cpu.h" |
fcf5ef2a | 33 | #include "target/i386/cpu.h" |
72c194f7 | 34 | #include "hw/timer/hpet.h" |
395e5fb4 | 35 | #include "hw/acpi/acpi-defs.h" |
72c194f7 | 36 | #include "hw/acpi/acpi.h" |
679dd1a9 | 37 | #include "hw/acpi/cpu.h" |
72c194f7 | 38 | #include "hw/nvram/fw_cfg.h" |
0058ae1d | 39 | #include "hw/acpi/bios-linker-loader.h" |
5876d9b5 | 40 | #include "hw/acpi/acpi_aml_interface.h" |
5334bf57 | 41 | #include "hw/input/i8042.h" |
bef3492d | 42 | #include "hw/acpi/memory_hotplug.h" |
711b20b4 SB |
43 | #include "sysemu/tpm.h" |
44 | #include "hw/acpi/tpm.h" | |
d03637bc | 45 | #include "hw/acpi/vmgenid.h" |
8486f12f | 46 | #include "hw/acpi/erst.h" |
2bfd0845 | 47 | #include "hw/acpi/piix4.h" |
5cb18b3d | 48 | #include "sysemu/tpm_backend.h" |
bcdb9064 | 49 | #include "hw/rtc/mc146818rtc_regs.h" |
d6454270 | 50 | #include "migration/vmstate.h" |
2cc0e2e8 | 51 | #include "hw/mem/memory-device.h" |
4b997690 | 52 | #include "hw/mem/nvdimm.h" |
1f3aba37 | 53 | #include "sysemu/numa.h" |
71e8a915 | 54 | #include "sysemu/reset.h" |
6775d15d | 55 | #include "hw/hyperv/vmbus-bridge.h" |
72c194f7 MT |
56 | |
57 | /* Supported chipsets: */ | |
1a6981bb | 58 | #include "hw/southbridge/ich9.h" |
fff123b8 | 59 | #include "hw/southbridge/piix.h" |
99fd437d | 60 | #include "hw/acpi/pcihp.h" |
89a289c7 | 61 | #include "hw/i386/fw_cfg.h" |
71671814 | 62 | #include "hw/i386/pc.h" |
72c194f7 | 63 | #include "hw/pci/pci_bus.h" |
b496a17d | 64 | #include "hw/pci-host/i440fx.h" |
72c194f7 | 65 | #include "hw/pci-host/q35.h" |
1cf5fd57 | 66 | #include "hw/i386/x86-iommu.h" |
72c194f7 | 67 | |
19934e0e | 68 | #include "hw/acpi/aml-build.h" |
82f76c67 | 69 | #include "hw/acpi/utils.h" |
48cefd94 | 70 | #include "hw/acpi/pci.h" |
2a3282c6 | 71 | #include "hw/acpi/cxl.h" |
19934e0e | 72 | |
72c194f7 | 73 | #include "qom/qom-qobject.h" |
fb9f5926 DK |
74 | #include "hw/i386/amd_iommu.h" |
75 | #include "hw/i386/intel_iommu.h" | |
36efa250 | 76 | #include "hw/virtio/virtio-iommu.h" |
72c194f7 | 77 | |
e6f123c3 | 78 | #include "hw/acpi/hmat.h" |
36efa250 | 79 | #include "hw/acpi/viot.h" |
86e91dd7 | 80 | |
8486f12f ED |
81 | #include CONFIG_DEVICES |
82 | ||
07fb6176 PB |
83 | /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and |
84 | * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows | |
85 | * a little bit, there should be plenty of free space since the DSDT | |
86 | * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. | |
87 | */ | |
88 | #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 | |
89 | #define ACPI_BUILD_ALIGN_SIZE 0x1000 | |
90 | ||
868270f2 | 91 | #define ACPI_BUILD_TABLE_SIZE 0x20000 |
18045fb9 | 92 | |
8b310fc4 GA |
93 | /* #define DEBUG_ACPI_BUILD */ |
94 | #ifdef DEBUG_ACPI_BUILD | |
95 | #define ACPI_BUILD_DPRINTF(fmt, ...) \ | |
96 | do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) | |
97 | #else | |
98 | #define ACPI_BUILD_DPRINTF(fmt, ...) | |
99 | #endif | |
100 | ||
72c194f7 MT |
101 | typedef struct AcpiPmInfo { |
102 | bool s3_disabled; | |
103 | bool s4_disabled; | |
133a2da4 | 104 | bool pcihp_bridge_en; |
6d837f1f | 105 | bool smi_on_cpuhp; |
892aae74 | 106 | bool smi_on_cpu_unplug; |
df4008c9 | 107 | bool pcihp_root_en; |
72c194f7 | 108 | uint8_t s4_val; |
937d1b58 | 109 | AcpiFadtData fadt; |
ddf1ec2f | 110 | uint16_t cpu_hp_io_base; |
500b11ea IM |
111 | uint16_t pcihp_io_base; |
112 | uint16_t pcihp_io_len; | |
72c194f7 MT |
113 | } AcpiPmInfo; |
114 | ||
115 | typedef struct AcpiMiscInfo { | |
116 | bool has_hpet; | |
11fb99e6 | 117 | #ifdef CONFIG_TPM |
5cb18b3d | 118 | TPMVersion tpm_version; |
11fb99e6 | 119 | #endif |
72c194f7 MT |
120 | } AcpiMiscInfo; |
121 | ||
0fe24669 SB |
122 | typedef struct FwCfgTPMConfig { |
123 | uint32_t tpmppi_address; | |
124 | uint8_t tpm_version; | |
125 | uint8_t tpmppi_version; | |
126 | } QEMU_PACKED FwCfgTPMConfig; | |
127 | ||
4a441836 GH |
128 | static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); |
129 | ||
5c94b826 KL |
130 | const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { |
131 | .space_id = AML_AS_SYSTEM_IO, | |
132 | .address = NVDIMM_ACPI_IO_BASE, | |
133 | .bit_width = NVDIMM_ACPI_IO_LEN << 3 | |
134 | }; | |
135 | ||
0e11fc69 LX |
136 | static void init_common_fadt_data(MachineState *ms, Object *o, |
137 | AcpiFadtData *data) | |
937d1b58 | 138 | { |
33b44fda IY |
139 | X86MachineState *x86ms = X86_MACHINE(ms); |
140 | /* | |
141 | * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old | |
142 | * behavior for compatibility irrelevant to smm_enabled, which doesn't | |
143 | * comforms to ACPI spec. | |
144 | */ | |
145 | bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? | |
146 | true : x86_machine_is_smm_enabled(x86ms); | |
937d1b58 IM |
147 | uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); |
148 | AmlAddressSpace as = AML_AS_SYSTEM_IO; | |
149 | AcpiFadtData fadt = { | |
150 | .rev = 3, | |
151 | .flags = | |
152 | (1 << ACPI_FADT_F_WBINVD) | | |
153 | (1 << ACPI_FADT_F_PROC_C1) | | |
154 | (1 << ACPI_FADT_F_SLP_BUTTON) | | |
155 | (1 << ACPI_FADT_F_RTC_S4) | | |
156 | (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | | |
157 | /* APIC destination mode ("Flat Logical") has an upper limit of 8 | |
158 | * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be | |
159 | * used | |
160 | */ | |
0e11fc69 LX |
161 | ((ms->smp.max_cpus > 8) ? |
162 | (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), | |
937d1b58 IM |
163 | .int_model = 1 /* Multiple APIC */, |
164 | .rtc_century = RTC_CENTURY, | |
165 | .plvl2_lat = 0xfff /* C2 state not supported */, | |
166 | .plvl3_lat = 0xfff /* C3 state not supported */, | |
33b44fda | 167 | .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, |
937d1b58 IM |
168 | .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), |
169 | .acpi_enable_cmd = | |
33b44fda IY |
170 | smm_enabled ? |
171 | object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : | |
172 | 0, | |
937d1b58 | 173 | .acpi_disable_cmd = |
33b44fda IY |
174 | smm_enabled ? |
175 | object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : | |
176 | 0, | |
937d1b58 IM |
177 | .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, |
178 | .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, | |
179 | .address = io + 0x04 }, | |
180 | .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, | |
181 | .gpe0_blk = { .space_id = as, .bit_width = | |
182 | object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, | |
183 | .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) | |
184 | }, | |
185 | }; | |
5334bf57 LA |
186 | |
187 | /* | |
188 | * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture | |
189 | * Flags, bit offset 1 - 8042. | |
190 | */ | |
191 | fadt.iapc_boot_arch = iapc_boot_arch_8042(); | |
192 | ||
937d1b58 IM |
193 | *data = fadt; |
194 | } | |
195 | ||
81c48dd7 PMD |
196 | static Object *object_resolve_type_unambiguous(const char *typename) |
197 | { | |
198 | bool ambig; | |
199 | Object *o = object_resolve_path_type("", typename, &ambig); | |
200 | ||
201 | if (ambig || !o) { | |
202 | return NULL; | |
203 | } | |
204 | return o; | |
205 | } | |
206 | ||
0e11fc69 | 207 | static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) |
72c194f7 | 208 | { |
81c48dd7 PMD |
209 | Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); |
210 | Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); | |
697155cd | 211 | Object *obj = piix ? piix : lpc; |
72c194f7 | 212 | QObject *o; |
94aaca64 | 213 | pm->cpu_hp_io_base = 0; |
500b11ea IM |
214 | pm->pcihp_io_base = 0; |
215 | pm->pcihp_io_len = 0; | |
6d837f1f | 216 | pm->smi_on_cpuhp = false; |
892aae74 | 217 | pm->smi_on_cpu_unplug = false; |
937d1b58 | 218 | |
6fa5171f | 219 | assert(obj); |
a0628599 | 220 | init_common_fadt_data(machine, obj, &pm->fadt); |
72c194f7 | 221 | if (piix) { |
3a3fcc75 | 222 | /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ |
937d1b58 | 223 | pm->fadt.rev = 1; |
ddf1ec2f | 224 | pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; |
72c194f7 MT |
225 | } |
226 | if (lpc) { | |
6d837f1f IM |
227 | uint64_t smi_features = object_property_get_uint(lpc, |
228 | ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); | |
937d1b58 IM |
229 | struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, |
230 | .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; | |
231 | pm->fadt.reset_reg = r; | |
232 | pm->fadt.reset_val = 0xf; | |
233 | pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; | |
ddf1ec2f | 234 | pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; |
6d837f1f IM |
235 | pm->smi_on_cpuhp = |
236 | !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); | |
892aae74 IM |
237 | pm->smi_on_cpu_unplug = |
238 | !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); | |
72c194f7 | 239 | } |
caf108bc JS |
240 | pm->pcihp_io_base = |
241 | object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); | |
242 | pm->pcihp_io_len = | |
243 | object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); | |
72c194f7 | 244 | |
937d1b58 IM |
245 | /* The above need not be conditional on machine type because the reset port |
246 | * happens to be the same on PIIX (pc) and ICH9 (q35). */ | |
0063454a | 247 | QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); |
937d1b58 | 248 | |
72c194f7 MT |
249 | /* Fill in optional s3/s4 related properties */ |
250 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); | |
251 | if (o) { | |
7dc847eb | 252 | pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); |
72c194f7 MT |
253 | } else { |
254 | pm->s3_disabled = false; | |
255 | } | |
cb3e7f08 | 256 | qobject_unref(o); |
72c194f7 MT |
257 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); |
258 | if (o) { | |
7dc847eb | 259 | pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); |
72c194f7 MT |
260 | } else { |
261 | pm->s4_disabled = false; | |
262 | } | |
cb3e7f08 | 263 | qobject_unref(o); |
72c194f7 MT |
264 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); |
265 | if (o) { | |
7dc847eb | 266 | pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); |
72c194f7 MT |
267 | } else { |
268 | pm->s4_val = false; | |
269 | } | |
cb3e7f08 | 270 | qobject_unref(o); |
72c194f7 | 271 | |
133a2da4 | 272 | pm->pcihp_bridge_en = |
aa29466b | 273 | object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, |
133a2da4 | 274 | NULL); |
df4008c9 | 275 | pm->pcihp_root_en = |
aa29466b | 276 | object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, |
df4008c9 | 277 | NULL); |
72c194f7 MT |
278 | } |
279 | ||
72c194f7 MT |
280 | static void acpi_get_misc_info(AcpiMiscInfo *info) |
281 | { | |
282 | info->has_hpet = hpet_find(); | |
11fb99e6 | 283 | #ifdef CONFIG_TPM |
3dfd5a2a | 284 | info->tpm_version = tpm_get_version(tpm_find()); |
11fb99e6 | 285 | #endif |
72c194f7 MT |
286 | } |
287 | ||
ca6c1855 MA |
288 | /* |
289 | * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. | |
290 | * On i386 arch we only have two pci hosts, so we can look only for them. | |
291 | */ | |
c0e427d6 | 292 | Object *acpi_get_i386_pci_host(void) |
ca6c1855 MA |
293 | { |
294 | PCIHostState *host; | |
295 | ||
b914e741 | 296 | host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); |
ca6c1855 | 297 | if (!host) { |
b914e741 | 298 | host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); |
ca6c1855 MA |
299 | } |
300 | ||
301 | return OBJECT(host); | |
302 | } | |
303 | ||
01c9742d | 304 | static void acpi_get_pci_holes(Range *hole, Range *hole64) |
72c194f7 MT |
305 | { |
306 | Object *pci_host; | |
72c194f7 | 307 | |
ca6c1855 | 308 | pci_host = acpi_get_i386_pci_host(); |
c0e427d6 JS |
309 | |
310 | if (!pci_host) { | |
311 | return; | |
312 | } | |
72c194f7 | 313 | |
a0efbf16 | 314 | range_set_bounds1(hole, |
60555365 MAL |
315 | object_property_get_uint(pci_host, |
316 | PCI_HOST_PROP_PCI_HOLE_START, | |
317 | NULL), | |
318 | object_property_get_uint(pci_host, | |
319 | PCI_HOST_PROP_PCI_HOLE_END, | |
320 | NULL)); | |
a0efbf16 | 321 | range_set_bounds1(hole64, |
60555365 MAL |
322 | object_property_get_uint(pci_host, |
323 | PCI_HOST_PROP_PCI_HOLE64_START, | |
324 | NULL), | |
325 | object_property_get_uint(pci_host, | |
326 | PCI_HOST_PROP_PCI_HOLE64_END, | |
327 | NULL)); | |
72c194f7 MT |
328 | } |
329 | ||
72c194f7 MT |
330 | static void acpi_align_size(GArray *blob, unsigned align) |
331 | { | |
332 | /* Align size to multiple of given size. This reduces the chance | |
333 | * we need to change size in the future (breaking cross version migration). | |
334 | */ | |
134d42d6 | 335 | g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); |
72c194f7 MT |
336 | } |
337 | ||
cf68410b IM |
338 | /* |
339 | * ACPI spec 1.0b, | |
340 | * 5.2.6 Firmware ACPI Control Structure | |
341 | */ | |
72c194f7 | 342 | static void |
009180bd | 343 | build_facs(GArray *table_data) |
72c194f7 | 344 | { |
cf68410b IM |
345 | const char *sig = "FACS"; |
346 | const uint8_t reserved[40] = {}; | |
347 | ||
348 | g_array_append_vals(table_data, sig, 4); /* Signature */ | |
349 | build_append_int_noprefix(table_data, 64, 4); /* Length */ | |
350 | build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ | |
351 | build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ | |
352 | build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ | |
353 | build_append_int_noprefix(table_data, 0, 4); /* Flags */ | |
354 | g_array_append_vals(table_data, reserved, 40); /* Reserved */ | |
72c194f7 MT |
355 | } |
356 | ||
5840a163 IM |
357 | Aml *aml_pci_device_dsm(void) |
358 | { | |
359 | Aml *method; | |
360 | ||
361 | method = aml_method("_DSM", 4, AML_SERIALIZED); | |
362 | { | |
363 | Aml *params = aml_local(0); | |
364 | Aml *pkg = aml_package(2); | |
365 | aml_append(pkg, aml_name("BSEL")); | |
366 | aml_append(pkg, aml_name("ASUN")); | |
367 | aml_append(method, aml_store(pkg, params)); | |
368 | aml_append(method, | |
369 | aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), | |
370 | aml_arg(2), aml_arg(3), params)) | |
371 | ); | |
372 | } | |
373 | return method; | |
374 | } | |
375 | ||
62b52c26 | 376 | static void build_append_pcihp_notify_entry(Aml *method, int slot) |
99fd437d | 377 | { |
62b52c26 IM |
378 | Aml *if_ctx; |
379 | int32_t devfn = PCI_DEVFN(slot, 0); | |
380 | ||
5530427f | 381 | if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); |
62b52c26 IM |
382 | aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); |
383 | aml_append(method, if_ctx); | |
99fd437d MT |
384 | } |
385 | ||
6fe5518e | 386 | static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus) |
a06c15a3 IM |
387 | { |
388 | const PCIDevice *pdev = bus->devices[devfn]; | |
389 | ||
6fe5518e IM |
390 | if (PCI_FUNC(devfn)) { |
391 | if (IS_PCI_BRIDGE(pdev)) { | |
392 | /* | |
393 | * Ignore only hotplugged PCI bridges on !0 functions, but | |
394 | * allow describing cold plugged bridges on all functions | |
395 | */ | |
396 | if (DEVICE(pdev)->hotplugged) { | |
a06c15a3 IM |
397 | return true; |
398 | } | |
6fe5518e IM |
399 | } else if (!get_dev_aml_func(DEVICE(pdev))) { |
400 | /* | |
401 | * Ignore all other devices on !0 functions unless they | |
402 | * have AML description (i.e have get_dev_aml_func() != 0) | |
403 | */ | |
404 | return true; | |
a06c15a3 | 405 | } |
6fe5518e IM |
406 | } |
407 | return false; | |
408 | } | |
409 | ||
410 | static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus) | |
411 | { | |
64a55106 IM |
412 | PCIDevice *pdev = bus->devices[devfn]; |
413 | if (pdev) { | |
414 | return is_devfn_ignored_generic(devfn, bus) || | |
17f4cedb | 415 | !DEVICE_GET_CLASS(pdev)->hotpluggable || |
64a55106 IM |
416 | /* Cold plugged bridges aren't themselves hot-pluggable */ |
417 | (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged); | |
a06c15a3 | 418 | } else { /* non populated slots */ |
6fe5518e | 419 | /* |
a06c15a3 IM |
420 | * hotplug is supported only for non-multifunction device |
421 | * so generate device description only for function 0 | |
422 | */ | |
6fe5518e | 423 | if (PCI_FUNC(devfn) || |
a06c15a3 IM |
424 | (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) { |
425 | return true; | |
426 | } | |
427 | } | |
428 | return false; | |
429 | } | |
430 | ||
6fe5518e IM |
431 | static void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus, |
432 | QObject *bsel) | |
99fd437d | 433 | { |
d7346e61 | 434 | int devfn; |
6fe5518e IM |
435 | Aml *dev, *notify_method = NULL, *method; |
436 | uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); | |
133a2da4 | 437 | |
6fe5518e IM |
438 | aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); |
439 | notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); | |
99fd437d | 440 | |
d7346e61 | 441 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
d7346e61 | 442 | int slot = PCI_SLOT(devfn); |
6fe5518e | 443 | int adr = slot << 16 | PCI_FUNC(devfn); |
99fd437d | 444 | |
6fe5518e | 445 | if (is_devfn_ignored_hotplug(devfn, bus)) { |
a06c15a3 IM |
446 | continue; |
447 | } | |
3216ab2a | 448 | |
17f4cedb | 449 | if (bus->devices[devfn]) { |
6fe5518e IM |
450 | dev = aml_scope("S%.02X", devfn); |
451 | } else { | |
452 | dev = aml_device("S%.02X", devfn); | |
453 | aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); | |
d7346e61 IM |
454 | } |
455 | ||
6fe5518e IM |
456 | /* |
457 | * Can't declare _SUN here for every device as it changes 'slot' | |
458 | * enumeration order in linux kernel, so use another variable for it | |
459 | */ | |
460 | aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); | |
461 | aml_append(dev, aml_pci_device_dsm()); | |
62b52c26 | 462 | |
17f4cedb IM |
463 | aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); |
464 | /* add _EJ0 to make slot hotpluggable */ | |
465 | method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); | |
466 | aml_append(method, | |
467 | aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) | |
468 | ); | |
469 | aml_append(dev, method); | |
3216ab2a | 470 | |
17f4cedb | 471 | build_append_pcihp_notify_entry(notify_method, slot); |
3216ab2a | 472 | |
d7346e61 | 473 | /* device descriptor has been composed, add it into parent context */ |
62b52c26 | 474 | aml_append(parent_scope, dev); |
8dcf525a | 475 | } |
6fe5518e IM |
476 | aml_append(parent_scope, notify_method); |
477 | } | |
478 | ||
479 | void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus) | |
480 | { | |
481 | QObject *bsel; | |
482 | int devfn; | |
483 | Aml *dev; | |
484 | ||
485 | bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); | |
486 | ||
487 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { | |
488 | /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ | |
489 | int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn); | |
17f4cedb | 490 | PCIDevice *pdev = bus->devices[devfn]; |
6fe5518e | 491 | |
17f4cedb | 492 | if (!pdev || is_devfn_ignored_generic(devfn, bus)) { |
6fe5518e IM |
493 | continue; |
494 | } | |
495 | ||
496 | /* start to compose PCI device descriptor */ | |
497 | dev = aml_device("S%.02X", devfn); | |
498 | aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); | |
499 | ||
500 | call_dev_aml_func(DEVICE(bus->devices[devfn]), dev); | |
501 | ||
502 | /* device descriptor has been composed, add it into parent context */ | |
503 | aml_append(parent_scope, dev); | |
504 | } | |
8dcf525a MT |
505 | |
506 | if (bsel) { | |
6fe5518e | 507 | build_append_pcihp_slots(parent_scope, bus, bsel); |
99fd437d MT |
508 | } |
509 | ||
ddab4d3f IM |
510 | qobject_unref(bsel); |
511 | } | |
512 | ||
219e638f | 513 | static bool build_append_notfication_callback(Aml *parent_scope, |
ddab4d3f IM |
514 | const PCIBus *bus) |
515 | { | |
516 | Aml *method; | |
517 | PCIBus *sec; | |
518 | QObject *bsel; | |
219e638f | 519 | int nr_notifiers = 0; |
ddab4d3f IM |
520 | |
521 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
522 | Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn); | |
523 | if (pci_bus_is_root(sec) || | |
524 | !object_property_find(OBJECT(sec), ACPI_PCIHP_PROP_BSEL)) { | |
525 | continue; | |
526 | } | |
219e638f IM |
527 | nr_notifiers = nr_notifiers + |
528 | build_append_notfication_callback(br_scope, sec); | |
ddab4d3f IM |
529 | aml_append(parent_scope, br_scope); |
530 | } | |
531 | ||
19f5052c IM |
532 | /* |
533 | * Append PCNT method to notify about events on local and child buses. | |
ddab4d3f IM |
534 | * ps: hostbridge might not have hotplug (bsel) enabled but might have |
535 | * child bridges that do have bsel. | |
72c194f7 | 536 | */ |
19f5052c | 537 | method = aml_method("PCNT", 0, AML_NOTSERIALIZED); |
811c74fb | 538 | |
19f5052c | 539 | /* If bus supports hotplug select it and notify about local events */ |
ddab4d3f | 540 | bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); |
19f5052c IM |
541 | if (bsel) { |
542 | uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); | |
99fd437d | 543 | |
19f5052c IM |
544 | aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); |
545 | aml_append(method, aml_call2("DVNT", aml_name("PCIU"), | |
546 | aml_int(1))); /* Device Check */ | |
547 | aml_append(method, aml_call2("DVNT", aml_name("PCID"), | |
548 | aml_int(3))); /* Eject Request */ | |
219e638f | 549 | nr_notifiers++; |
19f5052c | 550 | } |
c99cb18e | 551 | |
19f5052c IM |
552 | /* Notify about child bus events in any case */ |
553 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
554 | if (pci_bus_is_root(sec) || | |
555 | !object_property_find(OBJECT(sec), ACPI_PCIHP_PROP_BSEL)) { | |
556 | continue; | |
99fd437d | 557 | } |
df4008c9 | 558 | |
19f5052c | 559 | aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn)); |
df4008c9 | 560 | } |
19f5052c IM |
561 | |
562 | aml_append(parent_scope, method); | |
cb3e7f08 | 563 | qobject_unref(bsel); |
219e638f | 564 | return !!nr_notifiers; |
72c194f7 MT |
565 | } |
566 | ||
5840a163 | 567 | static Aml *aml_pci_pdsm(void) |
b7f23f62 | 568 | { |
a12cf692 IM |
569 | Aml *method, *UUID, *ifctx, *ifctx1; |
570 | Aml *ret = aml_local(0); | |
571 | Aml *caps = aml_local(1); | |
572 | Aml *acpi_index = aml_local(2); | |
b7f23f62 | 573 | Aml *zero = aml_int(0); |
a12cf692 | 574 | Aml *one = aml_int(1); |
b7f23f62 IM |
575 | Aml *func = aml_arg(2); |
576 | Aml *rev = aml_arg(1); | |
467d099a IM |
577 | Aml *params = aml_arg(4); |
578 | Aml *bnum = aml_derefof(aml_index(params, aml_int(0))); | |
579 | Aml *sunum = aml_derefof(aml_index(params, aml_int(1))); | |
b7f23f62 | 580 | |
467d099a | 581 | method = aml_method("PDSM", 5, AML_SERIALIZED); |
b7f23f62 | 582 | |
a12cf692 IM |
583 | /* get supported functions */ |
584 | ifctx = aml_if(aml_equal(func, zero)); | |
585 | { | |
586 | uint8_t byte_list[1] = { 0 }; /* nothing supported yet */ | |
587 | aml_append(ifctx, aml_store(aml_buffer(1, byte_list), ret)); | |
588 | aml_append(ifctx, aml_store(zero, caps)); | |
589 | ||
590 | /* | |
591 | * PCI Firmware Specification 3.1 | |
592 | * 4.6. _DSM Definitions for PCI | |
593 | */ | |
594 | UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); | |
595 | ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); | |
596 | { | |
597 | /* call is for unsupported UUID, bail out */ | |
598 | aml_append(ifctx1, aml_return(ret)); | |
599 | } | |
600 | aml_append(ifctx, ifctx1); | |
601 | ||
602 | ifctx1 = aml_if(aml_lless(rev, aml_int(2))); | |
603 | { | |
604 | /* call is for unsupported REV, bail out */ | |
605 | aml_append(ifctx1, aml_return(ret)); | |
606 | } | |
607 | aml_append(ifctx, ifctx1); | |
608 | ||
609 | aml_append(ifctx, | |
610 | aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); | |
611 | /* | |
612 | * advertise function 7 if device has acpi-index | |
613 | * acpi_index values: | |
614 | * 0: not present (default value) | |
615 | * FFFFFFFF: not supported (old QEMU without PIDX reg) | |
616 | * other: device's acpi-index | |
617 | */ | |
618 | ifctx1 = aml_if(aml_lnot( | |
619 | aml_or(aml_equal(acpi_index, zero), | |
620 | aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) | |
621 | )); | |
622 | { | |
623 | /* have supported functions */ | |
624 | aml_append(ifctx1, aml_or(caps, one, caps)); | |
625 | /* support for function 7 */ | |
626 | aml_append(ifctx1, | |
627 | aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); | |
628 | } | |
629 | aml_append(ifctx, ifctx1); | |
630 | ||
631 | aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); | |
632 | aml_append(ifctx, aml_return(ret)); | |
633 | } | |
634 | aml_append(method, ifctx); | |
635 | ||
636 | /* handle specific functions requests */ | |
b7f23f62 IM |
637 | /* |
638 | * PCI Firmware Specification 3.1 | |
a12cf692 IM |
639 | * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under |
640 | * Operating Systems | |
b7f23f62 | 641 | */ |
a12cf692 | 642 | ifctx = aml_if(aml_equal(func, aml_int(7))); |
b7f23f62 | 643 | { |
a12cf692 IM |
644 | Aml *pkg = aml_package(2); |
645 | ||
646 | aml_append(pkg, zero); | |
647 | /* | |
648 | * optional, if not impl. should return null string | |
649 | */ | |
650 | aml_append(pkg, aml_string("%s", "")); | |
651 | aml_append(ifctx, aml_store(pkg, ret)); | |
652 | ||
653 | aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); | |
654 | /* | |
655 | * update acpi-index to actual value | |
656 | */ | |
657 | aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero))); | |
467d099a | 658 | aml_append(ifctx, aml_return(ret)); |
b7f23f62 | 659 | } |
a12cf692 | 660 | |
b7f23f62 IM |
661 | aml_append(method, ifctx); |
662 | return method; | |
663 | } | |
664 | ||
196e2137 IM |
665 | /** |
666 | * build_prt_entry: | |
667 | * @link_name: link name for PCI route entry | |
668 | * | |
669 | * build AML package containing a PCI route entry for @link_name | |
670 | */ | |
671 | static Aml *build_prt_entry(const char *link_name) | |
672 | { | |
673 | Aml *a_zero = aml_int(0); | |
674 | Aml *pkg = aml_package(4); | |
675 | aml_append(pkg, a_zero); | |
676 | aml_append(pkg, a_zero); | |
677 | aml_append(pkg, aml_name("%s", link_name)); | |
678 | aml_append(pkg, a_zero); | |
679 | return pkg; | |
680 | } | |
681 | ||
0d8935e3 MA |
682 | /* |
683 | * initialize_route - Initialize the interrupt routing rule | |
684 | * through a specific LINK: | |
685 | * if (lnk_idx == idx) | |
686 | * route using link 'link_name' | |
687 | */ | |
688 | static Aml *initialize_route(Aml *route, const char *link_name, | |
689 | Aml *lnk_idx, int idx) | |
690 | { | |
691 | Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); | |
196e2137 | 692 | Aml *pkg = build_prt_entry(link_name); |
0d8935e3 | 693 | |
0d8935e3 MA |
694 | aml_append(if_ctx, aml_store(pkg, route)); |
695 | ||
696 | return if_ctx; | |
697 | } | |
698 | ||
699 | /* | |
700 | * build_prt - Define interrupt rounting rules | |
701 | * | |
702 | * Returns an array of 128 routes, one for each device, | |
703 | * based on device location. | |
704 | * The main goal is to equaly distribute the interrupts | |
705 | * over the 4 existing ACPI links (works only for i440fx). | |
706 | * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". | |
707 | * | |
708 | */ | |
196e2137 | 709 | static Aml *build_prt(bool is_pci0_prt) |
0d8935e3 MA |
710 | { |
711 | Aml *method, *while_ctx, *pin, *res; | |
712 | ||
4dbfc881 | 713 | method = aml_method("_PRT", 0, AML_NOTSERIALIZED); |
0d8935e3 MA |
714 | res = aml_local(0); |
715 | pin = aml_local(1); | |
716 | aml_append(method, aml_store(aml_package(128), res)); | |
717 | aml_append(method, aml_store(aml_int(0), pin)); | |
718 | ||
719 | /* while (pin < 128) */ | |
720 | while_ctx = aml_while(aml_lless(pin, aml_int(128))); | |
721 | { | |
722 | Aml *slot = aml_local(2); | |
723 | Aml *lnk_idx = aml_local(3); | |
724 | Aml *route = aml_local(4); | |
725 | ||
726 | /* slot = pin >> 2 */ | |
727 | aml_append(while_ctx, | |
c360639a | 728 | aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); |
0d8935e3 MA |
729 | /* lnk_idx = (slot + pin) & 3 */ |
730 | aml_append(while_ctx, | |
5530427f IM |
731 | aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), |
732 | lnk_idx)); | |
0d8935e3 MA |
733 | |
734 | /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ | |
735 | aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); | |
196e2137 IM |
736 | if (is_pci0_prt) { |
737 | Aml *if_device_1, *if_pin_4, *else_pin_4; | |
738 | ||
739 | /* device 1 is the power-management device, needs SCI */ | |
740 | if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); | |
741 | { | |
742 | if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); | |
743 | { | |
744 | aml_append(if_pin_4, | |
745 | aml_store(build_prt_entry("LNKS"), route)); | |
746 | } | |
747 | aml_append(if_device_1, if_pin_4); | |
748 | else_pin_4 = aml_else(); | |
749 | { | |
750 | aml_append(else_pin_4, | |
751 | aml_store(build_prt_entry("LNKA"), route)); | |
752 | } | |
753 | aml_append(if_device_1, else_pin_4); | |
754 | } | |
755 | aml_append(while_ctx, if_device_1); | |
756 | } else { | |
757 | aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); | |
758 | } | |
0d8935e3 MA |
759 | aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); |
760 | aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); | |
761 | ||
762 | /* route[0] = 0x[slot]FFFF */ | |
763 | aml_append(while_ctx, | |
ca3df95d IM |
764 | aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), |
765 | NULL), | |
0d8935e3 MA |
766 | aml_index(route, aml_int(0)))); |
767 | /* route[1] = pin & 3 */ | |
768 | aml_append(while_ctx, | |
5530427f IM |
769 | aml_store(aml_and(pin, aml_int(3), NULL), |
770 | aml_index(route, aml_int(1)))); | |
0d8935e3 MA |
771 | /* res[pin] = route */ |
772 | aml_append(while_ctx, aml_store(route, aml_index(res, pin))); | |
773 | /* pin++ */ | |
774 | aml_append(while_ctx, aml_increment(pin)); | |
775 | } | |
776 | aml_append(method, while_ctx); | |
777 | /* return res*/ | |
778 | aml_append(method, aml_return(res)); | |
779 | ||
780 | return method; | |
781 | } | |
782 | ||
a57d708d IM |
783 | static void build_hpet_aml(Aml *table) |
784 | { | |
785 | Aml *crs; | |
786 | Aml *field; | |
787 | Aml *method; | |
788 | Aml *if_ctx; | |
789 | Aml *scope = aml_scope("_SB"); | |
790 | Aml *dev = aml_device("HPET"); | |
791 | Aml *zero = aml_int(0); | |
792 | Aml *id = aml_local(0); | |
793 | Aml *period = aml_local(1); | |
794 | ||
795 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); | |
796 | aml_append(dev, aml_name_decl("_UID", zero)); | |
797 | ||
798 | aml_append(dev, | |
3f3009c0 XG |
799 | aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), |
800 | HPET_LEN)); | |
a57d708d IM |
801 | field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); |
802 | aml_append(field, aml_named_field("VEND", 32)); | |
803 | aml_append(field, aml_named_field("PRD", 32)); | |
804 | aml_append(dev, field); | |
805 | ||
806 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
807 | aml_append(method, aml_store(aml_name("VEND"), id)); | |
808 | aml_append(method, aml_store(aml_name("PRD"), period)); | |
809 | aml_append(method, aml_shiftright(id, aml_int(16), id)); | |
810 | if_ctx = aml_if(aml_lor(aml_equal(id, zero), | |
811 | aml_equal(id, aml_int(0xffff)))); | |
812 | { | |
813 | aml_append(if_ctx, aml_return(zero)); | |
814 | } | |
815 | aml_append(method, if_ctx); | |
816 | ||
817 | if_ctx = aml_if(aml_lor(aml_equal(period, zero), | |
818 | aml_lgreater(period, aml_int(100000000)))); | |
819 | { | |
820 | aml_append(if_ctx, aml_return(zero)); | |
821 | } | |
822 | aml_append(method, if_ctx); | |
823 | ||
824 | aml_append(method, aml_return(aml_int(0x0F))); | |
825 | aml_append(dev, method); | |
826 | ||
827 | crs = aml_resource_template(); | |
828 | aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); | |
829 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
830 | ||
831 | aml_append(scope, dev); | |
832 | aml_append(table, scope); | |
833 | } | |
834 | ||
6775d15d JD |
835 | static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) |
836 | { | |
837 | Aml *dev; | |
838 | Aml *method; | |
839 | Aml *crs; | |
840 | ||
841 | dev = aml_device("VMBS"); | |
842 | aml_append(dev, aml_name_decl("STA", aml_int(0xF))); | |
843 | aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); | |
844 | aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); | |
845 | aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); | |
846 | ||
847 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
848 | aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), | |
849 | aml_name("STA"))); | |
850 | aml_append(dev, method); | |
851 | ||
852 | method = aml_method("_PS0", 0, AML_NOTSERIALIZED); | |
853 | aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), | |
854 | aml_name("STA"))); | |
855 | aml_append(dev, method); | |
856 | ||
857 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
858 | aml_append(method, aml_return(aml_name("STA"))); | |
859 | aml_append(dev, method); | |
860 | ||
861 | aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); | |
862 | ||
863 | crs = aml_resource_template(); | |
8f06f22f | 864 | aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); |
6775d15d JD |
865 | aml_append(dev, aml_name_decl("_CRS", crs)); |
866 | ||
867 | return dev; | |
868 | } | |
869 | ||
3892a2b7 IM |
870 | static void build_dbg_aml(Aml *table) |
871 | { | |
872 | Aml *field; | |
873 | Aml *method; | |
874 | Aml *while_ctx; | |
875 | Aml *scope = aml_scope("\\"); | |
876 | Aml *buf = aml_local(0); | |
877 | Aml *len = aml_local(1); | |
878 | Aml *idx = aml_local(2); | |
879 | ||
880 | aml_append(scope, | |
3f3009c0 | 881 | aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); |
3892a2b7 IM |
882 | field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); |
883 | aml_append(field, aml_named_field("DBGB", 8)); | |
884 | aml_append(scope, field); | |
885 | ||
886 | method = aml_method("DBUG", 1, AML_NOTSERIALIZED); | |
887 | ||
888 | aml_append(method, aml_to_hexstring(aml_arg(0), buf)); | |
889 | aml_append(method, aml_to_buffer(buf, buf)); | |
890 | aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); | |
891 | aml_append(method, aml_store(aml_int(0), idx)); | |
892 | ||
893 | while_ctx = aml_while(aml_lless(idx, len)); | |
894 | aml_append(while_ctx, | |
895 | aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); | |
896 | aml_append(while_ctx, aml_increment(idx)); | |
897 | aml_append(method, while_ctx); | |
898 | ||
899 | aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); | |
900 | aml_append(scope, method); | |
901 | ||
902 | aml_append(table, scope); | |
903 | } | |
904 | ||
c35b6e80 IM |
905 | static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) |
906 | { | |
907 | Aml *dev; | |
908 | Aml *crs; | |
909 | Aml *method; | |
910 | uint32_t irqs[] = {5, 10, 11}; | |
911 | ||
912 | dev = aml_device("%s", name); | |
913 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); | |
914 | aml_append(dev, aml_name_decl("_UID", aml_int(uid))); | |
915 | ||
916 | crs = aml_resource_template(); | |
917 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
918 | AML_SHARED, irqs, ARRAY_SIZE(irqs))); | |
919 | aml_append(dev, aml_name_decl("_PRS", crs)); | |
920 | ||
921 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
922 | aml_append(method, aml_return(aml_call1("IQST", reg))); | |
923 | aml_append(dev, method); | |
924 | ||
925 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
926 | aml_append(method, aml_or(reg, aml_int(0x80), reg)); | |
927 | aml_append(dev, method); | |
928 | ||
929 | method = aml_method("_CRS", 0, AML_NOTSERIALIZED); | |
930 | aml_append(method, aml_return(aml_call1("IQCR", reg))); | |
931 | aml_append(dev, method); | |
932 | ||
933 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); | |
934 | aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); | |
935 | aml_append(method, aml_store(aml_name("PRRI"), reg)); | |
936 | aml_append(dev, method); | |
937 | ||
938 | return dev; | |
939 | } | |
940 | ||
80b32df5 IM |
941 | static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) |
942 | { | |
943 | Aml *dev; | |
944 | Aml *crs; | |
945 | Aml *method; | |
946 | uint32_t irqs; | |
947 | ||
948 | dev = aml_device("%s", name); | |
949 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); | |
950 | aml_append(dev, aml_name_decl("_UID", aml_int(uid))); | |
951 | ||
952 | crs = aml_resource_template(); | |
953 | irqs = gsi; | |
954 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
955 | AML_SHARED, &irqs, 1)); | |
956 | aml_append(dev, aml_name_decl("_PRS", crs)); | |
957 | ||
958 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
959 | ||
c82f503d MA |
960 | /* |
961 | * _DIS can be no-op because the interrupt cannot be disabled. | |
962 | */ | |
963 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
964 | aml_append(dev, method); | |
965 | ||
80b32df5 IM |
966 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); |
967 | aml_append(dev, method); | |
968 | ||
969 | return dev; | |
970 | } | |
971 | ||
16682a9d IM |
972 | /* _CRS method - get current settings */ |
973 | static Aml *build_iqcr_method(bool is_piix4) | |
974 | { | |
975 | Aml *if_ctx; | |
976 | uint32_t irqs; | |
977 | Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); | |
978 | Aml *crs = aml_resource_template(); | |
979 | ||
980 | irqs = 0; | |
981 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, | |
982 | AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); | |
983 | aml_append(method, aml_name_decl("PRR0", crs)); | |
984 | ||
985 | aml_append(method, | |
986 | aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); | |
987 | ||
988 | if (is_piix4) { | |
989 | if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); | |
990 | aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); | |
991 | aml_append(method, if_ctx); | |
992 | } else { | |
993 | aml_append(method, | |
994 | aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), | |
995 | aml_name("PRRI"))); | |
996 | } | |
997 | ||
998 | aml_append(method, aml_return(aml_name("PRR0"))); | |
999 | return method; | |
1000 | } | |
1001 | ||
78e1ad05 IM |
1002 | /* _STA method - get status */ |
1003 | static Aml *build_irq_status_method(void) | |
1004 | { | |
1005 | Aml *if_ctx; | |
1006 | Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); | |
1007 | ||
1008 | if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); | |
1009 | aml_append(if_ctx, aml_return(aml_int(0x09))); | |
1010 | aml_append(method, if_ctx); | |
1011 | aml_append(method, aml_return(aml_int(0x0B))); | |
1012 | return method; | |
1013 | } | |
1014 | ||
e4db2798 IM |
1015 | static void build_piix4_pci0_int(Aml *table) |
1016 | { | |
c35b6e80 IM |
1017 | Aml *dev; |
1018 | Aml *crs; | |
c35b6e80 IM |
1019 | Aml *method; |
1020 | uint32_t irqs; | |
e4db2798 | 1021 | Aml *sb_scope = aml_scope("_SB"); |
196e2137 IM |
1022 | Aml *pci0_scope = aml_scope("PCI0"); |
1023 | ||
1024 | aml_append(pci0_scope, build_prt(true)); | |
1025 | aml_append(sb_scope, pci0_scope); | |
e4db2798 | 1026 | |
78e1ad05 | 1027 | aml_append(sb_scope, build_irq_status_method()); |
16682a9d | 1028 | aml_append(sb_scope, build_iqcr_method(true)); |
100681cc | 1029 | |
c35b6e80 IM |
1030 | aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); |
1031 | aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); | |
1032 | aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); | |
1033 | aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); | |
1034 | ||
1035 | dev = aml_device("LNKS"); | |
1036 | { | |
1037 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); | |
1038 | aml_append(dev, aml_name_decl("_UID", aml_int(4))); | |
1039 | ||
1040 | crs = aml_resource_template(); | |
1041 | irqs = 9; | |
1042 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, | |
1043 | AML_ACTIVE_HIGH, AML_SHARED, | |
1044 | &irqs, 1)); | |
1045 | aml_append(dev, aml_name_decl("_PRS", crs)); | |
1046 | ||
1047 | /* The SCI cannot be disabled and is always attached to GSI 9, | |
1048 | * so these are no-ops. We only need this link to override the | |
1049 | * polarity to active high and match the content of the MADT. | |
1050 | */ | |
1051 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
1052 | aml_append(method, aml_return(aml_int(0x0b))); | |
1053 | aml_append(dev, method); | |
1054 | ||
1055 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
1056 | aml_append(dev, method); | |
1057 | ||
1058 | method = aml_method("_CRS", 0, AML_NOTSERIALIZED); | |
1059 | aml_append(method, aml_return(aml_name("_PRS"))); | |
1060 | aml_append(dev, method); | |
1061 | ||
1062 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); | |
1063 | aml_append(dev, method); | |
1064 | } | |
1065 | aml_append(sb_scope, dev); | |
1066 | ||
e4db2798 IM |
1067 | aml_append(table, sb_scope); |
1068 | } | |
1069 | ||
22b5b8bf IM |
1070 | static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) |
1071 | { | |
1072 | int i; | |
1073 | int head; | |
1074 | Aml *pkg; | |
1075 | char base = name[3] < 'E' ? 'A' : 'E'; | |
1076 | char *s = g_strdup(name); | |
1077 | Aml *a_nr = aml_int((nr << 16) | 0xffff); | |
1078 | ||
1079 | assert(strlen(s) == 4); | |
1080 | ||
1081 | head = name[3] - base; | |
1082 | for (i = 0; i < 4; i++) { | |
1083 | if (head + i > 3) { | |
1084 | head = i * -1; | |
1085 | } | |
1086 | s[3] = base + head + i; | |
1087 | pkg = aml_package(4); | |
1088 | aml_append(pkg, a_nr); | |
1089 | aml_append(pkg, aml_int(i)); | |
1090 | aml_append(pkg, aml_name("%s", s)); | |
1091 | aml_append(pkg, aml_int(0)); | |
1092 | aml_append(ctx, pkg); | |
1093 | } | |
1094 | g_free(s); | |
1095 | } | |
1096 | ||
1097 | static Aml *build_q35_routing_table(const char *str) | |
1098 | { | |
1099 | int i; | |
1100 | Aml *pkg; | |
1101 | char *name = g_strdup_printf("%s ", str); | |
1102 | ||
1103 | pkg = aml_package(128); | |
1104 | for (i = 0; i < 0x18; i++) { | |
1105 | name[3] = 'E' + (i & 0x3); | |
1106 | append_q35_prt_entry(pkg, i, name); | |
1107 | } | |
1108 | ||
1109 | name[3] = 'E'; | |
1110 | append_q35_prt_entry(pkg, 0x18, name); | |
1111 | ||
1112 | /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ | |
1113 | for (i = 0x0019; i < 0x1e; i++) { | |
1114 | name[3] = 'A'; | |
1115 | append_q35_prt_entry(pkg, i, name); | |
1116 | } | |
1117 | ||
1118 | /* PCIe->PCI bridge. use PIRQ[E-H] */ | |
1119 | name[3] = 'E'; | |
1120 | append_q35_prt_entry(pkg, 0x1e, name); | |
1121 | name[3] = 'A'; | |
1122 | append_q35_prt_entry(pkg, 0x1f, name); | |
1123 | ||
1124 | g_free(name); | |
1125 | return pkg; | |
1126 | } | |
1127 | ||
80b32df5 IM |
1128 | static void build_q35_pci0_int(Aml *table) |
1129 | { | |
0dafe3b3 | 1130 | Aml *method; |
80b32df5 | 1131 | Aml *sb_scope = aml_scope("_SB"); |
0dafe3b3 IM |
1132 | Aml *pci0_scope = aml_scope("PCI0"); |
1133 | ||
e9fce798 IM |
1134 | /* Zero => PIC mode, One => APIC Mode */ |
1135 | aml_append(table, aml_name_decl("PICF", aml_int(0))); | |
1136 | method = aml_method("_PIC", 1, AML_NOTSERIALIZED); | |
1137 | { | |
1138 | aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); | |
1139 | } | |
1140 | aml_append(table, method); | |
1141 | ||
65aef4de IM |
1142 | aml_append(pci0_scope, |
1143 | aml_name_decl("PRTP", build_q35_routing_table("LNK"))); | |
22b5b8bf IM |
1144 | aml_append(pci0_scope, |
1145 | aml_name_decl("PRTA", build_q35_routing_table("GSI"))); | |
1146 | ||
0dafe3b3 IM |
1147 | method = aml_method("_PRT", 0, AML_NOTSERIALIZED); |
1148 | { | |
1149 | Aml *if_ctx; | |
1150 | Aml *else_ctx; | |
1151 | ||
1152 | /* PCI IRQ routing table, example from ACPI 2.0a specification, | |
1153 | section 6.2.8.1 */ | |
1154 | /* Note: we provide the same info as the PCI routing | |
1155 | table of the Bochs BIOS */ | |
1156 | if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); | |
1157 | aml_append(if_ctx, aml_return(aml_name("PRTP"))); | |
1158 | aml_append(method, if_ctx); | |
1159 | else_ctx = aml_else(); | |
1160 | aml_append(else_ctx, aml_return(aml_name("PRTA"))); | |
1161 | aml_append(method, else_ctx); | |
1162 | } | |
1163 | aml_append(pci0_scope, method); | |
1164 | aml_append(sb_scope, pci0_scope); | |
80b32df5 | 1165 | |
78e1ad05 | 1166 | aml_append(sb_scope, build_irq_status_method()); |
16682a9d IM |
1167 | aml_append(sb_scope, build_iqcr_method(false)); |
1168 | ||
12e3b1f7 IM |
1169 | aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); |
1170 | aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); | |
1171 | aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); | |
1172 | aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); | |
1173 | aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); | |
1174 | aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); | |
1175 | aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); | |
1176 | aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); | |
1177 | ||
6a991e07 MA |
1178 | aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); |
1179 | aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); | |
1180 | aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); | |
1181 | aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); | |
1182 | aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); | |
1183 | aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); | |
1184 | aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); | |
1185 | aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); | |
80b32df5 IM |
1186 | |
1187 | aml_append(table, sb_scope); | |
1188 | } | |
1189 | ||
e3fb55f0 IY |
1190 | static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) |
1191 | { | |
1192 | Aml *dev; | |
1193 | Aml *resource_template; | |
1194 | ||
1195 | /* DRAM controller */ | |
1196 | dev = aml_device("DRAC"); | |
1197 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); | |
1198 | ||
1199 | resource_template = aml_resource_template(); | |
1200 | if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { | |
1201 | aml_append(resource_template, | |
1202 | aml_qword_memory(AML_POS_DECODE, | |
1203 | AML_MIN_FIXED, | |
1204 | AML_MAX_FIXED, | |
1205 | AML_NON_CACHEABLE, | |
1206 | AML_READ_WRITE, | |
1207 | 0x0000000000000000, | |
1208 | mcfg->base, | |
1209 | mcfg->base + mcfg->size - 1, | |
1210 | 0x0000000000000000, | |
1211 | mcfg->size)); | |
1212 | } else { | |
1213 | aml_append(resource_template, | |
1214 | aml_dword_memory(AML_POS_DECODE, | |
1215 | AML_MIN_FIXED, | |
1216 | AML_MAX_FIXED, | |
1217 | AML_NON_CACHEABLE, | |
1218 | AML_READ_WRITE, | |
1219 | 0x0000000000000000, | |
1220 | mcfg->base, | |
1221 | mcfg->base + mcfg->size - 1, | |
1222 | 0x0000000000000000, | |
1223 | mcfg->size)); | |
1224 | } | |
1225 | aml_append(dev, aml_name_decl("_CRS", resource_template)); | |
1226 | ||
1227 | return dev; | |
1228 | } | |
1229 | ||
caf108bc | 1230 | static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) |
b616ec4d IM |
1231 | { |
1232 | Aml *scope; | |
1233 | Aml *field; | |
1234 | Aml *method; | |
1235 | ||
1236 | scope = aml_scope("_SB.PCI0"); | |
1237 | ||
1238 | aml_append(scope, | |
caf108bc | 1239 | aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); |
b616ec4d IM |
1240 | field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); |
1241 | aml_append(field, aml_named_field("PCIU", 32)); | |
1242 | aml_append(field, aml_named_field("PCID", 32)); | |
1243 | aml_append(scope, field); | |
1244 | ||
1245 | aml_append(scope, | |
caf108bc JS |
1246 | aml_operation_region("SEJ", AML_SYSTEM_IO, |
1247 | aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); | |
b616ec4d IM |
1248 | field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); |
1249 | aml_append(field, aml_named_field("B0EJ", 32)); | |
1250 | aml_append(scope, field); | |
1251 | ||
1252 | aml_append(scope, | |
caf108bc JS |
1253 | aml_operation_region("BNMR", AML_SYSTEM_IO, |
1254 | aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); | |
b616ec4d IM |
1255 | field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); |
1256 | aml_append(field, aml_named_field("BNUM", 32)); | |
b32bd763 | 1257 | aml_append(field, aml_named_field("PIDX", 32)); |
b616ec4d IM |
1258 | aml_append(scope, field); |
1259 | ||
1260 | aml_append(scope, aml_mutex("BLCK", 0)); | |
1261 | ||
1262 | method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); | |
1263 | aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); | |
1264 | aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); | |
1265 | aml_append(method, | |
1266 | aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); | |
1267 | aml_append(method, aml_release(aml_name("BLCK"))); | |
1268 | aml_append(method, aml_return(aml_int(0))); | |
1269 | aml_append(scope, method); | |
1270 | ||
b32bd763 IM |
1271 | method = aml_method("AIDX", 2, AML_NOTSERIALIZED); |
1272 | aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); | |
1273 | aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); | |
1274 | aml_append(method, | |
1275 | aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); | |
1276 | aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); | |
1277 | aml_append(method, aml_release(aml_name("BLCK"))); | |
1278 | aml_append(method, aml_return(aml_local(0))); | |
1279 | aml_append(scope, method); | |
1280 | ||
5840a163 | 1281 | aml_append(scope, aml_pci_pdsm()); |
b7f23f62 | 1282 | |
b616ec4d IM |
1283 | aml_append(table, scope); |
1284 | } | |
1285 | ||
211afe5c | 1286 | static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) |
f97a88a8 IM |
1287 | { |
1288 | Aml *if_ctx; | |
1289 | Aml *if_ctx2; | |
1290 | Aml *else_ctx; | |
1291 | Aml *method; | |
1292 | Aml *a_cwd1 = aml_name("CDW1"); | |
b3c782db | 1293 | Aml *a_ctrl = aml_local(0); |
f97a88a8 IM |
1294 | |
1295 | method = aml_method("_OSC", 4, AML_NOTSERIALIZED); | |
1296 | aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); | |
1297 | ||
1298 | if_ctx = aml_if(aml_equal( | |
1299 | aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); | |
1300 | aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); | |
1301 | aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); | |
1302 | ||
f97a88a8 IM |
1303 | aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); |
1304 | ||
1305 | /* | |
1306 | * Always allow native PME, AER (no dependencies) | |
a41c78c1 | 1307 | * Allow SHPC (PCI bridges can have SHPC controller) |
211afe5c | 1308 | * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. |
f97a88a8 | 1309 | */ |
211afe5c JS |
1310 | aml_append(if_ctx, aml_and(a_ctrl, |
1311 | aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); | |
f97a88a8 IM |
1312 | |
1313 | if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); | |
1314 | /* Unknown revision */ | |
1315 | aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); | |
1316 | aml_append(if_ctx, if_ctx2); | |
1317 | ||
1318 | if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); | |
1319 | /* Capabilities bits were masked */ | |
1320 | aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); | |
1321 | aml_append(if_ctx, if_ctx2); | |
1322 | ||
1323 | /* Update DWORD3 in the buffer */ | |
1324 | aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); | |
1325 | aml_append(method, if_ctx); | |
1326 | ||
1327 | else_ctx = aml_else(); | |
1328 | /* Unrecognized UUID */ | |
1329 | aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); | |
1330 | aml_append(method, else_ctx); | |
1331 | ||
1332 | aml_append(method, aml_return(aml_arg(3))); | |
1333 | return method; | |
1334 | } | |
b616ec4d | 1335 | |
3d6a69b6 BW |
1336 | static void build_acpi0017(Aml *table) |
1337 | { | |
1338 | Aml *dev, *scope, *method; | |
1339 | ||
1340 | scope = aml_scope("_SB"); | |
1341 | dev = aml_device("CXLM"); | |
1342 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); | |
1343 | ||
1344 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
1345 | aml_append(method, aml_return(aml_int(0x01))); | |
1346 | aml_append(dev, method); | |
1347 | ||
1348 | aml_append(scope, dev); | |
1349 | aml_append(table, scope); | |
1350 | } | |
1351 | ||
72c194f7 | 1352 | static void |
0e9b9eda | 1353 | build_dsdt(GArray *table_data, BIOSLinker *linker, |
adcb89d5 | 1354 | AcpiPmInfo *pm, AcpiMiscInfo *misc, |
01c9742d | 1355 | Range *pci_hole, Range *pci_hole64, MachineState *machine) |
72c194f7 | 1356 | { |
b496a17d BB |
1357 | Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE); |
1358 | Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE); | |
41fa5c04 IM |
1359 | CrsRangeEntry *entry; |
1360 | Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; | |
2df5a7b5 | 1361 | CrsRangeSet crs_range_set; |
fb306ffe | 1362 | PCMachineState *pcms = PC_MACHINE(machine); |
679dd1a9 | 1363 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); |
f0bb276b | 1364 | X86MachineState *x86ms = X86_MACHINE(machine); |
4a441836 | 1365 | AcpiMcfgInfo mcfg; |
e3fb55f0 | 1366 | bool mcfg_valid = !!acpi_get_mcfg(&mcfg); |
bef3492d | 1367 | uint32_t nr_mem = machine->ram_slots; |
dcdca296 | 1368 | int root_bus_limit = 0xFF; |
41fa5c04 | 1369 | PCIBus *bus = NULL; |
11fb99e6 | 1370 | #ifdef CONFIG_TPM |
ac6dd31e | 1371 | TPMIf *tpm = tpm_find(); |
11fb99e6 | 1372 | #endif |
3d6a69b6 | 1373 | bool cxl_present = false; |
72c194f7 | 1374 | int i; |
8f814ea1 | 1375 | VMBusBridge *vmbus_bridge = vmbus_bridge_find(); |
5c142bc4 IM |
1376 | AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, |
1377 | .oem_table_id = x86ms->oem_table_id }; | |
72c194f7 | 1378 | |
b496a17d | 1379 | assert(!!i440fx != !!q35); |
bbaa5c41 | 1380 | |
5c142bc4 | 1381 | acpi_table_begin(&table, table_data); |
41fa5c04 | 1382 | dsdt = init_aml_allocator(); |
2fd71f1b | 1383 | |
41fa5c04 | 1384 | build_dbg_aml(dsdt); |
b496a17d | 1385 | if (i440fx) { |
41fa5c04 IM |
1386 | sb_scope = aml_scope("_SB"); |
1387 | dev = aml_device("PCI0"); | |
1388 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); | |
1389 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
0a343a5a | 1390 | aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); |
41fa5c04 IM |
1391 | aml_append(sb_scope, dev); |
1392 | aml_append(dsdt, sb_scope); | |
1393 | ||
df4008c9 | 1394 | if (pm->pcihp_bridge_en || pm->pcihp_root_en) { |
caf108bc | 1395 | build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); |
df4008c9 | 1396 | } |
41fa5c04 | 1397 | build_piix4_pci0_int(dsdt); |
b496a17d | 1398 | } else if (q35) { |
41fa5c04 IM |
1399 | sb_scope = aml_scope("_SB"); |
1400 | dev = aml_device("PCI0"); | |
1401 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); | |
1402 | aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); | |
1403 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
0a343a5a | 1404 | aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); |
211afe5c | 1405 | aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); |
41fa5c04 | 1406 | aml_append(sb_scope, dev); |
e3fb55f0 IY |
1407 | if (mcfg_valid) { |
1408 | aml_append(sb_scope, build_q35_dram_controller(&mcfg)); | |
1409 | } | |
998ba950 IM |
1410 | |
1411 | if (pm->smi_on_cpuhp) { | |
1412 | /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ | |
1413 | dev = aml_device("PCI0.SMI0"); | |
1414 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); | |
1415 | aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); | |
1416 | crs = aml_resource_template(); | |
1417 | aml_append(crs, | |
1418 | aml_io( | |
1419 | AML_DECODE16, | |
1420 | ACPI_PORT_SMI_CMD, | |
1421 | ACPI_PORT_SMI_CMD, | |
1422 | 1, | |
1423 | 2) | |
1424 | ); | |
1425 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1426 | aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, | |
1427 | aml_int(ACPI_PORT_SMI_CMD), 2)); | |
1428 | field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, | |
1429 | AML_WRITE_AS_ZEROS); | |
1430 | aml_append(field, aml_named_field("SMIC", 8)); | |
1431 | aml_append(field, aml_reserved_field(8)); | |
1432 | aml_append(dev, field); | |
1433 | aml_append(sb_scope, dev); | |
1434 | } | |
1435 | ||
41fa5c04 IM |
1436 | aml_append(dsdt, sb_scope); |
1437 | ||
caf108bc JS |
1438 | if (pm->pcihp_bridge_en) { |
1439 | build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); | |
1440 | } | |
41fa5c04 IM |
1441 | build_q35_pci0_int(dsdt); |
1442 | } | |
1443 | ||
e05acc36 IM |
1444 | if (misc->has_hpet) { |
1445 | build_hpet_aml(dsdt); | |
1446 | } | |
1447 | ||
8f814ea1 JD |
1448 | if (vmbus_bridge) { |
1449 | sb_scope = aml_scope("_SB"); | |
1450 | aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); | |
1451 | aml_append(dsdt, sb_scope); | |
1452 | } | |
1453 | ||
d12dbd44 IM |
1454 | scope = aml_scope("_GPE"); |
1455 | { | |
1456 | aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); | |
1457 | if (machine->nvdimms_state->is_enabled) { | |
1458 | method = aml_method("_E04", 0, AML_NOTSERIALIZED); | |
1459 | aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), | |
1460 | aml_int(0x80))); | |
1461 | aml_append(scope, method); | |
1462 | } | |
1463 | } | |
1464 | aml_append(dsdt, scope); | |
1465 | ||
679dd1a9 IM |
1466 | if (pcmc->legacy_cpu_hotplug) { |
1467 | build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); | |
1468 | } else { | |
1469 | CPUHotplugFeatures opts = { | |
998ba950 IM |
1470 | .acpi_1_compatible = true, .has_legacy_cphp = true, |
1471 | .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, | |
69dea9d6 | 1472 | .fw_unplugs_cpu = pm->smi_on_cpu_unplug, |
679dd1a9 IM |
1473 | }; |
1474 | build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, | |
1475 | "\\_SB.PCI0", "\\_GPE._E02"); | |
1476 | } | |
091c466e SK |
1477 | |
1478 | if (pcms->memhp_io_base && nr_mem) { | |
1479 | build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", | |
1480 | "\\_GPE._E03", AML_SYSTEM_IO, | |
1481 | pcms->memhp_io_base); | |
1482 | } | |
41fa5c04 | 1483 | |
2df5a7b5 | 1484 | crs_range_set_init(&crs_range_set); |
81ed6482 | 1485 | bus = PC_MACHINE(machine)->bus; |
a4894206 MA |
1486 | if (bus) { |
1487 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1488 | uint8_t bus_num = pci_bus_num(bus); | |
0e79e51a | 1489 | uint8_t numa_node = pci_bus_numa_node(bus); |
a4894206 MA |
1490 | |
1491 | /* look only for expander root buses */ | |
1492 | if (!pci_bus_is_root(bus)) { | |
1493 | continue; | |
1494 | } | |
1495 | ||
dcdca296 MA |
1496 | if (bus_num < root_bus_limit) { |
1497 | root_bus_limit = bus_num - 1; | |
1498 | } | |
1499 | ||
a4894206 | 1500 | scope = aml_scope("\\_SB"); |
6e4e3ae9 BW |
1501 | |
1502 | if (pci_bus_is_cxl(bus)) { | |
1503 | dev = aml_device("CL%.02X", bus_num); | |
1504 | } else { | |
1505 | dev = aml_device("PC%.02X", bus_num); | |
1506 | } | |
c96d9286 | 1507 | aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); |
a4894206 | 1508 | aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); |
6e4e3ae9 | 1509 | if (pci_bus_is_cxl(bus)) { |
2a3282c6 BW |
1510 | struct Aml *pkg = aml_package(2); |
1511 | ||
1512 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); | |
1513 | aml_append(pkg, aml_eisaid("PNP0A08")); | |
1514 | aml_append(pkg, aml_eisaid("PNP0A03")); | |
1515 | aml_append(dev, aml_name_decl("_CID", pkg)); | |
1516 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
2a3282c6 | 1517 | build_cxl_osc_method(dev); |
6e4e3ae9 | 1518 | } else if (pci_bus_is_express(bus)) { |
ee4b0c86 EY |
1519 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); |
1520 | aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); | |
211afe5c JS |
1521 | |
1522 | /* Expander bridges do not have ACPI PCI Hot-plug enabled */ | |
1523 | aml_append(dev, build_q35_osc_method(true)); | |
ee4b0c86 EY |
1524 | } else { |
1525 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); | |
077dd742 | 1526 | } |
0e79e51a MA |
1527 | |
1528 | if (numa_node != NUMA_NODE_UNASSIGNED) { | |
1529 | aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); | |
1530 | } | |
1531 | ||
196e2137 | 1532 | aml_append(dev, build_prt(false)); |
e41ee855 JC |
1533 | crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, |
1534 | 0, 0, 0, 0); | |
a43c6e27 | 1535 | aml_append(dev, aml_name_decl("_CRS", crs)); |
a4894206 | 1536 | aml_append(scope, dev); |
41fa5c04 | 1537 | aml_append(dsdt, scope); |
6e4e3ae9 BW |
1538 | |
1539 | /* Handle the ranges for the PXB expanders */ | |
1540 | if (pci_bus_is_cxl(bus)) { | |
1ebf9001 | 1541 | MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; |
6e4e3ae9 BW |
1542 | uint64_t base = mr->addr; |
1543 | ||
3d6a69b6 | 1544 | cxl_present = true; |
6e4e3ae9 BW |
1545 | crs_range_insert(crs_range_set.mem_ranges, base, |
1546 | base + memory_region_size(mr) - 1); | |
1547 | } | |
a4894206 MA |
1548 | } |
1549 | } | |
1550 | ||
3d6a69b6 BW |
1551 | if (cxl_present) { |
1552 | build_acpi0017(dsdt); | |
1553 | } | |
1554 | ||
4a441836 GH |
1555 | /* |
1556 | * At this point crs_range_set has all the ranges used by pci | |
1557 | * busses *other* than PCI0. These ranges will be excluded from | |
1558 | * the PCI0._CRS. Add mmconfig to the set so it will be excluded | |
1559 | * too. | |
1560 | */ | |
e3fb55f0 | 1561 | if (mcfg_valid) { |
4a441836 GH |
1562 | crs_range_insert(crs_range_set.mem_ranges, |
1563 | mcfg.base, mcfg.base + mcfg.size - 1); | |
1564 | } | |
1565 | ||
500b11ea | 1566 | scope = aml_scope("\\_SB.PCI0"); |
60efd429 IM |
1567 | /* build PCI0._CRS */ |
1568 | crs = aml_resource_template(); | |
1569 | aml_append(crs, | |
ff80dc7f | 1570 | aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, |
dcdca296 MA |
1571 | 0x0000, 0x0, root_bus_limit, |
1572 | 0x0000, root_bus_limit + 1)); | |
ff80dc7f | 1573 | aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); |
60efd429 IM |
1574 | |
1575 | aml_append(crs, | |
ff80dc7f SZ |
1576 | aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, |
1577 | AML_POS_DECODE, AML_ENTIRE_RANGE, | |
60efd429 | 1578 | 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); |
dcdca296 | 1579 | |
2df5a7b5 MA |
1580 | crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); |
1581 | for (i = 0; i < crs_range_set.io_ranges->len; i++) { | |
1582 | entry = g_ptr_array_index(crs_range_set.io_ranges, i); | |
dcdca296 MA |
1583 | aml_append(crs, |
1584 | aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, | |
1585 | AML_POS_DECODE, AML_ENTIRE_RANGE, | |
1586 | 0x0000, entry->base, entry->limit, | |
1587 | 0x0000, entry->limit - entry->base + 1)); | |
1588 | } | |
1589 | ||
60efd429 | 1590 | aml_append(crs, |
ff80dc7f SZ |
1591 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, |
1592 | AML_CACHEABLE, AML_READ_WRITE, | |
60efd429 | 1593 | 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); |
dcdca296 | 1594 | |
2df5a7b5 | 1595 | crs_replace_with_free_ranges(crs_range_set.mem_ranges, |
a0efbf16 MA |
1596 | range_lob(pci_hole), |
1597 | range_upb(pci_hole)); | |
2df5a7b5 MA |
1598 | for (i = 0; i < crs_range_set.mem_ranges->len; i++) { |
1599 | entry = g_ptr_array_index(crs_range_set.mem_ranges, i); | |
dcdca296 MA |
1600 | aml_append(crs, |
1601 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, | |
1602 | AML_NON_CACHEABLE, AML_READ_WRITE, | |
1603 | 0, entry->base, entry->limit, | |
1604 | 0, entry->limit - entry->base + 1)); | |
1605 | } | |
1606 | ||
a0efbf16 | 1607 | if (!range_is_empty(pci_hole64)) { |
16de88a4 MA |
1608 | crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, |
1609 | range_lob(pci_hole64), | |
1610 | range_upb(pci_hole64)); | |
1611 | for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { | |
1612 | entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); | |
1613 | aml_append(crs, | |
1614 | aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, | |
1615 | AML_MAX_FIXED, | |
1616 | AML_CACHEABLE, AML_READ_WRITE, | |
1617 | 0, entry->base, entry->limit, | |
1618 | 0, entry->limit - entry->base + 1)); | |
1619 | } | |
60efd429 | 1620 | } |
2b1c2e8e | 1621 | |
11fb99e6 | 1622 | #ifdef CONFIG_TPM |
43bc7f84 | 1623 | if (TPM_IS_TIS_ISA(tpm_find())) { |
2b1c2e8e IM |
1624 | aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, |
1625 | TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); | |
1626 | } | |
11fb99e6 | 1627 | #endif |
60efd429 IM |
1628 | aml_append(scope, aml_name_decl("_CRS", crs)); |
1629 | ||
d31c909e IM |
1630 | /* reserve GPE0 block resources */ |
1631 | dev = aml_device("GPE0"); | |
1632 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
1633 | aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); | |
1634 | /* device present, functioning, decoding, not shown in UI */ | |
1635 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1636 | crs = aml_resource_template(); | |
1637 | aml_append(crs, | |
937d1b58 IM |
1638 | aml_io( |
1639 | AML_DECODE16, | |
1640 | pm->fadt.gpe0_blk.address, | |
1641 | pm->fadt.gpe0_blk.address, | |
1642 | 1, | |
1643 | pm->fadt.gpe0_blk.bit_width / 8) | |
d31c909e IM |
1644 | ); |
1645 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1646 | aml_append(scope, dev); | |
1647 | ||
2df5a7b5 | 1648 | crs_range_set_free(&crs_range_set); |
dcdca296 | 1649 | |
500b11ea | 1650 | /* reserve PCIHP resources */ |
df4008c9 | 1651 | if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { |
500b11ea IM |
1652 | dev = aml_device("PHPR"); |
1653 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
1654 | aml_append(dev, | |
1655 | aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); | |
1656 | /* device present, functioning, decoding, not shown in UI */ | |
1657 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1658 | crs = aml_resource_template(); | |
1659 | aml_append(crs, | |
ff80dc7f | 1660 | aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, |
500b11ea IM |
1661 | pm->pcihp_io_len) |
1662 | ); | |
1663 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1664 | aml_append(scope, dev); | |
1665 | } | |
41fa5c04 | 1666 | aml_append(dsdt, scope); |
500b11ea | 1667 | |
ebc3028f IM |
1668 | /* create S3_ / S4_ / S5_ packages if necessary */ |
1669 | scope = aml_scope("\\"); | |
1670 | if (!pm->s3_disabled) { | |
1671 | pkg = aml_package(4); | |
1672 | aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ | |
1673 | aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
1674 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1675 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1676 | aml_append(scope, aml_name_decl("_S3", pkg)); | |
1677 | } | |
1678 | ||
1679 | if (!pm->s4_disabled) { | |
1680 | pkg = aml_package(4); | |
1681 | aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ | |
1682 | /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
1683 | aml_append(pkg, aml_int(pm->s4_val)); | |
1684 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1685 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1686 | aml_append(scope, aml_name_decl("_S4", pkg)); | |
1687 | } | |
1688 | ||
1689 | pkg = aml_package(4); | |
1690 | aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ | |
1691 | aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ | |
1692 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1693 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1694 | aml_append(scope, aml_name_decl("_S5", pkg)); | |
41fa5c04 | 1695 | aml_append(dsdt, scope); |
ebc3028f | 1696 | |
e2ec7568 GS |
1697 | /* create fw_cfg node, unconditionally */ |
1698 | { | |
e2ec7568 | 1699 | scope = aml_scope("\\_SB.PCI0"); |
0575c2fd | 1700 | fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); |
e2ec7568 GS |
1701 | aml_append(dsdt, scope); |
1702 | } | |
1703 | ||
7824df38 | 1704 | sb_scope = aml_scope("\\_SB"); |
72c194f7 | 1705 | { |
d3ecb22c | 1706 | Object *pci_host = acpi_get_i386_pci_host(); |
c0e427d6 | 1707 | |
8b35ab27 | 1708 | if (pci_host) { |
d3ecb22c | 1709 | PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; |
8b35ab27 IM |
1710 | Aml *scope = aml_scope("PCI0"); |
1711 | /* Scan all PCI buses. Generate tables to support hotplug. */ | |
6c36ec46 | 1712 | build_append_pci_bus_devices(scope, bus); |
8b35ab27 | 1713 | aml_append(sb_scope, scope); |
72c194f7 | 1714 | } |
72c194f7 | 1715 | } |
4ab6cb4c | 1716 | |
11fb99e6 | 1717 | #ifdef CONFIG_TPM |
ac6dd31e | 1718 | if (TPM_IS_CRB(tpm)) { |
4ab6cb4c MAL |
1719 | dev = aml_device("TPM"); |
1720 | aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); | |
5903646d SB |
1721 | aml_append(dev, aml_name_decl("_STR", |
1722 | aml_string("TPM 2.0 Device"))); | |
4ab6cb4c MAL |
1723 | crs = aml_resource_template(); |
1724 | aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, | |
1725 | TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); | |
1726 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1727 | ||
88b3648f | 1728 | aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); |
5903646d | 1729 | aml_append(dev, aml_name_decl("_UID", aml_int(1))); |
4ab6cb4c | 1730 | |
ac6dd31e SB |
1731 | tpm_build_ppi_acpi(tpm, dev); |
1732 | ||
4ab6cb4c MAL |
1733 | aml_append(sb_scope, dev); |
1734 | } | |
11fb99e6 | 1735 | #endif |
4ab6cb4c | 1736 | |
c8a9899c SC |
1737 | if (pcms->sgx_epc.size != 0) { |
1738 | uint64_t epc_base = pcms->sgx_epc.base; | |
1739 | uint64_t epc_size = pcms->sgx_epc.size; | |
1740 | ||
1741 | dev = aml_device("EPC"); | |
1742 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); | |
1743 | aml_append(dev, aml_name_decl("_STR", | |
1744 | aml_unicode("Enclave Page Cache 1.0"))); | |
1745 | crs = aml_resource_template(); | |
1746 | aml_append(crs, | |
1747 | aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, | |
1748 | AML_MAX_FIXED, AML_NON_CACHEABLE, | |
1749 | AML_READ_WRITE, 0, epc_base, | |
1750 | epc_base + epc_size - 1, 0, epc_size)); | |
1751 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1752 | ||
1753 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
1754 | aml_append(method, aml_return(aml_int(0x0f))); | |
1755 | aml_append(dev, method); | |
1756 | ||
1757 | aml_append(sb_scope, dev); | |
1758 | } | |
8b35ab27 | 1759 | aml_append(dsdt, sb_scope); |
72c194f7 | 1760 | |
d12dbd44 | 1761 | if (pm->pcihp_bridge_en || pm->pcihp_root_en) { |
219e638f IM |
1762 | bool has_pcnt; |
1763 | ||
ddab4d3f IM |
1764 | Object *pci_host = acpi_get_i386_pci_host(); |
1765 | PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; | |
1766 | ||
1767 | scope = aml_scope("\\_SB.PCI0"); | |
219e638f IM |
1768 | has_pcnt = build_append_notfication_callback(scope, bus); |
1769 | if (has_pcnt) { | |
1770 | aml_append(dsdt, scope); | |
1771 | } | |
ddab4d3f | 1772 | |
d12dbd44 IM |
1773 | scope = aml_scope("_GPE"); |
1774 | { | |
1775 | method = aml_method("_E01", 0, AML_NOTSERIALIZED); | |
219e638f IM |
1776 | if (has_pcnt) { |
1777 | aml_append(method, | |
1778 | aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); | |
1779 | aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); | |
1780 | aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); | |
1781 | } | |
d12dbd44 IM |
1782 | aml_append(scope, method); |
1783 | } | |
1784 | aml_append(dsdt, scope); | |
1785 | } | |
1786 | ||
011bb749 | 1787 | /* copy AML table into ACPI tables blob and patch header there */ |
41fa5c04 | 1788 | g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); |
5c142bc4 | 1789 | acpi_table_end(linker, &table); |
011bb749 | 1790 | free_aml_allocator(); |
72c194f7 MT |
1791 | } |
1792 | ||
43dde170 IM |
1793 | /* |
1794 | * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) | |
1795 | * 3.2.4The ACPI 2.0 HPET Description Table (HPET) | |
1796 | */ | |
72c194f7 | 1797 | static void |
602b4582 MP |
1798 | build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, |
1799 | const char *oem_table_id) | |
72c194f7 | 1800 | { |
43dde170 IM |
1801 | AcpiTable table = { .sig = "HPET", .rev = 1, |
1802 | .oem_id = oem_id, .oem_table_id = oem_table_id }; | |
72c194f7 | 1803 | |
43dde170 | 1804 | acpi_table_begin(&table, table_data); |
72c194f7 MT |
1805 | /* Note timer_block_id value must be kept in sync with value advertised by |
1806 | * emulated hpet | |
1807 | */ | |
43dde170 IM |
1808 | /* Event Timer Block ID */ |
1809 | build_append_int_noprefix(table_data, 0x8086a201, 4); | |
1810 | /* BASE_ADDRESS */ | |
1811 | build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); | |
1812 | /* HPET Number */ | |
1813 | build_append_int_noprefix(table_data, 0, 1); | |
1814 | /* Main Counter Minimum Clock_tick in Periodic Mode */ | |
1815 | build_append_int_noprefix(table_data, 0, 2); | |
1816 | /* Page Protection And OEM Attribute */ | |
1817 | build_append_int_noprefix(table_data, 0, 1); | |
1818 | acpi_table_end(linker, &table); | |
72c194f7 MT |
1819 | } |
1820 | ||
11fb99e6 | 1821 | #ifdef CONFIG_TPM |
57cb8cfb IM |
1822 | /* |
1823 | * TCPA Description Table | |
1824 | * | |
1825 | * Following Level 00, Rev 00.37 of specs: | |
1826 | * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification | |
1827 | * 7.1.2 ACPI Table Layout | |
1828 | */ | |
711b20b4 | 1829 | static void |
602b4582 MP |
1830 | build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, |
1831 | const char *oem_id, const char *oem_table_id) | |
711b20b4 | 1832 | { |
57cb8cfb IM |
1833 | unsigned log_addr_offset; |
1834 | AcpiTable table = { .sig = "TCPA", .rev = 2, | |
1835 | .oem_id = oem_id, .oem_table_id = oem_table_id }; | |
711b20b4 | 1836 | |
57cb8cfb IM |
1837 | acpi_table_begin(&table, table_data); |
1838 | /* Platform Class */ | |
1839 | build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); | |
1840 | /* Log Area Minimum Length (LAML) */ | |
1841 | build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); | |
1842 | /* Log Area Start Address (LASA) */ | |
1843 | log_addr_offset = table_data->len; | |
1844 | build_append_int_noprefix(table_data, 0, 8); | |
1845 | ||
1846 | /* allocate/reserve space for TPM log area */ | |
1847 | acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); | |
ad9671b8 | 1848 | bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, |
42a5b308 | 1849 | false /* high memory */); |
711b20b4 | 1850 | /* log area start address to be filled by Guest linker */ |
57cb8cfb IM |
1851 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, |
1852 | log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); | |
711b20b4 | 1853 | |
57cb8cfb | 1854 | acpi_table_end(linker, &table); |
711b20b4 | 1855 | } |
11fb99e6 | 1856 | #endif |
711b20b4 | 1857 | |
d471bf3e PB |
1858 | #define HOLE_640K_START (640 * KiB) |
1859 | #define HOLE_640K_END (1 * MiB) | |
4926403c | 1860 | |
e5b6d55a IM |
1861 | /* |
1862 | * ACPI spec, Revision 3.0 | |
1863 | * 5.2.15 System Resource Affinity Table (SRAT) | |
1864 | */ | |
72c194f7 | 1865 | static void |
0e9b9eda | 1866 | build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) |
72c194f7 | 1867 | { |
72c194f7 | 1868 | int i; |
e5b6d55a | 1869 | int numa_mem_start, slots; |
72c194f7 | 1870 | uint64_t mem_len, mem_base, next_base; |
5803fce3 | 1871 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
f0bb276b | 1872 | X86MachineState *x86ms = X86_MACHINE(machine); |
80e5db30 | 1873 | const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); |
3d3ebcad | 1874 | PCMachineState *pcms = PC_MACHINE(machine); |
e77af21a JL |
1875 | int nb_numa_nodes = machine->numa_state->num_nodes; |
1876 | NodeInfo *numa_info = machine->numa_state->nodes; | |
4be8bfcb | 1877 | ram_addr_t hotpluggable_address_space_size = |
f2ffbe2b | 1878 | object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, |
cec65193 | 1879 | NULL); |
255bf20f IM |
1880 | AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, |
1881 | .oem_table_id = x86ms->oem_table_id }; | |
72c194f7 | 1882 | |
255bf20f IM |
1883 | acpi_table_begin(&table, table_data); |
1884 | build_append_int_noprefix(table_data, 1, 4); /* Reserved */ | |
1885 | build_append_int_noprefix(table_data, 0, 8); /* Reserved */ | |
72c194f7 | 1886 | |
5803fce3 | 1887 | for (i = 0; i < apic_ids->len; i++) { |
d41f3e75 | 1888 | int node_id = apic_ids->cpus[i].props.node_id; |
5eff33a2 | 1889 | uint32_t apic_id = apic_ids->cpus[i].arch_id; |
5803fce3 | 1890 | |
5eff33a2 | 1891 | if (apic_id < 255) { |
e5b6d55a IM |
1892 | /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ |
1893 | build_append_int_noprefix(table_data, 0, 1); /* Type */ | |
1894 | build_append_int_noprefix(table_data, 16, 1); /* Length */ | |
1895 | /* Proximity Domain [7:0] */ | |
1896 | build_append_int_noprefix(table_data, node_id, 1); | |
1897 | build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ | |
1898 | /* Flags, Table 5-36 */ | |
1899 | build_append_int_noprefix(table_data, 1, 4); | |
1900 | build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ | |
1901 | /* Proximity Domain [31:8] */ | |
1902 | build_append_int_noprefix(table_data, 0, 3); | |
1903 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
5eff33a2 | 1904 | } else { |
e5b6d55a IM |
1905 | /* |
1906 | * ACPI spec, Revision 4.0 | |
1907 | * 5.2.16.3 Processor Local x2APIC Affinity Structure | |
1908 | */ | |
1909 | build_append_int_noprefix(table_data, 2, 1); /* Type */ | |
1910 | build_append_int_noprefix(table_data, 24, 1); /* Length */ | |
1911 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
1912 | /* Proximity Domain */ | |
1913 | build_append_int_noprefix(table_data, node_id, 4); | |
1914 | build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ | |
1915 | /* Flags, Table 5-39 */ | |
1916 | build_append_int_noprefix(table_data, 1 /* Enabled */, 4); | |
1917 | build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ | |
1918 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
1f3aba37 | 1919 | } |
72c194f7 MT |
1920 | } |
1921 | ||
72c194f7 MT |
1922 | /* the memory map is a bit tricky, it contains at least one hole |
1923 | * from 640k-1M and possibly another one from 3.5G-4G. | |
1924 | */ | |
1925 | next_base = 0; | |
e5b6d55a | 1926 | numa_mem_start = table_data->len; |
72c194f7 | 1927 | |
e77af21a | 1928 | for (i = 1; i < nb_numa_nodes + 1; ++i) { |
72c194f7 | 1929 | mem_base = next_base; |
e77af21a | 1930 | mem_len = numa_info[i - 1].node_mem; |
72c194f7 MT |
1931 | next_base = mem_base + mem_len; |
1932 | ||
4926403c EH |
1933 | /* Cut out the 640K hole */ |
1934 | if (mem_base <= HOLE_640K_START && | |
1935 | next_base > HOLE_640K_START) { | |
1936 | mem_len -= next_base - HOLE_640K_START; | |
1937 | if (mem_len > 0) { | |
e5b6d55a | 1938 | build_srat_memory(table_data, mem_base, mem_len, i - 1, |
4926403c EH |
1939 | MEM_AFFINITY_ENABLED); |
1940 | } | |
1941 | ||
1942 | /* Check for the rare case: 640K < RAM < 1M */ | |
1943 | if (next_base <= HOLE_640K_END) { | |
1944 | next_base = HOLE_640K_END; | |
1945 | continue; | |
1946 | } | |
1947 | mem_base = HOLE_640K_END; | |
1948 | mem_len = next_base - HOLE_640K_END; | |
1949 | } | |
1950 | ||
72c194f7 | 1951 | /* Cut out the ACPI_PCI hole */ |
f0bb276b PB |
1952 | if (mem_base <= x86ms->below_4g_mem_size && |
1953 | next_base > x86ms->below_4g_mem_size) { | |
1954 | mem_len -= next_base - x86ms->below_4g_mem_size; | |
72c194f7 | 1955 | if (mem_len > 0) { |
e5b6d55a | 1956 | build_srat_memory(table_data, mem_base, mem_len, i - 1, |
64b83136 | 1957 | MEM_AFFINITY_ENABLED); |
72c194f7 | 1958 | } |
4ab4c330 | 1959 | mem_base = x86ms->above_4g_mem_start; |
f0bb276b | 1960 | mem_len = next_base - x86ms->below_4g_mem_size; |
6cf6fe39 | 1961 | next_base = mem_base + mem_len; |
72c194f7 | 1962 | } |
16b42263 DL |
1963 | |
1964 | if (mem_len > 0) { | |
e5b6d55a | 1965 | build_srat_memory(table_data, mem_base, mem_len, i - 1, |
16b42263 DL |
1966 | MEM_AFFINITY_ENABLED); |
1967 | } | |
72c194f7 | 1968 | } |
c3b0cf6e VV |
1969 | |
1970 | if (machine->nvdimms_state->is_enabled) { | |
1971 | nvdimm_build_srat(table_data); | |
1972 | } | |
1973 | ||
11058123 YZ |
1974 | sgx_epc_build_srat(table_data); |
1975 | ||
e5b6d55a IM |
1976 | /* |
1977 | * TODO: this part is not in ACPI spec and current linux kernel boots fine | |
1978 | * without these entries. But I recall there were issues the last time I | |
1979 | * tried to remove it with some ancient guest OS, however I can't remember | |
1980 | * what that was so keep this around for now | |
1981 | */ | |
1982 | slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; | |
e77af21a | 1983 | for (; slots < nb_numa_nodes + 2; slots++) { |
e5b6d55a | 1984 | build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); |
72c194f7 MT |
1985 | } |
1986 | ||
dbb6da8b IM |
1987 | /* |
1988 | * Entry is required for Windows to enable memory hotplug in OS | |
1989 | * and for Linux to enable SWIOTLB when booted with less than | |
1990 | * 4G of RAM. Windows works better if the entry sets proximity | |
1991 | * to the highest NUMA node in the machine. | |
1992 | * Memory devices may override proximity set by this entry, | |
1993 | * providing _PXM method if necessary. | |
1994 | */ | |
4be8bfcb | 1995 | if (hotpluggable_address_space_size) { |
e5b6d55a | 1996 | build_srat_memory(table_data, machine->device_memory->base, |
4be8bfcb | 1997 | hotpluggable_address_space_size, nb_numa_nodes - 1, |
dbb6da8b | 1998 | MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); |
cec65193 IM |
1999 | } |
2000 | ||
255bf20f | 2001 | acpi_table_end(linker, &table); |
72c194f7 MT |
2002 | } |
2003 | ||
26863366 XW |
2004 | /* |
2005 | * Insert DMAR scope for PCI bridges and endpoint devcie | |
2006 | */ | |
2007 | static void | |
2008 | insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) | |
2009 | { | |
91a6b975 IM |
2010 | const size_t device_scope_size = 6 /* device scope structure */ + |
2011 | 2 /* 1 path entry */; | |
26863366 | 2012 | GArray *scope_blob = opaque; |
26863366 XW |
2013 | |
2014 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { | |
2015 | /* Dmar Scope Type: 0x02 for PCI Bridge */ | |
2016 | build_append_int_noprefix(scope_blob, 0x02, 1); | |
2017 | } else { | |
2018 | /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ | |
2019 | build_append_int_noprefix(scope_blob, 0x01, 1); | |
2020 | } | |
2021 | ||
2022 | /* length */ | |
91a6b975 | 2023 | build_append_int_noprefix(scope_blob, device_scope_size, 1); |
26863366 XW |
2024 | /* reserved */ |
2025 | build_append_int_noprefix(scope_blob, 0, 2); | |
2026 | /* enumeration_id */ | |
2027 | build_append_int_noprefix(scope_blob, 0, 1); | |
2028 | /* bus */ | |
2029 | build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); | |
2030 | /* device */ | |
2031 | build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); | |
2032 | /* function */ | |
2033 | build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); | |
2034 | } | |
2035 | ||
2036 | /* For a given PCI host bridge, walk and insert DMAR scope */ | |
2037 | static int | |
2038 | dmar_host_bridges(Object *obj, void *opaque) | |
2039 | { | |
2040 | GArray *scope_blob = opaque; | |
2041 | ||
2042 | if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { | |
2043 | PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; | |
2044 | ||
2045 | if (bus && !pci_bus_bypass_iommu(bus)) { | |
2914fc61 | 2046 | pci_for_each_device_under_bus(bus, insert_scope, scope_blob); |
26863366 XW |
2047 | } |
2048 | } | |
2049 | ||
2050 | return 0; | |
2051 | } | |
2052 | ||
d46114f9 | 2053 | /* |
91a6b975 IM |
2054 | * Intel ® Virtualization Technology for Directed I/O |
2055 | * Architecture Specification. Revision 3.3 | |
2056 | * 8.1 DMA Remapping Reporting Structure | |
d46114f9 | 2057 | */ |
d4eb9119 | 2058 | static void |
602b4582 MP |
2059 | build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, |
2060 | const char *oem_table_id) | |
d4eb9119 | 2061 | { |
d46114f9 | 2062 | uint8_t dmar_flags = 0; |
91a6b975 IM |
2063 | uint8_t rsvd10[10] = {}; |
2064 | /* Root complex IOAPIC uses one path only */ | |
2065 | const size_t ioapic_scope_size = 6 /* device scope structure */ + | |
2066 | 2 /* 1 path entry */; | |
d46114f9 | 2067 | X86IOMMUState *iommu = x86_iommu_get_default(); |
37f51384 | 2068 | IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); |
26863366 XW |
2069 | GArray *scope_blob = g_array_new(false, true, 1); |
2070 | ||
91a6b975 IM |
2071 | AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, |
2072 | .oem_table_id = oem_table_id }; | |
2073 | ||
26863366 XW |
2074 | /* |
2075 | * A PCI bus walk, for each PCI host bridge. | |
2076 | * Insert scope for each PCI bridge and endpoint device which | |
2077 | * is attached to a bus with iommu enabled. | |
2078 | */ | |
2079 | object_child_foreach_recursive(object_get_root(), | |
2080 | dmar_host_bridges, scope_blob); | |
d46114f9 PX |
2081 | |
2082 | assert(iommu); | |
a924b3d8 | 2083 | if (x86_iommu_ir_supported(iommu)) { |
d46114f9 PX |
2084 | dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ |
2085 | } | |
d4eb9119 | 2086 | |
91a6b975 IM |
2087 | acpi_table_begin(&table, table_data); |
2088 | /* Host Address Width */ | |
2089 | build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); | |
2090 | build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ | |
2091 | g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ | |
2092 | ||
2093 | /* 8.3 DMAR Remapping Hardware Unit Definition structure */ | |
2094 | build_append_int_noprefix(table_data, 0, 2); /* Type */ | |
2095 | /* Length */ | |
2096 | build_append_int_noprefix(table_data, | |
2097 | 16 + ioapic_scope_size + scope_blob->len, 2); | |
2098 | /* Flags */ | |
2099 | build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , | |
2100 | 1); | |
2101 | build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ | |
2102 | build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ | |
2103 | /* Register Base Address */ | |
2104 | build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); | |
d4eb9119 | 2105 | |
cfc13df4 PX |
2106 | /* Scope definition for the root-complex IOAPIC. See VT-d spec |
2107 | * 8.3.1 (version Oct. 2014 or later). */ | |
91a6b975 IM |
2108 | build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ |
2109 | build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ | |
2110 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
2111 | /* Enumeration ID */ | |
2112 | build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); | |
2113 | /* Start Bus Number */ | |
2114 | build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); | |
2115 | /* Path, {Device, Function} pair */ | |
2116 | build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); | |
2117 | build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); | |
cfc13df4 | 2118 | |
26863366 XW |
2119 | /* Add scope found above */ |
2120 | g_array_append_vals(table_data, scope_blob->data, scope_blob->len); | |
2121 | g_array_free(scope_blob, true); | |
2122 | ||
bd2baacc | 2123 | if (iommu->dt_supported) { |
91a6b975 IM |
2124 | /* 8.5 Root Port ATS Capability Reporting Structure */ |
2125 | build_append_int_noprefix(table_data, 2, 2); /* Type */ | |
2126 | build_append_int_noprefix(table_data, 8, 2); /* Length */ | |
2127 | build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ | |
2128 | build_append_int_noprefix(table_data, 0, 1); /* Reserved */ | |
2129 | build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ | |
bd2baacc JW |
2130 | } |
2131 | ||
91a6b975 | 2132 | acpi_table_end(linker, &table); |
d4eb9119 | 2133 | } |
14cda350 LA |
2134 | |
2135 | /* | |
2136 | * Windows ACPI Emulated Devices Table | |
2137 | * (Version 1.0 - April 6, 2009) | |
2138 | * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx | |
2139 | * | |
2140 | * Helpful to speedup Windows guests and ignored by others. | |
2141 | */ | |
2142 | static void | |
602b4582 MP |
2143 | build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, |
2144 | const char *oem_table_id) | |
14cda350 | 2145 | { |
eaa50764 IM |
2146 | AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, |
2147 | .oem_table_id = oem_table_id }; | |
14cda350 | 2148 | |
eaa50764 | 2149 | acpi_table_begin(&table, table_data); |
14cda350 LA |
2150 | /* |
2151 | * Set "ACPI PM timer good" flag. | |
2152 | * | |
2153 | * Tells Windows guests that our ACPI PM timer is reliable in the | |
2154 | * sense that guest can read it only once to obtain a reliable value. | |
2155 | * Which avoids costly VMExits caused by guest re-reading it unnecessarily. | |
2156 | */ | |
2157 | build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); | |
eaa50764 | 2158 | acpi_table_end(linker, &table); |
14cda350 LA |
2159 | } |
2160 | ||
fb9f5926 DK |
2161 | /* |
2162 | * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 | |
2163 | * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf | |
2164 | */ | |
c028818d BS |
2165 | #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) |
2166 | ||
977aff10 AW |
2167 | /* |
2168 | * Insert IVHD entry for device and recurse, insert alias, or insert range as | |
2169 | * necessary for the PCI topology. | |
2170 | */ | |
2171 | static void | |
2172 | insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) | |
2173 | { | |
2174 | GArray *table_data = opaque; | |
2175 | uint32_t entry; | |
2176 | ||
2177 | /* "Select" IVHD entry, type 0x2 */ | |
2178 | entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; | |
2179 | build_append_int_noprefix(table_data, entry, 4); | |
2180 | ||
2181 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { | |
2182 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); | |
2183 | uint8_t sec = pci_bus_num(sec_bus); | |
2184 | uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; | |
2185 | ||
2186 | if (pci_bus_is_express(sec_bus)) { | |
2187 | /* | |
2188 | * Walk the bus if there are subordinates, otherwise use a range | |
2189 | * to cover an entire leaf bus. We could potentially also use a | |
2190 | * range for traversed buses, but we'd need to take care not to | |
2191 | * create both Select and Range entries covering the same device. | |
2192 | * This is easier and potentially more compact. | |
2193 | * | |
2194 | * An example bare metal system seems to use Select entries for | |
2195 | * root ports without a slot (ie. built-ins) and Range entries | |
2196 | * when there is a slot. The same system also only hard-codes | |
2197 | * the alias range for an onboard PCIe-to-PCI bridge, apparently | |
2198 | * making no effort to support nested bridges. We attempt to | |
2199 | * be more thorough here. | |
2200 | */ | |
2201 | if (sec == sub) { /* leaf bus */ | |
2202 | /* "Start of Range" IVHD entry, type 0x3 */ | |
2203 | entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; | |
2204 | build_append_int_noprefix(table_data, entry, 4); | |
2205 | /* "End of Range" IVHD entry, type 0x4 */ | |
2206 | entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; | |
2207 | build_append_int_noprefix(table_data, entry, 4); | |
2208 | } else { | |
2209 | pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); | |
2210 | } | |
2211 | } else { | |
2212 | /* | |
2213 | * If the secondary bus is conventional, then we need to create an | |
2214 | * Alias range for everything downstream. The range covers the | |
2215 | * first devfn on the secondary bus to the last devfn on the | |
2216 | * subordinate bus. The alias target depends on legacy versus | |
2217 | * express bridges, just as in pci_device_iommu_address_space(). | |
2218 | * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. | |
2219 | */ | |
2220 | uint16_t dev_id_a, dev_id_b; | |
2221 | ||
2222 | dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); | |
2223 | ||
2224 | if (pci_is_express(dev) && | |
2225 | pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
2226 | dev_id_b = dev_id_a; | |
2227 | } else { | |
2228 | dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); | |
2229 | } | |
2230 | ||
2231 | /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ | |
2232 | build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); | |
2233 | build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); | |
2234 | ||
2235 | /* "End of Range" IVHD entry, type 0x4 */ | |
2236 | entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; | |
2237 | build_append_int_noprefix(table_data, entry, 4); | |
2238 | } | |
2239 | } | |
2240 | } | |
2241 | ||
2242 | /* For all PCI host bridges, walk and insert IVHD entries */ | |
2243 | static int | |
2244 | ivrs_host_bridges(Object *obj, void *opaque) | |
2245 | { | |
2246 | GArray *ivhd_blob = opaque; | |
2247 | ||
2248 | if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { | |
2249 | PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; | |
2250 | ||
dec2f563 | 2251 | if (bus && !pci_bus_bypass_iommu(bus)) { |
2914fc61 | 2252 | pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); |
977aff10 AW |
2253 | } |
2254 | } | |
2255 | ||
2256 | return 0; | |
2257 | } | |
2258 | ||
fb9f5926 | 2259 | static void |
602b4582 MP |
2260 | build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, |
2261 | const char *oem_table_id) | |
fb9f5926 | 2262 | { |
977aff10 | 2263 | int ivhd_table_len = 24; |
fb9f5926 | 2264 | AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); |
977aff10 | 2265 | GArray *ivhd_blob = g_array_new(false, true, 1); |
b0a45ff6 IM |
2266 | AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, |
2267 | .oem_table_id = oem_table_id }; | |
fb9f5926 | 2268 | |
b0a45ff6 | 2269 | acpi_table_begin(&table, table_data); |
fb9f5926 DK |
2270 | /* IVinfo - IO virtualization information common to all |
2271 | * IOMMU units in a system | |
2272 | */ | |
2273 | build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); | |
2274 | /* reserved */ | |
2275 | build_append_int_noprefix(table_data, 0, 8); | |
2276 | ||
2277 | /* IVHD definition - type 10h */ | |
2278 | build_append_int_noprefix(table_data, 0x10, 1); | |
2279 | /* virtualization flags */ | |
2280 | build_append_int_noprefix(table_data, | |
2281 | (1UL << 0) | /* HtTunEn */ | |
2282 | (1UL << 4) | /* iotblSup */ | |
2283 | (1UL << 6) | /* PrefSup */ | |
2284 | (1UL << 7), /* PPRSup */ | |
2285 | 1); | |
c028818d | 2286 | |
977aff10 AW |
2287 | /* |
2288 | * A PCI bus walk, for each PCI host bridge, is necessary to create a | |
2289 | * complete set of IVHD entries. Do this into a separate blob so that we | |
2290 | * can calculate the total IVRS table length here and then append the new | |
2291 | * blob further below. Fall back to an entry covering all devices, which | |
2292 | * is sufficient when no aliases are present. | |
2293 | */ | |
2294 | object_child_foreach_recursive(object_get_root(), | |
2295 | ivrs_host_bridges, ivhd_blob); | |
2296 | ||
2297 | if (!ivhd_blob->len) { | |
2298 | /* | |
2299 | * Type 1 device entry reporting all devices | |
2300 | * These are 4-byte device entries currently reporting the range of | |
2301 | * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) | |
2302 | */ | |
2303 | build_append_int_noprefix(ivhd_blob, 0x0000001, 4); | |
2304 | } | |
2305 | ||
2306 | ivhd_table_len += ivhd_blob->len; | |
2307 | ||
c028818d BS |
2308 | /* |
2309 | * When interrupt remapping is supported, we add a special IVHD device | |
2310 | * for type IO-APIC. | |
2311 | */ | |
a924b3d8 | 2312 | if (x86_iommu_ir_supported(x86_iommu_get_default())) { |
c028818d BS |
2313 | ivhd_table_len += 8; |
2314 | } | |
977aff10 | 2315 | |
fb9f5926 | 2316 | /* IVHD length */ |
c028818d | 2317 | build_append_int_noprefix(table_data, ivhd_table_len, 2); |
fb9f5926 DK |
2318 | /* DeviceID */ |
2319 | build_append_int_noprefix(table_data, s->devid, 2); | |
2320 | /* Capability offset */ | |
2321 | build_append_int_noprefix(table_data, s->capab_offset, 2); | |
2322 | /* IOMMU base address */ | |
2323 | build_append_int_noprefix(table_data, s->mmio.addr, 8); | |
2324 | /* PCI Segment Group */ | |
2325 | build_append_int_noprefix(table_data, 0, 2); | |
2326 | /* IOMMU info */ | |
2327 | build_append_int_noprefix(table_data, 0, 2); | |
2328 | /* IOMMU Feature Reporting */ | |
2329 | build_append_int_noprefix(table_data, | |
2330 | (48UL << 30) | /* HATS */ | |
2331 | (48UL << 28) | /* GATS */ | |
12499b23 BS |
2332 | (1UL << 2) | /* GTSup */ |
2333 | (1UL << 6), /* GASup */ | |
fb9f5926 | 2334 | 4); |
977aff10 AW |
2335 | |
2336 | /* IVHD entries as found above */ | |
2337 | g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); | |
2338 | g_array_free(ivhd_blob, TRUE); | |
fb9f5926 | 2339 | |
c028818d BS |
2340 | /* |
2341 | * Add a special IVHD device type. | |
2342 | * Refer to spec - Table 95: IVHD device entry type codes | |
2343 | * | |
2344 | * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). | |
2345 | * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' | |
2346 | */ | |
a924b3d8 | 2347 | if (x86_iommu_ir_supported(x86_iommu_get_default())) { |
c028818d BS |
2348 | build_append_int_noprefix(table_data, |
2349 | (0x1ull << 56) | /* type IOAPIC */ | |
2350 | (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ | |
2351 | 0x48, /* special device */ | |
2352 | 8); | |
2353 | } | |
b0a45ff6 | 2354 | acpi_table_end(linker, &table); |
fb9f5926 | 2355 | } |
d4eb9119 | 2356 | |
72c194f7 MT |
2357 | typedef |
2358 | struct AcpiBuildState { | |
2359 | /* Copy of table in RAM (for patching). */ | |
339240b5 | 2360 | MemoryRegion *table_mr; |
72c194f7 MT |
2361 | /* Is table patched? */ |
2362 | uint8_t patched; | |
d70414a5 | 2363 | void *rsdp; |
339240b5 PB |
2364 | MemoryRegion *rsdp_mr; |
2365 | MemoryRegion *linker_mr; | |
72c194f7 MT |
2366 | } AcpiBuildState; |
2367 | ||
2368 | static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) | |
2369 | { | |
2370 | Object *pci_host; | |
2371 | QObject *o; | |
72c194f7 | 2372 | |
ca6c1855 | 2373 | pci_host = acpi_get_i386_pci_host(); |
c0e427d6 JS |
2374 | if (!pci_host) { |
2375 | return false; | |
2376 | } | |
72c194f7 MT |
2377 | |
2378 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); | |
2379 | if (!o) { | |
2380 | return false; | |
2381 | } | |
c309434e | 2382 | mcfg->base = qnum_get_uint(qobject_to(QNum, o)); |
cb3e7f08 | 2383 | qobject_unref(o); |
c309434e | 2384 | if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { |
fe4970ad IM |
2385 | return false; |
2386 | } | |
72c194f7 MT |
2387 | |
2388 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); | |
2389 | assert(o); | |
c309434e | 2390 | mcfg->size = qnum_get_uint(qobject_to(QNum, o)); |
cb3e7f08 | 2391 | qobject_unref(o); |
72c194f7 MT |
2392 | return true; |
2393 | } | |
2394 | ||
2395 | static | |
3d3ebcad | 2396 | void acpi_build(AcpiBuildTables *tables, MachineState *machine) |
72c194f7 | 2397 | { |
3d3ebcad | 2398 | PCMachineState *pcms = PC_MACHINE(machine); |
bb292f5a | 2399 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 2400 | X86MachineState *x86ms = X86_MACHINE(machine); |
36efa250 | 2401 | DeviceState *iommu = pcms->iommu; |
72c194f7 | 2402 | GArray *table_offsets; |
41fa5c04 | 2403 | unsigned facs, dsdt, rsdt, fadt; |
72c194f7 MT |
2404 | AcpiPmInfo pm; |
2405 | AcpiMiscInfo misc; | |
2406 | AcpiMcfgInfo mcfg; | |
c0e427d6 | 2407 | Range pci_hole = {}, pci_hole64 = {}; |
72c194f7 | 2408 | uint8_t *u; |
07fb6176 | 2409 | size_t aml_len = 0; |
7c2c1fa5 | 2410 | GArray *tables_blob = tables->table_data; |
ae123749 | 2411 | AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; |
d03637bc | 2412 | Object *vmgenid_dev; |
602b4582 MP |
2413 | char *oem_id; |
2414 | char *oem_table_id; | |
72c194f7 | 2415 | |
0e11fc69 | 2416 | acpi_get_pm_info(machine, &pm); |
72c194f7 | 2417 | acpi_get_misc_info(&misc); |
01c9742d | 2418 | acpi_get_pci_holes(&pci_hole, &pci_hole64); |
ae123749 | 2419 | acpi_get_slic_oem(&slic_oem); |
72c194f7 | 2420 | |
602b4582 MP |
2421 | if (slic_oem.id) { |
2422 | oem_id = slic_oem.id; | |
2423 | } else { | |
d07b2286 | 2424 | oem_id = x86ms->oem_id; |
602b4582 MP |
2425 | } |
2426 | ||
2427 | if (slic_oem.table_id) { | |
2428 | oem_table_id = slic_oem.table_id; | |
2429 | } else { | |
d07b2286 | 2430 | oem_table_id = x86ms->oem_table_id; |
602b4582 MP |
2431 | } |
2432 | ||
72c194f7 MT |
2433 | table_offsets = g_array_new(false, true /* clear */, |
2434 | sizeof(uint32_t)); | |
8b310fc4 | 2435 | ACPI_BUILD_DPRINTF("init ACPI tables\n"); |
72c194f7 | 2436 | |
ad9671b8 IM |
2437 | bios_linker_loader_alloc(tables->linker, |
2438 | ACPI_BUILD_TABLE_FILE, tables_blob, | |
72c194f7 MT |
2439 | 64 /* Ensure FACS is aligned */, |
2440 | false /* high memory */); | |
2441 | ||
2442 | /* | |
2443 | * FACS is pointed to by FADT. | |
2444 | * We place it first since it's the only table that has alignment | |
2445 | * requirements. | |
2446 | */ | |
7c2c1fa5 | 2447 | facs = tables_blob->len; |
009180bd | 2448 | build_facs(tables_blob); |
72c194f7 MT |
2449 | |
2450 | /* DSDT is pointed to by FADT */ | |
7c2c1fa5 | 2451 | dsdt = tables_blob->len; |
01c9742d MA |
2452 | build_dsdt(tables_blob, tables->linker, &pm, &misc, |
2453 | &pci_hole, &pci_hole64, machine); | |
72c194f7 | 2454 | |
07fb6176 PB |
2455 | /* Count the size of the DSDT and SSDT, we will need it for legacy |
2456 | * sizing of ACPI tables. | |
2457 | */ | |
7c2c1fa5 | 2458 | aml_len += tables_blob->len - dsdt; |
07fb6176 | 2459 | |
72c194f7 | 2460 | /* ACPI tables pointed to by RSDT */ |
41fa5c04 | 2461 | fadt = tables_blob->len; |
7c2c1fa5 | 2462 | acpi_add_table(table_offsets, tables_blob); |
937d1b58 IM |
2463 | pm.fadt.facs_tbl_offset = &facs; |
2464 | pm.fadt.dsdt_tbl_offset = &dsdt; | |
2465 | pm.fadt.xdsdt_tbl_offset = &dsdt; | |
602b4582 | 2466 | build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); |
41fa5c04 | 2467 | aml_len += tables_blob->len - fadt; |
72c194f7 | 2468 | |
7c2c1fa5 | 2469 | acpi_add_table(table_offsets, tables_blob); |
eb66ffab | 2470 | acpi_build_madt(tables_blob, tables->linker, x86ms, |
d07b2286 MP |
2471 | ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, |
2472 | x86ms->oem_table_id); | |
9ac1c4c0 | 2473 | |
8486f12f ED |
2474 | #ifdef CONFIG_ACPI_ERST |
2475 | { | |
2476 | Object *erst_dev; | |
2477 | erst_dev = find_erst_dev(); | |
2478 | if (erst_dev) { | |
2479 | acpi_add_table(table_offsets, tables_blob); | |
2480 | build_erst(tables_blob, tables->linker, erst_dev, | |
2481 | x86ms->oem_id, x86ms->oem_table_id); | |
2482 | } | |
2483 | } | |
2484 | #endif | |
2485 | ||
d03637bc BW |
2486 | vmgenid_dev = find_vmgenid_dev(); |
2487 | if (vmgenid_dev) { | |
2488 | acpi_add_table(table_offsets, tables_blob); | |
2489 | vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, | |
d07b2286 | 2490 | tables->vmgenid, tables->linker, x86ms->oem_id); |
d03637bc BW |
2491 | } |
2492 | ||
72c194f7 | 2493 | if (misc.has_hpet) { |
7c2c1fa5 | 2494 | acpi_add_table(table_offsets, tables_blob); |
d07b2286 MP |
2495 | build_hpet(tables_blob, tables->linker, x86ms->oem_id, |
2496 | x86ms->oem_table_id); | |
711b20b4 | 2497 | } |
11fb99e6 | 2498 | #ifdef CONFIG_TPM |
5cb18b3d | 2499 | if (misc.tpm_version != TPM_VERSION_UNSPEC) { |
7e7c1b84 SB |
2500 | if (misc.tpm_version == TPM_VERSION_1_2) { |
2501 | acpi_add_table(table_offsets, tables_blob); | |
602b4582 | 2502 | build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, |
d07b2286 | 2503 | x86ms->oem_id, x86ms->oem_table_id); |
7e7c1b84 | 2504 | } else { /* TPM_VERSION_2_0 */ |
72d97b3a | 2505 | acpi_add_table(table_offsets, tables_blob); |
602b4582 | 2506 | build_tpm2(tables_blob, tables->linker, tables->tcpalog, |
d07b2286 | 2507 | x86ms->oem_id, x86ms->oem_table_id); |
5cb18b3d | 2508 | } |
72c194f7 | 2509 | } |
11fb99e6 | 2510 | #endif |
e77af21a | 2511 | if (machine->numa_state->num_nodes) { |
7c2c1fa5 | 2512 | acpi_add_table(table_offsets, tables_blob); |
3d3ebcad | 2513 | build_srat(tables_blob, tables->linker, machine); |
118154b7 | 2514 | if (machine->numa_state->have_numa_distance) { |
0f203430 | 2515 | acpi_add_table(table_offsets, tables_blob); |
d07b2286 MP |
2516 | build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, |
2517 | x86ms->oem_table_id); | |
0f203430 | 2518 | } |
e6f123c3 LJ |
2519 | if (machine->numa_state->hmat_enabled) { |
2520 | acpi_add_table(table_offsets, tables_blob); | |
602b4582 | 2521 | build_hmat(tables_blob, tables->linker, machine->numa_state, |
d07b2286 | 2522 | x86ms->oem_id, x86ms->oem_table_id); |
e6f123c3 | 2523 | } |
72c194f7 MT |
2524 | } |
2525 | if (acpi_get_mcfg(&mcfg)) { | |
7c2c1fa5 | 2526 | acpi_add_table(table_offsets, tables_blob); |
d07b2286 MP |
2527 | build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, |
2528 | x86ms->oem_table_id); | |
72c194f7 | 2529 | } |
867e9c9f JPB |
2530 | if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { |
2531 | acpi_add_table(table_offsets, tables_blob); | |
2532 | build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, | |
2533 | x86ms->oem_table_id); | |
2534 | } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { | |
2535 | acpi_add_table(table_offsets, tables_blob); | |
2536 | build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, | |
2537 | x86ms->oem_table_id); | |
36efa250 JPB |
2538 | } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { |
2539 | PCIDevice *pdev = PCI_DEVICE(iommu); | |
2540 | ||
2541 | acpi_add_table(table_offsets, tables_blob); | |
2542 | build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), | |
2543 | x86ms->oem_id, x86ms->oem_table_id); | |
d4eb9119 | 2544 | } |
f6a0d06b | 2545 | if (machine->nvdimms_state->is_enabled) { |
ad9671b8 | 2546 | nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, |
602b4582 | 2547 | machine->nvdimms_state, machine->ram_slots, |
d07b2286 | 2548 | x86ms->oem_id, x86ms->oem_table_id); |
87252e1b | 2549 | } |
1ebf9001 | 2550 | if (pcms->cxl_devices_state.is_enabled) { |
51359805 | 2551 | cxl_build_cedt(table_offsets, tables_blob, tables->linker, |
1ebf9001 | 2552 | x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); |
3d6a69b6 | 2553 | } |
87252e1b | 2554 | |
14cda350 | 2555 | acpi_add_table(table_offsets, tables_blob); |
d07b2286 | 2556 | build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); |
14cda350 | 2557 | |
72c194f7 MT |
2558 | /* Add tables supplied by user (if any) */ |
2559 | for (u = acpi_table_first(); u; u = acpi_table_next(u)) { | |
2560 | unsigned len = acpi_table_len(u); | |
2561 | ||
7c2c1fa5 IM |
2562 | acpi_add_table(table_offsets, tables_blob); |
2563 | g_array_append_vals(tables_blob, u, len); | |
72c194f7 MT |
2564 | } |
2565 | ||
2566 | /* RSDT is pointed to by RSDP */ | |
7c2c1fa5 | 2567 | rsdt = tables_blob->len; |
ae123749 | 2568 | build_rsdt(tables_blob, tables->linker, table_offsets, |
602b4582 | 2569 | oem_id, oem_table_id); |
72c194f7 MT |
2570 | |
2571 | /* RSDP is in FSEG memory, so allocate it separately */ | |
a46ce1c2 SO |
2572 | { |
2573 | AcpiRsdpData rsdp_data = { | |
2574 | .revision = 0, | |
d07b2286 | 2575 | .oem_id = x86ms->oem_id, |
a46ce1c2 SO |
2576 | .xsdt_tbl_offset = NULL, |
2577 | .rsdt_tbl_offset = &rsdt, | |
2578 | }; | |
2579 | build_rsdp(tables->rsdp, tables->linker, &rsdp_data); | |
2580 | if (!pcmc->rsdp_in_ram) { | |
2581 | /* We used to allocate some extra space for RSDP revision 2 but | |
2582 | * only used the RSDP revision 0 space. The extra bytes were | |
2583 | * zeroed out and not used. | |
2584 | * Here we continue wasting those extra 16 bytes to make sure we | |
2585 | * don't break migration for machine types 2.2 and older due to | |
2586 | * RSDP blob size mismatch. | |
2587 | */ | |
2588 | build_append_int_noprefix(tables->rsdp, 0, 16); | |
2589 | } | |
2590 | } | |
72c194f7 | 2591 | |
07fb6176 | 2592 | /* We'll expose it all to Guest so we want to reduce |
72c194f7 | 2593 | * chance of size changes. |
07fb6176 PB |
2594 | * |
2595 | * We used to align the tables to 4k, but of course this would | |
2596 | * too simple to be enough. 4k turned out to be too small an | |
2597 | * alignment very soon, and in fact it is almost impossible to | |
2598 | * keep the table size stable for all (max_cpus, max_memory_slots) | |
2599 | * combinations. So the table size is always 64k for pc-i440fx-2.1 | |
2600 | * and we give an error if the table grows beyond that limit. | |
2601 | * | |
2602 | * We still have the problem of migrating from "-M pc-i440fx-2.0". For | |
2603 | * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables | |
2604 | * than 2.0 and we can always pad the smaller tables with zeros. We can | |
2605 | * then use the exact size of the 2.0 tables. | |
2606 | * | |
2607 | * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. | |
72c194f7 | 2608 | */ |
bb292f5a | 2609 | if (pcmc->legacy_acpi_table_size) { |
07fb6176 PB |
2610 | /* Subtracting aml_len gives the size of fixed tables. Then add the |
2611 | * size of the PIIX4 DSDT/SSDT in QEMU 2.0. | |
2612 | */ | |
2613 | int legacy_aml_len = | |
bb292f5a | 2614 | pcmc->legacy_acpi_table_size + |
f0bb276b | 2615 | ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; |
07fb6176 | 2616 | int legacy_table_size = |
7c2c1fa5 | 2617 | ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, |
07fb6176 | 2618 | ACPI_BUILD_ALIGN_SIZE); |
7c2c1fa5 | 2619 | if (tables_blob->len > legacy_table_size) { |
07fb6176 | 2620 | /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ |
9e5d2c52 AF |
2621 | warn_report("ACPI table size %u exceeds %d bytes," |
2622 | " migration may not work", | |
2623 | tables_blob->len, legacy_table_size); | |
2624 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
2625 | " or PCI bridges."); | |
07fb6176 | 2626 | } |
7c2c1fa5 | 2627 | g_array_set_size(tables_blob, legacy_table_size); |
07fb6176 | 2628 | } else { |
868270f2 | 2629 | /* Make sure we have a buffer in case we need to resize the tables. */ |
7c2c1fa5 | 2630 | if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { |
18045fb9 | 2631 | /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ |
9e5d2c52 AF |
2632 | warn_report("ACPI table size %u exceeds %d bytes," |
2633 | " migration may not work", | |
2634 | tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); | |
2635 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
2636 | " or PCI bridges."); | |
18045fb9 | 2637 | } |
7c2c1fa5 | 2638 | acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); |
07fb6176 | 2639 | } |
72c194f7 | 2640 | |
0e9b9eda | 2641 | acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); |
72c194f7 MT |
2642 | |
2643 | /* Cleanup memory that's no longer used. */ | |
2644 | g_array_free(table_offsets, true); | |
8cdb99af IM |
2645 | g_free(slic_oem.id); |
2646 | g_free(slic_oem.table_id); | |
72c194f7 MT |
2647 | } |
2648 | ||
339240b5 | 2649 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) |
42d85900 MT |
2650 | { |
2651 | uint32_t size = acpi_data_len(data); | |
2652 | ||
2653 | /* Make sure RAM size is correct - in case it got changed e.g. by migration */ | |
339240b5 | 2654 | memory_region_ram_resize(mr, size, &error_abort); |
42d85900 | 2655 | |
339240b5 PB |
2656 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); |
2657 | memory_region_set_dirty(mr, 0, size); | |
42d85900 MT |
2658 | } |
2659 | ||
3f8752b4 | 2660 | static void acpi_build_update(void *build_opaque) |
72c194f7 MT |
2661 | { |
2662 | AcpiBuildState *build_state = build_opaque; | |
2663 | AcpiBuildTables tables; | |
2664 | ||
2665 | /* No state to update or already patched? Nothing to do. */ | |
2666 | if (!build_state || build_state->patched) { | |
2667 | return; | |
2668 | } | |
2669 | build_state->patched = 1; | |
2670 | ||
2671 | acpi_build_tables_init(&tables); | |
2672 | ||
3d3ebcad | 2673 | acpi_build(&tables, MACHINE(qdev_get_machine())); |
72c194f7 | 2674 | |
339240b5 | 2675 | acpi_ram_update(build_state->table_mr, tables.table_data); |
a1666142 | 2676 | |
42d85900 MT |
2677 | if (build_state->rsdp) { |
2678 | memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); | |
2679 | } else { | |
339240b5 | 2680 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); |
42d85900 | 2681 | } |
ad5b88b1 | 2682 | |
0e9b9eda | 2683 | acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); |
72c194f7 MT |
2684 | acpi_build_tables_cleanup(&tables, true); |
2685 | } | |
2686 | ||
2687 | static void acpi_build_reset(void *build_opaque) | |
2688 | { | |
2689 | AcpiBuildState *build_state = build_opaque; | |
2690 | build_state->patched = 0; | |
2691 | } | |
2692 | ||
72c194f7 MT |
2693 | static const VMStateDescription vmstate_acpi_build = { |
2694 | .name = "acpi_build", | |
2695 | .version_id = 1, | |
2696 | .minimum_version_id = 1, | |
d49805ae | 2697 | .fields = (VMStateField[]) { |
72c194f7 MT |
2698 | VMSTATE_UINT8(patched, AcpiBuildState), |
2699 | VMSTATE_END_OF_LIST() | |
2700 | }, | |
2701 | }; | |
2702 | ||
fb306ffe | 2703 | void acpi_setup(void) |
72c194f7 | 2704 | { |
fb306ffe | 2705 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); |
bb292f5a | 2706 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 2707 | X86MachineState *x86ms = X86_MACHINE(pcms); |
72c194f7 MT |
2708 | AcpiBuildTables tables; |
2709 | AcpiBuildState *build_state; | |
d03637bc | 2710 | Object *vmgenid_dev; |
11fb99e6 | 2711 | #ifdef CONFIG_TPM |
0fe24669 SB |
2712 | TPMIf *tpm; |
2713 | static FwCfgTPMConfig tpm_config; | |
11fb99e6 | 2714 | #endif |
72c194f7 | 2715 | |
f0bb276b | 2716 | if (!x86ms->fw_cfg) { |
8b310fc4 | 2717 | ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); |
72c194f7 MT |
2718 | return; |
2719 | } | |
2720 | ||
021746c1 | 2721 | if (!pcms->acpi_build_enabled) { |
8b310fc4 | 2722 | ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); |
72c194f7 MT |
2723 | return; |
2724 | } | |
2725 | ||
17e89077 | 2726 | if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { |
8b310fc4 | 2727 | ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); |
81adc513 MT |
2728 | return; |
2729 | } | |
2730 | ||
72c194f7 MT |
2731 | build_state = g_malloc0(sizeof *build_state); |
2732 | ||
72c194f7 | 2733 | acpi_build_tables_init(&tables); |
3d3ebcad | 2734 | acpi_build(&tables, MACHINE(pcms)); |
72c194f7 MT |
2735 | |
2736 | /* Now expose it all to Guest */ | |
82f76c67 WY |
2737 | build_state->table_mr = acpi_add_rom_blob(acpi_build_update, |
2738 | build_state, tables.table_data, | |
6930ba0d | 2739 | ACPI_BUILD_TABLE_FILE); |
339240b5 | 2740 | assert(build_state->table_mr != NULL); |
72c194f7 | 2741 | |
339240b5 | 2742 | build_state->linker_mr = |
82f76c67 | 2743 | acpi_add_rom_blob(acpi_build_update, build_state, |
6930ba0d | 2744 | tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); |
72c194f7 | 2745 | |
11fb99e6 | 2746 | #ifdef CONFIG_TPM |
f0bb276b | 2747 | fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, |
42a5b308 SB |
2748 | tables.tcpalog->data, acpi_data_len(tables.tcpalog)); |
2749 | ||
0fe24669 SB |
2750 | tpm = tpm_find(); |
2751 | if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { | |
2752 | tpm_config = (FwCfgTPMConfig) { | |
2753 | .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), | |
2754 | .tpm_version = tpm_get_version(tpm), | |
ac6dd31e | 2755 | .tpmppi_version = TPM_PPI_VERSION_1_30 |
0fe24669 | 2756 | }; |
f0bb276b | 2757 | fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", |
0fe24669 SB |
2758 | &tpm_config, sizeof tpm_config); |
2759 | } | |
11fb99e6 | 2760 | #endif |
0fe24669 | 2761 | |
d03637bc BW |
2762 | vmgenid_dev = find_vmgenid_dev(); |
2763 | if (vmgenid_dev) { | |
f0bb276b | 2764 | vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, |
d03637bc BW |
2765 | tables.vmgenid); |
2766 | } | |
2767 | ||
bb292f5a | 2768 | if (!pcmc->rsdp_in_ram) { |
358774d7 IM |
2769 | /* |
2770 | * Keep for compatibility with old machine types. | |
2771 | * Though RSDP is small, its contents isn't immutable, so | |
afaa2e4b | 2772 | * we'll update it along with the rest of tables on guest access. |
358774d7 | 2773 | */ |
afaa2e4b MT |
2774 | uint32_t rsdp_size = acpi_data_len(tables.rsdp); |
2775 | ||
2776 | build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); | |
f0bb276b | 2777 | fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, |
5f9252f7 | 2778 | acpi_build_update, NULL, build_state, |
baf2d5bf | 2779 | build_state->rsdp, rsdp_size, true); |
339240b5 | 2780 | build_state->rsdp_mr = NULL; |
358774d7 | 2781 | } else { |
42d85900 | 2782 | build_state->rsdp = NULL; |
82f76c67 WY |
2783 | build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, |
2784 | build_state, tables.rsdp, | |
6930ba0d | 2785 | ACPI_BUILD_RSDP_FILE); |
358774d7 | 2786 | } |
72c194f7 MT |
2787 | |
2788 | qemu_register_reset(acpi_build_reset, build_state); | |
2789 | acpi_build_reset(build_state); | |
2790 | vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); | |
2791 | ||
2792 | /* Cleanup tables but don't free the memory: we track it | |
2793 | * in build_state. | |
2794 | */ | |
2795 | acpi_build_tables_cleanup(&tables, false); | |
2796 | } |