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72c194f7 MT |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
4 | * Copyright (C) 2006 Fabrice Bellard | |
5 | * Copyright (C) 2013 Red Hat Inc | |
6 | * | |
7 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | ||
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | ||
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
b6a0aa05 | 23 | #include "qemu/osdep.h" |
da34e65c | 24 | #include "qapi/error.h" |
15280c36 | 25 | #include "qapi/qmp/qnum.h" |
72c194f7 | 26 | #include "acpi-build.h" |
eb66ffab | 27 | #include "acpi-common.h" |
72c194f7 | 28 | #include "qemu/bitmap.h" |
07fb6176 | 29 | #include "qemu/error-report.h" |
72c194f7 | 30 | #include "hw/pci/pci.h" |
6e4e3ae9 | 31 | #include "hw/cxl/cxl.h" |
2e5b09fd | 32 | #include "hw/core/cpu.h" |
fcf5ef2a | 33 | #include "target/i386/cpu.h" |
72c194f7 | 34 | #include "hw/timer/hpet.h" |
395e5fb4 | 35 | #include "hw/acpi/acpi-defs.h" |
72c194f7 | 36 | #include "hw/acpi/acpi.h" |
679dd1a9 | 37 | #include "hw/acpi/cpu.h" |
72c194f7 | 38 | #include "hw/nvram/fw_cfg.h" |
0058ae1d | 39 | #include "hw/acpi/bios-linker-loader.h" |
5876d9b5 | 40 | #include "hw/acpi/acpi_aml_interface.h" |
5334bf57 | 41 | #include "hw/input/i8042.h" |
bef3492d | 42 | #include "hw/acpi/memory_hotplug.h" |
711b20b4 SB |
43 | #include "sysemu/tpm.h" |
44 | #include "hw/acpi/tpm.h" | |
d03637bc | 45 | #include "hw/acpi/vmgenid.h" |
8486f12f | 46 | #include "hw/acpi/erst.h" |
2bfd0845 | 47 | #include "hw/acpi/piix4.h" |
5cb18b3d | 48 | #include "sysemu/tpm_backend.h" |
bcdb9064 | 49 | #include "hw/rtc/mc146818rtc_regs.h" |
d6454270 | 50 | #include "migration/vmstate.h" |
2cc0e2e8 | 51 | #include "hw/mem/memory-device.h" |
4b997690 | 52 | #include "hw/mem/nvdimm.h" |
1f3aba37 | 53 | #include "sysemu/numa.h" |
71e8a915 | 54 | #include "sysemu/reset.h" |
6775d15d | 55 | #include "hw/hyperv/vmbus-bridge.h" |
72c194f7 MT |
56 | |
57 | /* Supported chipsets: */ | |
fff123b8 | 58 | #include "hw/southbridge/piix.h" |
99fd437d | 59 | #include "hw/acpi/pcihp.h" |
89a289c7 | 60 | #include "hw/i386/fw_cfg.h" |
72c194f7 MT |
61 | #include "hw/i386/ich9.h" |
62 | #include "hw/pci/pci_bus.h" | |
63 | #include "hw/pci-host/q35.h" | |
1cf5fd57 | 64 | #include "hw/i386/x86-iommu.h" |
72c194f7 | 65 | |
19934e0e | 66 | #include "hw/acpi/aml-build.h" |
82f76c67 | 67 | #include "hw/acpi/utils.h" |
48cefd94 | 68 | #include "hw/acpi/pci.h" |
2a3282c6 | 69 | #include "hw/acpi/cxl.h" |
19934e0e | 70 | |
72c194f7 | 71 | #include "qom/qom-qobject.h" |
fb9f5926 DK |
72 | #include "hw/i386/amd_iommu.h" |
73 | #include "hw/i386/intel_iommu.h" | |
36efa250 | 74 | #include "hw/virtio/virtio-iommu.h" |
72c194f7 | 75 | |
e6f123c3 | 76 | #include "hw/acpi/hmat.h" |
36efa250 | 77 | #include "hw/acpi/viot.h" |
3d6a69b6 | 78 | #include "hw/acpi/cxl.h" |
86e91dd7 | 79 | |
8486f12f ED |
80 | #include CONFIG_DEVICES |
81 | ||
07fb6176 PB |
82 | /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and |
83 | * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows | |
84 | * a little bit, there should be plenty of free space since the DSDT | |
85 | * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. | |
86 | */ | |
87 | #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 | |
88 | #define ACPI_BUILD_ALIGN_SIZE 0x1000 | |
89 | ||
868270f2 | 90 | #define ACPI_BUILD_TABLE_SIZE 0x20000 |
18045fb9 | 91 | |
8b310fc4 GA |
92 | /* #define DEBUG_ACPI_BUILD */ |
93 | #ifdef DEBUG_ACPI_BUILD | |
94 | #define ACPI_BUILD_DPRINTF(fmt, ...) \ | |
95 | do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) | |
96 | #else | |
97 | #define ACPI_BUILD_DPRINTF(fmt, ...) | |
98 | #endif | |
99 | ||
72c194f7 MT |
100 | typedef struct AcpiPmInfo { |
101 | bool s3_disabled; | |
102 | bool s4_disabled; | |
133a2da4 | 103 | bool pcihp_bridge_en; |
6d837f1f | 104 | bool smi_on_cpuhp; |
892aae74 | 105 | bool smi_on_cpu_unplug; |
df4008c9 | 106 | bool pcihp_root_en; |
72c194f7 | 107 | uint8_t s4_val; |
937d1b58 | 108 | AcpiFadtData fadt; |
ddf1ec2f | 109 | uint16_t cpu_hp_io_base; |
500b11ea IM |
110 | uint16_t pcihp_io_base; |
111 | uint16_t pcihp_io_len; | |
72c194f7 MT |
112 | } AcpiPmInfo; |
113 | ||
114 | typedef struct AcpiMiscInfo { | |
e4db2798 | 115 | bool is_piix4; |
72c194f7 | 116 | bool has_hpet; |
11fb99e6 | 117 | #ifdef CONFIG_TPM |
5cb18b3d | 118 | TPMVersion tpm_version; |
11fb99e6 | 119 | #endif |
72c194f7 MT |
120 | const unsigned char *dsdt_code; |
121 | unsigned dsdt_size; | |
72c194f7 MT |
122 | } AcpiMiscInfo; |
123 | ||
99fd437d MT |
124 | typedef struct AcpiBuildPciBusHotplugState { |
125 | GArray *device_table; | |
126 | GArray *notify_table; | |
127 | struct AcpiBuildPciBusHotplugState *parent; | |
133a2da4 | 128 | bool pcihp_bridge_en; |
99fd437d MT |
129 | } AcpiBuildPciBusHotplugState; |
130 | ||
0fe24669 SB |
131 | typedef struct FwCfgTPMConfig { |
132 | uint32_t tpmppi_address; | |
133 | uint8_t tpm_version; | |
134 | uint8_t tpmppi_version; | |
135 | } QEMU_PACKED FwCfgTPMConfig; | |
136 | ||
4a441836 GH |
137 | static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); |
138 | ||
5c94b826 KL |
139 | const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { |
140 | .space_id = AML_AS_SYSTEM_IO, | |
141 | .address = NVDIMM_ACPI_IO_BASE, | |
142 | .bit_width = NVDIMM_ACPI_IO_LEN << 3 | |
143 | }; | |
144 | ||
0e11fc69 LX |
145 | static void init_common_fadt_data(MachineState *ms, Object *o, |
146 | AcpiFadtData *data) | |
937d1b58 | 147 | { |
33b44fda IY |
148 | X86MachineState *x86ms = X86_MACHINE(ms); |
149 | /* | |
150 | * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old | |
151 | * behavior for compatibility irrelevant to smm_enabled, which doesn't | |
152 | * comforms to ACPI spec. | |
153 | */ | |
154 | bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? | |
155 | true : x86_machine_is_smm_enabled(x86ms); | |
937d1b58 IM |
156 | uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); |
157 | AmlAddressSpace as = AML_AS_SYSTEM_IO; | |
158 | AcpiFadtData fadt = { | |
159 | .rev = 3, | |
160 | .flags = | |
161 | (1 << ACPI_FADT_F_WBINVD) | | |
162 | (1 << ACPI_FADT_F_PROC_C1) | | |
163 | (1 << ACPI_FADT_F_SLP_BUTTON) | | |
164 | (1 << ACPI_FADT_F_RTC_S4) | | |
165 | (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | | |
166 | /* APIC destination mode ("Flat Logical") has an upper limit of 8 | |
167 | * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be | |
168 | * used | |
169 | */ | |
0e11fc69 LX |
170 | ((ms->smp.max_cpus > 8) ? |
171 | (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), | |
937d1b58 IM |
172 | .int_model = 1 /* Multiple APIC */, |
173 | .rtc_century = RTC_CENTURY, | |
174 | .plvl2_lat = 0xfff /* C2 state not supported */, | |
175 | .plvl3_lat = 0xfff /* C3 state not supported */, | |
33b44fda | 176 | .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, |
937d1b58 IM |
177 | .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), |
178 | .acpi_enable_cmd = | |
33b44fda IY |
179 | smm_enabled ? |
180 | object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : | |
181 | 0, | |
937d1b58 | 182 | .acpi_disable_cmd = |
33b44fda IY |
183 | smm_enabled ? |
184 | object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : | |
185 | 0, | |
937d1b58 IM |
186 | .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, |
187 | .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, | |
188 | .address = io + 0x04 }, | |
189 | .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, | |
190 | .gpe0_blk = { .space_id = as, .bit_width = | |
191 | object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, | |
192 | .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) | |
193 | }, | |
194 | }; | |
5334bf57 LA |
195 | |
196 | /* | |
197 | * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture | |
198 | * Flags, bit offset 1 - 8042. | |
199 | */ | |
200 | fadt.iapc_boot_arch = iapc_boot_arch_8042(); | |
201 | ||
937d1b58 IM |
202 | *data = fadt; |
203 | } | |
204 | ||
81c48dd7 PMD |
205 | static Object *object_resolve_type_unambiguous(const char *typename) |
206 | { | |
207 | bool ambig; | |
208 | Object *o = object_resolve_path_type("", typename, &ambig); | |
209 | ||
210 | if (ambig || !o) { | |
211 | return NULL; | |
212 | } | |
213 | return o; | |
214 | } | |
215 | ||
0e11fc69 | 216 | static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) |
72c194f7 | 217 | { |
81c48dd7 PMD |
218 | Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); |
219 | Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); | |
697155cd | 220 | Object *obj = piix ? piix : lpc; |
72c194f7 | 221 | QObject *o; |
94aaca64 | 222 | pm->cpu_hp_io_base = 0; |
500b11ea IM |
223 | pm->pcihp_io_base = 0; |
224 | pm->pcihp_io_len = 0; | |
6d837f1f | 225 | pm->smi_on_cpuhp = false; |
892aae74 | 226 | pm->smi_on_cpu_unplug = false; |
937d1b58 | 227 | |
6fa5171f | 228 | assert(obj); |
a0628599 | 229 | init_common_fadt_data(machine, obj, &pm->fadt); |
72c194f7 | 230 | if (piix) { |
3a3fcc75 | 231 | /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ |
937d1b58 | 232 | pm->fadt.rev = 1; |
ddf1ec2f | 233 | pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; |
72c194f7 MT |
234 | } |
235 | if (lpc) { | |
6d837f1f IM |
236 | uint64_t smi_features = object_property_get_uint(lpc, |
237 | ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); | |
937d1b58 IM |
238 | struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, |
239 | .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; | |
240 | pm->fadt.reset_reg = r; | |
241 | pm->fadt.reset_val = 0xf; | |
242 | pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; | |
ddf1ec2f | 243 | pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; |
6d837f1f IM |
244 | pm->smi_on_cpuhp = |
245 | !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); | |
892aae74 IM |
246 | pm->smi_on_cpu_unplug = |
247 | !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); | |
72c194f7 | 248 | } |
caf108bc JS |
249 | pm->pcihp_io_base = |
250 | object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); | |
251 | pm->pcihp_io_len = | |
252 | object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); | |
72c194f7 | 253 | |
937d1b58 IM |
254 | /* The above need not be conditional on machine type because the reset port |
255 | * happens to be the same on PIIX (pc) and ICH9 (q35). */ | |
0063454a | 256 | QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); |
937d1b58 | 257 | |
72c194f7 MT |
258 | /* Fill in optional s3/s4 related properties */ |
259 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); | |
260 | if (o) { | |
7dc847eb | 261 | pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); |
72c194f7 MT |
262 | } else { |
263 | pm->s3_disabled = false; | |
264 | } | |
cb3e7f08 | 265 | qobject_unref(o); |
72c194f7 MT |
266 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); |
267 | if (o) { | |
7dc847eb | 268 | pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); |
72c194f7 MT |
269 | } else { |
270 | pm->s4_disabled = false; | |
271 | } | |
cb3e7f08 | 272 | qobject_unref(o); |
72c194f7 MT |
273 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); |
274 | if (o) { | |
7dc847eb | 275 | pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); |
72c194f7 MT |
276 | } else { |
277 | pm->s4_val = false; | |
278 | } | |
cb3e7f08 | 279 | qobject_unref(o); |
72c194f7 | 280 | |
133a2da4 | 281 | pm->pcihp_bridge_en = |
aa29466b | 282 | object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, |
133a2da4 | 283 | NULL); |
df4008c9 | 284 | pm->pcihp_root_en = |
aa29466b | 285 | object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, |
df4008c9 | 286 | NULL); |
72c194f7 MT |
287 | } |
288 | ||
72c194f7 MT |
289 | static void acpi_get_misc_info(AcpiMiscInfo *info) |
290 | { | |
81c48dd7 PMD |
291 | Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); |
292 | Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); | |
3db119da IM |
293 | assert(!!piix != !!lpc); |
294 | ||
295 | if (piix) { | |
296 | info->is_piix4 = true; | |
297 | } | |
298 | if (lpc) { | |
299 | info->is_piix4 = false; | |
300 | } | |
301 | ||
72c194f7 | 302 | info->has_hpet = hpet_find(); |
11fb99e6 | 303 | #ifdef CONFIG_TPM |
3dfd5a2a | 304 | info->tpm_version = tpm_get_version(tpm_find()); |
11fb99e6 | 305 | #endif |
72c194f7 MT |
306 | } |
307 | ||
ca6c1855 MA |
308 | /* |
309 | * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. | |
310 | * On i386 arch we only have two pci hosts, so we can look only for them. | |
311 | */ | |
c0e427d6 | 312 | Object *acpi_get_i386_pci_host(void) |
ca6c1855 MA |
313 | { |
314 | PCIHostState *host; | |
315 | ||
b914e741 | 316 | host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); |
ca6c1855 | 317 | if (!host) { |
b914e741 | 318 | host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); |
ca6c1855 MA |
319 | } |
320 | ||
321 | return OBJECT(host); | |
322 | } | |
323 | ||
01c9742d | 324 | static void acpi_get_pci_holes(Range *hole, Range *hole64) |
72c194f7 MT |
325 | { |
326 | Object *pci_host; | |
72c194f7 | 327 | |
ca6c1855 | 328 | pci_host = acpi_get_i386_pci_host(); |
c0e427d6 JS |
329 | |
330 | if (!pci_host) { | |
331 | return; | |
332 | } | |
72c194f7 | 333 | |
a0efbf16 | 334 | range_set_bounds1(hole, |
60555365 MAL |
335 | object_property_get_uint(pci_host, |
336 | PCI_HOST_PROP_PCI_HOLE_START, | |
337 | NULL), | |
338 | object_property_get_uint(pci_host, | |
339 | PCI_HOST_PROP_PCI_HOLE_END, | |
340 | NULL)); | |
a0efbf16 | 341 | range_set_bounds1(hole64, |
60555365 MAL |
342 | object_property_get_uint(pci_host, |
343 | PCI_HOST_PROP_PCI_HOLE64_START, | |
344 | NULL), | |
345 | object_property_get_uint(pci_host, | |
346 | PCI_HOST_PROP_PCI_HOLE64_END, | |
347 | NULL)); | |
72c194f7 MT |
348 | } |
349 | ||
72c194f7 MT |
350 | static void acpi_align_size(GArray *blob, unsigned align) |
351 | { | |
352 | /* Align size to multiple of given size. This reduces the chance | |
353 | * we need to change size in the future (breaking cross version migration). | |
354 | */ | |
134d42d6 | 355 | g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); |
72c194f7 MT |
356 | } |
357 | ||
cf68410b IM |
358 | /* |
359 | * ACPI spec 1.0b, | |
360 | * 5.2.6 Firmware ACPI Control Structure | |
361 | */ | |
72c194f7 | 362 | static void |
009180bd | 363 | build_facs(GArray *table_data) |
72c194f7 | 364 | { |
cf68410b IM |
365 | const char *sig = "FACS"; |
366 | const uint8_t reserved[40] = {}; | |
367 | ||
368 | g_array_append_vals(table_data, sig, 4); /* Signature */ | |
369 | build_append_int_noprefix(table_data, 64, 4); /* Length */ | |
370 | build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ | |
371 | build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ | |
372 | build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ | |
373 | build_append_int_noprefix(table_data, 0, 4); /* Flags */ | |
374 | g_array_append_vals(table_data, reserved, 40); /* Reserved */ | |
72c194f7 MT |
375 | } |
376 | ||
62b52c26 | 377 | static void build_append_pcihp_notify_entry(Aml *method, int slot) |
99fd437d | 378 | { |
62b52c26 IM |
379 | Aml *if_ctx; |
380 | int32_t devfn = PCI_DEVFN(slot, 0); | |
381 | ||
5530427f | 382 | if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); |
62b52c26 IM |
383 | aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); |
384 | aml_append(method, if_ctx); | |
99fd437d MT |
385 | } |
386 | ||
62b52c26 | 387 | static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, |
b23046ab | 388 | bool pcihp_bridge_en) |
99fd437d | 389 | { |
7dc847eb | 390 | Aml *dev, *notify_method = NULL, *method; |
99fd437d | 391 | QObject *bsel; |
b23046ab | 392 | PCIBus *sec; |
d7346e61 | 393 | int devfn; |
133a2da4 | 394 | |
99fd437d MT |
395 | bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); |
396 | if (bsel) { | |
7dc847eb | 397 | uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); |
62b52c26 IM |
398 | |
399 | aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); | |
4dbfc881 | 400 | notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); |
8dcf525a | 401 | } |
99fd437d | 402 | |
d7346e61 | 403 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
8dcf525a MT |
404 | DeviceClass *dc; |
405 | PCIDeviceClass *pc; | |
d7346e61 IM |
406 | PCIDevice *pdev = bus->devices[devfn]; |
407 | int slot = PCI_SLOT(devfn); | |
408 | int func = PCI_FUNC(devfn); | |
409 | /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ | |
410 | int adr = slot << 16 | func; | |
b23046ab | 411 | bool hotplug_enabled_dev; |
093a35e5 | 412 | bool bridge_in_acpi; |
15a5b254 | 413 | bool cold_plugged_bridge; |
99fd437d | 414 | |
8dcf525a | 415 | if (!pdev) { |
d7346e61 IM |
416 | /* |
417 | * add hotplug slots for non present devices. | |
418 | * hotplug is supported only for non-multifunction device | |
419 | * so generate device description only for function 0 | |
420 | */ | |
421 | if (bsel && !func) { | |
caf108bc JS |
422 | if (pci_bus_is_express(bus) && slot > 0) { |
423 | break; | |
424 | } | |
d7346e61 | 425 | dev = aml_device("S%.02X", devfn); |
62b52c26 | 426 | aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); |
d7346e61 | 427 | aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); |
4dbfc881 | 428 | method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); |
62b52c26 IM |
429 | aml_append(method, |
430 | aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) | |
431 | ); | |
432 | aml_append(dev, method); | |
b7f23f62 | 433 | method = aml_method("_DSM", 4, AML_SERIALIZED); |
467d099a IM |
434 | { |
435 | Aml *params = aml_local(0); | |
436 | Aml *pkg = aml_package(2); | |
437 | aml_append(pkg, aml_name("BSEL")); | |
438 | aml_append(pkg, aml_name("_SUN")); | |
439 | aml_append(method, aml_store(pkg, params)); | |
440 | aml_append(method, | |
441 | aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), | |
442 | aml_arg(2), aml_arg(3), params)) | |
443 | ); | |
444 | } | |
b7f23f62 | 445 | aml_append(dev, method); |
62b52c26 IM |
446 | aml_append(parent_scope, dev); |
447 | ||
448 | build_append_pcihp_notify_entry(notify_method, slot); | |
b23046ab | 449 | } |
8dcf525a MT |
450 | continue; |
451 | } | |
99fd437d | 452 | |
8dcf525a MT |
453 | pc = PCI_DEVICE_GET_CLASS(pdev); |
454 | dc = DEVICE_GET_CLASS(pdev); | |
99fd437d | 455 | |
15a5b254 AS |
456 | /* |
457 | * Cold plugged bridges aren't themselves hot-pluggable. | |
a20275fa | 458 | * Hotplugged bridges *are* hot-pluggable. |
093a35e5 | 459 | */ |
15a5b254 AS |
460 | cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; |
461 | bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; | |
b23046ab | 462 | |
15a5b254 | 463 | hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; |
093a35e5 | 464 | |
b23046ab IM |
465 | if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { |
466 | continue; | |
99fd437d MT |
467 | } |
468 | ||
d7346e61 IM |
469 | /* |
470 | * allow describing coldplugged bridges in ACPI even if they are not | |
471 | * on function 0, as they are not unpluggable, for all other devices | |
472 | * generate description only for function 0 per slot | |
473 | */ | |
474 | if (func && !bridge_in_acpi) { | |
475 | continue; | |
476 | } | |
477 | ||
478 | /* start to compose PCI device descriptor */ | |
479 | dev = aml_device("S%.02X", devfn); | |
480 | aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); | |
62b52c26 | 481 | |
b7f23f62 | 482 | if (bsel) { |
7193d7cd IM |
483 | /* |
484 | * Can't declare _SUN here for every device as it changes 'slot' | |
485 | * enumeration order in linux kernel, so use another variable for it | |
486 | */ | |
487 | aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); | |
b7f23f62 | 488 | method = aml_method("_DSM", 4, AML_SERIALIZED); |
467d099a IM |
489 | { |
490 | Aml *params = aml_local(0); | |
491 | Aml *pkg = aml_package(2); | |
492 | aml_append(pkg, aml_name("BSEL")); | |
493 | aml_append(pkg, aml_name("ASUN")); | |
494 | aml_append(method, aml_store(pkg, params)); | |
495 | aml_append(method, aml_return( | |
496 | aml_call5("PDSM", aml_arg(0), aml_arg(1), aml_arg(2), | |
497 | aml_arg(3), params) | |
498 | )); | |
499 | } | |
b7f23f62 IM |
500 | aml_append(dev, method); |
501 | } | |
502 | ||
8dcf525a | 503 | if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { |
62b52c26 IM |
504 | /* add VGA specific AML methods */ |
505 | int s3d; | |
506 | ||
8dcf525a | 507 | if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { |
62b52c26 | 508 | s3d = 3; |
b23046ab | 509 | } else { |
62b52c26 | 510 | s3d = 0; |
99fd437d | 511 | } |
62b52c26 | 512 | |
4dbfc881 | 513 | method = aml_method("_S1D", 0, AML_NOTSERIALIZED); |
62b52c26 IM |
514 | aml_append(method, aml_return(aml_int(0))); |
515 | aml_append(dev, method); | |
516 | ||
4dbfc881 | 517 | method = aml_method("_S2D", 0, AML_NOTSERIALIZED); |
62b52c26 IM |
518 | aml_append(method, aml_return(aml_int(0))); |
519 | aml_append(dev, method); | |
520 | ||
4dbfc881 | 521 | method = aml_method("_S3D", 0, AML_NOTSERIALIZED); |
62b52c26 IM |
522 | aml_append(method, aml_return(aml_int(s3d))); |
523 | aml_append(dev, method); | |
b23046ab | 524 | } else if (hotplug_enabled_dev) { |
7193d7cd | 525 | aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); |
b7f23f62 | 526 | /* add _EJ0 to make slot hotpluggable */ |
4dbfc881 | 527 | method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); |
62b52c26 IM |
528 | aml_append(method, |
529 | aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) | |
530 | ); | |
531 | aml_append(dev, method); | |
532 | ||
533 | if (bsel) { | |
534 | build_append_pcihp_notify_entry(notify_method, slot); | |
535 | } | |
b23046ab | 536 | } else if (bridge_in_acpi) { |
62b52c26 IM |
537 | /* |
538 | * device is coldplugged bridge, | |
539 | * add child device descriptions into its scope | |
540 | */ | |
b23046ab | 541 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); |
b23046ab | 542 | |
62b52c26 | 543 | build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); |
8dcf525a | 544 | } |
d7346e61 | 545 | /* device descriptor has been composed, add it into parent context */ |
62b52c26 | 546 | aml_append(parent_scope, dev); |
8dcf525a MT |
547 | } |
548 | ||
549 | if (bsel) { | |
62b52c26 | 550 | aml_append(parent_scope, notify_method); |
99fd437d MT |
551 | } |
552 | ||
553 | /* Append PCNT method to notify about events on local and child buses. | |
df4008c9 AS |
554 | * Add this method for root bus only when hotplug is enabled since DSDT |
555 | * expects it. | |
72c194f7 | 556 | */ |
df4008c9 AS |
557 | if (bsel || pcihp_bridge_en) { |
558 | method = aml_method("PCNT", 0, AML_NOTSERIALIZED); | |
01b2ffce | 559 | |
811c74fb PMD |
560 | /* If bus supports hotplug select it and notify about local events */ |
561 | if (bsel) { | |
562 | uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); | |
563 | ||
564 | aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); | |
565 | aml_append(method, aml_call2("DVNT", aml_name("PCIU"), | |
566 | aml_int(1))); /* Device Check */ | |
567 | aml_append(method, aml_call2("DVNT", aml_name("PCID"), | |
568 | aml_int(3))); /* Eject Request */ | |
569 | } | |
99fd437d | 570 | |
811c74fb PMD |
571 | /* Notify about child bus events in any case */ |
572 | if (pcihp_bridge_en) { | |
573 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
caf108bc | 574 | if (pci_bus_is_root(sec)) { |
811c74fb PMD |
575 | continue; |
576 | } | |
c99cb18e | 577 | |
d7346e61 IM |
578 | aml_append(method, aml_name("^S%.02X.PCNT", |
579 | sec->parent_dev->devfn)); | |
811c74fb | 580 | } |
99fd437d | 581 | } |
df4008c9 | 582 | |
df4008c9 AS |
583 | aml_append(parent_scope, method); |
584 | } | |
cb3e7f08 | 585 | qobject_unref(bsel); |
72c194f7 MT |
586 | } |
587 | ||
b7f23f62 IM |
588 | Aml *aml_pci_device_dsm(void) |
589 | { | |
a12cf692 IM |
590 | Aml *method, *UUID, *ifctx, *ifctx1; |
591 | Aml *ret = aml_local(0); | |
592 | Aml *caps = aml_local(1); | |
593 | Aml *acpi_index = aml_local(2); | |
b7f23f62 | 594 | Aml *zero = aml_int(0); |
a12cf692 | 595 | Aml *one = aml_int(1); |
b7f23f62 IM |
596 | Aml *func = aml_arg(2); |
597 | Aml *rev = aml_arg(1); | |
467d099a IM |
598 | Aml *params = aml_arg(4); |
599 | Aml *bnum = aml_derefof(aml_index(params, aml_int(0))); | |
600 | Aml *sunum = aml_derefof(aml_index(params, aml_int(1))); | |
b7f23f62 | 601 | |
467d099a | 602 | method = aml_method("PDSM", 5, AML_SERIALIZED); |
b7f23f62 | 603 | |
a12cf692 IM |
604 | /* get supported functions */ |
605 | ifctx = aml_if(aml_equal(func, zero)); | |
606 | { | |
607 | uint8_t byte_list[1] = { 0 }; /* nothing supported yet */ | |
608 | aml_append(ifctx, aml_store(aml_buffer(1, byte_list), ret)); | |
609 | aml_append(ifctx, aml_store(zero, caps)); | |
610 | ||
611 | /* | |
612 | * PCI Firmware Specification 3.1 | |
613 | * 4.6. _DSM Definitions for PCI | |
614 | */ | |
615 | UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); | |
616 | ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); | |
617 | { | |
618 | /* call is for unsupported UUID, bail out */ | |
619 | aml_append(ifctx1, aml_return(ret)); | |
620 | } | |
621 | aml_append(ifctx, ifctx1); | |
622 | ||
623 | ifctx1 = aml_if(aml_lless(rev, aml_int(2))); | |
624 | { | |
625 | /* call is for unsupported REV, bail out */ | |
626 | aml_append(ifctx1, aml_return(ret)); | |
627 | } | |
628 | aml_append(ifctx, ifctx1); | |
629 | ||
630 | aml_append(ifctx, | |
631 | aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); | |
632 | /* | |
633 | * advertise function 7 if device has acpi-index | |
634 | * acpi_index values: | |
635 | * 0: not present (default value) | |
636 | * FFFFFFFF: not supported (old QEMU without PIDX reg) | |
637 | * other: device's acpi-index | |
638 | */ | |
639 | ifctx1 = aml_if(aml_lnot( | |
640 | aml_or(aml_equal(acpi_index, zero), | |
641 | aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) | |
642 | )); | |
643 | { | |
644 | /* have supported functions */ | |
645 | aml_append(ifctx1, aml_or(caps, one, caps)); | |
646 | /* support for function 7 */ | |
647 | aml_append(ifctx1, | |
648 | aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); | |
649 | } | |
650 | aml_append(ifctx, ifctx1); | |
651 | ||
652 | aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); | |
653 | aml_append(ifctx, aml_return(ret)); | |
654 | } | |
655 | aml_append(method, ifctx); | |
656 | ||
657 | /* handle specific functions requests */ | |
b7f23f62 IM |
658 | /* |
659 | * PCI Firmware Specification 3.1 | |
a12cf692 IM |
660 | * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under |
661 | * Operating Systems | |
b7f23f62 | 662 | */ |
a12cf692 | 663 | ifctx = aml_if(aml_equal(func, aml_int(7))); |
b7f23f62 | 664 | { |
a12cf692 IM |
665 | Aml *pkg = aml_package(2); |
666 | ||
667 | aml_append(pkg, zero); | |
668 | /* | |
669 | * optional, if not impl. should return null string | |
670 | */ | |
671 | aml_append(pkg, aml_string("%s", "")); | |
672 | aml_append(ifctx, aml_store(pkg, ret)); | |
673 | ||
674 | aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); | |
675 | /* | |
676 | * update acpi-index to actual value | |
677 | */ | |
678 | aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero))); | |
467d099a | 679 | aml_append(ifctx, aml_return(ret)); |
b7f23f62 | 680 | } |
a12cf692 | 681 | |
b7f23f62 IM |
682 | aml_append(method, ifctx); |
683 | return method; | |
684 | } | |
685 | ||
196e2137 IM |
686 | /** |
687 | * build_prt_entry: | |
688 | * @link_name: link name for PCI route entry | |
689 | * | |
690 | * build AML package containing a PCI route entry for @link_name | |
691 | */ | |
692 | static Aml *build_prt_entry(const char *link_name) | |
693 | { | |
694 | Aml *a_zero = aml_int(0); | |
695 | Aml *pkg = aml_package(4); | |
696 | aml_append(pkg, a_zero); | |
697 | aml_append(pkg, a_zero); | |
698 | aml_append(pkg, aml_name("%s", link_name)); | |
699 | aml_append(pkg, a_zero); | |
700 | return pkg; | |
701 | } | |
702 | ||
0d8935e3 MA |
703 | /* |
704 | * initialize_route - Initialize the interrupt routing rule | |
705 | * through a specific LINK: | |
706 | * if (lnk_idx == idx) | |
707 | * route using link 'link_name' | |
708 | */ | |
709 | static Aml *initialize_route(Aml *route, const char *link_name, | |
710 | Aml *lnk_idx, int idx) | |
711 | { | |
712 | Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); | |
196e2137 | 713 | Aml *pkg = build_prt_entry(link_name); |
0d8935e3 | 714 | |
0d8935e3 MA |
715 | aml_append(if_ctx, aml_store(pkg, route)); |
716 | ||
717 | return if_ctx; | |
718 | } | |
719 | ||
720 | /* | |
721 | * build_prt - Define interrupt rounting rules | |
722 | * | |
723 | * Returns an array of 128 routes, one for each device, | |
724 | * based on device location. | |
725 | * The main goal is to equaly distribute the interrupts | |
726 | * over the 4 existing ACPI links (works only for i440fx). | |
727 | * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". | |
728 | * | |
729 | */ | |
196e2137 | 730 | static Aml *build_prt(bool is_pci0_prt) |
0d8935e3 MA |
731 | { |
732 | Aml *method, *while_ctx, *pin, *res; | |
733 | ||
4dbfc881 | 734 | method = aml_method("_PRT", 0, AML_NOTSERIALIZED); |
0d8935e3 MA |
735 | res = aml_local(0); |
736 | pin = aml_local(1); | |
737 | aml_append(method, aml_store(aml_package(128), res)); | |
738 | aml_append(method, aml_store(aml_int(0), pin)); | |
739 | ||
740 | /* while (pin < 128) */ | |
741 | while_ctx = aml_while(aml_lless(pin, aml_int(128))); | |
742 | { | |
743 | Aml *slot = aml_local(2); | |
744 | Aml *lnk_idx = aml_local(3); | |
745 | Aml *route = aml_local(4); | |
746 | ||
747 | /* slot = pin >> 2 */ | |
748 | aml_append(while_ctx, | |
c360639a | 749 | aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); |
0d8935e3 MA |
750 | /* lnk_idx = (slot + pin) & 3 */ |
751 | aml_append(while_ctx, | |
5530427f IM |
752 | aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), |
753 | lnk_idx)); | |
0d8935e3 MA |
754 | |
755 | /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ | |
756 | aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); | |
196e2137 IM |
757 | if (is_pci0_prt) { |
758 | Aml *if_device_1, *if_pin_4, *else_pin_4; | |
759 | ||
760 | /* device 1 is the power-management device, needs SCI */ | |
761 | if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); | |
762 | { | |
763 | if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); | |
764 | { | |
765 | aml_append(if_pin_4, | |
766 | aml_store(build_prt_entry("LNKS"), route)); | |
767 | } | |
768 | aml_append(if_device_1, if_pin_4); | |
769 | else_pin_4 = aml_else(); | |
770 | { | |
771 | aml_append(else_pin_4, | |
772 | aml_store(build_prt_entry("LNKA"), route)); | |
773 | } | |
774 | aml_append(if_device_1, else_pin_4); | |
775 | } | |
776 | aml_append(while_ctx, if_device_1); | |
777 | } else { | |
778 | aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); | |
779 | } | |
0d8935e3 MA |
780 | aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); |
781 | aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); | |
782 | ||
783 | /* route[0] = 0x[slot]FFFF */ | |
784 | aml_append(while_ctx, | |
ca3df95d IM |
785 | aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), |
786 | NULL), | |
0d8935e3 MA |
787 | aml_index(route, aml_int(0)))); |
788 | /* route[1] = pin & 3 */ | |
789 | aml_append(while_ctx, | |
5530427f IM |
790 | aml_store(aml_and(pin, aml_int(3), NULL), |
791 | aml_index(route, aml_int(1)))); | |
0d8935e3 MA |
792 | /* res[pin] = route */ |
793 | aml_append(while_ctx, aml_store(route, aml_index(res, pin))); | |
794 | /* pin++ */ | |
795 | aml_append(while_ctx, aml_increment(pin)); | |
796 | } | |
797 | aml_append(method, while_ctx); | |
798 | /* return res*/ | |
799 | aml_append(method, aml_return(res)); | |
800 | ||
801 | return method; | |
802 | } | |
803 | ||
a57d708d IM |
804 | static void build_hpet_aml(Aml *table) |
805 | { | |
806 | Aml *crs; | |
807 | Aml *field; | |
808 | Aml *method; | |
809 | Aml *if_ctx; | |
810 | Aml *scope = aml_scope("_SB"); | |
811 | Aml *dev = aml_device("HPET"); | |
812 | Aml *zero = aml_int(0); | |
813 | Aml *id = aml_local(0); | |
814 | Aml *period = aml_local(1); | |
815 | ||
816 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); | |
817 | aml_append(dev, aml_name_decl("_UID", zero)); | |
818 | ||
819 | aml_append(dev, | |
3f3009c0 XG |
820 | aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), |
821 | HPET_LEN)); | |
a57d708d IM |
822 | field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); |
823 | aml_append(field, aml_named_field("VEND", 32)); | |
824 | aml_append(field, aml_named_field("PRD", 32)); | |
825 | aml_append(dev, field); | |
826 | ||
827 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
828 | aml_append(method, aml_store(aml_name("VEND"), id)); | |
829 | aml_append(method, aml_store(aml_name("PRD"), period)); | |
830 | aml_append(method, aml_shiftright(id, aml_int(16), id)); | |
831 | if_ctx = aml_if(aml_lor(aml_equal(id, zero), | |
832 | aml_equal(id, aml_int(0xffff)))); | |
833 | { | |
834 | aml_append(if_ctx, aml_return(zero)); | |
835 | } | |
836 | aml_append(method, if_ctx); | |
837 | ||
838 | if_ctx = aml_if(aml_lor(aml_equal(period, zero), | |
839 | aml_lgreater(period, aml_int(100000000)))); | |
840 | { | |
841 | aml_append(if_ctx, aml_return(zero)); | |
842 | } | |
843 | aml_append(method, if_ctx); | |
844 | ||
845 | aml_append(method, aml_return(aml_int(0x0F))); | |
846 | aml_append(dev, method); | |
847 | ||
848 | crs = aml_resource_template(); | |
849 | aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); | |
850 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
851 | ||
852 | aml_append(scope, dev); | |
853 | aml_append(table, scope); | |
854 | } | |
855 | ||
6775d15d JD |
856 | static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) |
857 | { | |
858 | Aml *dev; | |
859 | Aml *method; | |
860 | Aml *crs; | |
861 | ||
862 | dev = aml_device("VMBS"); | |
863 | aml_append(dev, aml_name_decl("STA", aml_int(0xF))); | |
864 | aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); | |
865 | aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); | |
866 | aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); | |
867 | ||
868 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
869 | aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), | |
870 | aml_name("STA"))); | |
871 | aml_append(dev, method); | |
872 | ||
873 | method = aml_method("_PS0", 0, AML_NOTSERIALIZED); | |
874 | aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), | |
875 | aml_name("STA"))); | |
876 | aml_append(dev, method); | |
877 | ||
878 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
879 | aml_append(method, aml_return(aml_name("STA"))); | |
880 | aml_append(dev, method); | |
881 | ||
882 | aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); | |
883 | ||
884 | crs = aml_resource_template(); | |
8f06f22f | 885 | aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); |
6775d15d JD |
886 | aml_append(dev, aml_name_decl("_CRS", crs)); |
887 | ||
888 | return dev; | |
889 | } | |
890 | ||
3892a2b7 IM |
891 | static void build_dbg_aml(Aml *table) |
892 | { | |
893 | Aml *field; | |
894 | Aml *method; | |
895 | Aml *while_ctx; | |
896 | Aml *scope = aml_scope("\\"); | |
897 | Aml *buf = aml_local(0); | |
898 | Aml *len = aml_local(1); | |
899 | Aml *idx = aml_local(2); | |
900 | ||
901 | aml_append(scope, | |
3f3009c0 | 902 | aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); |
3892a2b7 IM |
903 | field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); |
904 | aml_append(field, aml_named_field("DBGB", 8)); | |
905 | aml_append(scope, field); | |
906 | ||
907 | method = aml_method("DBUG", 1, AML_NOTSERIALIZED); | |
908 | ||
909 | aml_append(method, aml_to_hexstring(aml_arg(0), buf)); | |
910 | aml_append(method, aml_to_buffer(buf, buf)); | |
911 | aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); | |
912 | aml_append(method, aml_store(aml_int(0), idx)); | |
913 | ||
914 | while_ctx = aml_while(aml_lless(idx, len)); | |
915 | aml_append(while_ctx, | |
916 | aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); | |
917 | aml_append(while_ctx, aml_increment(idx)); | |
918 | aml_append(method, while_ctx); | |
919 | ||
920 | aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); | |
921 | aml_append(scope, method); | |
922 | ||
923 | aml_append(table, scope); | |
924 | } | |
925 | ||
c35b6e80 IM |
926 | static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) |
927 | { | |
928 | Aml *dev; | |
929 | Aml *crs; | |
930 | Aml *method; | |
931 | uint32_t irqs[] = {5, 10, 11}; | |
932 | ||
933 | dev = aml_device("%s", name); | |
934 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); | |
935 | aml_append(dev, aml_name_decl("_UID", aml_int(uid))); | |
936 | ||
937 | crs = aml_resource_template(); | |
938 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
939 | AML_SHARED, irqs, ARRAY_SIZE(irqs))); | |
940 | aml_append(dev, aml_name_decl("_PRS", crs)); | |
941 | ||
942 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
943 | aml_append(method, aml_return(aml_call1("IQST", reg))); | |
944 | aml_append(dev, method); | |
945 | ||
946 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
947 | aml_append(method, aml_or(reg, aml_int(0x80), reg)); | |
948 | aml_append(dev, method); | |
949 | ||
950 | method = aml_method("_CRS", 0, AML_NOTSERIALIZED); | |
951 | aml_append(method, aml_return(aml_call1("IQCR", reg))); | |
952 | aml_append(dev, method); | |
953 | ||
954 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); | |
955 | aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); | |
956 | aml_append(method, aml_store(aml_name("PRRI"), reg)); | |
957 | aml_append(dev, method); | |
958 | ||
959 | return dev; | |
960 | } | |
961 | ||
80b32df5 IM |
962 | static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) |
963 | { | |
964 | Aml *dev; | |
965 | Aml *crs; | |
966 | Aml *method; | |
967 | uint32_t irqs; | |
968 | ||
969 | dev = aml_device("%s", name); | |
970 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); | |
971 | aml_append(dev, aml_name_decl("_UID", aml_int(uid))); | |
972 | ||
973 | crs = aml_resource_template(); | |
974 | irqs = gsi; | |
975 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
976 | AML_SHARED, &irqs, 1)); | |
977 | aml_append(dev, aml_name_decl("_PRS", crs)); | |
978 | ||
979 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
980 | ||
c82f503d MA |
981 | /* |
982 | * _DIS can be no-op because the interrupt cannot be disabled. | |
983 | */ | |
984 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
985 | aml_append(dev, method); | |
986 | ||
80b32df5 IM |
987 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); |
988 | aml_append(dev, method); | |
989 | ||
990 | return dev; | |
991 | } | |
992 | ||
16682a9d IM |
993 | /* _CRS method - get current settings */ |
994 | static Aml *build_iqcr_method(bool is_piix4) | |
995 | { | |
996 | Aml *if_ctx; | |
997 | uint32_t irqs; | |
998 | Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); | |
999 | Aml *crs = aml_resource_template(); | |
1000 | ||
1001 | irqs = 0; | |
1002 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, | |
1003 | AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); | |
1004 | aml_append(method, aml_name_decl("PRR0", crs)); | |
1005 | ||
1006 | aml_append(method, | |
1007 | aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); | |
1008 | ||
1009 | if (is_piix4) { | |
1010 | if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); | |
1011 | aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); | |
1012 | aml_append(method, if_ctx); | |
1013 | } else { | |
1014 | aml_append(method, | |
1015 | aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), | |
1016 | aml_name("PRRI"))); | |
1017 | } | |
1018 | ||
1019 | aml_append(method, aml_return(aml_name("PRR0"))); | |
1020 | return method; | |
1021 | } | |
1022 | ||
78e1ad05 IM |
1023 | /* _STA method - get status */ |
1024 | static Aml *build_irq_status_method(void) | |
1025 | { | |
1026 | Aml *if_ctx; | |
1027 | Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); | |
1028 | ||
1029 | if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); | |
1030 | aml_append(if_ctx, aml_return(aml_int(0x09))); | |
1031 | aml_append(method, if_ctx); | |
1032 | aml_append(method, aml_return(aml_int(0x0B))); | |
1033 | return method; | |
1034 | } | |
1035 | ||
e4db2798 IM |
1036 | static void build_piix4_pci0_int(Aml *table) |
1037 | { | |
c35b6e80 IM |
1038 | Aml *dev; |
1039 | Aml *crs; | |
e4db2798 | 1040 | Aml *field; |
c35b6e80 IM |
1041 | Aml *method; |
1042 | uint32_t irqs; | |
e4db2798 | 1043 | Aml *sb_scope = aml_scope("_SB"); |
196e2137 IM |
1044 | Aml *pci0_scope = aml_scope("PCI0"); |
1045 | ||
1046 | aml_append(pci0_scope, build_prt(true)); | |
1047 | aml_append(sb_scope, pci0_scope); | |
e4db2798 IM |
1048 | |
1049 | field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); | |
1050 | aml_append(field, aml_named_field("PRQ0", 8)); | |
1051 | aml_append(field, aml_named_field("PRQ1", 8)); | |
1052 | aml_append(field, aml_named_field("PRQ2", 8)); | |
1053 | aml_append(field, aml_named_field("PRQ3", 8)); | |
1054 | aml_append(sb_scope, field); | |
1055 | ||
78e1ad05 | 1056 | aml_append(sb_scope, build_irq_status_method()); |
16682a9d | 1057 | aml_append(sb_scope, build_iqcr_method(true)); |
100681cc | 1058 | |
c35b6e80 IM |
1059 | aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); |
1060 | aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); | |
1061 | aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); | |
1062 | aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); | |
1063 | ||
1064 | dev = aml_device("LNKS"); | |
1065 | { | |
1066 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); | |
1067 | aml_append(dev, aml_name_decl("_UID", aml_int(4))); | |
1068 | ||
1069 | crs = aml_resource_template(); | |
1070 | irqs = 9; | |
1071 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, | |
1072 | AML_ACTIVE_HIGH, AML_SHARED, | |
1073 | &irqs, 1)); | |
1074 | aml_append(dev, aml_name_decl("_PRS", crs)); | |
1075 | ||
1076 | /* The SCI cannot be disabled and is always attached to GSI 9, | |
1077 | * so these are no-ops. We only need this link to override the | |
1078 | * polarity to active high and match the content of the MADT. | |
1079 | */ | |
1080 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
1081 | aml_append(method, aml_return(aml_int(0x0b))); | |
1082 | aml_append(dev, method); | |
1083 | ||
1084 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
1085 | aml_append(dev, method); | |
1086 | ||
1087 | method = aml_method("_CRS", 0, AML_NOTSERIALIZED); | |
1088 | aml_append(method, aml_return(aml_name("_PRS"))); | |
1089 | aml_append(dev, method); | |
1090 | ||
1091 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); | |
1092 | aml_append(dev, method); | |
1093 | } | |
1094 | aml_append(sb_scope, dev); | |
1095 | ||
e4db2798 IM |
1096 | aml_append(table, sb_scope); |
1097 | } | |
1098 | ||
22b5b8bf IM |
1099 | static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) |
1100 | { | |
1101 | int i; | |
1102 | int head; | |
1103 | Aml *pkg; | |
1104 | char base = name[3] < 'E' ? 'A' : 'E'; | |
1105 | char *s = g_strdup(name); | |
1106 | Aml *a_nr = aml_int((nr << 16) | 0xffff); | |
1107 | ||
1108 | assert(strlen(s) == 4); | |
1109 | ||
1110 | head = name[3] - base; | |
1111 | for (i = 0; i < 4; i++) { | |
1112 | if (head + i > 3) { | |
1113 | head = i * -1; | |
1114 | } | |
1115 | s[3] = base + head + i; | |
1116 | pkg = aml_package(4); | |
1117 | aml_append(pkg, a_nr); | |
1118 | aml_append(pkg, aml_int(i)); | |
1119 | aml_append(pkg, aml_name("%s", s)); | |
1120 | aml_append(pkg, aml_int(0)); | |
1121 | aml_append(ctx, pkg); | |
1122 | } | |
1123 | g_free(s); | |
1124 | } | |
1125 | ||
1126 | static Aml *build_q35_routing_table(const char *str) | |
1127 | { | |
1128 | int i; | |
1129 | Aml *pkg; | |
1130 | char *name = g_strdup_printf("%s ", str); | |
1131 | ||
1132 | pkg = aml_package(128); | |
1133 | for (i = 0; i < 0x18; i++) { | |
1134 | name[3] = 'E' + (i & 0x3); | |
1135 | append_q35_prt_entry(pkg, i, name); | |
1136 | } | |
1137 | ||
1138 | name[3] = 'E'; | |
1139 | append_q35_prt_entry(pkg, 0x18, name); | |
1140 | ||
1141 | /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ | |
1142 | for (i = 0x0019; i < 0x1e; i++) { | |
1143 | name[3] = 'A'; | |
1144 | append_q35_prt_entry(pkg, i, name); | |
1145 | } | |
1146 | ||
1147 | /* PCIe->PCI bridge. use PIRQ[E-H] */ | |
1148 | name[3] = 'E'; | |
1149 | append_q35_prt_entry(pkg, 0x1e, name); | |
1150 | name[3] = 'A'; | |
1151 | append_q35_prt_entry(pkg, 0x1f, name); | |
1152 | ||
1153 | g_free(name); | |
1154 | return pkg; | |
1155 | } | |
1156 | ||
80b32df5 IM |
1157 | static void build_q35_pci0_int(Aml *table) |
1158 | { | |
41f95a52 | 1159 | Aml *field; |
0dafe3b3 | 1160 | Aml *method; |
80b32df5 | 1161 | Aml *sb_scope = aml_scope("_SB"); |
0dafe3b3 IM |
1162 | Aml *pci0_scope = aml_scope("PCI0"); |
1163 | ||
e9fce798 IM |
1164 | /* Zero => PIC mode, One => APIC Mode */ |
1165 | aml_append(table, aml_name_decl("PICF", aml_int(0))); | |
1166 | method = aml_method("_PIC", 1, AML_NOTSERIALIZED); | |
1167 | { | |
1168 | aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); | |
1169 | } | |
1170 | aml_append(table, method); | |
1171 | ||
65aef4de IM |
1172 | aml_append(pci0_scope, |
1173 | aml_name_decl("PRTP", build_q35_routing_table("LNK"))); | |
22b5b8bf IM |
1174 | aml_append(pci0_scope, |
1175 | aml_name_decl("PRTA", build_q35_routing_table("GSI"))); | |
1176 | ||
0dafe3b3 IM |
1177 | method = aml_method("_PRT", 0, AML_NOTSERIALIZED); |
1178 | { | |
1179 | Aml *if_ctx; | |
1180 | Aml *else_ctx; | |
1181 | ||
1182 | /* PCI IRQ routing table, example from ACPI 2.0a specification, | |
1183 | section 6.2.8.1 */ | |
1184 | /* Note: we provide the same info as the PCI routing | |
1185 | table of the Bochs BIOS */ | |
1186 | if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); | |
1187 | aml_append(if_ctx, aml_return(aml_name("PRTP"))); | |
1188 | aml_append(method, if_ctx); | |
1189 | else_ctx = aml_else(); | |
1190 | aml_append(else_ctx, aml_return(aml_name("PRTA"))); | |
1191 | aml_append(method, else_ctx); | |
1192 | } | |
1193 | aml_append(pci0_scope, method); | |
1194 | aml_append(sb_scope, pci0_scope); | |
80b32df5 | 1195 | |
41f95a52 IM |
1196 | field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); |
1197 | aml_append(field, aml_named_field("PRQA", 8)); | |
1198 | aml_append(field, aml_named_field("PRQB", 8)); | |
1199 | aml_append(field, aml_named_field("PRQC", 8)); | |
1200 | aml_append(field, aml_named_field("PRQD", 8)); | |
1201 | aml_append(field, aml_reserved_field(0x20)); | |
1202 | aml_append(field, aml_named_field("PRQE", 8)); | |
1203 | aml_append(field, aml_named_field("PRQF", 8)); | |
1204 | aml_append(field, aml_named_field("PRQG", 8)); | |
1205 | aml_append(field, aml_named_field("PRQH", 8)); | |
1206 | aml_append(sb_scope, field); | |
1207 | ||
78e1ad05 | 1208 | aml_append(sb_scope, build_irq_status_method()); |
16682a9d IM |
1209 | aml_append(sb_scope, build_iqcr_method(false)); |
1210 | ||
12e3b1f7 IM |
1211 | aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); |
1212 | aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); | |
1213 | aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); | |
1214 | aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); | |
1215 | aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); | |
1216 | aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); | |
1217 | aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); | |
1218 | aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); | |
1219 | ||
6a991e07 MA |
1220 | aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); |
1221 | aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); | |
1222 | aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); | |
1223 | aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); | |
1224 | aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); | |
1225 | aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); | |
1226 | aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); | |
1227 | aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); | |
80b32df5 IM |
1228 | |
1229 | aml_append(table, sb_scope); | |
1230 | } | |
1231 | ||
e3fb55f0 IY |
1232 | static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) |
1233 | { | |
1234 | Aml *dev; | |
1235 | Aml *resource_template; | |
1236 | ||
1237 | /* DRAM controller */ | |
1238 | dev = aml_device("DRAC"); | |
1239 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); | |
1240 | ||
1241 | resource_template = aml_resource_template(); | |
1242 | if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { | |
1243 | aml_append(resource_template, | |
1244 | aml_qword_memory(AML_POS_DECODE, | |
1245 | AML_MIN_FIXED, | |
1246 | AML_MAX_FIXED, | |
1247 | AML_NON_CACHEABLE, | |
1248 | AML_READ_WRITE, | |
1249 | 0x0000000000000000, | |
1250 | mcfg->base, | |
1251 | mcfg->base + mcfg->size - 1, | |
1252 | 0x0000000000000000, | |
1253 | mcfg->size)); | |
1254 | } else { | |
1255 | aml_append(resource_template, | |
1256 | aml_dword_memory(AML_POS_DECODE, | |
1257 | AML_MIN_FIXED, | |
1258 | AML_MAX_FIXED, | |
1259 | AML_NON_CACHEABLE, | |
1260 | AML_READ_WRITE, | |
1261 | 0x0000000000000000, | |
1262 | mcfg->base, | |
1263 | mcfg->base + mcfg->size - 1, | |
1264 | 0x0000000000000000, | |
1265 | mcfg->size)); | |
1266 | } | |
1267 | aml_append(dev, aml_name_decl("_CRS", resource_template)); | |
1268 | ||
1269 | return dev; | |
1270 | } | |
1271 | ||
41f95a52 IM |
1272 | static void build_q35_isa_bridge(Aml *table) |
1273 | { | |
1274 | Aml *dev; | |
1275 | Aml *scope; | |
887e8e9d IM |
1276 | Object *obj; |
1277 | bool ambiguous; | |
1278 | ||
1279 | /* | |
1280 | * temporarily fish out isa bridge, build_q35_isa_bridge() will be dropped | |
1281 | * once PCI is converted to AcpiDevAmlIf and would be ble to generate | |
1282 | * AML for bridge itself | |
1283 | */ | |
1284 | obj = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambiguous); | |
1285 | assert(obj && !ambiguous); | |
41f95a52 IM |
1286 | |
1287 | scope = aml_scope("_SB.PCI0"); | |
1288 | dev = aml_device("ISA"); | |
1289 | aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); | |
1290 | ||
887e8e9d | 1291 | call_dev_aml_func(DEVICE(obj), dev); |
41f95a52 IM |
1292 | aml_append(scope, dev); |
1293 | aml_append(table, scope); | |
1294 | } | |
1295 | ||
e4db2798 IM |
1296 | static void build_piix4_isa_bridge(Aml *table) |
1297 | { | |
1298 | Aml *dev; | |
1299 | Aml *scope; | |
92ea7fb3 IM |
1300 | Object *obj; |
1301 | bool ambiguous; | |
1302 | ||
1303 | /* | |
1304 | * temporarily fish out isa bridge, build_piix4_isa_bridge() will be dropped | |
1305 | * once PCI is converted to AcpiDevAmlIf and would be ble to generate | |
1306 | * AML for bridge itself | |
1307 | */ | |
1308 | obj = object_resolve_path_type("", TYPE_PIIX3_PCI_DEVICE, &ambiguous); | |
1309 | assert(obj && !ambiguous); | |
e4db2798 IM |
1310 | |
1311 | scope = aml_scope("_SB.PCI0"); | |
1312 | dev = aml_device("ISA"); | |
1313 | aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); | |
1314 | ||
92ea7fb3 | 1315 | call_dev_aml_func(DEVICE(obj), dev); |
e4db2798 IM |
1316 | aml_append(scope, dev); |
1317 | aml_append(table, scope); | |
1318 | } | |
1319 | ||
caf108bc | 1320 | static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) |
b616ec4d IM |
1321 | { |
1322 | Aml *scope; | |
1323 | Aml *field; | |
1324 | Aml *method; | |
1325 | ||
1326 | scope = aml_scope("_SB.PCI0"); | |
1327 | ||
1328 | aml_append(scope, | |
caf108bc | 1329 | aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); |
b616ec4d IM |
1330 | field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); |
1331 | aml_append(field, aml_named_field("PCIU", 32)); | |
1332 | aml_append(field, aml_named_field("PCID", 32)); | |
1333 | aml_append(scope, field); | |
1334 | ||
1335 | aml_append(scope, | |
caf108bc JS |
1336 | aml_operation_region("SEJ", AML_SYSTEM_IO, |
1337 | aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); | |
b616ec4d IM |
1338 | field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); |
1339 | aml_append(field, aml_named_field("B0EJ", 32)); | |
1340 | aml_append(scope, field); | |
1341 | ||
1342 | aml_append(scope, | |
caf108bc JS |
1343 | aml_operation_region("BNMR", AML_SYSTEM_IO, |
1344 | aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); | |
b616ec4d IM |
1345 | field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); |
1346 | aml_append(field, aml_named_field("BNUM", 32)); | |
b32bd763 | 1347 | aml_append(field, aml_named_field("PIDX", 32)); |
b616ec4d IM |
1348 | aml_append(scope, field); |
1349 | ||
1350 | aml_append(scope, aml_mutex("BLCK", 0)); | |
1351 | ||
1352 | method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); | |
1353 | aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); | |
1354 | aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); | |
1355 | aml_append(method, | |
1356 | aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); | |
1357 | aml_append(method, aml_release(aml_name("BLCK"))); | |
1358 | aml_append(method, aml_return(aml_int(0))); | |
1359 | aml_append(scope, method); | |
1360 | ||
b32bd763 IM |
1361 | method = aml_method("AIDX", 2, AML_NOTSERIALIZED); |
1362 | aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); | |
1363 | aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); | |
1364 | aml_append(method, | |
1365 | aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); | |
1366 | aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); | |
1367 | aml_append(method, aml_release(aml_name("BLCK"))); | |
1368 | aml_append(method, aml_return(aml_local(0))); | |
1369 | aml_append(scope, method); | |
1370 | ||
b7f23f62 IM |
1371 | aml_append(scope, aml_pci_device_dsm()); |
1372 | ||
b616ec4d IM |
1373 | aml_append(table, scope); |
1374 | } | |
1375 | ||
211afe5c | 1376 | static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) |
f97a88a8 IM |
1377 | { |
1378 | Aml *if_ctx; | |
1379 | Aml *if_ctx2; | |
1380 | Aml *else_ctx; | |
1381 | Aml *method; | |
1382 | Aml *a_cwd1 = aml_name("CDW1"); | |
b3c782db | 1383 | Aml *a_ctrl = aml_local(0); |
f97a88a8 IM |
1384 | |
1385 | method = aml_method("_OSC", 4, AML_NOTSERIALIZED); | |
1386 | aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); | |
1387 | ||
1388 | if_ctx = aml_if(aml_equal( | |
1389 | aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); | |
1390 | aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); | |
1391 | aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); | |
1392 | ||
f97a88a8 IM |
1393 | aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); |
1394 | ||
1395 | /* | |
1396 | * Always allow native PME, AER (no dependencies) | |
a41c78c1 | 1397 | * Allow SHPC (PCI bridges can have SHPC controller) |
211afe5c | 1398 | * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. |
f97a88a8 | 1399 | */ |
211afe5c JS |
1400 | aml_append(if_ctx, aml_and(a_ctrl, |
1401 | aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); | |
f97a88a8 IM |
1402 | |
1403 | if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); | |
1404 | /* Unknown revision */ | |
1405 | aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); | |
1406 | aml_append(if_ctx, if_ctx2); | |
1407 | ||
1408 | if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); | |
1409 | /* Capabilities bits were masked */ | |
1410 | aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); | |
1411 | aml_append(if_ctx, if_ctx2); | |
1412 | ||
1413 | /* Update DWORD3 in the buffer */ | |
1414 | aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); | |
1415 | aml_append(method, if_ctx); | |
1416 | ||
1417 | else_ctx = aml_else(); | |
1418 | /* Unrecognized UUID */ | |
1419 | aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); | |
1420 | aml_append(method, else_ctx); | |
1421 | ||
1422 | aml_append(method, aml_return(aml_arg(3))); | |
1423 | return method; | |
1424 | } | |
b616ec4d | 1425 | |
5876d9b5 | 1426 | static void build_smb0(Aml *table, int devnr, int func) |
ebe15582 CM |
1427 | { |
1428 | Aml *scope = aml_scope("_SB.PCI0"); | |
1429 | Aml *dev = aml_device("SMB0"); | |
5876d9b5 IM |
1430 | bool ambiguous; |
1431 | Object *obj; | |
1432 | /* | |
1433 | * temporarily fish out device hosting SMBUS, build_smb0 will be gone once | |
1434 | * PCI enumeration will be switched to call_dev_aml_func() | |
1435 | */ | |
1436 | obj = object_resolve_path_type("", TYPE_ICH9_SMB_DEVICE, &ambiguous); | |
1437 | assert(obj && !ambiguous); | |
ebe15582 | 1438 | |
ebe15582 | 1439 | aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); |
5876d9b5 | 1440 | call_dev_aml_func(DEVICE(obj), dev); |
ebe15582 CM |
1441 | aml_append(scope, dev); |
1442 | aml_append(table, scope); | |
1443 | } | |
1444 | ||
3d6a69b6 BW |
1445 | static void build_acpi0017(Aml *table) |
1446 | { | |
1447 | Aml *dev, *scope, *method; | |
1448 | ||
1449 | scope = aml_scope("_SB"); | |
1450 | dev = aml_device("CXLM"); | |
1451 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); | |
1452 | ||
1453 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
1454 | aml_append(method, aml_return(aml_int(0x01))); | |
1455 | aml_append(dev, method); | |
1456 | ||
1457 | aml_append(scope, dev); | |
1458 | aml_append(table, scope); | |
1459 | } | |
1460 | ||
72c194f7 | 1461 | static void |
0e9b9eda | 1462 | build_dsdt(GArray *table_data, BIOSLinker *linker, |
adcb89d5 | 1463 | AcpiPmInfo *pm, AcpiMiscInfo *misc, |
01c9742d | 1464 | Range *pci_hole, Range *pci_hole64, MachineState *machine) |
72c194f7 | 1465 | { |
41fa5c04 IM |
1466 | CrsRangeEntry *entry; |
1467 | Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; | |
2df5a7b5 | 1468 | CrsRangeSet crs_range_set; |
fb306ffe | 1469 | PCMachineState *pcms = PC_MACHINE(machine); |
679dd1a9 | 1470 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); |
f0bb276b | 1471 | X86MachineState *x86ms = X86_MACHINE(machine); |
4a441836 | 1472 | AcpiMcfgInfo mcfg; |
e3fb55f0 | 1473 | bool mcfg_valid = !!acpi_get_mcfg(&mcfg); |
bef3492d | 1474 | uint32_t nr_mem = machine->ram_slots; |
dcdca296 | 1475 | int root_bus_limit = 0xFF; |
41fa5c04 | 1476 | PCIBus *bus = NULL; |
11fb99e6 | 1477 | #ifdef CONFIG_TPM |
ac6dd31e | 1478 | TPMIf *tpm = tpm_find(); |
11fb99e6 | 1479 | #endif |
3d6a69b6 | 1480 | bool cxl_present = false; |
72c194f7 | 1481 | int i; |
8f814ea1 | 1482 | VMBusBridge *vmbus_bridge = vmbus_bridge_find(); |
5c142bc4 IM |
1483 | AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, |
1484 | .oem_table_id = x86ms->oem_table_id }; | |
72c194f7 | 1485 | |
5c142bc4 | 1486 | acpi_table_begin(&table, table_data); |
41fa5c04 | 1487 | dsdt = init_aml_allocator(); |
2fd71f1b | 1488 | |
41fa5c04 IM |
1489 | build_dbg_aml(dsdt); |
1490 | if (misc->is_piix4) { | |
1491 | sb_scope = aml_scope("_SB"); | |
1492 | dev = aml_device("PCI0"); | |
1493 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); | |
1494 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
0a343a5a | 1495 | aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); |
41fa5c04 IM |
1496 | aml_append(sb_scope, dev); |
1497 | aml_append(dsdt, sb_scope); | |
1498 | ||
41fa5c04 | 1499 | build_piix4_isa_bridge(dsdt); |
df4008c9 | 1500 | if (pm->pcihp_bridge_en || pm->pcihp_root_en) { |
caf108bc | 1501 | build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); |
df4008c9 | 1502 | } |
41fa5c04 IM |
1503 | build_piix4_pci0_int(dsdt); |
1504 | } else { | |
41fa5c04 IM |
1505 | sb_scope = aml_scope("_SB"); |
1506 | dev = aml_device("PCI0"); | |
1507 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); | |
1508 | aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); | |
1509 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
0a343a5a | 1510 | aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); |
211afe5c | 1511 | aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); |
41fa5c04 | 1512 | aml_append(sb_scope, dev); |
e3fb55f0 IY |
1513 | if (mcfg_valid) { |
1514 | aml_append(sb_scope, build_q35_dram_controller(&mcfg)); | |
1515 | } | |
998ba950 IM |
1516 | |
1517 | if (pm->smi_on_cpuhp) { | |
1518 | /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ | |
1519 | dev = aml_device("PCI0.SMI0"); | |
1520 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); | |
1521 | aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); | |
1522 | crs = aml_resource_template(); | |
1523 | aml_append(crs, | |
1524 | aml_io( | |
1525 | AML_DECODE16, | |
1526 | ACPI_PORT_SMI_CMD, | |
1527 | ACPI_PORT_SMI_CMD, | |
1528 | 1, | |
1529 | 2) | |
1530 | ); | |
1531 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1532 | aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, | |
1533 | aml_int(ACPI_PORT_SMI_CMD), 2)); | |
1534 | field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, | |
1535 | AML_WRITE_AS_ZEROS); | |
1536 | aml_append(field, aml_named_field("SMIC", 8)); | |
1537 | aml_append(field, aml_reserved_field(8)); | |
1538 | aml_append(dev, field); | |
1539 | aml_append(sb_scope, dev); | |
1540 | } | |
1541 | ||
41fa5c04 IM |
1542 | aml_append(dsdt, sb_scope); |
1543 | ||
41fa5c04 | 1544 | build_q35_isa_bridge(dsdt); |
caf108bc JS |
1545 | if (pm->pcihp_bridge_en) { |
1546 | build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); | |
1547 | } | |
41fa5c04 | 1548 | build_q35_pci0_int(dsdt); |
38003951 | 1549 | if (pcms->smbus) { |
5876d9b5 | 1550 | build_smb0(dsdt, ICH9_SMB_DEV, ICH9_SMB_FUNC); |
ebe15582 | 1551 | } |
41fa5c04 IM |
1552 | } |
1553 | ||
e05acc36 IM |
1554 | if (misc->has_hpet) { |
1555 | build_hpet_aml(dsdt); | |
1556 | } | |
1557 | ||
8f814ea1 JD |
1558 | if (vmbus_bridge) { |
1559 | sb_scope = aml_scope("_SB"); | |
1560 | aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); | |
1561 | aml_append(dsdt, sb_scope); | |
1562 | } | |
1563 | ||
679dd1a9 IM |
1564 | if (pcmc->legacy_cpu_hotplug) { |
1565 | build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); | |
1566 | } else { | |
1567 | CPUHotplugFeatures opts = { | |
998ba950 IM |
1568 | .acpi_1_compatible = true, .has_legacy_cphp = true, |
1569 | .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, | |
69dea9d6 | 1570 | .fw_unplugs_cpu = pm->smi_on_cpu_unplug, |
679dd1a9 IM |
1571 | }; |
1572 | build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, | |
1573 | "\\_SB.PCI0", "\\_GPE._E02"); | |
1574 | } | |
091c466e SK |
1575 | |
1576 | if (pcms->memhp_io_base && nr_mem) { | |
1577 | build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", | |
1578 | "\\_GPE._E03", AML_SYSTEM_IO, | |
1579 | pcms->memhp_io_base); | |
1580 | } | |
41fa5c04 IM |
1581 | |
1582 | scope = aml_scope("_GPE"); | |
1583 | { | |
1584 | aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); | |
1585 | ||
caf108bc | 1586 | if (pm->pcihp_bridge_en || pm->pcihp_root_en) { |
41fa5c04 IM |
1587 | method = aml_method("_E01", 0, AML_NOTSERIALIZED); |
1588 | aml_append(method, | |
1589 | aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); | |
1590 | aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); | |
1591 | aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); | |
1592 | aml_append(scope, method); | |
41fa5c04 IM |
1593 | } |
1594 | ||
f6a0d06b | 1595 | if (machine->nvdimms_state->is_enabled) { |
b097cc52 XG |
1596 | method = aml_method("_E04", 0, AML_NOTSERIALIZED); |
1597 | aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), | |
1598 | aml_int(0x80))); | |
1599 | aml_append(scope, method); | |
1600 | } | |
41fa5c04 IM |
1601 | } |
1602 | aml_append(dsdt, scope); | |
72c194f7 | 1603 | |
2df5a7b5 | 1604 | crs_range_set_init(&crs_range_set); |
81ed6482 | 1605 | bus = PC_MACHINE(machine)->bus; |
a4894206 MA |
1606 | if (bus) { |
1607 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1608 | uint8_t bus_num = pci_bus_num(bus); | |
0e79e51a | 1609 | uint8_t numa_node = pci_bus_numa_node(bus); |
a4894206 MA |
1610 | |
1611 | /* look only for expander root buses */ | |
1612 | if (!pci_bus_is_root(bus)) { | |
1613 | continue; | |
1614 | } | |
1615 | ||
dcdca296 MA |
1616 | if (bus_num < root_bus_limit) { |
1617 | root_bus_limit = bus_num - 1; | |
1618 | } | |
1619 | ||
a4894206 | 1620 | scope = aml_scope("\\_SB"); |
6e4e3ae9 BW |
1621 | |
1622 | if (pci_bus_is_cxl(bus)) { | |
1623 | dev = aml_device("CL%.02X", bus_num); | |
1624 | } else { | |
1625 | dev = aml_device("PC%.02X", bus_num); | |
1626 | } | |
c96d9286 | 1627 | aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); |
a4894206 | 1628 | aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); |
6e4e3ae9 | 1629 | if (pci_bus_is_cxl(bus)) { |
2a3282c6 BW |
1630 | struct Aml *pkg = aml_package(2); |
1631 | ||
1632 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); | |
1633 | aml_append(pkg, aml_eisaid("PNP0A08")); | |
1634 | aml_append(pkg, aml_eisaid("PNP0A03")); | |
1635 | aml_append(dev, aml_name_decl("_CID", pkg)); | |
1636 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
1637 | aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); | |
1638 | build_cxl_osc_method(dev); | |
6e4e3ae9 | 1639 | } else if (pci_bus_is_express(bus)) { |
ee4b0c86 EY |
1640 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); |
1641 | aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); | |
211afe5c JS |
1642 | |
1643 | /* Expander bridges do not have ACPI PCI Hot-plug enabled */ | |
1644 | aml_append(dev, build_q35_osc_method(true)); | |
ee4b0c86 EY |
1645 | } else { |
1646 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); | |
077dd742 | 1647 | } |
0e79e51a MA |
1648 | |
1649 | if (numa_node != NUMA_NODE_UNASSIGNED) { | |
1650 | aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); | |
1651 | } | |
1652 | ||
196e2137 | 1653 | aml_append(dev, build_prt(false)); |
e41ee855 JC |
1654 | crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, |
1655 | 0, 0, 0, 0); | |
a43c6e27 | 1656 | aml_append(dev, aml_name_decl("_CRS", crs)); |
a4894206 | 1657 | aml_append(scope, dev); |
41fa5c04 | 1658 | aml_append(dsdt, scope); |
6e4e3ae9 BW |
1659 | |
1660 | /* Handle the ranges for the PXB expanders */ | |
1661 | if (pci_bus_is_cxl(bus)) { | |
1ebf9001 | 1662 | MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; |
6e4e3ae9 BW |
1663 | uint64_t base = mr->addr; |
1664 | ||
3d6a69b6 | 1665 | cxl_present = true; |
6e4e3ae9 BW |
1666 | crs_range_insert(crs_range_set.mem_ranges, base, |
1667 | base + memory_region_size(mr) - 1); | |
1668 | } | |
a4894206 MA |
1669 | } |
1670 | } | |
1671 | ||
3d6a69b6 BW |
1672 | if (cxl_present) { |
1673 | build_acpi0017(dsdt); | |
1674 | } | |
1675 | ||
4a441836 GH |
1676 | /* |
1677 | * At this point crs_range_set has all the ranges used by pci | |
1678 | * busses *other* than PCI0. These ranges will be excluded from | |
1679 | * the PCI0._CRS. Add mmconfig to the set so it will be excluded | |
1680 | * too. | |
1681 | */ | |
e3fb55f0 | 1682 | if (mcfg_valid) { |
4a441836 GH |
1683 | crs_range_insert(crs_range_set.mem_ranges, |
1684 | mcfg.base, mcfg.base + mcfg.size - 1); | |
1685 | } | |
1686 | ||
500b11ea | 1687 | scope = aml_scope("\\_SB.PCI0"); |
60efd429 IM |
1688 | /* build PCI0._CRS */ |
1689 | crs = aml_resource_template(); | |
1690 | aml_append(crs, | |
ff80dc7f | 1691 | aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, |
dcdca296 MA |
1692 | 0x0000, 0x0, root_bus_limit, |
1693 | 0x0000, root_bus_limit + 1)); | |
ff80dc7f | 1694 | aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); |
60efd429 IM |
1695 | |
1696 | aml_append(crs, | |
ff80dc7f SZ |
1697 | aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, |
1698 | AML_POS_DECODE, AML_ENTIRE_RANGE, | |
60efd429 | 1699 | 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); |
dcdca296 | 1700 | |
2df5a7b5 MA |
1701 | crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); |
1702 | for (i = 0; i < crs_range_set.io_ranges->len; i++) { | |
1703 | entry = g_ptr_array_index(crs_range_set.io_ranges, i); | |
dcdca296 MA |
1704 | aml_append(crs, |
1705 | aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, | |
1706 | AML_POS_DECODE, AML_ENTIRE_RANGE, | |
1707 | 0x0000, entry->base, entry->limit, | |
1708 | 0x0000, entry->limit - entry->base + 1)); | |
1709 | } | |
1710 | ||
60efd429 | 1711 | aml_append(crs, |
ff80dc7f SZ |
1712 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, |
1713 | AML_CACHEABLE, AML_READ_WRITE, | |
60efd429 | 1714 | 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); |
dcdca296 | 1715 | |
2df5a7b5 | 1716 | crs_replace_with_free_ranges(crs_range_set.mem_ranges, |
a0efbf16 MA |
1717 | range_lob(pci_hole), |
1718 | range_upb(pci_hole)); | |
2df5a7b5 MA |
1719 | for (i = 0; i < crs_range_set.mem_ranges->len; i++) { |
1720 | entry = g_ptr_array_index(crs_range_set.mem_ranges, i); | |
dcdca296 MA |
1721 | aml_append(crs, |
1722 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, | |
1723 | AML_NON_CACHEABLE, AML_READ_WRITE, | |
1724 | 0, entry->base, entry->limit, | |
1725 | 0, entry->limit - entry->base + 1)); | |
1726 | } | |
1727 | ||
a0efbf16 | 1728 | if (!range_is_empty(pci_hole64)) { |
16de88a4 MA |
1729 | crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, |
1730 | range_lob(pci_hole64), | |
1731 | range_upb(pci_hole64)); | |
1732 | for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { | |
1733 | entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); | |
1734 | aml_append(crs, | |
1735 | aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, | |
1736 | AML_MAX_FIXED, | |
1737 | AML_CACHEABLE, AML_READ_WRITE, | |
1738 | 0, entry->base, entry->limit, | |
1739 | 0, entry->limit - entry->base + 1)); | |
1740 | } | |
60efd429 | 1741 | } |
2b1c2e8e | 1742 | |
11fb99e6 | 1743 | #ifdef CONFIG_TPM |
43bc7f84 | 1744 | if (TPM_IS_TIS_ISA(tpm_find())) { |
2b1c2e8e IM |
1745 | aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, |
1746 | TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); | |
1747 | } | |
11fb99e6 | 1748 | #endif |
60efd429 IM |
1749 | aml_append(scope, aml_name_decl("_CRS", crs)); |
1750 | ||
d31c909e IM |
1751 | /* reserve GPE0 block resources */ |
1752 | dev = aml_device("GPE0"); | |
1753 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
1754 | aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); | |
1755 | /* device present, functioning, decoding, not shown in UI */ | |
1756 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1757 | crs = aml_resource_template(); | |
1758 | aml_append(crs, | |
937d1b58 IM |
1759 | aml_io( |
1760 | AML_DECODE16, | |
1761 | pm->fadt.gpe0_blk.address, | |
1762 | pm->fadt.gpe0_blk.address, | |
1763 | 1, | |
1764 | pm->fadt.gpe0_blk.bit_width / 8) | |
d31c909e IM |
1765 | ); |
1766 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1767 | aml_append(scope, dev); | |
1768 | ||
2df5a7b5 | 1769 | crs_range_set_free(&crs_range_set); |
dcdca296 | 1770 | |
500b11ea | 1771 | /* reserve PCIHP resources */ |
df4008c9 | 1772 | if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { |
500b11ea IM |
1773 | dev = aml_device("PHPR"); |
1774 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
1775 | aml_append(dev, | |
1776 | aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); | |
1777 | /* device present, functioning, decoding, not shown in UI */ | |
1778 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1779 | crs = aml_resource_template(); | |
1780 | aml_append(crs, | |
ff80dc7f | 1781 | aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, |
500b11ea IM |
1782 | pm->pcihp_io_len) |
1783 | ); | |
1784 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1785 | aml_append(scope, dev); | |
1786 | } | |
41fa5c04 | 1787 | aml_append(dsdt, scope); |
500b11ea | 1788 | |
ebc3028f IM |
1789 | /* create S3_ / S4_ / S5_ packages if necessary */ |
1790 | scope = aml_scope("\\"); | |
1791 | if (!pm->s3_disabled) { | |
1792 | pkg = aml_package(4); | |
1793 | aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ | |
1794 | aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
1795 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1796 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1797 | aml_append(scope, aml_name_decl("_S3", pkg)); | |
1798 | } | |
1799 | ||
1800 | if (!pm->s4_disabled) { | |
1801 | pkg = aml_package(4); | |
1802 | aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ | |
1803 | /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
1804 | aml_append(pkg, aml_int(pm->s4_val)); | |
1805 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1806 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1807 | aml_append(scope, aml_name_decl("_S4", pkg)); | |
1808 | } | |
1809 | ||
1810 | pkg = aml_package(4); | |
1811 | aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ | |
1812 | aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ | |
1813 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1814 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1815 | aml_append(scope, aml_name_decl("_S5", pkg)); | |
41fa5c04 | 1816 | aml_append(dsdt, scope); |
ebc3028f | 1817 | |
e2ec7568 GS |
1818 | /* create fw_cfg node, unconditionally */ |
1819 | { | |
e2ec7568 | 1820 | scope = aml_scope("\\_SB.PCI0"); |
0575c2fd | 1821 | fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); |
e2ec7568 GS |
1822 | aml_append(dsdt, scope); |
1823 | } | |
1824 | ||
7824df38 | 1825 | sb_scope = aml_scope("\\_SB"); |
72c194f7 | 1826 | { |
d3ecb22c | 1827 | Object *pci_host = acpi_get_i386_pci_host(); |
c0e427d6 | 1828 | |
8b35ab27 | 1829 | if (pci_host) { |
d3ecb22c | 1830 | PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; |
8b35ab27 IM |
1831 | Aml *scope = aml_scope("PCI0"); |
1832 | /* Scan all PCI buses. Generate tables to support hotplug. */ | |
1833 | build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); | |
8b35ab27 | 1834 | aml_append(sb_scope, scope); |
72c194f7 | 1835 | } |
72c194f7 | 1836 | } |
4ab6cb4c | 1837 | |
11fb99e6 | 1838 | #ifdef CONFIG_TPM |
ac6dd31e | 1839 | if (TPM_IS_CRB(tpm)) { |
4ab6cb4c MAL |
1840 | dev = aml_device("TPM"); |
1841 | aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); | |
5903646d SB |
1842 | aml_append(dev, aml_name_decl("_STR", |
1843 | aml_string("TPM 2.0 Device"))); | |
4ab6cb4c MAL |
1844 | crs = aml_resource_template(); |
1845 | aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, | |
1846 | TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); | |
1847 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1848 | ||
88b3648f | 1849 | aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); |
5903646d | 1850 | aml_append(dev, aml_name_decl("_UID", aml_int(1))); |
4ab6cb4c | 1851 | |
ac6dd31e SB |
1852 | tpm_build_ppi_acpi(tpm, dev); |
1853 | ||
4ab6cb4c MAL |
1854 | aml_append(sb_scope, dev); |
1855 | } | |
11fb99e6 | 1856 | #endif |
4ab6cb4c | 1857 | |
c8a9899c SC |
1858 | if (pcms->sgx_epc.size != 0) { |
1859 | uint64_t epc_base = pcms->sgx_epc.base; | |
1860 | uint64_t epc_size = pcms->sgx_epc.size; | |
1861 | ||
1862 | dev = aml_device("EPC"); | |
1863 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); | |
1864 | aml_append(dev, aml_name_decl("_STR", | |
1865 | aml_unicode("Enclave Page Cache 1.0"))); | |
1866 | crs = aml_resource_template(); | |
1867 | aml_append(crs, | |
1868 | aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, | |
1869 | AML_MAX_FIXED, AML_NON_CACHEABLE, | |
1870 | AML_READ_WRITE, 0, epc_base, | |
1871 | epc_base + epc_size - 1, 0, epc_size)); | |
1872 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1873 | ||
1874 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
1875 | aml_append(method, aml_return(aml_int(0x0f))); | |
1876 | aml_append(dev, method); | |
1877 | ||
1878 | aml_append(sb_scope, dev); | |
1879 | } | |
8b35ab27 | 1880 | aml_append(dsdt, sb_scope); |
72c194f7 | 1881 | |
011bb749 | 1882 | /* copy AML table into ACPI tables blob and patch header there */ |
41fa5c04 | 1883 | g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); |
5c142bc4 | 1884 | acpi_table_end(linker, &table); |
011bb749 | 1885 | free_aml_allocator(); |
72c194f7 MT |
1886 | } |
1887 | ||
43dde170 IM |
1888 | /* |
1889 | * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) | |
1890 | * 3.2.4The ACPI 2.0 HPET Description Table (HPET) | |
1891 | */ | |
72c194f7 | 1892 | static void |
602b4582 MP |
1893 | build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, |
1894 | const char *oem_table_id) | |
72c194f7 | 1895 | { |
43dde170 IM |
1896 | AcpiTable table = { .sig = "HPET", .rev = 1, |
1897 | .oem_id = oem_id, .oem_table_id = oem_table_id }; | |
72c194f7 | 1898 | |
43dde170 | 1899 | acpi_table_begin(&table, table_data); |
72c194f7 MT |
1900 | /* Note timer_block_id value must be kept in sync with value advertised by |
1901 | * emulated hpet | |
1902 | */ | |
43dde170 IM |
1903 | /* Event Timer Block ID */ |
1904 | build_append_int_noprefix(table_data, 0x8086a201, 4); | |
1905 | /* BASE_ADDRESS */ | |
1906 | build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); | |
1907 | /* HPET Number */ | |
1908 | build_append_int_noprefix(table_data, 0, 1); | |
1909 | /* Main Counter Minimum Clock_tick in Periodic Mode */ | |
1910 | build_append_int_noprefix(table_data, 0, 2); | |
1911 | /* Page Protection And OEM Attribute */ | |
1912 | build_append_int_noprefix(table_data, 0, 1); | |
1913 | acpi_table_end(linker, &table); | |
72c194f7 MT |
1914 | } |
1915 | ||
11fb99e6 | 1916 | #ifdef CONFIG_TPM |
57cb8cfb IM |
1917 | /* |
1918 | * TCPA Description Table | |
1919 | * | |
1920 | * Following Level 00, Rev 00.37 of specs: | |
1921 | * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification | |
1922 | * 7.1.2 ACPI Table Layout | |
1923 | */ | |
711b20b4 | 1924 | static void |
602b4582 MP |
1925 | build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, |
1926 | const char *oem_id, const char *oem_table_id) | |
711b20b4 | 1927 | { |
57cb8cfb IM |
1928 | unsigned log_addr_offset; |
1929 | AcpiTable table = { .sig = "TCPA", .rev = 2, | |
1930 | .oem_id = oem_id, .oem_table_id = oem_table_id }; | |
711b20b4 | 1931 | |
57cb8cfb IM |
1932 | acpi_table_begin(&table, table_data); |
1933 | /* Platform Class */ | |
1934 | build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); | |
1935 | /* Log Area Minimum Length (LAML) */ | |
1936 | build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); | |
1937 | /* Log Area Start Address (LASA) */ | |
1938 | log_addr_offset = table_data->len; | |
1939 | build_append_int_noprefix(table_data, 0, 8); | |
1940 | ||
1941 | /* allocate/reserve space for TPM log area */ | |
1942 | acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); | |
ad9671b8 | 1943 | bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, |
42a5b308 | 1944 | false /* high memory */); |
711b20b4 | 1945 | /* log area start address to be filled by Guest linker */ |
57cb8cfb IM |
1946 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, |
1947 | log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); | |
711b20b4 | 1948 | |
57cb8cfb | 1949 | acpi_table_end(linker, &table); |
711b20b4 | 1950 | } |
11fb99e6 | 1951 | #endif |
711b20b4 | 1952 | |
d471bf3e PB |
1953 | #define HOLE_640K_START (640 * KiB) |
1954 | #define HOLE_640K_END (1 * MiB) | |
4926403c | 1955 | |
e5b6d55a IM |
1956 | /* |
1957 | * ACPI spec, Revision 3.0 | |
1958 | * 5.2.15 System Resource Affinity Table (SRAT) | |
1959 | */ | |
72c194f7 | 1960 | static void |
0e9b9eda | 1961 | build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) |
72c194f7 | 1962 | { |
72c194f7 | 1963 | int i; |
e5b6d55a | 1964 | int numa_mem_start, slots; |
72c194f7 | 1965 | uint64_t mem_len, mem_base, next_base; |
5803fce3 | 1966 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
f0bb276b | 1967 | X86MachineState *x86ms = X86_MACHINE(machine); |
80e5db30 | 1968 | const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); |
3d3ebcad | 1969 | PCMachineState *pcms = PC_MACHINE(machine); |
e77af21a JL |
1970 | int nb_numa_nodes = machine->numa_state->num_nodes; |
1971 | NodeInfo *numa_info = machine->numa_state->nodes; | |
4be8bfcb | 1972 | ram_addr_t hotpluggable_address_space_size = |
f2ffbe2b | 1973 | object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, |
cec65193 | 1974 | NULL); |
255bf20f IM |
1975 | AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, |
1976 | .oem_table_id = x86ms->oem_table_id }; | |
72c194f7 | 1977 | |
255bf20f IM |
1978 | acpi_table_begin(&table, table_data); |
1979 | build_append_int_noprefix(table_data, 1, 4); /* Reserved */ | |
1980 | build_append_int_noprefix(table_data, 0, 8); /* Reserved */ | |
72c194f7 | 1981 | |
5803fce3 | 1982 | for (i = 0; i < apic_ids->len; i++) { |
d41f3e75 | 1983 | int node_id = apic_ids->cpus[i].props.node_id; |
5eff33a2 | 1984 | uint32_t apic_id = apic_ids->cpus[i].arch_id; |
5803fce3 | 1985 | |
5eff33a2 | 1986 | if (apic_id < 255) { |
e5b6d55a IM |
1987 | /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ |
1988 | build_append_int_noprefix(table_data, 0, 1); /* Type */ | |
1989 | build_append_int_noprefix(table_data, 16, 1); /* Length */ | |
1990 | /* Proximity Domain [7:0] */ | |
1991 | build_append_int_noprefix(table_data, node_id, 1); | |
1992 | build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ | |
1993 | /* Flags, Table 5-36 */ | |
1994 | build_append_int_noprefix(table_data, 1, 4); | |
1995 | build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ | |
1996 | /* Proximity Domain [31:8] */ | |
1997 | build_append_int_noprefix(table_data, 0, 3); | |
1998 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
5eff33a2 | 1999 | } else { |
e5b6d55a IM |
2000 | /* |
2001 | * ACPI spec, Revision 4.0 | |
2002 | * 5.2.16.3 Processor Local x2APIC Affinity Structure | |
2003 | */ | |
2004 | build_append_int_noprefix(table_data, 2, 1); /* Type */ | |
2005 | build_append_int_noprefix(table_data, 24, 1); /* Length */ | |
2006 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
2007 | /* Proximity Domain */ | |
2008 | build_append_int_noprefix(table_data, node_id, 4); | |
2009 | build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ | |
2010 | /* Flags, Table 5-39 */ | |
2011 | build_append_int_noprefix(table_data, 1 /* Enabled */, 4); | |
2012 | build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ | |
2013 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
1f3aba37 | 2014 | } |
72c194f7 MT |
2015 | } |
2016 | ||
72c194f7 MT |
2017 | /* the memory map is a bit tricky, it contains at least one hole |
2018 | * from 640k-1M and possibly another one from 3.5G-4G. | |
2019 | */ | |
2020 | next_base = 0; | |
e5b6d55a | 2021 | numa_mem_start = table_data->len; |
72c194f7 | 2022 | |
e77af21a | 2023 | for (i = 1; i < nb_numa_nodes + 1; ++i) { |
72c194f7 | 2024 | mem_base = next_base; |
e77af21a | 2025 | mem_len = numa_info[i - 1].node_mem; |
72c194f7 MT |
2026 | next_base = mem_base + mem_len; |
2027 | ||
4926403c EH |
2028 | /* Cut out the 640K hole */ |
2029 | if (mem_base <= HOLE_640K_START && | |
2030 | next_base > HOLE_640K_START) { | |
2031 | mem_len -= next_base - HOLE_640K_START; | |
2032 | if (mem_len > 0) { | |
e5b6d55a | 2033 | build_srat_memory(table_data, mem_base, mem_len, i - 1, |
4926403c EH |
2034 | MEM_AFFINITY_ENABLED); |
2035 | } | |
2036 | ||
2037 | /* Check for the rare case: 640K < RAM < 1M */ | |
2038 | if (next_base <= HOLE_640K_END) { | |
2039 | next_base = HOLE_640K_END; | |
2040 | continue; | |
2041 | } | |
2042 | mem_base = HOLE_640K_END; | |
2043 | mem_len = next_base - HOLE_640K_END; | |
2044 | } | |
2045 | ||
72c194f7 | 2046 | /* Cut out the ACPI_PCI hole */ |
f0bb276b PB |
2047 | if (mem_base <= x86ms->below_4g_mem_size && |
2048 | next_base > x86ms->below_4g_mem_size) { | |
2049 | mem_len -= next_base - x86ms->below_4g_mem_size; | |
72c194f7 | 2050 | if (mem_len > 0) { |
e5b6d55a | 2051 | build_srat_memory(table_data, mem_base, mem_len, i - 1, |
64b83136 | 2052 | MEM_AFFINITY_ENABLED); |
72c194f7 | 2053 | } |
4ab4c330 | 2054 | mem_base = x86ms->above_4g_mem_start; |
f0bb276b | 2055 | mem_len = next_base - x86ms->below_4g_mem_size; |
6cf6fe39 | 2056 | next_base = mem_base + mem_len; |
72c194f7 | 2057 | } |
16b42263 DL |
2058 | |
2059 | if (mem_len > 0) { | |
e5b6d55a | 2060 | build_srat_memory(table_data, mem_base, mem_len, i - 1, |
16b42263 DL |
2061 | MEM_AFFINITY_ENABLED); |
2062 | } | |
72c194f7 | 2063 | } |
c3b0cf6e VV |
2064 | |
2065 | if (machine->nvdimms_state->is_enabled) { | |
2066 | nvdimm_build_srat(table_data); | |
2067 | } | |
2068 | ||
11058123 YZ |
2069 | sgx_epc_build_srat(table_data); |
2070 | ||
e5b6d55a IM |
2071 | /* |
2072 | * TODO: this part is not in ACPI spec and current linux kernel boots fine | |
2073 | * without these entries. But I recall there were issues the last time I | |
2074 | * tried to remove it with some ancient guest OS, however I can't remember | |
2075 | * what that was so keep this around for now | |
2076 | */ | |
2077 | slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; | |
e77af21a | 2078 | for (; slots < nb_numa_nodes + 2; slots++) { |
e5b6d55a | 2079 | build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); |
72c194f7 MT |
2080 | } |
2081 | ||
dbb6da8b IM |
2082 | /* |
2083 | * Entry is required for Windows to enable memory hotplug in OS | |
2084 | * and for Linux to enable SWIOTLB when booted with less than | |
2085 | * 4G of RAM. Windows works better if the entry sets proximity | |
2086 | * to the highest NUMA node in the machine. | |
2087 | * Memory devices may override proximity set by this entry, | |
2088 | * providing _PXM method if necessary. | |
2089 | */ | |
4be8bfcb | 2090 | if (hotpluggable_address_space_size) { |
e5b6d55a | 2091 | build_srat_memory(table_data, machine->device_memory->base, |
4be8bfcb | 2092 | hotpluggable_address_space_size, nb_numa_nodes - 1, |
dbb6da8b | 2093 | MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); |
cec65193 IM |
2094 | } |
2095 | ||
255bf20f | 2096 | acpi_table_end(linker, &table); |
72c194f7 MT |
2097 | } |
2098 | ||
26863366 XW |
2099 | /* |
2100 | * Insert DMAR scope for PCI bridges and endpoint devcie | |
2101 | */ | |
2102 | static void | |
2103 | insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) | |
2104 | { | |
91a6b975 IM |
2105 | const size_t device_scope_size = 6 /* device scope structure */ + |
2106 | 2 /* 1 path entry */; | |
26863366 | 2107 | GArray *scope_blob = opaque; |
26863366 XW |
2108 | |
2109 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { | |
2110 | /* Dmar Scope Type: 0x02 for PCI Bridge */ | |
2111 | build_append_int_noprefix(scope_blob, 0x02, 1); | |
2112 | } else { | |
2113 | /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ | |
2114 | build_append_int_noprefix(scope_blob, 0x01, 1); | |
2115 | } | |
2116 | ||
2117 | /* length */ | |
91a6b975 | 2118 | build_append_int_noprefix(scope_blob, device_scope_size, 1); |
26863366 XW |
2119 | /* reserved */ |
2120 | build_append_int_noprefix(scope_blob, 0, 2); | |
2121 | /* enumeration_id */ | |
2122 | build_append_int_noprefix(scope_blob, 0, 1); | |
2123 | /* bus */ | |
2124 | build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); | |
2125 | /* device */ | |
2126 | build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); | |
2127 | /* function */ | |
2128 | build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); | |
2129 | } | |
2130 | ||
2131 | /* For a given PCI host bridge, walk and insert DMAR scope */ | |
2132 | static int | |
2133 | dmar_host_bridges(Object *obj, void *opaque) | |
2134 | { | |
2135 | GArray *scope_blob = opaque; | |
2136 | ||
2137 | if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { | |
2138 | PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; | |
2139 | ||
2140 | if (bus && !pci_bus_bypass_iommu(bus)) { | |
2914fc61 | 2141 | pci_for_each_device_under_bus(bus, insert_scope, scope_blob); |
26863366 XW |
2142 | } |
2143 | } | |
2144 | ||
2145 | return 0; | |
2146 | } | |
2147 | ||
d46114f9 | 2148 | /* |
91a6b975 IM |
2149 | * Intel ® Virtualization Technology for Directed I/O |
2150 | * Architecture Specification. Revision 3.3 | |
2151 | * 8.1 DMA Remapping Reporting Structure | |
d46114f9 | 2152 | */ |
d4eb9119 | 2153 | static void |
602b4582 MP |
2154 | build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, |
2155 | const char *oem_table_id) | |
d4eb9119 | 2156 | { |
d46114f9 | 2157 | uint8_t dmar_flags = 0; |
91a6b975 IM |
2158 | uint8_t rsvd10[10] = {}; |
2159 | /* Root complex IOAPIC uses one path only */ | |
2160 | const size_t ioapic_scope_size = 6 /* device scope structure */ + | |
2161 | 2 /* 1 path entry */; | |
d46114f9 | 2162 | X86IOMMUState *iommu = x86_iommu_get_default(); |
37f51384 | 2163 | IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); |
26863366 XW |
2164 | GArray *scope_blob = g_array_new(false, true, 1); |
2165 | ||
91a6b975 IM |
2166 | AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, |
2167 | .oem_table_id = oem_table_id }; | |
2168 | ||
26863366 XW |
2169 | /* |
2170 | * A PCI bus walk, for each PCI host bridge. | |
2171 | * Insert scope for each PCI bridge and endpoint device which | |
2172 | * is attached to a bus with iommu enabled. | |
2173 | */ | |
2174 | object_child_foreach_recursive(object_get_root(), | |
2175 | dmar_host_bridges, scope_blob); | |
d46114f9 PX |
2176 | |
2177 | assert(iommu); | |
a924b3d8 | 2178 | if (x86_iommu_ir_supported(iommu)) { |
d46114f9 PX |
2179 | dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ |
2180 | } | |
d4eb9119 | 2181 | |
91a6b975 IM |
2182 | acpi_table_begin(&table, table_data); |
2183 | /* Host Address Width */ | |
2184 | build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); | |
2185 | build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ | |
2186 | g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ | |
2187 | ||
2188 | /* 8.3 DMAR Remapping Hardware Unit Definition structure */ | |
2189 | build_append_int_noprefix(table_data, 0, 2); /* Type */ | |
2190 | /* Length */ | |
2191 | build_append_int_noprefix(table_data, | |
2192 | 16 + ioapic_scope_size + scope_blob->len, 2); | |
2193 | /* Flags */ | |
2194 | build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , | |
2195 | 1); | |
2196 | build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ | |
2197 | build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ | |
2198 | /* Register Base Address */ | |
2199 | build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); | |
d4eb9119 | 2200 | |
cfc13df4 PX |
2201 | /* Scope definition for the root-complex IOAPIC. See VT-d spec |
2202 | * 8.3.1 (version Oct. 2014 or later). */ | |
91a6b975 IM |
2203 | build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ |
2204 | build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ | |
2205 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
2206 | /* Enumeration ID */ | |
2207 | build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); | |
2208 | /* Start Bus Number */ | |
2209 | build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); | |
2210 | /* Path, {Device, Function} pair */ | |
2211 | build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); | |
2212 | build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); | |
cfc13df4 | 2213 | |
26863366 XW |
2214 | /* Add scope found above */ |
2215 | g_array_append_vals(table_data, scope_blob->data, scope_blob->len); | |
2216 | g_array_free(scope_blob, true); | |
2217 | ||
bd2baacc | 2218 | if (iommu->dt_supported) { |
91a6b975 IM |
2219 | /* 8.5 Root Port ATS Capability Reporting Structure */ |
2220 | build_append_int_noprefix(table_data, 2, 2); /* Type */ | |
2221 | build_append_int_noprefix(table_data, 8, 2); /* Length */ | |
2222 | build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ | |
2223 | build_append_int_noprefix(table_data, 0, 1); /* Reserved */ | |
2224 | build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ | |
bd2baacc JW |
2225 | } |
2226 | ||
91a6b975 | 2227 | acpi_table_end(linker, &table); |
d4eb9119 | 2228 | } |
14cda350 LA |
2229 | |
2230 | /* | |
2231 | * Windows ACPI Emulated Devices Table | |
2232 | * (Version 1.0 - April 6, 2009) | |
2233 | * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx | |
2234 | * | |
2235 | * Helpful to speedup Windows guests and ignored by others. | |
2236 | */ | |
2237 | static void | |
602b4582 MP |
2238 | build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, |
2239 | const char *oem_table_id) | |
14cda350 | 2240 | { |
eaa50764 IM |
2241 | AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, |
2242 | .oem_table_id = oem_table_id }; | |
14cda350 | 2243 | |
eaa50764 | 2244 | acpi_table_begin(&table, table_data); |
14cda350 LA |
2245 | /* |
2246 | * Set "ACPI PM timer good" flag. | |
2247 | * | |
2248 | * Tells Windows guests that our ACPI PM timer is reliable in the | |
2249 | * sense that guest can read it only once to obtain a reliable value. | |
2250 | * Which avoids costly VMExits caused by guest re-reading it unnecessarily. | |
2251 | */ | |
2252 | build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); | |
eaa50764 | 2253 | acpi_table_end(linker, &table); |
14cda350 LA |
2254 | } |
2255 | ||
fb9f5926 DK |
2256 | /* |
2257 | * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 | |
2258 | * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf | |
2259 | */ | |
c028818d BS |
2260 | #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) |
2261 | ||
977aff10 AW |
2262 | /* |
2263 | * Insert IVHD entry for device and recurse, insert alias, or insert range as | |
2264 | * necessary for the PCI topology. | |
2265 | */ | |
2266 | static void | |
2267 | insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) | |
2268 | { | |
2269 | GArray *table_data = opaque; | |
2270 | uint32_t entry; | |
2271 | ||
2272 | /* "Select" IVHD entry, type 0x2 */ | |
2273 | entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; | |
2274 | build_append_int_noprefix(table_data, entry, 4); | |
2275 | ||
2276 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { | |
2277 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); | |
2278 | uint8_t sec = pci_bus_num(sec_bus); | |
2279 | uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; | |
2280 | ||
2281 | if (pci_bus_is_express(sec_bus)) { | |
2282 | /* | |
2283 | * Walk the bus if there are subordinates, otherwise use a range | |
2284 | * to cover an entire leaf bus. We could potentially also use a | |
2285 | * range for traversed buses, but we'd need to take care not to | |
2286 | * create both Select and Range entries covering the same device. | |
2287 | * This is easier and potentially more compact. | |
2288 | * | |
2289 | * An example bare metal system seems to use Select entries for | |
2290 | * root ports without a slot (ie. built-ins) and Range entries | |
2291 | * when there is a slot. The same system also only hard-codes | |
2292 | * the alias range for an onboard PCIe-to-PCI bridge, apparently | |
2293 | * making no effort to support nested bridges. We attempt to | |
2294 | * be more thorough here. | |
2295 | */ | |
2296 | if (sec == sub) { /* leaf bus */ | |
2297 | /* "Start of Range" IVHD entry, type 0x3 */ | |
2298 | entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; | |
2299 | build_append_int_noprefix(table_data, entry, 4); | |
2300 | /* "End of Range" IVHD entry, type 0x4 */ | |
2301 | entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; | |
2302 | build_append_int_noprefix(table_data, entry, 4); | |
2303 | } else { | |
2304 | pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); | |
2305 | } | |
2306 | } else { | |
2307 | /* | |
2308 | * If the secondary bus is conventional, then we need to create an | |
2309 | * Alias range for everything downstream. The range covers the | |
2310 | * first devfn on the secondary bus to the last devfn on the | |
2311 | * subordinate bus. The alias target depends on legacy versus | |
2312 | * express bridges, just as in pci_device_iommu_address_space(). | |
2313 | * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. | |
2314 | */ | |
2315 | uint16_t dev_id_a, dev_id_b; | |
2316 | ||
2317 | dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); | |
2318 | ||
2319 | if (pci_is_express(dev) && | |
2320 | pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
2321 | dev_id_b = dev_id_a; | |
2322 | } else { | |
2323 | dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); | |
2324 | } | |
2325 | ||
2326 | /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ | |
2327 | build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); | |
2328 | build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); | |
2329 | ||
2330 | /* "End of Range" IVHD entry, type 0x4 */ | |
2331 | entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; | |
2332 | build_append_int_noprefix(table_data, entry, 4); | |
2333 | } | |
2334 | } | |
2335 | } | |
2336 | ||
2337 | /* For all PCI host bridges, walk and insert IVHD entries */ | |
2338 | static int | |
2339 | ivrs_host_bridges(Object *obj, void *opaque) | |
2340 | { | |
2341 | GArray *ivhd_blob = opaque; | |
2342 | ||
2343 | if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { | |
2344 | PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; | |
2345 | ||
dec2f563 | 2346 | if (bus && !pci_bus_bypass_iommu(bus)) { |
2914fc61 | 2347 | pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); |
977aff10 AW |
2348 | } |
2349 | } | |
2350 | ||
2351 | return 0; | |
2352 | } | |
2353 | ||
fb9f5926 | 2354 | static void |
602b4582 MP |
2355 | build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, |
2356 | const char *oem_table_id) | |
fb9f5926 | 2357 | { |
977aff10 | 2358 | int ivhd_table_len = 24; |
fb9f5926 | 2359 | AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); |
977aff10 | 2360 | GArray *ivhd_blob = g_array_new(false, true, 1); |
b0a45ff6 IM |
2361 | AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, |
2362 | .oem_table_id = oem_table_id }; | |
fb9f5926 | 2363 | |
b0a45ff6 | 2364 | acpi_table_begin(&table, table_data); |
fb9f5926 DK |
2365 | /* IVinfo - IO virtualization information common to all |
2366 | * IOMMU units in a system | |
2367 | */ | |
2368 | build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); | |
2369 | /* reserved */ | |
2370 | build_append_int_noprefix(table_data, 0, 8); | |
2371 | ||
2372 | /* IVHD definition - type 10h */ | |
2373 | build_append_int_noprefix(table_data, 0x10, 1); | |
2374 | /* virtualization flags */ | |
2375 | build_append_int_noprefix(table_data, | |
2376 | (1UL << 0) | /* HtTunEn */ | |
2377 | (1UL << 4) | /* iotblSup */ | |
2378 | (1UL << 6) | /* PrefSup */ | |
2379 | (1UL << 7), /* PPRSup */ | |
2380 | 1); | |
c028818d | 2381 | |
977aff10 AW |
2382 | /* |
2383 | * A PCI bus walk, for each PCI host bridge, is necessary to create a | |
2384 | * complete set of IVHD entries. Do this into a separate blob so that we | |
2385 | * can calculate the total IVRS table length here and then append the new | |
2386 | * blob further below. Fall back to an entry covering all devices, which | |
2387 | * is sufficient when no aliases are present. | |
2388 | */ | |
2389 | object_child_foreach_recursive(object_get_root(), | |
2390 | ivrs_host_bridges, ivhd_blob); | |
2391 | ||
2392 | if (!ivhd_blob->len) { | |
2393 | /* | |
2394 | * Type 1 device entry reporting all devices | |
2395 | * These are 4-byte device entries currently reporting the range of | |
2396 | * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) | |
2397 | */ | |
2398 | build_append_int_noprefix(ivhd_blob, 0x0000001, 4); | |
2399 | } | |
2400 | ||
2401 | ivhd_table_len += ivhd_blob->len; | |
2402 | ||
c028818d BS |
2403 | /* |
2404 | * When interrupt remapping is supported, we add a special IVHD device | |
2405 | * for type IO-APIC. | |
2406 | */ | |
a924b3d8 | 2407 | if (x86_iommu_ir_supported(x86_iommu_get_default())) { |
c028818d BS |
2408 | ivhd_table_len += 8; |
2409 | } | |
977aff10 | 2410 | |
fb9f5926 | 2411 | /* IVHD length */ |
c028818d | 2412 | build_append_int_noprefix(table_data, ivhd_table_len, 2); |
fb9f5926 DK |
2413 | /* DeviceID */ |
2414 | build_append_int_noprefix(table_data, s->devid, 2); | |
2415 | /* Capability offset */ | |
2416 | build_append_int_noprefix(table_data, s->capab_offset, 2); | |
2417 | /* IOMMU base address */ | |
2418 | build_append_int_noprefix(table_data, s->mmio.addr, 8); | |
2419 | /* PCI Segment Group */ | |
2420 | build_append_int_noprefix(table_data, 0, 2); | |
2421 | /* IOMMU info */ | |
2422 | build_append_int_noprefix(table_data, 0, 2); | |
2423 | /* IOMMU Feature Reporting */ | |
2424 | build_append_int_noprefix(table_data, | |
2425 | (48UL << 30) | /* HATS */ | |
2426 | (48UL << 28) | /* GATS */ | |
12499b23 BS |
2427 | (1UL << 2) | /* GTSup */ |
2428 | (1UL << 6), /* GASup */ | |
fb9f5926 | 2429 | 4); |
977aff10 AW |
2430 | |
2431 | /* IVHD entries as found above */ | |
2432 | g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); | |
2433 | g_array_free(ivhd_blob, TRUE); | |
fb9f5926 | 2434 | |
c028818d BS |
2435 | /* |
2436 | * Add a special IVHD device type. | |
2437 | * Refer to spec - Table 95: IVHD device entry type codes | |
2438 | * | |
2439 | * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). | |
2440 | * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' | |
2441 | */ | |
a924b3d8 | 2442 | if (x86_iommu_ir_supported(x86_iommu_get_default())) { |
c028818d BS |
2443 | build_append_int_noprefix(table_data, |
2444 | (0x1ull << 56) | /* type IOAPIC */ | |
2445 | (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ | |
2446 | 0x48, /* special device */ | |
2447 | 8); | |
2448 | } | |
b0a45ff6 | 2449 | acpi_table_end(linker, &table); |
fb9f5926 | 2450 | } |
d4eb9119 | 2451 | |
72c194f7 MT |
2452 | typedef |
2453 | struct AcpiBuildState { | |
2454 | /* Copy of table in RAM (for patching). */ | |
339240b5 | 2455 | MemoryRegion *table_mr; |
72c194f7 MT |
2456 | /* Is table patched? */ |
2457 | uint8_t patched; | |
d70414a5 | 2458 | void *rsdp; |
339240b5 PB |
2459 | MemoryRegion *rsdp_mr; |
2460 | MemoryRegion *linker_mr; | |
72c194f7 MT |
2461 | } AcpiBuildState; |
2462 | ||
2463 | static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) | |
2464 | { | |
2465 | Object *pci_host; | |
2466 | QObject *o; | |
72c194f7 | 2467 | |
ca6c1855 | 2468 | pci_host = acpi_get_i386_pci_host(); |
c0e427d6 JS |
2469 | if (!pci_host) { |
2470 | return false; | |
2471 | } | |
72c194f7 MT |
2472 | |
2473 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); | |
2474 | if (!o) { | |
2475 | return false; | |
2476 | } | |
c309434e | 2477 | mcfg->base = qnum_get_uint(qobject_to(QNum, o)); |
cb3e7f08 | 2478 | qobject_unref(o); |
c309434e | 2479 | if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { |
fe4970ad IM |
2480 | return false; |
2481 | } | |
72c194f7 MT |
2482 | |
2483 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); | |
2484 | assert(o); | |
c309434e | 2485 | mcfg->size = qnum_get_uint(qobject_to(QNum, o)); |
cb3e7f08 | 2486 | qobject_unref(o); |
72c194f7 MT |
2487 | return true; |
2488 | } | |
2489 | ||
2490 | static | |
3d3ebcad | 2491 | void acpi_build(AcpiBuildTables *tables, MachineState *machine) |
72c194f7 | 2492 | { |
3d3ebcad | 2493 | PCMachineState *pcms = PC_MACHINE(machine); |
bb292f5a | 2494 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 2495 | X86MachineState *x86ms = X86_MACHINE(machine); |
36efa250 | 2496 | DeviceState *iommu = pcms->iommu; |
72c194f7 | 2497 | GArray *table_offsets; |
41fa5c04 | 2498 | unsigned facs, dsdt, rsdt, fadt; |
72c194f7 MT |
2499 | AcpiPmInfo pm; |
2500 | AcpiMiscInfo misc; | |
2501 | AcpiMcfgInfo mcfg; | |
c0e427d6 | 2502 | Range pci_hole = {}, pci_hole64 = {}; |
72c194f7 | 2503 | uint8_t *u; |
07fb6176 | 2504 | size_t aml_len = 0; |
7c2c1fa5 | 2505 | GArray *tables_blob = tables->table_data; |
ae123749 | 2506 | AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; |
d03637bc | 2507 | Object *vmgenid_dev; |
602b4582 MP |
2508 | char *oem_id; |
2509 | char *oem_table_id; | |
72c194f7 | 2510 | |
0e11fc69 | 2511 | acpi_get_pm_info(machine, &pm); |
72c194f7 | 2512 | acpi_get_misc_info(&misc); |
01c9742d | 2513 | acpi_get_pci_holes(&pci_hole, &pci_hole64); |
ae123749 | 2514 | acpi_get_slic_oem(&slic_oem); |
72c194f7 | 2515 | |
602b4582 MP |
2516 | if (slic_oem.id) { |
2517 | oem_id = slic_oem.id; | |
2518 | } else { | |
d07b2286 | 2519 | oem_id = x86ms->oem_id; |
602b4582 MP |
2520 | } |
2521 | ||
2522 | if (slic_oem.table_id) { | |
2523 | oem_table_id = slic_oem.table_id; | |
2524 | } else { | |
d07b2286 | 2525 | oem_table_id = x86ms->oem_table_id; |
602b4582 MP |
2526 | } |
2527 | ||
72c194f7 MT |
2528 | table_offsets = g_array_new(false, true /* clear */, |
2529 | sizeof(uint32_t)); | |
8b310fc4 | 2530 | ACPI_BUILD_DPRINTF("init ACPI tables\n"); |
72c194f7 | 2531 | |
ad9671b8 IM |
2532 | bios_linker_loader_alloc(tables->linker, |
2533 | ACPI_BUILD_TABLE_FILE, tables_blob, | |
72c194f7 MT |
2534 | 64 /* Ensure FACS is aligned */, |
2535 | false /* high memory */); | |
2536 | ||
2537 | /* | |
2538 | * FACS is pointed to by FADT. | |
2539 | * We place it first since it's the only table that has alignment | |
2540 | * requirements. | |
2541 | */ | |
7c2c1fa5 | 2542 | facs = tables_blob->len; |
009180bd | 2543 | build_facs(tables_blob); |
72c194f7 MT |
2544 | |
2545 | /* DSDT is pointed to by FADT */ | |
7c2c1fa5 | 2546 | dsdt = tables_blob->len; |
01c9742d MA |
2547 | build_dsdt(tables_blob, tables->linker, &pm, &misc, |
2548 | &pci_hole, &pci_hole64, machine); | |
72c194f7 | 2549 | |
07fb6176 PB |
2550 | /* Count the size of the DSDT and SSDT, we will need it for legacy |
2551 | * sizing of ACPI tables. | |
2552 | */ | |
7c2c1fa5 | 2553 | aml_len += tables_blob->len - dsdt; |
07fb6176 | 2554 | |
72c194f7 | 2555 | /* ACPI tables pointed to by RSDT */ |
41fa5c04 | 2556 | fadt = tables_blob->len; |
7c2c1fa5 | 2557 | acpi_add_table(table_offsets, tables_blob); |
937d1b58 IM |
2558 | pm.fadt.facs_tbl_offset = &facs; |
2559 | pm.fadt.dsdt_tbl_offset = &dsdt; | |
2560 | pm.fadt.xdsdt_tbl_offset = &dsdt; | |
602b4582 | 2561 | build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); |
41fa5c04 | 2562 | aml_len += tables_blob->len - fadt; |
72c194f7 | 2563 | |
7c2c1fa5 | 2564 | acpi_add_table(table_offsets, tables_blob); |
eb66ffab | 2565 | acpi_build_madt(tables_blob, tables->linker, x86ms, |
d07b2286 MP |
2566 | ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, |
2567 | x86ms->oem_table_id); | |
9ac1c4c0 | 2568 | |
8486f12f ED |
2569 | #ifdef CONFIG_ACPI_ERST |
2570 | { | |
2571 | Object *erst_dev; | |
2572 | erst_dev = find_erst_dev(); | |
2573 | if (erst_dev) { | |
2574 | acpi_add_table(table_offsets, tables_blob); | |
2575 | build_erst(tables_blob, tables->linker, erst_dev, | |
2576 | x86ms->oem_id, x86ms->oem_table_id); | |
2577 | } | |
2578 | } | |
2579 | #endif | |
2580 | ||
d03637bc BW |
2581 | vmgenid_dev = find_vmgenid_dev(); |
2582 | if (vmgenid_dev) { | |
2583 | acpi_add_table(table_offsets, tables_blob); | |
2584 | vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, | |
d07b2286 | 2585 | tables->vmgenid, tables->linker, x86ms->oem_id); |
d03637bc BW |
2586 | } |
2587 | ||
72c194f7 | 2588 | if (misc.has_hpet) { |
7c2c1fa5 | 2589 | acpi_add_table(table_offsets, tables_blob); |
d07b2286 MP |
2590 | build_hpet(tables_blob, tables->linker, x86ms->oem_id, |
2591 | x86ms->oem_table_id); | |
711b20b4 | 2592 | } |
11fb99e6 | 2593 | #ifdef CONFIG_TPM |
5cb18b3d | 2594 | if (misc.tpm_version != TPM_VERSION_UNSPEC) { |
7e7c1b84 SB |
2595 | if (misc.tpm_version == TPM_VERSION_1_2) { |
2596 | acpi_add_table(table_offsets, tables_blob); | |
602b4582 | 2597 | build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, |
d07b2286 | 2598 | x86ms->oem_id, x86ms->oem_table_id); |
7e7c1b84 | 2599 | } else { /* TPM_VERSION_2_0 */ |
72d97b3a | 2600 | acpi_add_table(table_offsets, tables_blob); |
602b4582 | 2601 | build_tpm2(tables_blob, tables->linker, tables->tcpalog, |
d07b2286 | 2602 | x86ms->oem_id, x86ms->oem_table_id); |
5cb18b3d | 2603 | } |
72c194f7 | 2604 | } |
11fb99e6 | 2605 | #endif |
e77af21a | 2606 | if (machine->numa_state->num_nodes) { |
7c2c1fa5 | 2607 | acpi_add_table(table_offsets, tables_blob); |
3d3ebcad | 2608 | build_srat(tables_blob, tables->linker, machine); |
118154b7 | 2609 | if (machine->numa_state->have_numa_distance) { |
0f203430 | 2610 | acpi_add_table(table_offsets, tables_blob); |
d07b2286 MP |
2611 | build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, |
2612 | x86ms->oem_table_id); | |
0f203430 | 2613 | } |
e6f123c3 LJ |
2614 | if (machine->numa_state->hmat_enabled) { |
2615 | acpi_add_table(table_offsets, tables_blob); | |
602b4582 | 2616 | build_hmat(tables_blob, tables->linker, machine->numa_state, |
d07b2286 | 2617 | x86ms->oem_id, x86ms->oem_table_id); |
e6f123c3 | 2618 | } |
72c194f7 MT |
2619 | } |
2620 | if (acpi_get_mcfg(&mcfg)) { | |
7c2c1fa5 | 2621 | acpi_add_table(table_offsets, tables_blob); |
d07b2286 MP |
2622 | build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, |
2623 | x86ms->oem_table_id); | |
72c194f7 | 2624 | } |
867e9c9f JPB |
2625 | if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { |
2626 | acpi_add_table(table_offsets, tables_blob); | |
2627 | build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, | |
2628 | x86ms->oem_table_id); | |
2629 | } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { | |
2630 | acpi_add_table(table_offsets, tables_blob); | |
2631 | build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, | |
2632 | x86ms->oem_table_id); | |
36efa250 JPB |
2633 | } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { |
2634 | PCIDevice *pdev = PCI_DEVICE(iommu); | |
2635 | ||
2636 | acpi_add_table(table_offsets, tables_blob); | |
2637 | build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), | |
2638 | x86ms->oem_id, x86ms->oem_table_id); | |
d4eb9119 | 2639 | } |
f6a0d06b | 2640 | if (machine->nvdimms_state->is_enabled) { |
ad9671b8 | 2641 | nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, |
602b4582 | 2642 | machine->nvdimms_state, machine->ram_slots, |
d07b2286 | 2643 | x86ms->oem_id, x86ms->oem_table_id); |
87252e1b | 2644 | } |
1ebf9001 | 2645 | if (pcms->cxl_devices_state.is_enabled) { |
51359805 | 2646 | cxl_build_cedt(table_offsets, tables_blob, tables->linker, |
1ebf9001 | 2647 | x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); |
3d6a69b6 | 2648 | } |
87252e1b | 2649 | |
14cda350 | 2650 | acpi_add_table(table_offsets, tables_blob); |
d07b2286 | 2651 | build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); |
14cda350 | 2652 | |
72c194f7 MT |
2653 | /* Add tables supplied by user (if any) */ |
2654 | for (u = acpi_table_first(); u; u = acpi_table_next(u)) { | |
2655 | unsigned len = acpi_table_len(u); | |
2656 | ||
7c2c1fa5 IM |
2657 | acpi_add_table(table_offsets, tables_blob); |
2658 | g_array_append_vals(tables_blob, u, len); | |
72c194f7 MT |
2659 | } |
2660 | ||
2661 | /* RSDT is pointed to by RSDP */ | |
7c2c1fa5 | 2662 | rsdt = tables_blob->len; |
ae123749 | 2663 | build_rsdt(tables_blob, tables->linker, table_offsets, |
602b4582 | 2664 | oem_id, oem_table_id); |
72c194f7 MT |
2665 | |
2666 | /* RSDP is in FSEG memory, so allocate it separately */ | |
a46ce1c2 SO |
2667 | { |
2668 | AcpiRsdpData rsdp_data = { | |
2669 | .revision = 0, | |
d07b2286 | 2670 | .oem_id = x86ms->oem_id, |
a46ce1c2 SO |
2671 | .xsdt_tbl_offset = NULL, |
2672 | .rsdt_tbl_offset = &rsdt, | |
2673 | }; | |
2674 | build_rsdp(tables->rsdp, tables->linker, &rsdp_data); | |
2675 | if (!pcmc->rsdp_in_ram) { | |
2676 | /* We used to allocate some extra space for RSDP revision 2 but | |
2677 | * only used the RSDP revision 0 space. The extra bytes were | |
2678 | * zeroed out and not used. | |
2679 | * Here we continue wasting those extra 16 bytes to make sure we | |
2680 | * don't break migration for machine types 2.2 and older due to | |
2681 | * RSDP blob size mismatch. | |
2682 | */ | |
2683 | build_append_int_noprefix(tables->rsdp, 0, 16); | |
2684 | } | |
2685 | } | |
72c194f7 | 2686 | |
07fb6176 | 2687 | /* We'll expose it all to Guest so we want to reduce |
72c194f7 | 2688 | * chance of size changes. |
07fb6176 PB |
2689 | * |
2690 | * We used to align the tables to 4k, but of course this would | |
2691 | * too simple to be enough. 4k turned out to be too small an | |
2692 | * alignment very soon, and in fact it is almost impossible to | |
2693 | * keep the table size stable for all (max_cpus, max_memory_slots) | |
2694 | * combinations. So the table size is always 64k for pc-i440fx-2.1 | |
2695 | * and we give an error if the table grows beyond that limit. | |
2696 | * | |
2697 | * We still have the problem of migrating from "-M pc-i440fx-2.0". For | |
2698 | * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables | |
2699 | * than 2.0 and we can always pad the smaller tables with zeros. We can | |
2700 | * then use the exact size of the 2.0 tables. | |
2701 | * | |
2702 | * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. | |
72c194f7 | 2703 | */ |
bb292f5a | 2704 | if (pcmc->legacy_acpi_table_size) { |
07fb6176 PB |
2705 | /* Subtracting aml_len gives the size of fixed tables. Then add the |
2706 | * size of the PIIX4 DSDT/SSDT in QEMU 2.0. | |
2707 | */ | |
2708 | int legacy_aml_len = | |
bb292f5a | 2709 | pcmc->legacy_acpi_table_size + |
f0bb276b | 2710 | ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; |
07fb6176 | 2711 | int legacy_table_size = |
7c2c1fa5 | 2712 | ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, |
07fb6176 | 2713 | ACPI_BUILD_ALIGN_SIZE); |
7c2c1fa5 | 2714 | if (tables_blob->len > legacy_table_size) { |
07fb6176 | 2715 | /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ |
9e5d2c52 AF |
2716 | warn_report("ACPI table size %u exceeds %d bytes," |
2717 | " migration may not work", | |
2718 | tables_blob->len, legacy_table_size); | |
2719 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
2720 | " or PCI bridges."); | |
07fb6176 | 2721 | } |
7c2c1fa5 | 2722 | g_array_set_size(tables_blob, legacy_table_size); |
07fb6176 | 2723 | } else { |
868270f2 | 2724 | /* Make sure we have a buffer in case we need to resize the tables. */ |
7c2c1fa5 | 2725 | if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { |
18045fb9 | 2726 | /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ |
9e5d2c52 AF |
2727 | warn_report("ACPI table size %u exceeds %d bytes," |
2728 | " migration may not work", | |
2729 | tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); | |
2730 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
2731 | " or PCI bridges."); | |
18045fb9 | 2732 | } |
7c2c1fa5 | 2733 | acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); |
07fb6176 | 2734 | } |
72c194f7 | 2735 | |
0e9b9eda | 2736 | acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); |
72c194f7 MT |
2737 | |
2738 | /* Cleanup memory that's no longer used. */ | |
2739 | g_array_free(table_offsets, true); | |
8cdb99af IM |
2740 | g_free(slic_oem.id); |
2741 | g_free(slic_oem.table_id); | |
72c194f7 MT |
2742 | } |
2743 | ||
339240b5 | 2744 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) |
42d85900 MT |
2745 | { |
2746 | uint32_t size = acpi_data_len(data); | |
2747 | ||
2748 | /* Make sure RAM size is correct - in case it got changed e.g. by migration */ | |
339240b5 | 2749 | memory_region_ram_resize(mr, size, &error_abort); |
42d85900 | 2750 | |
339240b5 PB |
2751 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); |
2752 | memory_region_set_dirty(mr, 0, size); | |
42d85900 MT |
2753 | } |
2754 | ||
3f8752b4 | 2755 | static void acpi_build_update(void *build_opaque) |
72c194f7 MT |
2756 | { |
2757 | AcpiBuildState *build_state = build_opaque; | |
2758 | AcpiBuildTables tables; | |
2759 | ||
2760 | /* No state to update or already patched? Nothing to do. */ | |
2761 | if (!build_state || build_state->patched) { | |
2762 | return; | |
2763 | } | |
2764 | build_state->patched = 1; | |
2765 | ||
2766 | acpi_build_tables_init(&tables); | |
2767 | ||
3d3ebcad | 2768 | acpi_build(&tables, MACHINE(qdev_get_machine())); |
72c194f7 | 2769 | |
339240b5 | 2770 | acpi_ram_update(build_state->table_mr, tables.table_data); |
a1666142 | 2771 | |
42d85900 MT |
2772 | if (build_state->rsdp) { |
2773 | memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); | |
2774 | } else { | |
339240b5 | 2775 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); |
42d85900 | 2776 | } |
ad5b88b1 | 2777 | |
0e9b9eda | 2778 | acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); |
72c194f7 MT |
2779 | acpi_build_tables_cleanup(&tables, true); |
2780 | } | |
2781 | ||
2782 | static void acpi_build_reset(void *build_opaque) | |
2783 | { | |
2784 | AcpiBuildState *build_state = build_opaque; | |
2785 | build_state->patched = 0; | |
2786 | } | |
2787 | ||
72c194f7 MT |
2788 | static const VMStateDescription vmstate_acpi_build = { |
2789 | .name = "acpi_build", | |
2790 | .version_id = 1, | |
2791 | .minimum_version_id = 1, | |
d49805ae | 2792 | .fields = (VMStateField[]) { |
72c194f7 MT |
2793 | VMSTATE_UINT8(patched, AcpiBuildState), |
2794 | VMSTATE_END_OF_LIST() | |
2795 | }, | |
2796 | }; | |
2797 | ||
fb306ffe | 2798 | void acpi_setup(void) |
72c194f7 | 2799 | { |
fb306ffe | 2800 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); |
bb292f5a | 2801 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 2802 | X86MachineState *x86ms = X86_MACHINE(pcms); |
72c194f7 MT |
2803 | AcpiBuildTables tables; |
2804 | AcpiBuildState *build_state; | |
d03637bc | 2805 | Object *vmgenid_dev; |
11fb99e6 | 2806 | #ifdef CONFIG_TPM |
0fe24669 SB |
2807 | TPMIf *tpm; |
2808 | static FwCfgTPMConfig tpm_config; | |
11fb99e6 | 2809 | #endif |
72c194f7 | 2810 | |
f0bb276b | 2811 | if (!x86ms->fw_cfg) { |
8b310fc4 | 2812 | ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); |
72c194f7 MT |
2813 | return; |
2814 | } | |
2815 | ||
021746c1 | 2816 | if (!pcms->acpi_build_enabled) { |
8b310fc4 | 2817 | ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); |
72c194f7 MT |
2818 | return; |
2819 | } | |
2820 | ||
17e89077 | 2821 | if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { |
8b310fc4 | 2822 | ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); |
81adc513 MT |
2823 | return; |
2824 | } | |
2825 | ||
72c194f7 MT |
2826 | build_state = g_malloc0(sizeof *build_state); |
2827 | ||
72c194f7 | 2828 | acpi_build_tables_init(&tables); |
3d3ebcad | 2829 | acpi_build(&tables, MACHINE(pcms)); |
72c194f7 MT |
2830 | |
2831 | /* Now expose it all to Guest */ | |
82f76c67 WY |
2832 | build_state->table_mr = acpi_add_rom_blob(acpi_build_update, |
2833 | build_state, tables.table_data, | |
6930ba0d | 2834 | ACPI_BUILD_TABLE_FILE); |
339240b5 | 2835 | assert(build_state->table_mr != NULL); |
72c194f7 | 2836 | |
339240b5 | 2837 | build_state->linker_mr = |
82f76c67 | 2838 | acpi_add_rom_blob(acpi_build_update, build_state, |
6930ba0d | 2839 | tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); |
72c194f7 | 2840 | |
11fb99e6 | 2841 | #ifdef CONFIG_TPM |
f0bb276b | 2842 | fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, |
42a5b308 SB |
2843 | tables.tcpalog->data, acpi_data_len(tables.tcpalog)); |
2844 | ||
0fe24669 SB |
2845 | tpm = tpm_find(); |
2846 | if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { | |
2847 | tpm_config = (FwCfgTPMConfig) { | |
2848 | .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), | |
2849 | .tpm_version = tpm_get_version(tpm), | |
ac6dd31e | 2850 | .tpmppi_version = TPM_PPI_VERSION_1_30 |
0fe24669 | 2851 | }; |
f0bb276b | 2852 | fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", |
0fe24669 SB |
2853 | &tpm_config, sizeof tpm_config); |
2854 | } | |
11fb99e6 | 2855 | #endif |
0fe24669 | 2856 | |
d03637bc BW |
2857 | vmgenid_dev = find_vmgenid_dev(); |
2858 | if (vmgenid_dev) { | |
f0bb276b | 2859 | vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, |
d03637bc BW |
2860 | tables.vmgenid); |
2861 | } | |
2862 | ||
bb292f5a | 2863 | if (!pcmc->rsdp_in_ram) { |
358774d7 IM |
2864 | /* |
2865 | * Keep for compatibility with old machine types. | |
2866 | * Though RSDP is small, its contents isn't immutable, so | |
afaa2e4b | 2867 | * we'll update it along with the rest of tables on guest access. |
358774d7 | 2868 | */ |
afaa2e4b MT |
2869 | uint32_t rsdp_size = acpi_data_len(tables.rsdp); |
2870 | ||
2871 | build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); | |
f0bb276b | 2872 | fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, |
5f9252f7 | 2873 | acpi_build_update, NULL, build_state, |
baf2d5bf | 2874 | build_state->rsdp, rsdp_size, true); |
339240b5 | 2875 | build_state->rsdp_mr = NULL; |
358774d7 | 2876 | } else { |
42d85900 | 2877 | build_state->rsdp = NULL; |
82f76c67 WY |
2878 | build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, |
2879 | build_state, tables.rsdp, | |
6930ba0d | 2880 | ACPI_BUILD_RSDP_FILE); |
358774d7 | 2881 | } |
72c194f7 MT |
2882 | |
2883 | qemu_register_reset(acpi_build_reset, build_state); | |
2884 | acpi_build_reset(build_state); | |
2885 | vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); | |
2886 | ||
2887 | /* Cleanup tables but don't free the memory: we track it | |
2888 | * in build_state. | |
2889 | */ | |
2890 | acpi_build_tables_cleanup(&tables, false); | |
2891 | } |