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tpm: allocate/map buffer for TPM Physical Presence interface
[mirror_qemu.git] / hw / i386 / acpi-build.c
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72c194f7
MT		 1/* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
b6a0aa05 23#include "qemu/osdep.h"
da34e65c 24#include "qapi/error.h"
15280c36 25#include "qapi/qmp/qnum.h"
72c194f7 26#include "acpi-build.h"
72c194f7
MT		 27#include "qemu-common.h"
28#include "qemu/bitmap.h"
07fb6176 29#include "qemu/error-report.h"
72c194f7
MT		 30#include "hw/pci/pci.h"
31#include "qom/cpu.h"
fcf5ef2a 32#include "target/i386/cpu.h"
0d5d8a3a 33#include "hw/misc/pvpanic.h"
72c194f7 34#include "hw/timer/hpet.h"
395e5fb4 35#include "hw/acpi/acpi-defs.h"
72c194f7 36#include "hw/acpi/acpi.h"
679dd1a9 37#include "hw/acpi/cpu.h"
72c194f7 38#include "hw/nvram/fw_cfg.h"
0058ae1d 39#include "hw/acpi/bios-linker-loader.h"
72c194f7 40#include "hw/loader.h"
15bce1b7 41#include "hw/isa/isa.h"
27b9fc54 42#include "hw/block/fdc.h"
bef3492d 43#include "hw/acpi/memory_hotplug.h"
711b20b4
SB		 44#include "sysemu/tpm.h"
45#include "hw/acpi/tpm.h"
d03637bc 46#include "hw/acpi/vmgenid.h"
5cb18b3d 47#include "sysemu/tpm_backend.h"
f070efa8 48#include "hw/timer/mc146818rtc_regs.h"
2cc0e2e8 49#include "hw/mem/memory-device.h"
1f3aba37 50#include "sysemu/numa.h"
72c194f7
MT		 51
52/* Supported chipsets: */
53#include "hw/acpi/piix4.h"
99fd437d 54#include "hw/acpi/pcihp.h"
72c194f7
MT		 55#include "hw/i386/ich9.h"
56#include "hw/pci/pci_bus.h"
57#include "hw/pci-host/q35.h"
1cf5fd57 58#include "hw/i386/x86-iommu.h"
72c194f7 59
19934e0e
IM		 60#include "hw/acpi/aml-build.h"
61
72c194f7 62#include "qom/qom-qobject.h"
fb9f5926
DK		 63#include "hw/i386/amd_iommu.h"
64#include "hw/i386/intel_iommu.h"
72c194f7 65
86e91dd7
CM		 66#include "hw/acpi/ipmi.h"
67
07fb6176
PB		 68/* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
69 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
70 * a little bit, there should be plenty of free space since the DSDT
71 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
72 */
73#define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
74#define ACPI_BUILD_ALIGN_SIZE 0x1000
75
868270f2 76#define ACPI_BUILD_TABLE_SIZE 0x20000
18045fb9 77
8b310fc4
GA		 78/* #define DEBUG_ACPI_BUILD */
79#ifdef DEBUG_ACPI_BUILD
80#define ACPI_BUILD_DPRINTF(fmt, ...) \
81 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
82#else
83#define ACPI_BUILD_DPRINTF(fmt, ...)
84#endif
85
cfc13df4
PX		 86/* Default IOAPIC ID */
87#define ACPI_BUILD_IOAPIC_ID 0x0
88
72c194f7
MT		 89typedef struct AcpiMcfgInfo {
90 uint64_t mcfg_base;
91 uint32_t mcfg_size;
92} AcpiMcfgInfo;
93
94typedef struct AcpiPmInfo {
95 bool s3_disabled;
96 bool s4_disabled;
133a2da4 97 bool pcihp_bridge_en;
72c194f7 98 uint8_t s4_val;
937d1b58 99 AcpiFadtData fadt;
ddf1ec2f 100 uint16_t cpu_hp_io_base;
500b11ea
IM		 101 uint16_t pcihp_io_base;
102 uint16_t pcihp_io_len;
72c194f7
MT		 103} AcpiPmInfo;
104
105typedef struct AcpiMiscInfo {
e4db2798 106 bool is_piix4;
72c194f7 107 bool has_hpet;
5cb18b3d 108 TPMVersion tpm_version;
72c194f7
MT		 109 const unsigned char *dsdt_code;
110 unsigned dsdt_size;
111 uint16_t pvpanic_port;
8ac6f7a6 112 uint16_t applesmc_io_base;
72c194f7
MT		 113} AcpiMiscInfo;
114
99fd437d
MT		 115typedef struct AcpiBuildPciBusHotplugState {
116 GArray *device_table;
117 GArray *notify_table;
118 struct AcpiBuildPciBusHotplugState *parent;
133a2da4 119 bool pcihp_bridge_en;
99fd437d
MT		 120} AcpiBuildPciBusHotplugState;
121
937d1b58
IM		 122static void init_common_fadt_data(Object *o, AcpiFadtData *data)
123{
124 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
125 AmlAddressSpace as = AML_AS_SYSTEM_IO;
126 AcpiFadtData fadt = {
127 .rev = 3,
128 .flags =
129 (1 << ACPI_FADT_F_WBINVD) |
130 (1 << ACPI_FADT_F_PROC_C1) |
131 (1 << ACPI_FADT_F_SLP_BUTTON) |
132 (1 << ACPI_FADT_F_RTC_S4) |
133 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
134 /* APIC destination mode ("Flat Logical") has an upper limit of 8
135 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
136 * used
137 */
138 ((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
139 .int_model = 1 /* Multiple APIC */,
140 .rtc_century = RTC_CENTURY,
141 .plvl2_lat = 0xfff /* C2 state not supported */,
142 .plvl3_lat = 0xfff /* C3 state not supported */,
143 .smi_cmd = ACPI_PORT_SMI_CMD,
144 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
145 .acpi_enable_cmd =
146 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
147 .acpi_disable_cmd =
148 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
149 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
150 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
151 .address = io + 0x04 },
152 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
153 .gpe0_blk = { .space_id = as, .bit_width =
154 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
155 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
156 },
157 };
158 *data = fadt;
159}
160
72c194f7
MT		 161static void acpi_get_pm_info(AcpiPmInfo *pm)
162{
163 Object *piix = piix4_pm_find();
164 Object *lpc = ich9_lpc_find();
697155cd 165 Object *obj = piix ? piix : lpc;
72c194f7 166 QObject *o;
94aaca64 167 pm->cpu_hp_io_base = 0;
500b11ea
IM		 168 pm->pcihp_io_base = 0;
169 pm->pcihp_io_len = 0;
937d1b58
IM		 170
171 init_common_fadt_data(obj, &pm->fadt);
72c194f7 172 if (piix) {
3a3fcc75 173 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
937d1b58 174 pm->fadt.rev = 1;
ddf1ec2f 175 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
500b11ea 176 pm->pcihp_io_base =
35f91e50 177 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
500b11ea 178 pm->pcihp_io_len =
35f91e50 179 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
72c194f7
MT		 180 }
181 if (lpc) {
937d1b58
IM		 182 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
183 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
184 pm->fadt.reset_reg = r;
185 pm->fadt.reset_val = 0xf;
186 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
ddf1ec2f 187 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
72c194f7
MT		 188 }
189 assert(obj);
190
937d1b58
IM		 191 /* The above need not be conditional on machine type because the reset port
192 * happens to be the same on PIIX (pc) and ICH9 (q35). */
193 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
194
72c194f7
MT		 195 /* Fill in optional s3/s4 related properties */
196 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
197 if (o) {
7dc847eb 198 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
72c194f7
MT		 199 } else {
200 pm->s3_disabled = false;
201 }
cb3e7f08 202 qobject_unref(o);
72c194f7
MT		 203 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
204 if (o) {
7dc847eb 205 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
72c194f7
MT		 206 } else {
207 pm->s4_disabled = false;
208 }
cb3e7f08 209 qobject_unref(o);
72c194f7
MT		 210 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
211 if (o) {
7dc847eb 212 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
72c194f7
MT		 213 } else {
214 pm->s4_val = false;
215 }
cb3e7f08 216 qobject_unref(o);
72c194f7 217
133a2da4
IM		 218 pm->pcihp_bridge_en =
219 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
220 NULL);
72c194f7
MT		 221}
222
72c194f7
MT		 223static void acpi_get_misc_info(AcpiMiscInfo *info)
224{
3db119da
IM		 225 Object *piix = piix4_pm_find();
226 Object *lpc = ich9_lpc_find();
227 assert(!!piix != !!lpc);
228
229 if (piix) {
230 info->is_piix4 = true;
231 }
232 if (lpc) {
233 info->is_piix4 = false;
234 }
235
72c194f7 236 info->has_hpet = hpet_find();
3dfd5a2a 237 info->tpm_version = tpm_get_version(tpm_find());
72c194f7 238 info->pvpanic_port = pvpanic_port();
8ac6f7a6 239 info->applesmc_io_base = applesmc_port();
72c194f7
MT		 240}
241
ca6c1855
MA		 242/*
243 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
244 * On i386 arch we only have two pci hosts, so we can look only for them.
245 */
246static Object *acpi_get_i386_pci_host(void)
247{
248 PCIHostState *host;
249
250 host = OBJECT_CHECK(PCIHostState,
251 object_resolve_path("/machine/i440fx", NULL),
252 TYPE_PCI_HOST_BRIDGE);
253 if (!host) {
254 host = OBJECT_CHECK(PCIHostState,
255 object_resolve_path("/machine/q35", NULL),
256 TYPE_PCI_HOST_BRIDGE);
257 }
258
259 return OBJECT(host);
260}
261
01c9742d 262static void acpi_get_pci_holes(Range *hole, Range *hole64)
72c194f7
MT		 263{
264 Object *pci_host;
72c194f7 265
ca6c1855 266 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 267 g_assert(pci_host);
268
a0efbf16 269 range_set_bounds1(hole,
60555365
MAL		 270 object_property_get_uint(pci_host,
271 PCI_HOST_PROP_PCI_HOLE_START,
272 NULL),
273 object_property_get_uint(pci_host,
274 PCI_HOST_PROP_PCI_HOLE_END,
275 NULL));
a0efbf16 276 range_set_bounds1(hole64,
60555365
MAL		 277 object_property_get_uint(pci_host,
278 PCI_HOST_PROP_PCI_HOLE64_START,
279 NULL),
280 object_property_get_uint(pci_host,
281 PCI_HOST_PROP_PCI_HOLE64_END,
282 NULL));
72c194f7
MT		 283}
284
72c194f7
MT		 285static void acpi_align_size(GArray *blob, unsigned align)
286{
287 /* Align size to multiple of given size. This reduces the chance
288 * we need to change size in the future (breaking cross version migration).
289 */
134d42d6 290 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
72c194f7
MT		 291}
292
72c194f7
MT		 293/* FACS */
294static void
0e9b9eda 295build_facs(GArray *table_data, BIOSLinker *linker)
72c194f7
MT		 296{
297 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
821e3227 298 memcpy(&facs->signature, "FACS", 4);
72c194f7
MT		 299 facs->length = cpu_to_le32(sizeof(*facs));
300}
301
ac35f13b 302void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
80e5db30 303 const CPUArchIdList *apic_ids, GArray *entry)
ac35f13b 304{
e2c95939
IM		 305 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
306
307 /* ACPI spec says that LAPIC entry for non present
308 * CPU may be omitted from MADT or it must be marked
309 * as disabled. However omitting non present CPU from
310 * MADT breaks hotplug on linux. So possible CPUs
311 * should be put in MADT but kept disabled.
312 */
313 if (apic_id < 255) {
314 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
315
316 apic->type = ACPI_APIC_PROCESSOR;
317 apic->length = sizeof(*apic);
318 apic->processor_id = uid;
319 apic->local_apic_id = apic_id;
320 if (apic_ids->cpus[uid].cpu != NULL) {
321 apic->flags = cpu_to_le32(1);
322 } else {
323 apic->flags = cpu_to_le32(0);
324 }
ac35f13b 325 } else {
e2c95939
IM		 326 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
327
328 apic->type = ACPI_APIC_LOCAL_X2APIC;
329 apic->length = sizeof(*apic);
330 apic->uid = cpu_to_le32(uid);
331 apic->x2apic_id = cpu_to_le32(apic_id);
332 if (apic_ids->cpus[uid].cpu != NULL) {
333 apic->flags = cpu_to_le32(1);
334 } else {
335 apic->flags = cpu_to_le32(0);
336 }
ac35f13b
IM		 337 }
338}
339
72c194f7 340static void
0e9b9eda 341build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
72c194f7 342{
907e7c94 343 MachineClass *mc = MACHINE_GET_CLASS(pcms);
80e5db30 344 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
72c194f7 345 int madt_start = table_data->len;
ac35f13b
IM		 346 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
347 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
e2c95939 348 bool x2apic_mode = false;
72c194f7
MT		 349
350 AcpiMultipleApicTable *madt;
351 AcpiMadtIoApic *io_apic;
352 AcpiMadtIntsrcovr *intsrcovr;
72c194f7
MT		 353 int i;
354
355 madt = acpi_data_push(table_data, sizeof *madt);
356 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
357 madt->flags = cpu_to_le32(1);
358
907e7c94 359 for (i = 0; i < apic_ids->len; i++) {
ac35f13b 360 adevc->madt_cpu(adev, i, apic_ids, table_data);
e2c95939
IM		 361 if (apic_ids->cpus[i].arch_id > 254) {
362 x2apic_mode = true;
363 }
72c194f7 364 }
907e7c94 365
72c194f7
MT		 366 io_apic = acpi_data_push(table_data, sizeof *io_apic);
367 io_apic->type = ACPI_APIC_IO;
368 io_apic->length = sizeof(*io_apic);
72c194f7
MT		 369 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
370 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
371 io_apic->interrupt = cpu_to_le32(0);
372
dd4c2f01 373 if (pcms->apic_xrupt_override) {
72c194f7
MT		 374 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
375 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
376 intsrcovr->length = sizeof(*intsrcovr);
377 intsrcovr->source = 0;
378 intsrcovr->gsi = cpu_to_le32(2);
379 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
380 }
381 for (i = 1; i < 16; i++) {
382#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
383 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
384 /* No need for a INT source override structure. */
385 continue;
386 }
387 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
388 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
389 intsrcovr->length = sizeof(*intsrcovr);
390 intsrcovr->source = i;
391 intsrcovr->gsi = cpu_to_le32(i);
392 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
393 }
394
e2c95939
IM		 395 if (x2apic_mode) {
396 AcpiMadtLocalX2ApicNmi *local_nmi;
397
398 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
399 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
400 local_nmi->length = sizeof(*local_nmi);
401 local_nmi->uid = 0xFFFFFFFF; /* all processors */
402 local_nmi->flags = cpu_to_le16(0);
403 local_nmi->lint = 1; /* ACPI_LINT1 */
404 } else {
405 AcpiMadtLocalNmi *local_nmi;
406
407 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
408 local_nmi->type = ACPI_APIC_LOCAL_NMI;
409 local_nmi->length = sizeof(*local_nmi);
410 local_nmi->processor_id = 0xff; /* all processors */
411 local_nmi->flags = cpu_to_le16(0);
412 local_nmi->lint = 1; /* ACPI_LINT1 */
413 }
72c194f7
MT		 414
415 build_header(linker, table_data,
821e3227 416 (void *)(table_data->data + madt_start), "APIC",
37ad223c 417 table_data->len - madt_start, 1, NULL, NULL);
72c194f7
MT		 418}
419
62b52c26 420static void build_append_pcihp_notify_entry(Aml *method, int slot)
99fd437d 421{
62b52c26
IM		 422 Aml *if_ctx;
423 int32_t devfn = PCI_DEVFN(slot, 0);
424
5530427f 425 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
62b52c26
IM		 426 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
427 aml_append(method, if_ctx);
99fd437d
MT		 428}
429
62b52c26 430static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
b23046ab 431 bool pcihp_bridge_en)
99fd437d 432{
7dc847eb 433 Aml *dev, *notify_method = NULL, *method;
99fd437d 434 QObject *bsel;
b23046ab
IM		 435 PCIBus *sec;
436 int i;
133a2da4 437
99fd437d
MT		 438 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
439 if (bsel) {
7dc847eb 440 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
62b52c26
IM		 441
442 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
4dbfc881 443 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
8dcf525a 444 }
99fd437d 445
8dcf525a
MT		 446 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
447 DeviceClass *dc;
448 PCIDeviceClass *pc;
449 PCIDevice *pdev = bus->devices[i];
450 int slot = PCI_SLOT(i);
b23046ab 451 bool hotplug_enabled_dev;
093a35e5 452 bool bridge_in_acpi;
99fd437d 453
8dcf525a 454 if (!pdev) {
b23046ab 455 if (bsel) { /* add hotplug slots for non present devices */
62b52c26
IM		 456 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
457 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
458 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
4dbfc881 459 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 460 aml_append(method,
461 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
462 );
463 aml_append(dev, method);
464 aml_append(parent_scope, dev);
465
466 build_append_pcihp_notify_entry(notify_method, slot);
b23046ab 467 }
8dcf525a
MT		 468 continue;
469 }
99fd437d 470
8dcf525a
MT		 471 pc = PCI_DEVICE_GET_CLASS(pdev);
472 dc = DEVICE_GET_CLASS(pdev);
99fd437d 473
093a35e5
MT		 474 /* When hotplug for bridges is enabled, bridges are
475 * described in ACPI separately (see build_pci_bus_end).
476 * In this case they aren't themselves hot-pluggable.
a20275fa 477 * Hotplugged bridges *are* hot-pluggable.
093a35e5 478 */
b23046ab
IM		 479 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
480 !DEVICE(pdev)->hotplugged;
481
482 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
093a35e5 483
b23046ab
IM		 484 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
485 continue;
99fd437d
MT		 486 }
487
62b52c26
IM		 488 /* start to compose PCI slot descriptor */
489 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
490 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
491
8dcf525a 492 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
62b52c26
IM		 493 /* add VGA specific AML methods */
494 int s3d;
495
8dcf525a 496 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
62b52c26 497 s3d = 3;
b23046ab 498 } else {
62b52c26 499 s3d = 0;
99fd437d 500 }
62b52c26 501
4dbfc881 502 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 503 aml_append(method, aml_return(aml_int(0)));
504 aml_append(dev, method);
505
4dbfc881 506 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 507 aml_append(method, aml_return(aml_int(0)));
508 aml_append(dev, method);
509
4dbfc881 510 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 511 aml_append(method, aml_return(aml_int(s3d)));
512 aml_append(dev, method);
b23046ab 513 } else if (hotplug_enabled_dev) {
62b52c26
IM		 514 /* add _SUN/_EJ0 to make slot hotpluggable */
515 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
99fd437d 516
4dbfc881 517 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 518 aml_append(method,
519 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
520 );
521 aml_append(dev, method);
522
523 if (bsel) {
524 build_append_pcihp_notify_entry(notify_method, slot);
525 }
b23046ab 526 } else if (bridge_in_acpi) {
62b52c26
IM		 527 /*
528 * device is coldplugged bridge,
529 * add child device descriptions into its scope
530 */
b23046ab 531 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
b23046ab 532
62b52c26 533 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
8dcf525a 534 }
62b52c26
IM		 535 /* slot descriptor has been composed, add it into parent context */
536 aml_append(parent_scope, dev);
8dcf525a
MT		 537 }
538
539 if (bsel) {
62b52c26 540 aml_append(parent_scope, notify_method);
99fd437d
MT		 541 }
542
543 /* Append PCNT method to notify about events on local and child buses.
544 * Add unconditionally for root since DSDT expects it.
72c194f7 545 */
4dbfc881 546 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
99fd437d 547
b23046ab
IM		 548 /* If bus supports hotplug select it and notify about local events */
549 if (bsel) {
7dc847eb 550 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
01b2ffce 551
62b52c26
IM		 552 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
553 aml_append(method,
554 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
555 );
556 aml_append(method,
557 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
558 );
b23046ab 559 }
99fd437d 560
b23046ab
IM		 561 /* Notify about child bus events in any case */
562 if (pcihp_bridge_en) {
563 QLIST_FOREACH(sec, &bus->child, sibling) {
62b52c26
IM		 564 int32_t devfn = sec->parent_dev->devfn;
565
c99cb18e
MA		 566 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
567 continue;
568 }
569
62b52c26 570 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
99fd437d 571 }
72c194f7 572 }
62b52c26 573 aml_append(parent_scope, method);
cb3e7f08 574 qobject_unref(bsel);
72c194f7
MT		 575}
576
196e2137
IM		 577/**
578 * build_prt_entry:
579 * @link_name: link name for PCI route entry
580 *
581 * build AML package containing a PCI route entry for @link_name
582 */
583static Aml *build_prt_entry(const char *link_name)
584{
585 Aml *a_zero = aml_int(0);
586 Aml *pkg = aml_package(4);
587 aml_append(pkg, a_zero);
588 aml_append(pkg, a_zero);
589 aml_append(pkg, aml_name("%s", link_name));
590 aml_append(pkg, a_zero);
591 return pkg;
592}
593
0d8935e3
MA		 594/*
595 * initialize_route - Initialize the interrupt routing rule
596 * through a specific LINK:
597 * if (lnk_idx == idx)
598 * route using link 'link_name'
599 */
600static Aml *initialize_route(Aml *route, const char *link_name,
601 Aml *lnk_idx, int idx)
602{
603 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
196e2137 604 Aml *pkg = build_prt_entry(link_name);
0d8935e3 605
0d8935e3
MA		 606 aml_append(if_ctx, aml_store(pkg, route));
607
608 return if_ctx;
609}
610
611/*
612 * build_prt - Define interrupt rounting rules
613 *
614 * Returns an array of 128 routes, one for each device,
615 * based on device location.
616 * The main goal is to equaly distribute the interrupts
617 * over the 4 existing ACPI links (works only for i440fx).
618 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
619 *
620 */
196e2137 621static Aml *build_prt(bool is_pci0_prt)
0d8935e3
MA		 622{
623 Aml *method, *while_ctx, *pin, *res;
624
4dbfc881 625 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
0d8935e3
MA		 626 res = aml_local(0);
627 pin = aml_local(1);
628 aml_append(method, aml_store(aml_package(128), res));
629 aml_append(method, aml_store(aml_int(0), pin));
630
631 /* while (pin < 128) */
632 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
633 {
634 Aml *slot = aml_local(2);
635 Aml *lnk_idx = aml_local(3);
636 Aml *route = aml_local(4);
637
638 /* slot = pin >> 2 */
639 aml_append(while_ctx,
c360639a 640 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
0d8935e3
MA		 641 /* lnk_idx = (slot + pin) & 3 */
642 aml_append(while_ctx,
5530427f
IM		 643 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
644 lnk_idx));
0d8935e3
MA		 645
646 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
647 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
196e2137
IM		 648 if (is_pci0_prt) {
649 Aml *if_device_1, *if_pin_4, *else_pin_4;
650
651 /* device 1 is the power-management device, needs SCI */
652 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
653 {
654 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
655 {
656 aml_append(if_pin_4,
657 aml_store(build_prt_entry("LNKS"), route));
658 }
659 aml_append(if_device_1, if_pin_4);
660 else_pin_4 = aml_else();
661 {
662 aml_append(else_pin_4,
663 aml_store(build_prt_entry("LNKA"), route));
664 }
665 aml_append(if_device_1, else_pin_4);
666 }
667 aml_append(while_ctx, if_device_1);
668 } else {
669 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
670 }
0d8935e3
MA		 671 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
672 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
673
674 /* route[0] = 0x[slot]FFFF */
675 aml_append(while_ctx,
ca3df95d
IM		 676 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
677 NULL),
0d8935e3
MA		 678 aml_index(route, aml_int(0))));
679 /* route[1] = pin & 3 */
680 aml_append(while_ctx,
5530427f
IM		 681 aml_store(aml_and(pin, aml_int(3), NULL),
682 aml_index(route, aml_int(1))));
0d8935e3
MA		 683 /* res[pin] = route */
684 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
685 /* pin++ */
686 aml_append(while_ctx, aml_increment(pin));
687 }
688 aml_append(method, while_ctx);
689 /* return res*/
690 aml_append(method, aml_return(res));
691
692 return method;
693}
694
a43c6e27
MA		 695typedef struct CrsRangeEntry {
696 uint64_t base;
697 uint64_t limit;
698} CrsRangeEntry;
699
700static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
701{
702 CrsRangeEntry *entry;
703
704 entry = g_malloc(sizeof(*entry));
705 entry->base = base;
706 entry->limit = limit;
707
708 g_ptr_array_add(ranges, entry);
709}
710
711static void crs_range_free(gpointer data)
712{
713 CrsRangeEntry *entry = (CrsRangeEntry *)data;
714 g_free(entry);
715}
716
2df5a7b5
MA		 717typedef struct CrsRangeSet {
718 GPtrArray *io_ranges;
719 GPtrArray *mem_ranges;
16de88a4 720 GPtrArray *mem_64bit_ranges;
2df5a7b5
MA		 721 } CrsRangeSet;
722
723static void crs_range_set_init(CrsRangeSet *range_set)
724{
725 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
726 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
16de88a4
MA		 727 range_set->mem_64bit_ranges =
728 g_ptr_array_new_with_free_func(crs_range_free);
2df5a7b5
MA		 729}
730
731static void crs_range_set_free(CrsRangeSet *range_set)
732{
733 g_ptr_array_free(range_set->io_ranges, true);
734 g_ptr_array_free(range_set->mem_ranges, true);
16de88a4 735 g_ptr_array_free(range_set->mem_64bit_ranges, true);
2df5a7b5
MA		 736}
737
dcdca296
MA		 738static gint crs_range_compare(gconstpointer a, gconstpointer b)
739{
740 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
741 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
742
743 return (int64_t)entry_a->base - (int64_t)entry_b->base;
744}
745
746/*
747 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
748 * interval, computes the 'free' ranges from the same interval.
749 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
750 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
751 */
752static void crs_replace_with_free_ranges(GPtrArray *ranges,
753 uint64_t start, uint64_t end)
754{
354fb471 755 GPtrArray *free_ranges = g_ptr_array_new();
dcdca296
MA		 756 uint64_t free_base = start;
757 int i;
758
759 g_ptr_array_sort(ranges, crs_range_compare);
760 for (i = 0; i < ranges->len; i++) {
761 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
762
763 if (free_base < used->base) {
764 crs_range_insert(free_ranges, free_base, used->base - 1);
765 }
766
767 free_base = used->limit + 1;
768 }
769
770 if (free_base < end) {
771 crs_range_insert(free_ranges, free_base, end);
772 }
773
774 g_ptr_array_set_size(ranges, 0);
775 for (i = 0; i < free_ranges->len; i++) {
776 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
777 }
778
354fb471 779 g_ptr_array_free(free_ranges, true);
dcdca296
MA		 780}
781
d7fd0e69
MA		 782/*
783 * crs_range_merge - merges adjacent ranges in the given array.
784 * Array elements are deleted and replaced with the merged ranges.
785 */
786static void crs_range_merge(GPtrArray *range)
787{
788 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
789 CrsRangeEntry *entry;
790 uint64_t range_base, range_limit;
791 int i;
792
793 if (!range->len) {
794 return;
795 }
796
797 g_ptr_array_sort(range, crs_range_compare);
798
799 entry = g_ptr_array_index(range, 0);
800 range_base = entry->base;
801 range_limit = entry->limit;
802 for (i = 1; i < range->len; i++) {
803 entry = g_ptr_array_index(range, i);
804 if (entry->base - 1 == range_limit) {
805 range_limit = entry->limit;
806 } else {
807 crs_range_insert(tmp, range_base, range_limit);
808 range_base = entry->base;
809 range_limit = entry->limit;
810 }
811 }
812 crs_range_insert(tmp, range_base, range_limit);
813
814 g_ptr_array_set_size(range, 0);
815 for (i = 0; i < tmp->len; i++) {
816 entry = g_ptr_array_index(tmp, i);
817 crs_range_insert(range, entry->base, entry->limit);
818 }
819 g_ptr_array_free(tmp, true);
820}
821
2df5a7b5 822static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
a43c6e27
MA		 823{
824 Aml *crs = aml_resource_template();
2df5a7b5 825 CrsRangeSet temp_range_set;
d7fd0e69 826 CrsRangeEntry *entry;
a43c6e27
MA		 827 uint8_t max_bus = pci_bus_num(host->bus);
828 uint8_t type;
829 int devfn;
d7fd0e69 830 int i;
a43c6e27 831
2df5a7b5 832 crs_range_set_init(&temp_range_set);
a43c6e27 833 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
a43c6e27
MA		 834 uint64_t range_base, range_limit;
835 PCIDevice *dev = host->bus->devices[devfn];
836
837 if (!dev) {
838 continue;
839 }
840
841 for (i = 0; i < PCI_NUM_REGIONS; i++) {
842 PCIIORegion *r = &dev->io_regions[i];
843
844 range_base = r->addr;
845 range_limit = r->addr + r->size - 1;
846
0f6dd8e1
MA		 847 /*
848 * Work-around for old bioses
849 * that do not support multiple root buses
850 */
851 if (!range_base || range_base > range_limit) {
852 continue;
853 }
854
a43c6e27 855 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
2df5a7b5
MA		 856 crs_range_insert(temp_range_set.io_ranges,
857 range_base, range_limit);
a43c6e27 858 } else { /* "memory" */
2df5a7b5
MA		 859 crs_range_insert(temp_range_set.mem_ranges,
860 range_base, range_limit);
a43c6e27
MA		 861 }
862 }
863
864 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
865 if (type == PCI_HEADER_TYPE_BRIDGE) {
866 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
867 if (subordinate > max_bus) {
868 max_bus = subordinate;
869 }
870
871 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
872 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
0f6dd8e1
MA		 873
874 /*
875 * Work-around for old bioses
876 * that do not support multiple root buses
877 */
4ebc736e 878 if (range_base && range_base <= range_limit) {
2df5a7b5
MA		 879 crs_range_insert(temp_range_set.io_ranges,
880 range_base, range_limit);
0f6dd8e1 881 }
a43c6e27
MA		 882
883 range_base =
884 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
885 range_limit =
886 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
0f6dd8e1
MA		 887
888 /*
889 * Work-around for old bioses
890 * that do not support multiple root buses
891 */
4ebc736e 892 if (range_base && range_base <= range_limit) {
16de88a4
MA		 893 uint64_t length = range_limit - range_base + 1;
894 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
895 crs_range_insert(temp_range_set.mem_ranges,
896 range_base, range_limit);
897 } else {
898 crs_range_insert(temp_range_set.mem_64bit_ranges,
899 range_base, range_limit);
900 }
4ebc736e 901 }
a43c6e27
MA		 902
903 range_base =
904 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
905 range_limit =
906 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
0f6dd8e1
MA		 907
908 /*
909 * Work-around for old bioses
910 * that do not support multiple root buses
911 */
4ebc736e 912 if (range_base && range_base <= range_limit) {
16de88a4
MA		 913 uint64_t length = range_limit - range_base + 1;
914 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
915 crs_range_insert(temp_range_set.mem_ranges,
916 range_base, range_limit);
917 } else {
918 crs_range_insert(temp_range_set.mem_64bit_ranges,
919 range_base, range_limit);
920 }
0f6dd8e1 921 }
a43c6e27
MA		 922 }
923 }
924
2df5a7b5
MA		 925 crs_range_merge(temp_range_set.io_ranges);
926 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
927 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
d7fd0e69
MA		 928 aml_append(crs,
929 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
930 AML_POS_DECODE, AML_ENTIRE_RANGE,
931 0, entry->base, entry->limit, 0,
932 entry->limit - entry->base + 1));
2df5a7b5 933 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
d7fd0e69 934 }
d7fd0e69 935
2df5a7b5
MA		 936 crs_range_merge(temp_range_set.mem_ranges);
937 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
938 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
d7fd0e69
MA		 939 aml_append(crs,
940 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
941 AML_MAX_FIXED, AML_NON_CACHEABLE,
942 AML_READ_WRITE,
943 0, entry->base, entry->limit, 0,
944 entry->limit - entry->base + 1));
2df5a7b5 945 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
d7fd0e69 946 }
2df5a7b5 947
16de88a4
MA		 948 crs_range_merge(temp_range_set.mem_64bit_ranges);
949 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
950 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
951 aml_append(crs,
952 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
953 AML_MAX_FIXED, AML_NON_CACHEABLE,
954 AML_READ_WRITE,
955 0, entry->base, entry->limit, 0,
956 entry->limit - entry->base + 1));
957 crs_range_insert(range_set->mem_64bit_ranges,
958 entry->base, entry->limit);
959 }
960
2df5a7b5 961 crs_range_set_free(&temp_range_set);
d7fd0e69 962
a43c6e27 963 aml_append(crs,
dcdca296 964 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
a43c6e27
MA		 965 0,
966 pci_bus_num(host->bus),
967 max_bus,
968 0,
969 max_bus - pci_bus_num(host->bus) + 1));
970
971 return crs;
972}
973
a57d708d
IM		 974static void build_hpet_aml(Aml *table)
975{
976 Aml *crs;
977 Aml *field;
978 Aml *method;
979 Aml *if_ctx;
980 Aml *scope = aml_scope("_SB");
981 Aml *dev = aml_device("HPET");
982 Aml *zero = aml_int(0);
983 Aml *id = aml_local(0);
984 Aml *period = aml_local(1);
985
986 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
987 aml_append(dev, aml_name_decl("_UID", zero));
988
989 aml_append(dev,
3f3009c0
XG		 990 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
991 HPET_LEN));
a57d708d
IM		 992 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
993 aml_append(field, aml_named_field("VEND", 32));
994 aml_append(field, aml_named_field("PRD", 32));
995 aml_append(dev, field);
996
997 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
998 aml_append(method, aml_store(aml_name("VEND"), id));
999 aml_append(method, aml_store(aml_name("PRD"), period));
1000 aml_append(method, aml_shiftright(id, aml_int(16), id));
1001 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1002 aml_equal(id, aml_int(0xffff))));
1003 {
1004 aml_append(if_ctx, aml_return(zero));
1005 }
1006 aml_append(method, if_ctx);
1007
1008 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1009 aml_lgreater(period, aml_int(100000000))));
1010 {
1011 aml_append(if_ctx, aml_return(zero));
1012 }
1013 aml_append(method, if_ctx);
1014
1015 aml_append(method, aml_return(aml_int(0x0F)));
1016 aml_append(dev, method);
1017
1018 crs = aml_resource_template();
1019 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1020 aml_append(dev, aml_name_decl("_CRS", crs));
1021
1022 aml_append(scope, dev);
1023 aml_append(table, scope);
1024}
1025
27b9fc54 1026static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
95ed7e97 1027{
27b9fc54
RK		 1028 Aml *dev, *fdi;
1029 uint8_t maxc, maxh, maxs;
1030
1031 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1032
1033 dev = aml_device("FLP%c", 'A' + idx);
1034
1035 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1036
1037 fdi = aml_package(16);
1038 aml_append(fdi, aml_int(idx)); /* Drive Number */
1039 aml_append(fdi,
1040 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1041 /*
1042 * the values below are the limits of the drive, and are thus independent
1043 * of the inserted media
1044 */
1045 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1046 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1047 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1048 /*
1049 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1050 * the drive type, so shall we
1051 */
1052 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1053 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1054 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1055 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1056 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1057 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1058 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1059 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1060 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1061 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1062 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1063
1064 aml_append(dev, aml_name_decl("_FDI", fdi));
1065 return dev;
1066}
1067
1068static Aml *build_fdc_device_aml(ISADevice *fdc)
1069{
1070 int i;
95ed7e97
IM		 1071 Aml *dev;
1072 Aml *crs;
95ed7e97 1073
27b9fc54
RK		 1074#define ACPI_FDE_MAX_FD 4
1075 uint32_t fde_buf[5] = {
1076 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1077 cpu_to_le32(2) /* tape presence (2 == never present) */
1078 };
1079
95ed7e97
IM		 1080 dev = aml_device("FDC0");
1081 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1082
95ed7e97
IM		 1083 crs = aml_resource_template();
1084 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1085 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1086 aml_append(crs, aml_irq_no_flags(6));
1087 aml_append(crs,
1088 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1089 aml_append(dev, aml_name_decl("_CRS", crs));
1090
27b9fc54
RK		 1091 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1092 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1093
1094 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1095 fde_buf[i] = cpu_to_le32(1); /* drive present */
1096 aml_append(dev, build_fdinfo_aml(i, type));
1097 }
1098 }
1099 aml_append(dev, aml_name_decl("_FDE",
1100 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1101
95ed7e97
IM		 1102 return dev;
1103}
1104
ee135849
IM		 1105static Aml *build_rtc_device_aml(void)
1106{
1107 Aml *dev;
1108 Aml *crs;
1109
1110 dev = aml_device("RTC");
1111 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1112 crs = aml_resource_template();
1113 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1114 aml_append(crs, aml_irq_no_flags(8));
1115 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
95ed7e97 1116 aml_append(dev, aml_name_decl("_CRS", crs));
f58190e2
IM		 1117
1118 return dev;
1119}
1120
1121static Aml *build_kbd_device_aml(void)
1122{
1123 Aml *dev;
1124 Aml *crs;
1125 Aml *method;
1126
1127 dev = aml_device("KBD");
1128 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1129
1130 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1131 aml_append(method, aml_return(aml_int(0x0f)));
1132 aml_append(dev, method);
1133
1134 crs = aml_resource_template();
1135 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1136 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1137 aml_append(crs, aml_irq_no_flags(1));
ee135849
IM		 1138 aml_append(dev, aml_name_decl("_CRS", crs));
1139
1140 return dev;
1141}
1142
c355cb2c
IM		 1143static Aml *build_mouse_device_aml(void)
1144{
1145 Aml *dev;
1146 Aml *crs;
1147 Aml *method;
1148
1149 dev = aml_device("MOU");
1150 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1151
1152 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1153 aml_append(method, aml_return(aml_int(0x0f)));
1154 aml_append(dev, method);
1155
1156 crs = aml_resource_template();
1157 aml_append(crs, aml_irq_no_flags(12));
1158 aml_append(dev, aml_name_decl("_CRS", crs));
1159
1160 return dev;
1161}
1162
8b1da5f8
IM		 1163static Aml *build_lpt_device_aml(void)
1164{
1165 Aml *dev;
1166 Aml *crs;
1167 Aml *method;
1168 Aml *if_ctx;
1169 Aml *else_ctx;
1170 Aml *zero = aml_int(0);
1171 Aml *is_present = aml_local(0);
1172
1173 dev = aml_device("LPT");
1174 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1175
1176 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1177 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1178 if_ctx = aml_if(aml_equal(is_present, zero));
1179 {
1180 aml_append(if_ctx, aml_return(aml_int(0x00)));
1181 }
1182 aml_append(method, if_ctx);
1183 else_ctx = aml_else();
1184 {
1185 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1186 }
1187 aml_append(method, else_ctx);
1188 aml_append(dev, method);
1189
1190 crs = aml_resource_template();
1191 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1192 aml_append(crs, aml_irq_no_flags(7));
1193 aml_append(dev, aml_name_decl("_CRS", crs));
1194
1195 return dev;
1196}
1197
28f1f0e9
IM		 1198static Aml *build_com_device_aml(uint8_t uid)
1199{
1200 Aml *dev;
1201 Aml *crs;
1202 Aml *method;
1203 Aml *if_ctx;
1204 Aml *else_ctx;
1205 Aml *zero = aml_int(0);
1206 Aml *is_present = aml_local(0);
1207 const char *enabled_field = "CAEN";
1208 uint8_t irq = 4;
1209 uint16_t io_port = 0x03F8;
1210
1211 assert(uid == 1 || uid == 2);
1212 if (uid == 2) {
1213 enabled_field = "CBEN";
1214 irq = 3;
1215 io_port = 0x02F8;
1216 }
1217
1218 dev = aml_device("COM%d", uid);
1219 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1220 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1221
1222 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1223 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1224 if_ctx = aml_if(aml_equal(is_present, zero));
1225 {
1226 aml_append(if_ctx, aml_return(aml_int(0x00)));
1227 }
1228 aml_append(method, if_ctx);
1229 else_ctx = aml_else();
1230 {
1231 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1232 }
1233 aml_append(method, else_ctx);
1234 aml_append(dev, method);
1235
1236 crs = aml_resource_template();
1237 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1238 aml_append(crs, aml_irq_no_flags(irq));
1239 aml_append(dev, aml_name_decl("_CRS", crs));
1240
1241 return dev;
1242}
1243
ee135849
IM		 1244static void build_isa_devices_aml(Aml *table)
1245{
27b9fc54 1246 ISADevice *fdc = pc_find_fdc0();
86e91dd7 1247 bool ambiguous;
27b9fc54 1248
ee135849 1249 Aml *scope = aml_scope("_SB.PCI0.ISA");
86e91dd7 1250 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
ee135849
IM		 1251
1252 aml_append(scope, build_rtc_device_aml());
f58190e2 1253 aml_append(scope, build_kbd_device_aml());
c355cb2c 1254 aml_append(scope, build_mouse_device_aml());
27b9fc54
RK		 1255 if (fdc) {
1256 aml_append(scope, build_fdc_device_aml(fdc));
9b613f4e 1257 }
8b1da5f8 1258 aml_append(scope, build_lpt_device_aml());
28f1f0e9
IM		 1259 aml_append(scope, build_com_device_aml(1));
1260 aml_append(scope, build_com_device_aml(2));
ee135849 1261
86e91dd7
CM		 1262 if (ambiguous) {
1263 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1264 } else if (!obj) {
1265 error_report("No ISA bus, unable to define IPMI ACPI data");
1266 } else {
1267 build_acpi_ipmi_devices(scope, BUS(obj));
1268 }
1269
ee135849
IM		 1270 aml_append(table, scope);
1271}
1272
3892a2b7
IM		 1273static void build_dbg_aml(Aml *table)
1274{
1275 Aml *field;
1276 Aml *method;
1277 Aml *while_ctx;
1278 Aml *scope = aml_scope("\\");
1279 Aml *buf = aml_local(0);
1280 Aml *len = aml_local(1);
1281 Aml *idx = aml_local(2);
1282
1283 aml_append(scope,
3f3009c0 1284 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
3892a2b7
IM		 1285 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1286 aml_append(field, aml_named_field("DBGB", 8));
1287 aml_append(scope, field);
1288
1289 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1290
1291 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1292 aml_append(method, aml_to_buffer(buf, buf));
1293 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1294 aml_append(method, aml_store(aml_int(0), idx));
1295
1296 while_ctx = aml_while(aml_lless(idx, len));
1297 aml_append(while_ctx,
1298 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1299 aml_append(while_ctx, aml_increment(idx));
1300 aml_append(method, while_ctx);
1301
1302 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1303 aml_append(scope, method);
1304
1305 aml_append(table, scope);
1306}
1307
c35b6e80
IM		 1308static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1309{
1310 Aml *dev;
1311 Aml *crs;
1312 Aml *method;
1313 uint32_t irqs[] = {5, 10, 11};
1314
1315 dev = aml_device("%s", name);
1316 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1317 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1318
1319 crs = aml_resource_template();
1320 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1321 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1322 aml_append(dev, aml_name_decl("_PRS", crs));
1323
1324 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1325 aml_append(method, aml_return(aml_call1("IQST", reg)));
1326 aml_append(dev, method);
1327
1328 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1329 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1330 aml_append(dev, method);
1331
1332 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1333 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1334 aml_append(dev, method);
1335
1336 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1337 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1338 aml_append(method, aml_store(aml_name("PRRI"), reg));
1339 aml_append(dev, method);
1340
1341 return dev;
1342 }
1343
80b32df5
IM		 1344static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1345{
1346 Aml *dev;
1347 Aml *crs;
1348 Aml *method;
1349 uint32_t irqs;
1350
1351 dev = aml_device("%s", name);
1352 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1353 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1354
1355 crs = aml_resource_template();
1356 irqs = gsi;
1357 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1358 AML_SHARED, &irqs, 1));
1359 aml_append(dev, aml_name_decl("_PRS", crs));
1360
1361 aml_append(dev, aml_name_decl("_CRS", crs));
1362
c82f503d
MA		 1363 /*
1364 * _DIS can be no-op because the interrupt cannot be disabled.
1365 */
1366 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1367 aml_append(dev, method);
1368
80b32df5
IM		 1369 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1370 aml_append(dev, method);
1371
1372 return dev;
1373}
1374
16682a9d
IM		 1375/* _CRS method - get current settings */
1376static Aml *build_iqcr_method(bool is_piix4)
1377{
1378 Aml *if_ctx;
1379 uint32_t irqs;
1380 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1381 Aml *crs = aml_resource_template();
1382
1383 irqs = 0;
1384 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1385 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1386 aml_append(method, aml_name_decl("PRR0", crs));
1387
1388 aml_append(method,
1389 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1390
1391 if (is_piix4) {
1392 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1393 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1394 aml_append(method, if_ctx);
1395 } else {
1396 aml_append(method,
1397 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1398 aml_name("PRRI")));
1399 }
1400
1401 aml_append(method, aml_return(aml_name("PRR0")));
1402 return method;
1403}
1404
78e1ad05
IM		 1405/* _STA method - get status */
1406static Aml *build_irq_status_method(void)
1407{
1408 Aml *if_ctx;
1409 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1410
1411 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1412 aml_append(if_ctx, aml_return(aml_int(0x09)));
1413 aml_append(method, if_ctx);
1414 aml_append(method, aml_return(aml_int(0x0B)));
1415 return method;
1416}
1417
e4db2798
IM		 1418static void build_piix4_pci0_int(Aml *table)
1419{
c35b6e80
IM		 1420 Aml *dev;
1421 Aml *crs;
e4db2798 1422 Aml *field;
c35b6e80
IM		 1423 Aml *method;
1424 uint32_t irqs;
e4db2798 1425 Aml *sb_scope = aml_scope("_SB");
196e2137
IM		 1426 Aml *pci0_scope = aml_scope("PCI0");
1427
1428 aml_append(pci0_scope, build_prt(true));
1429 aml_append(sb_scope, pci0_scope);
e4db2798
IM		 1430
1431 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1432 aml_append(field, aml_named_field("PRQ0", 8));
1433 aml_append(field, aml_named_field("PRQ1", 8));
1434 aml_append(field, aml_named_field("PRQ2", 8));
1435 aml_append(field, aml_named_field("PRQ3", 8));
1436 aml_append(sb_scope, field);
1437
78e1ad05 1438 aml_append(sb_scope, build_irq_status_method());
16682a9d 1439 aml_append(sb_scope, build_iqcr_method(true));
100681cc 1440
c35b6e80
IM		 1441 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1442 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1443 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1444 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1445
1446 dev = aml_device("LNKS");
1447 {
1448 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1449 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1450
1451 crs = aml_resource_template();
1452 irqs = 9;
1453 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1454 AML_ACTIVE_HIGH, AML_SHARED,
1455 &irqs, 1));
1456 aml_append(dev, aml_name_decl("_PRS", crs));
1457
1458 /* The SCI cannot be disabled and is always attached to GSI 9,
1459 * so these are no-ops. We only need this link to override the
1460 * polarity to active high and match the content of the MADT.
1461 */
1462 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1463 aml_append(method, aml_return(aml_int(0x0b)));
1464 aml_append(dev, method);
1465
1466 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1467 aml_append(dev, method);
1468
1469 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1470 aml_append(method, aml_return(aml_name("_PRS")));
1471 aml_append(dev, method);
1472
1473 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1474 aml_append(dev, method);
1475 }
1476 aml_append(sb_scope, dev);
1477
e4db2798
IM		 1478 aml_append(table, sb_scope);
1479}
1480
22b5b8bf
IM		 1481static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1482{
1483 int i;
1484 int head;
1485 Aml *pkg;
1486 char base = name[3] < 'E' ? 'A' : 'E';
1487 char *s = g_strdup(name);
1488 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1489
1490 assert(strlen(s) == 4);
1491
1492 head = name[3] - base;
1493 for (i = 0; i < 4; i++) {
1494 if (head + i > 3) {
1495 head = i * -1;
1496 }
1497 s[3] = base + head + i;
1498 pkg = aml_package(4);
1499 aml_append(pkg, a_nr);
1500 aml_append(pkg, aml_int(i));
1501 aml_append(pkg, aml_name("%s", s));
1502 aml_append(pkg, aml_int(0));
1503 aml_append(ctx, pkg);
1504 }
1505 g_free(s);
1506}
1507
1508static Aml *build_q35_routing_table(const char *str)
1509{
1510 int i;
1511 Aml *pkg;
1512 char *name = g_strdup_printf("%s ", str);
1513
1514 pkg = aml_package(128);
1515 for (i = 0; i < 0x18; i++) {
1516 name[3] = 'E' + (i & 0x3);
1517 append_q35_prt_entry(pkg, i, name);
1518 }
1519
1520 name[3] = 'E';
1521 append_q35_prt_entry(pkg, 0x18, name);
1522
1523 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1524 for (i = 0x0019; i < 0x1e; i++) {
1525 name[3] = 'A';
1526 append_q35_prt_entry(pkg, i, name);
1527 }
1528
1529 /* PCIe->PCI bridge. use PIRQ[E-H] */
1530 name[3] = 'E';
1531 append_q35_prt_entry(pkg, 0x1e, name);
1532 name[3] = 'A';
1533 append_q35_prt_entry(pkg, 0x1f, name);
1534
1535 g_free(name);
1536 return pkg;
1537}
1538
80b32df5
IM		 1539static void build_q35_pci0_int(Aml *table)
1540{
41f95a52 1541 Aml *field;
0dafe3b3 1542 Aml *method;
80b32df5 1543 Aml *sb_scope = aml_scope("_SB");
0dafe3b3
IM		 1544 Aml *pci0_scope = aml_scope("PCI0");
1545
e9fce798
IM		 1546 /* Zero => PIC mode, One => APIC Mode */
1547 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1548 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1549 {
1550 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1551 }
1552 aml_append(table, method);
1553
65aef4de
IM		 1554 aml_append(pci0_scope,
1555 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
22b5b8bf
IM		 1556 aml_append(pci0_scope,
1557 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1558
0dafe3b3
IM		 1559 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1560 {
1561 Aml *if_ctx;
1562 Aml *else_ctx;
1563
1564 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1565 section 6.2.8.1 */
1566 /* Note: we provide the same info as the PCI routing
1567 table of the Bochs BIOS */
1568 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1569 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1570 aml_append(method, if_ctx);
1571 else_ctx = aml_else();
1572 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1573 aml_append(method, else_ctx);
1574 }
1575 aml_append(pci0_scope, method);
1576 aml_append(sb_scope, pci0_scope);
80b32df5 1577
41f95a52
IM		 1578 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1579 aml_append(field, aml_named_field("PRQA", 8));
1580 aml_append(field, aml_named_field("PRQB", 8));
1581 aml_append(field, aml_named_field("PRQC", 8));
1582 aml_append(field, aml_named_field("PRQD", 8));
1583 aml_append(field, aml_reserved_field(0x20));
1584 aml_append(field, aml_named_field("PRQE", 8));
1585 aml_append(field, aml_named_field("PRQF", 8));
1586 aml_append(field, aml_named_field("PRQG", 8));
1587 aml_append(field, aml_named_field("PRQH", 8));
1588 aml_append(sb_scope, field);
1589
78e1ad05 1590 aml_append(sb_scope, build_irq_status_method());
16682a9d
IM		 1591 aml_append(sb_scope, build_iqcr_method(false));
1592
12e3b1f7
IM		 1593 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1594 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1595 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1596 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1597 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1598 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1599 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1600 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1601
6a991e07
MA		 1602 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1603 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1604 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1605 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1606 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1607 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1608 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1609 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
80b32df5
IM		 1610
1611 aml_append(table, sb_scope);
1612}
1613
41f95a52
IM		 1614static void build_q35_isa_bridge(Aml *table)
1615{
1616 Aml *dev;
1617 Aml *scope;
1618 Aml *field;
1619
1620 scope = aml_scope("_SB.PCI0");
1621 dev = aml_device("ISA");
1622 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1623
1624 /* ICH9 PCI to ISA irq remapping */
1625 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
3f3009c0 1626 aml_int(0x60), 0x0C));
41f95a52
IM		 1627
1628 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
3f3009c0 1629 aml_int(0x80), 0x02));
41f95a52
IM		 1630 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1631 aml_append(field, aml_named_field("COMA", 3));
1632 aml_append(field, aml_reserved_field(1));
1633 aml_append(field, aml_named_field("COMB", 3));
1634 aml_append(field, aml_reserved_field(1));
1635 aml_append(field, aml_named_field("LPTD", 2));
41f95a52
IM		 1636 aml_append(dev, field);
1637
1638 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
3f3009c0 1639 aml_int(0x82), 0x02));
41f95a52
IM		 1640 /* enable bits */
1641 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1642 aml_append(field, aml_named_field("CAEN", 1));
1643 aml_append(field, aml_named_field("CBEN", 1));
1644 aml_append(field, aml_named_field("LPEN", 1));
41f95a52
IM		 1645 aml_append(dev, field);
1646
1647 aml_append(scope, dev);
1648 aml_append(table, scope);
1649}
1650
e4db2798
IM		 1651static void build_piix4_pm(Aml *table)
1652{
1653 Aml *dev;
1654 Aml *scope;
1655
1656 scope = aml_scope("_SB.PCI0");
1657 dev = aml_device("PX13");
1658 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1659
1660 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
3f3009c0 1661 aml_int(0x00), 0xff));
e4db2798
IM		 1662 aml_append(scope, dev);
1663 aml_append(table, scope);
1664}
1665
1666static void build_piix4_isa_bridge(Aml *table)
1667{
1668 Aml *dev;
1669 Aml *scope;
1670 Aml *field;
1671
1672 scope = aml_scope("_SB.PCI0");
1673 dev = aml_device("ISA");
1674 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1675
1676 /* PIIX PCI to ISA irq remapping */
1677 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
3f3009c0 1678 aml_int(0x60), 0x04));
e4db2798
IM		 1679 /* enable bits */
1680 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1681 /* Offset(0x5f),, 7, */
1682 aml_append(field, aml_reserved_field(0x2f8));
1683 aml_append(field, aml_reserved_field(7));
1684 aml_append(field, aml_named_field("LPEN", 1));
1685 /* Offset(0x67),, 3, */
1686 aml_append(field, aml_reserved_field(0x38));
1687 aml_append(field, aml_reserved_field(3));
1688 aml_append(field, aml_named_field("CAEN", 1));
1689 aml_append(field, aml_reserved_field(3));
1690 aml_append(field, aml_named_field("CBEN", 1));
1691 aml_append(dev, field);
e4db2798
IM		 1692
1693 aml_append(scope, dev);
1694 aml_append(table, scope);
1695}
1696
b616ec4d
IM		 1697static void build_piix4_pci_hotplug(Aml *table)
1698{
1699 Aml *scope;
1700 Aml *field;
1701 Aml *method;
1702
1703 scope = aml_scope("_SB.PCI0");
1704
1705 aml_append(scope,
3f3009c0 1706 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
b616ec4d
IM		 1707 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1708 aml_append(field, aml_named_field("PCIU", 32));
1709 aml_append(field, aml_named_field("PCID", 32));
1710 aml_append(scope, field);
1711
1712 aml_append(scope,
3f3009c0 1713 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
b616ec4d
IM		 1714 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1715 aml_append(field, aml_named_field("B0EJ", 32));
1716 aml_append(scope, field);
1717
1718 aml_append(scope,
3f3009c0 1719 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
b616ec4d
IM		 1720 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1721 aml_append(field, aml_named_field("BNUM", 32));
1722 aml_append(scope, field);
1723
1724 aml_append(scope, aml_mutex("BLCK", 0));
1725
1726 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1727 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1728 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1729 aml_append(method,
1730 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1731 aml_append(method, aml_release(aml_name("BLCK")));
1732 aml_append(method, aml_return(aml_int(0)));
1733 aml_append(scope, method);
1734
1735 aml_append(table, scope);
1736}
1737
f97a88a8
IM		 1738static Aml *build_q35_osc_method(void)
1739{
1740 Aml *if_ctx;
1741 Aml *if_ctx2;
1742 Aml *else_ctx;
1743 Aml *method;
1744 Aml *a_cwd1 = aml_name("CDW1");
b3c782db 1745 Aml *a_ctrl = aml_local(0);
f97a88a8
IM		 1746
1747 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1748 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1749
1750 if_ctx = aml_if(aml_equal(
1751 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1752 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1753 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1754
f97a88a8
IM		 1755 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1756
1757 /*
1758 * Always allow native PME, AER (no dependencies)
a41c78c1 1759 * Allow SHPC (PCI bridges can have SHPC controller)
f97a88a8 1760 */
a41c78c1 1761 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
f97a88a8
IM		 1762
1763 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1764 /* Unknown revision */
1765 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1766 aml_append(if_ctx, if_ctx2);
1767
1768 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1769 /* Capabilities bits were masked */
1770 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1771 aml_append(if_ctx, if_ctx2);
1772
1773 /* Update DWORD3 in the buffer */
1774 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1775 aml_append(method, if_ctx);
1776
1777 else_ctx = aml_else();
1778 /* Unrecognized UUID */
1779 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1780 aml_append(method, else_ctx);
1781
1782 aml_append(method, aml_return(aml_arg(3)));
1783 return method;
1784}
b616ec4d 1785
72c194f7 1786static void
0e9b9eda 1787build_dsdt(GArray *table_data, BIOSLinker *linker,
adcb89d5 1788 AcpiPmInfo *pm, AcpiMiscInfo *misc,
01c9742d 1789 Range *pci_hole, Range *pci_hole64, MachineState *machine)
72c194f7 1790{
41fa5c04
IM		 1791 CrsRangeEntry *entry;
1792 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
2df5a7b5 1793 CrsRangeSet crs_range_set;
fb306ffe 1794 PCMachineState *pcms = PC_MACHINE(machine);
679dd1a9 1795 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
bef3492d 1796 uint32_t nr_mem = machine->ram_slots;
dcdca296 1797 int root_bus_limit = 0xFF;
41fa5c04 1798 PCIBus *bus = NULL;
72c194f7
MT		 1799 int i;
1800
41fa5c04 1801 dsdt = init_aml_allocator();
2fd71f1b 1802
4ec8d2b3 1803 /* Reserve space for header */
41fa5c04
IM		 1804 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1805
1806 build_dbg_aml(dsdt);
1807 if (misc->is_piix4) {
1808 sb_scope = aml_scope("_SB");
1809 dev = aml_device("PCI0");
1810 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1811 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1812 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1813 aml_append(sb_scope, dev);
1814 aml_append(dsdt, sb_scope);
1815
1816 build_hpet_aml(dsdt);
1817 build_piix4_pm(dsdt);
1818 build_piix4_isa_bridge(dsdt);
1819 build_isa_devices_aml(dsdt);
1820 build_piix4_pci_hotplug(dsdt);
1821 build_piix4_pci0_int(dsdt);
1822 } else {
41fa5c04
IM		 1823 sb_scope = aml_scope("_SB");
1824 dev = aml_device("PCI0");
1825 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1826 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1827 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1828 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
41fa5c04
IM		 1829 aml_append(dev, build_q35_osc_method());
1830 aml_append(sb_scope, dev);
1831 aml_append(dsdt, sb_scope);
1832
1833 build_hpet_aml(dsdt);
1834 build_q35_isa_bridge(dsdt);
1835 build_isa_devices_aml(dsdt);
1836 build_q35_pci0_int(dsdt);
1837 }
1838
679dd1a9
IM		 1839 if (pcmc->legacy_cpu_hotplug) {
1840 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1841 } else {
1842 CPUHotplugFeatures opts = {
1843 .apci_1_compatible = true, .has_legacy_cphp = true
1844 };
1845 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1846 "\\_SB.PCI0", "\\_GPE._E02");
1847 }
80db0e78 1848 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03");
41fa5c04
IM		 1849
1850 scope = aml_scope("_GPE");
1851 {
1852 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1853
41fa5c04
IM		 1854 if (misc->is_piix4) {
1855 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1856 aml_append(method,
1857 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1858 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1859 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1860 aml_append(scope, method);
41fa5c04
IM		 1861 }
1862
b097cc52
XG		 1863 if (pcms->acpi_nvdimm_state.is_enabled) {
1864 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1865 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1866 aml_int(0x80)));
1867 aml_append(scope, method);
1868 }
41fa5c04
IM		 1869 }
1870 aml_append(dsdt, scope);
72c194f7 1871
2df5a7b5 1872 crs_range_set_init(&crs_range_set);
81ed6482 1873 bus = PC_MACHINE(machine)->bus;
a4894206
MA		 1874 if (bus) {
1875 QLIST_FOREACH(bus, &bus->child, sibling) {
1876 uint8_t bus_num = pci_bus_num(bus);
0e79e51a 1877 uint8_t numa_node = pci_bus_numa_node(bus);
a4894206
MA		 1878
1879 /* look only for expander root buses */
1880 if (!pci_bus_is_root(bus)) {
1881 continue;
1882 }
1883
dcdca296
MA		 1884 if (bus_num < root_bus_limit) {
1885 root_bus_limit = bus_num - 1;
1886 }
1887
a4894206
MA		 1888 scope = aml_scope("\\_SB");
1889 dev = aml_device("PC%.02X", bus_num);
c96d9286
LE		 1890 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1891 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
a4894206 1892 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
077dd742
MA		 1893 if (pci_bus_is_express(bus)) {
1894 aml_append(dev, build_q35_osc_method());
1895 }
0e79e51a
MA		 1896
1897 if (numa_node != NUMA_NODE_UNASSIGNED) {
1898 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1899 }
1900
196e2137 1901 aml_append(dev, build_prt(false));
2df5a7b5 1902 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
a43c6e27 1903 aml_append(dev, aml_name_decl("_CRS", crs));
a4894206 1904 aml_append(scope, dev);
41fa5c04 1905 aml_append(dsdt, scope);
a4894206
MA		 1906 }
1907 }
1908
500b11ea 1909 scope = aml_scope("\\_SB.PCI0");
60efd429
IM		 1910 /* build PCI0._CRS */
1911 crs = aml_resource_template();
1912 aml_append(crs,
ff80dc7f 1913 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
dcdca296
MA		 1914 0x0000, 0x0, root_bus_limit,
1915 0x0000, root_bus_limit + 1));
ff80dc7f 1916 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
60efd429
IM		 1917
1918 aml_append(crs,
ff80dc7f
SZ		 1919 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1920 AML_POS_DECODE, AML_ENTIRE_RANGE,
60efd429 1921 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
dcdca296 1922
2df5a7b5
MA		 1923 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1924 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1925 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
dcdca296
MA		 1926 aml_append(crs,
1927 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1928 AML_POS_DECODE, AML_ENTIRE_RANGE,
1929 0x0000, entry->base, entry->limit,
1930 0x0000, entry->limit - entry->base + 1));
1931 }
1932
60efd429 1933 aml_append(crs,
ff80dc7f
SZ		 1934 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1935 AML_CACHEABLE, AML_READ_WRITE,
60efd429 1936 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
dcdca296 1937
2df5a7b5 1938 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
a0efbf16
MA		 1939 range_lob(pci_hole),
1940 range_upb(pci_hole));
2df5a7b5
MA		 1941 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1942 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
dcdca296
MA		 1943 aml_append(crs,
1944 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1945 AML_NON_CACHEABLE, AML_READ_WRITE,
1946 0, entry->base, entry->limit,
1947 0, entry->limit - entry->base + 1));
1948 }
1949
a0efbf16 1950 if (!range_is_empty(pci_hole64)) {
16de88a4
MA		 1951 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1952 range_lob(pci_hole64),
1953 range_upb(pci_hole64));
1954 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1955 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1956 aml_append(crs,
1957 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1958 AML_MAX_FIXED,
1959 AML_CACHEABLE, AML_READ_WRITE,
1960 0, entry->base, entry->limit,
1961 0, entry->limit - entry->base + 1));
1962 }
60efd429 1963 }
2b1c2e8e 1964
ff5ce21e 1965 if (TPM_IS_TIS(tpm_find())) {
2b1c2e8e
IM		 1966 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1967 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1968 }
60efd429
IM		 1969 aml_append(scope, aml_name_decl("_CRS", crs));
1970
d31c909e
IM		 1971 /* reserve GPE0 block resources */
1972 dev = aml_device("GPE0");
1973 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1974 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1975 /* device present, functioning, decoding, not shown in UI */
1976 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1977 crs = aml_resource_template();
1978 aml_append(crs,
937d1b58
IM		 1979 aml_io(
1980 AML_DECODE16,
1981 pm->fadt.gpe0_blk.address,
1982 pm->fadt.gpe0_blk.address,
1983 1,
1984 pm->fadt.gpe0_blk.bit_width / 8)
d31c909e
IM		 1985 );
1986 aml_append(dev, aml_name_decl("_CRS", crs));
1987 aml_append(scope, dev);
1988
2df5a7b5 1989 crs_range_set_free(&crs_range_set);
dcdca296 1990
500b11ea
IM		 1991 /* reserve PCIHP resources */
1992 if (pm->pcihp_io_len) {
1993 dev = aml_device("PHPR");
1994 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1995 aml_append(dev,
1996 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1997 /* device present, functioning, decoding, not shown in UI */
1998 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1999 crs = aml_resource_template();
2000 aml_append(crs,
ff80dc7f 2001 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
500b11ea
IM		 2002 pm->pcihp_io_len)
2003 );
2004 aml_append(dev, aml_name_decl("_CRS", crs));
2005 aml_append(scope, dev);
2006 }
41fa5c04 2007 aml_append(dsdt, scope);
500b11ea 2008
ebc3028f
IM		 2009 /* create S3_ / S4_ / S5_ packages if necessary */
2010 scope = aml_scope("\\");
2011 if (!pm->s3_disabled) {
2012 pkg = aml_package(4);
2013 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2014 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2015 aml_append(pkg, aml_int(0)); /* reserved */
2016 aml_append(pkg, aml_int(0)); /* reserved */
2017 aml_append(scope, aml_name_decl("_S3", pkg));
2018 }
2019
2020 if (!pm->s4_disabled) {
2021 pkg = aml_package(4);
2022 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2023 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2024 aml_append(pkg, aml_int(pm->s4_val));
2025 aml_append(pkg, aml_int(0)); /* reserved */
2026 aml_append(pkg, aml_int(0)); /* reserved */
2027 aml_append(scope, aml_name_decl("_S4", pkg));
2028 }
2029
2030 pkg = aml_package(4);
2031 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2032 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2033 aml_append(pkg, aml_int(0)); /* reserved */
2034 aml_append(pkg, aml_int(0)); /* reserved */
2035 aml_append(scope, aml_name_decl("_S5", pkg));
41fa5c04 2036 aml_append(dsdt, scope);
ebc3028f 2037
e2ec7568
GS		 2038 /* create fw_cfg node, unconditionally */
2039 {
2040 /* when using port i/o, the 8-bit data register *always* overlaps
2041 * with half of the 16-bit control register. Hence, the total size
2042 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2043 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2044 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2045 "dma_enabled", NULL) ?
2046 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2047 FW_CFG_CTL_SIZE;
2048
2049 scope = aml_scope("\\_SB.PCI0");
2050 dev = aml_device("FWCF");
2051
2052 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2053
2054 /* device present, functioning, decoding, not shown in UI */
2055 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2056
2057 crs = aml_resource_template();
2058 aml_append(crs,
2059 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2060 );
2061 aml_append(dev, aml_name_decl("_CRS", crs));
2062
2063 aml_append(scope, dev);
2064 aml_append(dsdt, scope);
2065 }
2066
8ac6f7a6
IM		 2067 if (misc->applesmc_io_base) {
2068 scope = aml_scope("\\_SB.PCI0.ISA");
2069 dev = aml_device("SMC");
2070
2071 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2072 /* device present, functioning, decoding, not shown in UI */
2073 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2074
2075 crs = aml_resource_template();
2076 aml_append(crs,
ff80dc7f 2077 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
8ac6f7a6
IM		 2078 0x01, APPLESMC_MAX_DATA_LENGTH)
2079 );
2080 aml_append(crs, aml_irq_no_flags(6));
2081 aml_append(dev, aml_name_decl("_CRS", crs));
2082
2083 aml_append(scope, dev);
41fa5c04 2084 aml_append(dsdt, scope);
8ac6f7a6
IM		 2085 }
2086
cd61cb2e
IM		 2087 if (misc->pvpanic_port) {
2088 scope = aml_scope("\\_SB.PCI0.ISA");
2089
2332333c 2090 dev = aml_device("PEVT");
e65bef69 2091 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
cd61cb2e
IM		 2092
2093 crs = aml_resource_template();
2094 aml_append(crs,
ff80dc7f 2095 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
cd61cb2e
IM		 2096 );
2097 aml_append(dev, aml_name_decl("_CRS", crs));
2098
ff80dc7f 2099 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
3f3009c0 2100 aml_int(misc->pvpanic_port), 1));
36de884a 2101 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
cd61cb2e
IM		 2102 aml_append(field, aml_named_field("PEPT", 8));
2103 aml_append(dev, field);
2104
8ef3ea25
GH		 2105 /* device present, functioning, decoding, shown in UI */
2106 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2332333c 2107
4dbfc881 2108 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
cd61cb2e
IM		 2109 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2110 aml_append(method, aml_return(aml_local(0)));
2111 aml_append(dev, method);
2112
4dbfc881 2113 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
cd61cb2e
IM		 2114 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2115 aml_append(dev, method);
2116
2117 aml_append(scope, dev);
41fa5c04 2118 aml_append(dsdt, scope);
cd61cb2e
IM		 2119 }
2120
7824df38 2121 sb_scope = aml_scope("\\_SB");
72c194f7 2122 {
8b35ab27
IM		 2123 Object *pci_host;
2124 PCIBus *bus = NULL;
8698c0c0 2125
8b35ab27
IM		 2126 pci_host = acpi_get_i386_pci_host();
2127 if (pci_host) {
2128 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2129 }
8dcf525a 2130
8b35ab27
IM		 2131 if (bus) {
2132 Aml *scope = aml_scope("PCI0");
2133 /* Scan all PCI buses. Generate tables to support hotplug. */
2134 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2135
ff5ce21e 2136 if (TPM_IS_TIS(tpm_find())) {
8b35ab27
IM		 2137 dev = aml_device("ISA.TPM");
2138 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2139 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2140 crs = aml_resource_template();
2141 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2142 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2143 /*
2144 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2145 Rewrite to take IRQ from TPM device model and
2146 fix default IRQ value there to use some unused IRQ
2147 */
2148 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2149 aml_append(dev, aml_name_decl("_CRS", crs));
2150 aml_append(scope, dev);
8dcf525a 2151 }
72c194f7 2152
8b35ab27 2153 aml_append(sb_scope, scope);
72c194f7 2154 }
72c194f7 2155 }
4ab6cb4c
MAL		 2156
2157 if (TPM_IS_CRB(tpm_find())) {
2158 dev = aml_device("TPM");
2159 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
2160 crs = aml_resource_template();
2161 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
2162 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
2163 aml_append(dev, aml_name_decl("_CRS", crs));
2164
2165 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
2166 aml_append(method, aml_return(aml_int(0x0f)));
2167 aml_append(dev, method);
2168
2169 aml_append(sb_scope, dev);
2170 }
2171
8b35ab27 2172 aml_append(dsdt, sb_scope);
72c194f7 2173
011bb749 2174 /* copy AML table into ACPI tables blob and patch header there */
41fa5c04 2175 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
72c194f7 2176 build_header(linker, table_data,
41fa5c04 2177 (void *)(table_data->data + table_data->len - dsdt->buf->len),
37ad223c 2178 "DSDT", dsdt->buf->len, 1, NULL, NULL);
011bb749 2179 free_aml_allocator();
72c194f7
MT		 2180}
2181
2182static void
0e9b9eda 2183build_hpet(GArray *table_data, BIOSLinker *linker)
72c194f7
MT		 2184{
2185 Acpi20Hpet *hpet;
2186
2187 hpet = acpi_data_push(table_data, sizeof(*hpet));
2188 /* Note timer_block_id value must be kept in sync with value advertised by
2189 * emulated hpet
2190 */
2191 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2192 hpet->addr.address = cpu_to_le64(HPET_BASE);
2193 build_header(linker, table_data,
37ad223c 2194 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
72c194f7
MT		 2195}
2196
711b20b4 2197static void
0e9b9eda 2198build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
711b20b4
SB		 2199{
2200 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
4678124b
IM		 2201 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2202 unsigned log_addr_offset =
2203 (char *)&tcpa->log_area_start_address - table_data->data;
711b20b4
SB		 2204
2205 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2206 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
9774ccf7 2207 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
711b20b4 2208
ad9671b8 2209 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
42a5b308
SB		 2210 false /* high memory */);
2211
711b20b4 2212 /* log area start address to be filled by Guest linker */
4678124b
IM		 2213 bios_linker_loader_add_pointer(linker,
2214 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2215 ACPI_BUILD_TPMLOG_FILE, 0);
711b20b4
SB		 2216
2217 build_header(linker, table_data,
37ad223c 2218 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
711b20b4
SB		 2219}
2220
5cb18b3d 2221static void
4a42fa0e 2222build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
5cb18b3d 2223{
4a42fa0e
SB		 2224 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2225 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
2226 unsigned log_addr_offset =
2227 (char *)&tpm2_ptr->log_area_start_address - table_data->data;
5cb18b3d
SB		 2228
2229 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
ff5ce21e
MAL		 2230 if (TPM_IS_TIS(tpm_find())) {
2231 tpm2_ptr->control_area_address = cpu_to_le64(0);
2232 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
4ab6cb4c
MAL		 2233 } else if (TPM_IS_CRB(tpm_find())) {
2234 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL);
2235 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB);
ff5ce21e
MAL		 2236 } else {
2237 g_warn_if_reached();
2238 }
5cb18b3d 2239
4ab6cb4c
MAL		 2240 tpm2_ptr->log_area_minimum_length =
2241 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2242
2243 /* log area start address to be filled by Guest linker */
2244 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2245 log_addr_offset, log_addr_size,
2246 ACPI_BUILD_TPMLOG_FILE, 0);
5cb18b3d 2247 build_header(linker, table_data,
37ad223c 2248 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
5cb18b3d
SB		 2249}
2250
d471bf3e
PB		 2251#define HOLE_640K_START (640 * KiB)
2252#define HOLE_640K_END (1 * MiB)
4926403c 2253
72c194f7 2254static void
0e9b9eda 2255build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
72c194f7
MT		 2256{
2257 AcpiSystemResourceAffinityTable *srat;
72c194f7
MT		 2258 AcpiSratMemoryAffinity *numamem;
2259
2260 int i;
72c194f7
MT		 2261 int srat_start, numa_start, slots;
2262 uint64_t mem_len, mem_base, next_base;
5803fce3 2263 MachineClass *mc = MACHINE_GET_CLASS(machine);
80e5db30 2264 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
3d3ebcad 2265 PCMachineState *pcms = PC_MACHINE(machine);
cec65193 2266 ram_addr_t hotplugabble_address_space_size =
f2ffbe2b 2267 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
cec65193 2268 NULL);
72c194f7
MT		 2269
2270 srat_start = table_data->len;
2271
2272 srat = acpi_data_push(table_data, sizeof *srat);
2273 srat->reserved1 = cpu_to_le32(1);
72c194f7 2274
5803fce3 2275 for (i = 0; i < apic_ids->len; i++) {
d41f3e75 2276 int node_id = apic_ids->cpus[i].props.node_id;
5eff33a2 2277 uint32_t apic_id = apic_ids->cpus[i].arch_id;
5803fce3 2278
5eff33a2
IM		 2279 if (apic_id < 255) {
2280 AcpiSratProcessorAffinity *core;
2281
2282 core = acpi_data_push(table_data, sizeof *core);
2283 core->type = ACPI_SRAT_PROCESSOR_APIC;
2284 core->length = sizeof(*core);
2285 core->local_apic_id = apic_id;
ea265072 2286 core->proximity_lo = node_id;
5eff33a2
IM		 2287 memset(core->proximity_hi, 0, 3);
2288 core->local_sapic_eid = 0;
2289 core->flags = cpu_to_le32(1);
2290 } else {
2291 AcpiSratProcessorX2ApicAffinity *core;
2292
2293 core = acpi_data_push(table_data, sizeof *core);
2294 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2295 core->length = sizeof(*core);
2296 core->x2apic_id = cpu_to_le32(apic_id);
ea265072 2297 core->proximity_domain = cpu_to_le32(node_id);
5eff33a2 2298 core->flags = cpu_to_le32(1);
1f3aba37 2299 }
72c194f7
MT		 2300 }
2301
2302
2303 /* the memory map is a bit tricky, it contains at least one hole
2304 * from 640k-1M and possibly another one from 3.5G-4G.
2305 */
2306 next_base = 0;
2307 numa_start = table_data->len;
2308
dd4c2f01 2309 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
72c194f7 2310 mem_base = next_base;
dd4c2f01 2311 mem_len = pcms->node_mem[i - 1];
72c194f7
MT		 2312 next_base = mem_base + mem_len;
2313
4926403c
EH		 2314 /* Cut out the 640K hole */
2315 if (mem_base <= HOLE_640K_START &&
2316 next_base > HOLE_640K_START) {
2317 mem_len -= next_base - HOLE_640K_START;
2318 if (mem_len > 0) {
2319 numamem = acpi_data_push(table_data, sizeof *numamem);
2320 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2321 MEM_AFFINITY_ENABLED);
2322 }
2323
2324 /* Check for the rare case: 640K < RAM < 1M */
2325 if (next_base <= HOLE_640K_END) {
2326 next_base = HOLE_640K_END;
2327 continue;
2328 }
2329 mem_base = HOLE_640K_END;
2330 mem_len = next_base - HOLE_640K_END;
2331 }
2332
72c194f7 2333 /* Cut out the ACPI_PCI hole */
5299f1c7
EH		 2334 if (mem_base <= pcms->below_4g_mem_size &&
2335 next_base > pcms->below_4g_mem_size) {
2336 mem_len -= next_base - pcms->below_4g_mem_size;
72c194f7
MT		 2337 if (mem_len > 0) {
2338 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136
SZ		 2339 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2340 MEM_AFFINITY_ENABLED);
72c194f7
MT		 2341 }
2342 mem_base = 1ULL << 32;
5299f1c7 2343 mem_len = next_base - pcms->below_4g_mem_size;
6cf6fe39 2344 next_base = mem_base + mem_len;
72c194f7 2345 }
16b42263
DL		 2346
2347 if (mem_len > 0) {
2348 numamem = acpi_data_push(table_data, sizeof *numamem);
2349 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2350 MEM_AFFINITY_ENABLED);
2351 }
72c194f7
MT		 2352 }
2353 slots = (table_data->len - numa_start) / sizeof *numamem;
dd4c2f01 2354 for (; slots < pcms->numa_nodes + 2; slots++) {
72c194f7 2355 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136 2356 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
72c194f7
MT		 2357 }
2358
dbb6da8b
IM		 2359 /*
2360 * Entry is required for Windows to enable memory hotplug in OS
2361 * and for Linux to enable SWIOTLB when booted with less than
2362 * 4G of RAM. Windows works better if the entry sets proximity
2363 * to the highest NUMA node in the machine.
2364 * Memory devices may override proximity set by this entry,
2365 * providing _PXM method if necessary.
2366 */
cec65193 2367 if (hotplugabble_address_space_size) {
dbb6da8b
IM		 2368 numamem = acpi_data_push(table_data, sizeof *numamem);
2369 build_srat_memory(numamem, machine->device_memory->base,
2370 hotplugabble_address_space_size, pcms->numa_nodes - 1,
2371 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
cec65193
IM		 2372 }
2373
72c194f7
MT		 2374 build_header(linker, table_data,
2375 (void *)(table_data->data + srat_start),
821e3227 2376 "SRAT",
37ad223c 2377 table_data->len - srat_start, 1, NULL, NULL);
72c194f7
MT		 2378}
2379
2380static void
0e9b9eda 2381build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
72c194f7
MT		 2382{
2383 AcpiTableMcfg *mcfg;
821e3227 2384 const char *sig;
72c194f7
MT		 2385 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2386
2387 mcfg = acpi_data_push(table_data, len);
2388 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2389 /* Only a single allocation so no need to play with segments */
2390 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2391 mcfg->allocation[0].start_bus_number = 0;
2392 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2393
2394 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2395 * To avoid table size changes (which create migration issues),
2396 * always create the table even if there are no allocations,
2397 * but set the signature to a reserved value in this case.
2398 * ACPI spec requires OSPMs to ignore such tables.
2399 */
2400 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
821e3227
MT		 2401 /* Reserved signature: ignored by OSPM */
2402 sig = "QEMU";
72c194f7 2403 } else {
821e3227 2404 sig = "MCFG";
72c194f7 2405 }
37ad223c 2406 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
72c194f7
MT		 2407}
2408
d46114f9
PX		 2409/*
2410 * VT-d spec 8.1 DMA Remapping Reporting Structure
2411 * (version Oct. 2014 or later)
2412 */
d4eb9119 2413static void
0e9b9eda 2414build_dmar_q35(GArray *table_data, BIOSLinker *linker)
d4eb9119
LT		 2415{
2416 int dmar_start = table_data->len;
2417
2418 AcpiTableDmar *dmar;
2419 AcpiDmarHardwareUnit *drhd;
bd2baacc 2420 AcpiDmarRootPortATS *atsr;
d46114f9
PX		 2421 uint8_t dmar_flags = 0;
2422 X86IOMMUState *iommu = x86_iommu_get_default();
cfc13df4
PX		 2423 AcpiDmarDeviceScope *scope = NULL;
2424 /* Root complex IOAPIC use one path[0] only */
2425 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
37f51384 2426 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
d46114f9
PX		 2427
2428 assert(iommu);
a924b3d8 2429 if (x86_iommu_ir_supported(iommu)) {
d46114f9
PX		 2430 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2431 }
d4eb9119
LT		 2432
2433 dmar = acpi_data_push(table_data, sizeof(*dmar));
37f51384 2434 dmar->host_address_width = intel_iommu->aw_bits - 1;
d46114f9 2435 dmar->flags = dmar_flags;
d4eb9119
LT		 2436
2437 /* DMAR Remapping Hardware Unit Definition structure */
cfc13df4 2438 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
d4eb9119 2439 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
cfc13df4 2440 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
d4eb9119
LT		 2441 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2442 drhd->pci_segment = cpu_to_le16(0);
2443 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2444
cfc13df4
PX		 2445 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2446 * 8.3.1 (version Oct. 2014 or later). */
2447 scope = &drhd->scope[0];
2448 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2449 scope->length = ioapic_scope_size;
2450 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2451 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
1b39bc1c
PX		 2452 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2453 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
cfc13df4 2454
bd2baacc
JW		 2455 if (iommu->dt_supported) {
2456 atsr = acpi_data_push(table_data, sizeof(*atsr));
2457 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2458 atsr->length = cpu_to_le16(sizeof(*atsr));
2459 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2460 atsr->pci_segment = cpu_to_le16(0);
2461 }
2462
d4eb9119 2463 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
37ad223c 2464 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
d4eb9119 2465}
fb9f5926
DK		 2466/*
2467 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2468 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2469 */
c028818d
BS		 2470#define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2471
fb9f5926
DK		 2472static void
2473build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2474{
c028818d 2475 int ivhd_table_len = 28;
fb9f5926
DK		 2476 int iommu_start = table_data->len;
2477 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2478
2479 /* IVRS header */
2480 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2481 /* IVinfo - IO virtualization information common to all
2482 * IOMMU units in a system
2483 */
2484 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2485 /* reserved */
2486 build_append_int_noprefix(table_data, 0, 8);
2487
2488 /* IVHD definition - type 10h */
2489 build_append_int_noprefix(table_data, 0x10, 1);
2490 /* virtualization flags */
2491 build_append_int_noprefix(table_data,
2492 (1UL << 0) | /* HtTunEn */
2493 (1UL << 4) | /* iotblSup */
2494 (1UL << 6) | /* PrefSup */
2495 (1UL << 7), /* PPRSup */
2496 1);
c028818d
BS		 2497
2498 /*
2499 * When interrupt remapping is supported, we add a special IVHD device
2500 * for type IO-APIC.
2501 */
a924b3d8 2502 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
c028818d
BS		 2503 ivhd_table_len += 8;
2504 }
fb9f5926 2505 /* IVHD length */
c028818d 2506 build_append_int_noprefix(table_data, ivhd_table_len, 2);
fb9f5926
DK		 2507 /* DeviceID */
2508 build_append_int_noprefix(table_data, s->devid, 2);
2509 /* Capability offset */
2510 build_append_int_noprefix(table_data, s->capab_offset, 2);
2511 /* IOMMU base address */
2512 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2513 /* PCI Segment Group */
2514 build_append_int_noprefix(table_data, 0, 2);
2515 /* IOMMU info */
2516 build_append_int_noprefix(table_data, 0, 2);
2517 /* IOMMU Feature Reporting */
2518 build_append_int_noprefix(table_data,
2519 (48UL << 30) | /* HATS */
2520 (48UL << 28) | /* GATS */
12499b23
BS		 2521 (1UL << 2) | /* GTSup */
2522 (1UL << 6), /* GASup */
fb9f5926
DK		 2523 4);
2524 /*
2525 * Type 1 device entry reporting all devices
2526 * These are 4-byte device entries currently reporting the range of
2527 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2528 */
2529 build_append_int_noprefix(table_data, 0x0000001, 4);
2530
c028818d
BS		 2531 /*
2532 * Add a special IVHD device type.
2533 * Refer to spec - Table 95: IVHD device entry type codes
2534 *
2535 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2536 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2537 */
a924b3d8 2538 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
c028818d
BS		 2539 build_append_int_noprefix(table_data,
2540 (0x1ull << 56) | /* type IOAPIC */
2541 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2542 0x48, /* special device */
2543 8);
2544 }
2545
fb9f5926
DK		 2546 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2547 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2548}
d4eb9119 2549
72c194f7
MT		 2550typedef
2551struct AcpiBuildState {
2552 /* Copy of table in RAM (for patching). */
339240b5 2553 MemoryRegion *table_mr;
72c194f7
MT		 2554 /* Is table patched? */
2555 uint8_t patched;
d70414a5 2556 void *rsdp;
339240b5
PB		 2557 MemoryRegion *rsdp_mr;
2558 MemoryRegion *linker_mr;
72c194f7
MT		 2559} AcpiBuildState;
2560
2561static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2562{
2563 Object *pci_host;
2564 QObject *o;
72c194f7 2565
ca6c1855 2566 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 2567 g_assert(pci_host);
2568
2569 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2570 if (!o) {
2571 return false;
2572 }
7dc847eb 2573 mcfg->mcfg_base = qnum_get_uint(qobject_to(QNum, o));
cb3e7f08 2574 qobject_unref(o);
72c194f7
MT		 2575
2576 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2577 assert(o);
7dc847eb 2578 mcfg->mcfg_size = qnum_get_uint(qobject_to(QNum, o));
cb3e7f08 2579 qobject_unref(o);
72c194f7
MT		 2580 return true;
2581}
2582
2583static
3d3ebcad 2584void acpi_build(AcpiBuildTables *tables, MachineState *machine)
72c194f7 2585{
3d3ebcad 2586 PCMachineState *pcms = PC_MACHINE(machine);
bb292f5a 2587 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72c194f7 2588 GArray *table_offsets;
41fa5c04 2589 unsigned facs, dsdt, rsdt, fadt;
72c194f7
MT		 2590 AcpiPmInfo pm;
2591 AcpiMiscInfo misc;
2592 AcpiMcfgInfo mcfg;
01c9742d 2593 Range pci_hole, pci_hole64;
72c194f7 2594 uint8_t *u;
07fb6176 2595 size_t aml_len = 0;
7c2c1fa5 2596 GArray *tables_blob = tables->table_data;
ae123749 2597 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
d03637bc 2598 Object *vmgenid_dev;
72c194f7 2599
72c194f7 2600 acpi_get_pm_info(&pm);
72c194f7 2601 acpi_get_misc_info(&misc);
01c9742d 2602 acpi_get_pci_holes(&pci_hole, &pci_hole64);
ae123749 2603 acpi_get_slic_oem(&slic_oem);
72c194f7
MT		 2604
2605 table_offsets = g_array_new(false, true /* clear */,
2606 sizeof(uint32_t));
8b310fc4 2607 ACPI_BUILD_DPRINTF("init ACPI tables\n");
72c194f7 2608
ad9671b8
IM		 2609 bios_linker_loader_alloc(tables->linker,
2610 ACPI_BUILD_TABLE_FILE, tables_blob,
72c194f7
MT		 2611 64 /* Ensure FACS is aligned */,
2612 false /* high memory */);
2613
2614 /*
2615 * FACS is pointed to by FADT.
2616 * We place it first since it's the only table that has alignment
2617 * requirements.
2618 */
7c2c1fa5 2619 facs = tables_blob->len;
fb306ffe 2620 build_facs(tables_blob, tables->linker);
72c194f7
MT		 2621
2622 /* DSDT is pointed to by FADT */
7c2c1fa5 2623 dsdt = tables_blob->len;
01c9742d
MA		 2624 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2625 &pci_hole, &pci_hole64, machine);
72c194f7 2626
07fb6176
PB		 2627 /* Count the size of the DSDT and SSDT, we will need it for legacy
2628 * sizing of ACPI tables.
2629 */
7c2c1fa5 2630 aml_len += tables_blob->len - dsdt;
07fb6176 2631
72c194f7 2632 /* ACPI tables pointed to by RSDT */
41fa5c04 2633 fadt = tables_blob->len;
7c2c1fa5 2634 acpi_add_table(table_offsets, tables_blob);
937d1b58
IM		 2635 pm.fadt.facs_tbl_offset = &facs;
2636 pm.fadt.dsdt_tbl_offset = &dsdt;
2637 pm.fadt.xdsdt_tbl_offset = &dsdt;
2638 build_fadt(tables_blob, tables->linker, &pm.fadt,
ae123749 2639 slic_oem.id, slic_oem.table_id);
41fa5c04 2640 aml_len += tables_blob->len - fadt;
72c194f7 2641
7c2c1fa5 2642 acpi_add_table(table_offsets, tables_blob);
907e7c94 2643 build_madt(tables_blob, tables->linker, pcms);
9ac1c4c0 2644
d03637bc
BW		 2645 vmgenid_dev = find_vmgenid_dev();
2646 if (vmgenid_dev) {
2647 acpi_add_table(table_offsets, tables_blob);
2648 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2649 tables->vmgenid, tables->linker);
2650 }
2651
72c194f7 2652 if (misc.has_hpet) {
7c2c1fa5
IM		 2653 acpi_add_table(table_offsets, tables_blob);
2654 build_hpet(tables_blob, tables->linker);
711b20b4 2655 }
5cb18b3d 2656 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
7c2c1fa5
IM		 2657 acpi_add_table(table_offsets, tables_blob);
2658 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
711b20b4 2659
72d97b3a
IM		 2660 if (misc.tpm_version == TPM_VERSION_2_0) {
2661 acpi_add_table(table_offsets, tables_blob);
4a42fa0e 2662 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
5cb18b3d 2663 }
72c194f7 2664 }
dd4c2f01 2665 if (pcms->numa_nodes) {
7c2c1fa5 2666 acpi_add_table(table_offsets, tables_blob);
3d3ebcad 2667 build_srat(tables_blob, tables->linker, machine);
0f203430
HC		 2668 if (have_numa_distance) {
2669 acpi_add_table(table_offsets, tables_blob);
2670 build_slit(tables_blob, tables->linker);
2671 }
72c194f7
MT		 2672 }
2673 if (acpi_get_mcfg(&mcfg)) {
7c2c1fa5
IM		 2674 acpi_add_table(table_offsets, tables_blob);
2675 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
72c194f7 2676 }
fb9f5926
DK		 2677 if (x86_iommu_get_default()) {
2678 IommuType IOMMUType = x86_iommu_get_type();
2679 if (IOMMUType == TYPE_AMD) {
2680 acpi_add_table(table_offsets, tables_blob);
2681 build_amd_iommu(tables_blob, tables->linker);
2682 } else if (IOMMUType == TYPE_INTEL) {
2683 acpi_add_table(table_offsets, tables_blob);
2684 build_dmar_q35(tables_blob, tables->linker);
2685 }
d4eb9119 2686 }
5fe79386 2687 if (pcms->acpi_nvdimm_state.is_enabled) {
ad9671b8 2688 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
75b0713e 2689 &pcms->acpi_nvdimm_state, machine->ram_slots);
87252e1b
XG		 2690 }
2691
72c194f7
MT		 2692 /* Add tables supplied by user (if any) */
2693 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2694 unsigned len = acpi_table_len(u);
2695
7c2c1fa5
IM		 2696 acpi_add_table(table_offsets, tables_blob);
2697 g_array_append_vals(tables_blob, u, len);
72c194f7
MT		 2698 }
2699
2700 /* RSDT is pointed to by RSDP */
7c2c1fa5 2701 rsdt = tables_blob->len;
ae123749
LE		 2702 build_rsdt(tables_blob, tables->linker, table_offsets,
2703 slic_oem.id, slic_oem.table_id);
72c194f7
MT		 2704
2705 /* RSDP is in FSEG memory, so allocate it separately */
a46ce1c2
SO		 2706 {
2707 AcpiRsdpData rsdp_data = {
2708 .revision = 0,
2709 .oem_id = ACPI_BUILD_APPNAME6,
2710 .xsdt_tbl_offset = NULL,
2711 .rsdt_tbl_offset = &rsdt,
2712 };
2713 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2714 if (!pcmc->rsdp_in_ram) {
2715 /* We used to allocate some extra space for RSDP revision 2 but
2716 * only used the RSDP revision 0 space. The extra bytes were
2717 * zeroed out and not used.
2718 * Here we continue wasting those extra 16 bytes to make sure we
2719 * don't break migration for machine types 2.2 and older due to
2720 * RSDP blob size mismatch.
2721 */
2722 build_append_int_noprefix(tables->rsdp, 0, 16);
2723 }
2724 }
72c194f7 2725
07fb6176 2726 /* We'll expose it all to Guest so we want to reduce
72c194f7 2727 * chance of size changes.
07fb6176
PB		 2728 *
2729 * We used to align the tables to 4k, but of course this would
2730 * too simple to be enough. 4k turned out to be too small an
2731 * alignment very soon, and in fact it is almost impossible to
2732 * keep the table size stable for all (max_cpus, max_memory_slots)
2733 * combinations. So the table size is always 64k for pc-i440fx-2.1
2734 * and we give an error if the table grows beyond that limit.
2735 *
2736 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2737 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2738 * than 2.0 and we can always pad the smaller tables with zeros. We can
2739 * then use the exact size of the 2.0 tables.
2740 *
2741 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
72c194f7 2742 */
bb292f5a 2743 if (pcmc->legacy_acpi_table_size) {
07fb6176
PB		 2744 /* Subtracting aml_len gives the size of fixed tables. Then add the
2745 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2746 */
2747 int legacy_aml_len =
bb292f5a 2748 pcmc->legacy_acpi_table_size +
4b5b47ab 2749 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit;
07fb6176 2750 int legacy_table_size =
7c2c1fa5 2751 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
07fb6176 2752 ACPI_BUILD_ALIGN_SIZE);
7c2c1fa5 2753 if (tables_blob->len > legacy_table_size) {
07fb6176 2754 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
9e5d2c52
AF		 2755 warn_report("ACPI table size %u exceeds %d bytes,"
2756 " migration may not work",
2757 tables_blob->len, legacy_table_size);
2758 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2759 " or PCI bridges.");
07fb6176 2760 }
7c2c1fa5 2761 g_array_set_size(tables_blob, legacy_table_size);
07fb6176 2762 } else {
868270f2 2763 /* Make sure we have a buffer in case we need to resize the tables. */
7c2c1fa5 2764 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
18045fb9 2765 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
9e5d2c52
AF		 2766 warn_report("ACPI table size %u exceeds %d bytes,"
2767 " migration may not work",
2768 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2769 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2770 " or PCI bridges.");
18045fb9 2771 }
7c2c1fa5 2772 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
07fb6176 2773 }
72c194f7 2774
0e9b9eda 2775 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
72c194f7
MT		 2776
2777 /* Cleanup memory that's no longer used. */
2778 g_array_free(table_offsets, true);
2779}
2780
339240b5 2781static void acpi_ram_update(MemoryRegion *mr, GArray *data)
42d85900
MT		 2782{
2783 uint32_t size = acpi_data_len(data);
2784
2785 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
339240b5 2786 memory_region_ram_resize(mr, size, &error_abort);
42d85900 2787
339240b5
PB		 2788 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2789 memory_region_set_dirty(mr, 0, size);
42d85900
MT		 2790}
2791
3f8752b4 2792static void acpi_build_update(void *build_opaque)
72c194f7
MT		 2793{
2794 AcpiBuildState *build_state = build_opaque;
2795 AcpiBuildTables tables;
2796
2797 /* No state to update or already patched? Nothing to do. */
2798 if (!build_state || build_state->patched) {
2799 return;
2800 }
2801 build_state->patched = 1;
2802
2803 acpi_build_tables_init(&tables);
2804
3d3ebcad 2805 acpi_build(&tables, MACHINE(qdev_get_machine()));
72c194f7 2806
339240b5 2807 acpi_ram_update(build_state->table_mr, tables.table_data);
a1666142 2808
42d85900
MT		 2809 if (build_state->rsdp) {
2810 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2811 } else {
339240b5 2812 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
42d85900 2813 }
ad5b88b1 2814
0e9b9eda 2815 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
72c194f7
MT		 2816 acpi_build_tables_cleanup(&tables, true);
2817}
2818
2819static void acpi_build_reset(void *build_opaque)
2820{
2821 AcpiBuildState *build_state = build_opaque;
2822 build_state->patched = 0;
2823}
2824
339240b5
PB		 2825static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2826 GArray *blob, const char *name,
2827 uint64_t max_size)
72c194f7 2828{
a1666142 2829 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
baf2d5bf 2830 name, acpi_build_update, build_state, NULL, true);
72c194f7
MT		 2831}
2832
2833static const VMStateDescription vmstate_acpi_build = {
2834 .name = "acpi_build",
2835 .version_id = 1,
2836 .minimum_version_id = 1,
d49805ae 2837 .fields = (VMStateField[]) {
72c194f7
MT		 2838 VMSTATE_UINT8(patched, AcpiBuildState),
2839 VMSTATE_END_OF_LIST()
2840 },
2841};
2842
fb306ffe 2843void acpi_setup(void)
72c194f7 2844{
fb306ffe 2845 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
bb292f5a 2846 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72c194f7
MT		 2847 AcpiBuildTables tables;
2848 AcpiBuildState *build_state;
d03637bc 2849 Object *vmgenid_dev;
72c194f7 2850
f264d360 2851 if (!pcms->fw_cfg) {
8b310fc4 2852 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
72c194f7
MT		 2853 return;
2854 }
2855
021746c1 2856 if (!pcms->acpi_build_enabled) {
8b310fc4 2857 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
72c194f7
MT		 2858 return;
2859 }
2860
81adc513 2861 if (!acpi_enabled) {
8b310fc4 2862 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
81adc513
MT		 2863 return;
2864 }
2865
72c194f7
MT		 2866 build_state = g_malloc0(sizeof *build_state);
2867
72c194f7 2868 acpi_build_tables_init(&tables);
3d3ebcad 2869 acpi_build(&tables, MACHINE(pcms));
72c194f7
MT		 2870
2871 /* Now expose it all to Guest */
339240b5 2872 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
a1666142
MT		 2873 ACPI_BUILD_TABLE_FILE,
2874 ACPI_BUILD_TABLE_MAX_SIZE);
339240b5 2875 assert(build_state->table_mr != NULL);
72c194f7 2876
339240b5 2877 build_state->linker_mr =
0e9b9eda
IM		 2878 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2879 "etc/table-loader", 0);
72c194f7 2880
f264d360 2881 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
42a5b308
SB		 2882 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2883
d03637bc
BW		 2884 vmgenid_dev = find_vmgenid_dev();
2885 if (vmgenid_dev) {
2886 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg,
2887 tables.vmgenid);
2888 }
2889
bb292f5a 2890 if (!pcmc->rsdp_in_ram) {
358774d7
IM		 2891 /*
2892 * Keep for compatibility with old machine types.
2893 * Though RSDP is small, its contents isn't immutable, so
afaa2e4b 2894 * we'll update it along with the rest of tables on guest access.
358774d7 2895 */
afaa2e4b
MT		 2896 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2897
2898 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
f264d360 2899 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
5f9252f7 2900 acpi_build_update, NULL, build_state,
baf2d5bf 2901 build_state->rsdp, rsdp_size, true);
339240b5 2902 build_state->rsdp_mr = NULL;
358774d7 2903 } else {
42d85900 2904 build_state->rsdp = NULL;
339240b5 2905 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
42d85900 2906 ACPI_BUILD_RSDP_FILE, 0);
358774d7 2907 }
72c194f7
MT		 2908
2909 qemu_register_reset(acpi_build_reset, build_state);
2910 acpi_build_reset(build_state);
2911 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2912
2913 /* Cleanup tables but don't free the memory: we track it
2914 * in build_state.
2915 */
2916 acpi_build_tables_cleanup(&tables, false);
2917}
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