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72c194f7 MT |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
4 | * Copyright (C) 2006 Fabrice Bellard | |
5 | * Copyright (C) 2013 Red Hat Inc | |
6 | * | |
7 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | ||
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | ||
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include "acpi-build.h" | |
24 | #include <stddef.h> | |
25 | #include <glib.h> | |
26 | #include "qemu-common.h" | |
27 | #include "qemu/bitmap.h" | |
07fb6176 | 28 | #include "qemu/osdep.h" |
07fb6176 | 29 | #include "qemu/error-report.h" |
72c194f7 MT |
30 | #include "hw/pci/pci.h" |
31 | #include "qom/cpu.h" | |
32 | #include "hw/i386/pc.h" | |
33 | #include "target-i386/cpu.h" | |
34 | #include "hw/timer/hpet.h" | |
395e5fb4 | 35 | #include "hw/acpi/acpi-defs.h" |
72c194f7 MT |
36 | #include "hw/acpi/acpi.h" |
37 | #include "hw/nvram/fw_cfg.h" | |
0058ae1d | 38 | #include "hw/acpi/bios-linker-loader.h" |
72c194f7 | 39 | #include "hw/loader.h" |
15bce1b7 | 40 | #include "hw/isa/isa.h" |
bef3492d | 41 | #include "hw/acpi/memory_hotplug.h" |
711b20b4 SB |
42 | #include "sysemu/tpm.h" |
43 | #include "hw/acpi/tpm.h" | |
72c194f7 MT |
44 | |
45 | /* Supported chipsets: */ | |
46 | #include "hw/acpi/piix4.h" | |
99fd437d | 47 | #include "hw/acpi/pcihp.h" |
72c194f7 MT |
48 | #include "hw/i386/ich9.h" |
49 | #include "hw/pci/pci_bus.h" | |
50 | #include "hw/pci-host/q35.h" | |
d4eb9119 | 51 | #include "hw/i386/intel_iommu.h" |
72c194f7 MT |
52 | |
53 | #include "hw/i386/q35-acpi-dsdt.hex" | |
54 | #include "hw/i386/acpi-dsdt.hex" | |
55 | ||
19934e0e IM |
56 | #include "hw/acpi/aml-build.h" |
57 | ||
72c194f7 MT |
58 | #include "qapi/qmp/qint.h" |
59 | #include "qom/qom-qobject.h" | |
60 | ||
07fb6176 PB |
61 | /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and |
62 | * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows | |
63 | * a little bit, there should be plenty of free space since the DSDT | |
64 | * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. | |
65 | */ | |
66 | #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 | |
67 | #define ACPI_BUILD_ALIGN_SIZE 0x1000 | |
68 | ||
868270f2 | 69 | #define ACPI_BUILD_TABLE_SIZE 0x20000 |
18045fb9 | 70 | |
8b310fc4 GA |
71 | /* #define DEBUG_ACPI_BUILD */ |
72 | #ifdef DEBUG_ACPI_BUILD | |
73 | #define ACPI_BUILD_DPRINTF(fmt, ...) \ | |
74 | do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) | |
75 | #else | |
76 | #define ACPI_BUILD_DPRINTF(fmt, ...) | |
77 | #endif | |
78 | ||
72c194f7 | 79 | typedef struct AcpiCpuInfo { |
798325ed | 80 | DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); |
72c194f7 MT |
81 | } AcpiCpuInfo; |
82 | ||
83 | typedef struct AcpiMcfgInfo { | |
84 | uint64_t mcfg_base; | |
85 | uint32_t mcfg_size; | |
86 | } AcpiMcfgInfo; | |
87 | ||
88 | typedef struct AcpiPmInfo { | |
89 | bool s3_disabled; | |
90 | bool s4_disabled; | |
133a2da4 | 91 | bool pcihp_bridge_en; |
72c194f7 MT |
92 | uint8_t s4_val; |
93 | uint16_t sci_int; | |
94 | uint8_t acpi_enable_cmd; | |
95 | uint8_t acpi_disable_cmd; | |
96 | uint32_t gpe0_blk; | |
97 | uint32_t gpe0_blk_len; | |
98 | uint32_t io_base; | |
ddf1ec2f IM |
99 | uint16_t cpu_hp_io_base; |
100 | uint16_t cpu_hp_io_len; | |
2c6b94d8 IM |
101 | uint16_t mem_hp_io_base; |
102 | uint16_t mem_hp_io_len; | |
500b11ea IM |
103 | uint16_t pcihp_io_base; |
104 | uint16_t pcihp_io_len; | |
72c194f7 MT |
105 | } AcpiPmInfo; |
106 | ||
107 | typedef struct AcpiMiscInfo { | |
108 | bool has_hpet; | |
711b20b4 | 109 | bool has_tpm; |
72c194f7 MT |
110 | const unsigned char *dsdt_code; |
111 | unsigned dsdt_size; | |
112 | uint16_t pvpanic_port; | |
8ac6f7a6 | 113 | uint16_t applesmc_io_base; |
72c194f7 MT |
114 | } AcpiMiscInfo; |
115 | ||
99fd437d MT |
116 | typedef struct AcpiBuildPciBusHotplugState { |
117 | GArray *device_table; | |
118 | GArray *notify_table; | |
119 | struct AcpiBuildPciBusHotplugState *parent; | |
133a2da4 | 120 | bool pcihp_bridge_en; |
99fd437d MT |
121 | } AcpiBuildPciBusHotplugState; |
122 | ||
72c194f7 MT |
123 | static void acpi_get_dsdt(AcpiMiscInfo *info) |
124 | { | |
125 | Object *piix = piix4_pm_find(); | |
126 | Object *lpc = ich9_lpc_find(); | |
127 | assert(!!piix != !!lpc); | |
128 | ||
129 | if (piix) { | |
130 | info->dsdt_code = AcpiDsdtAmlCode; | |
131 | info->dsdt_size = sizeof AcpiDsdtAmlCode; | |
132 | } | |
133 | if (lpc) { | |
134 | info->dsdt_code = Q35AcpiDsdtAmlCode; | |
135 | info->dsdt_size = sizeof Q35AcpiDsdtAmlCode; | |
136 | } | |
137 | } | |
138 | ||
139 | static | |
140 | int acpi_add_cpu_info(Object *o, void *opaque) | |
141 | { | |
142 | AcpiCpuInfo *cpu = opaque; | |
143 | uint64_t apic_id; | |
144 | ||
145 | if (object_dynamic_cast(o, TYPE_CPU)) { | |
146 | apic_id = object_property_get_int(o, "apic-id", NULL); | |
798325ed | 147 | assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); |
72c194f7 MT |
148 | |
149 | set_bit(apic_id, cpu->found_cpus); | |
150 | } | |
151 | ||
152 | object_child_foreach(o, acpi_add_cpu_info, opaque); | |
153 | return 0; | |
154 | } | |
155 | ||
156 | static void acpi_get_cpu_info(AcpiCpuInfo *cpu) | |
157 | { | |
158 | Object *root = object_get_root(); | |
159 | ||
160 | memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); | |
161 | object_child_foreach(root, acpi_add_cpu_info, cpu); | |
162 | } | |
163 | ||
164 | static void acpi_get_pm_info(AcpiPmInfo *pm) | |
165 | { | |
166 | Object *piix = piix4_pm_find(); | |
167 | Object *lpc = ich9_lpc_find(); | |
168 | Object *obj = NULL; | |
169 | QObject *o; | |
170 | ||
500b11ea IM |
171 | pm->pcihp_io_base = 0; |
172 | pm->pcihp_io_len = 0; | |
72c194f7 MT |
173 | if (piix) { |
174 | obj = piix; | |
ddf1ec2f | 175 | pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; |
500b11ea IM |
176 | pm->pcihp_io_base = |
177 | object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); | |
178 | pm->pcihp_io_len = | |
179 | object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); | |
72c194f7 MT |
180 | } |
181 | if (lpc) { | |
182 | obj = lpc; | |
ddf1ec2f | 183 | pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; |
72c194f7 MT |
184 | } |
185 | assert(obj); | |
186 | ||
ddf1ec2f | 187 | pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; |
2c6b94d8 IM |
188 | pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; |
189 | pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; | |
190 | ||
72c194f7 MT |
191 | /* Fill in optional s3/s4 related properties */ |
192 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); | |
193 | if (o) { | |
194 | pm->s3_disabled = qint_get_int(qobject_to_qint(o)); | |
195 | } else { | |
196 | pm->s3_disabled = false; | |
197 | } | |
097a97a6 | 198 | qobject_decref(o); |
72c194f7 MT |
199 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); |
200 | if (o) { | |
201 | pm->s4_disabled = qint_get_int(qobject_to_qint(o)); | |
202 | } else { | |
203 | pm->s4_disabled = false; | |
204 | } | |
097a97a6 | 205 | qobject_decref(o); |
72c194f7 MT |
206 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); |
207 | if (o) { | |
208 | pm->s4_val = qint_get_int(qobject_to_qint(o)); | |
209 | } else { | |
210 | pm->s4_val = false; | |
211 | } | |
097a97a6 | 212 | qobject_decref(o); |
72c194f7 MT |
213 | |
214 | /* Fill in mandatory properties */ | |
215 | pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); | |
216 | ||
217 | pm->acpi_enable_cmd = object_property_get_int(obj, | |
218 | ACPI_PM_PROP_ACPI_ENABLE_CMD, | |
219 | NULL); | |
220 | pm->acpi_disable_cmd = object_property_get_int(obj, | |
221 | ACPI_PM_PROP_ACPI_DISABLE_CMD, | |
222 | NULL); | |
223 | pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, | |
224 | NULL); | |
225 | pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, | |
226 | NULL); | |
227 | pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, | |
228 | NULL); | |
133a2da4 IM |
229 | pm->pcihp_bridge_en = |
230 | object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", | |
231 | NULL); | |
72c194f7 MT |
232 | } |
233 | ||
72c194f7 MT |
234 | static void acpi_get_misc_info(AcpiMiscInfo *info) |
235 | { | |
236 | info->has_hpet = hpet_find(); | |
711b20b4 | 237 | info->has_tpm = tpm_find(); |
72c194f7 | 238 | info->pvpanic_port = pvpanic_port(); |
8ac6f7a6 | 239 | info->applesmc_io_base = applesmc_port(); |
72c194f7 MT |
240 | } |
241 | ||
242 | static void acpi_get_pci_info(PcPciInfo *info) | |
243 | { | |
244 | Object *pci_host; | |
245 | bool ambiguous; | |
246 | ||
247 | pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); | |
248 | g_assert(!ambiguous); | |
249 | g_assert(pci_host); | |
250 | ||
251 | info->w32.begin = object_property_get_int(pci_host, | |
252 | PCI_HOST_PROP_PCI_HOLE_START, | |
253 | NULL); | |
254 | info->w32.end = object_property_get_int(pci_host, | |
255 | PCI_HOST_PROP_PCI_HOLE_END, | |
256 | NULL); | |
257 | info->w64.begin = object_property_get_int(pci_host, | |
258 | PCI_HOST_PROP_PCI_HOLE64_START, | |
259 | NULL); | |
260 | info->w64.end = object_property_get_int(pci_host, | |
261 | PCI_HOST_PROP_PCI_HOLE64_END, | |
262 | NULL); | |
263 | } | |
264 | ||
72c194f7 MT |
265 | #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ |
266 | ||
72c194f7 MT |
267 | static void acpi_align_size(GArray *blob, unsigned align) |
268 | { | |
269 | /* Align size to multiple of given size. This reduces the chance | |
270 | * we need to change size in the future (breaking cross version migration). | |
271 | */ | |
134d42d6 | 272 | g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); |
72c194f7 MT |
273 | } |
274 | ||
72c194f7 MT |
275 | /* FACS */ |
276 | static void | |
277 | build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) | |
278 | { | |
279 | AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); | |
821e3227 | 280 | memcpy(&facs->signature, "FACS", 4); |
72c194f7 MT |
281 | facs->length = cpu_to_le32(sizeof(*facs)); |
282 | } | |
283 | ||
284 | /* Load chipset information in FADT */ | |
285 | static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) | |
286 | { | |
287 | fadt->model = 1; | |
288 | fadt->reserved1 = 0; | |
289 | fadt->sci_int = cpu_to_le16(pm->sci_int); | |
290 | fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); | |
291 | fadt->acpi_enable = pm->acpi_enable_cmd; | |
292 | fadt->acpi_disable = pm->acpi_disable_cmd; | |
293 | /* EVT, CNT, TMR offset matches hw/acpi/core.c */ | |
294 | fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); | |
295 | fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); | |
296 | fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); | |
297 | fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); | |
298 | /* EVT, CNT, TMR length matches hw/acpi/core.c */ | |
299 | fadt->pm1_evt_len = 4; | |
300 | fadt->pm1_cnt_len = 2; | |
301 | fadt->pm_tmr_len = 4; | |
302 | fadt->gpe0_blk_len = pm->gpe0_blk_len; | |
303 | fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ | |
304 | fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ | |
305 | fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | | |
306 | (1 << ACPI_FADT_F_PROC_C1) | | |
307 | (1 << ACPI_FADT_F_SLP_BUTTON) | | |
308 | (1 << ACPI_FADT_F_RTC_S4)); | |
309 | fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); | |
07b81ed9 HZ |
310 | /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs |
311 | * For more than 8 CPUs, "Clustered Logical" mode has to be used | |
312 | */ | |
313 | if (max_cpus > 8) { | |
314 | fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); | |
315 | } | |
72c194f7 MT |
316 | } |
317 | ||
318 | ||
319 | /* FADT */ | |
320 | static void | |
321 | build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, | |
322 | unsigned facs, unsigned dsdt) | |
323 | { | |
324 | AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); | |
325 | ||
326 | fadt->firmware_ctrl = cpu_to_le32(facs); | |
327 | /* FACS address to be filled by Guest linker */ | |
328 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, | |
329 | ACPI_BUILD_TABLE_FILE, | |
330 | table_data, &fadt->firmware_ctrl, | |
331 | sizeof fadt->firmware_ctrl); | |
332 | ||
333 | fadt->dsdt = cpu_to_le32(dsdt); | |
334 | /* DSDT address to be filled by Guest linker */ | |
335 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, | |
336 | ACPI_BUILD_TABLE_FILE, | |
337 | table_data, &fadt->dsdt, | |
338 | sizeof fadt->dsdt); | |
339 | ||
340 | fadt_setup(fadt, pm); | |
341 | ||
342 | build_header(linker, table_data, | |
821e3227 | 343 | (void *)fadt, "FACP", sizeof(*fadt), 1); |
72c194f7 MT |
344 | } |
345 | ||
346 | static void | |
347 | build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, | |
348 | PcGuestInfo *guest_info) | |
349 | { | |
350 | int madt_start = table_data->len; | |
351 | ||
352 | AcpiMultipleApicTable *madt; | |
353 | AcpiMadtIoApic *io_apic; | |
354 | AcpiMadtIntsrcovr *intsrcovr; | |
355 | AcpiMadtLocalNmi *local_nmi; | |
356 | int i; | |
357 | ||
358 | madt = acpi_data_push(table_data, sizeof *madt); | |
359 | madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); | |
360 | madt->flags = cpu_to_le32(1); | |
361 | ||
362 | for (i = 0; i < guest_info->apic_id_limit; i++) { | |
363 | AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); | |
364 | apic->type = ACPI_APIC_PROCESSOR; | |
365 | apic->length = sizeof(*apic); | |
366 | apic->processor_id = i; | |
367 | apic->local_apic_id = i; | |
368 | if (test_bit(i, cpu->found_cpus)) { | |
369 | apic->flags = cpu_to_le32(1); | |
370 | } else { | |
371 | apic->flags = cpu_to_le32(0); | |
372 | } | |
373 | } | |
374 | io_apic = acpi_data_push(table_data, sizeof *io_apic); | |
375 | io_apic->type = ACPI_APIC_IO; | |
376 | io_apic->length = sizeof(*io_apic); | |
377 | #define ACPI_BUILD_IOAPIC_ID 0x0 | |
378 | io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; | |
379 | io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); | |
380 | io_apic->interrupt = cpu_to_le32(0); | |
381 | ||
382 | if (guest_info->apic_xrupt_override) { | |
383 | intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); | |
384 | intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; | |
385 | intsrcovr->length = sizeof(*intsrcovr); | |
386 | intsrcovr->source = 0; | |
387 | intsrcovr->gsi = cpu_to_le32(2); | |
388 | intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ | |
389 | } | |
390 | for (i = 1; i < 16; i++) { | |
391 | #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) | |
392 | if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { | |
393 | /* No need for a INT source override structure. */ | |
394 | continue; | |
395 | } | |
396 | intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); | |
397 | intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; | |
398 | intsrcovr->length = sizeof(*intsrcovr); | |
399 | intsrcovr->source = i; | |
400 | intsrcovr->gsi = cpu_to_le32(i); | |
401 | intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ | |
402 | } | |
403 | ||
404 | local_nmi = acpi_data_push(table_data, sizeof *local_nmi); | |
405 | local_nmi->type = ACPI_APIC_LOCAL_NMI; | |
406 | local_nmi->length = sizeof(*local_nmi); | |
407 | local_nmi->processor_id = 0xff; /* all processors */ | |
408 | local_nmi->flags = cpu_to_le16(0); | |
409 | local_nmi->lint = 1; /* ACPI_LINT1 */ | |
410 | ||
411 | build_header(linker, table_data, | |
821e3227 | 412 | (void *)(table_data->data + madt_start), "APIC", |
72c194f7 MT |
413 | table_data->len - madt_start, 1); |
414 | } | |
415 | ||
711b20b4 | 416 | #include "hw/i386/ssdt-tpm.hex" |
72c194f7 | 417 | |
99fd437d MT |
418 | /* Assign BSEL property to all buses. In the future, this can be changed |
419 | * to only assign to buses that support hotplug. | |
420 | */ | |
421 | static void *acpi_set_bsel(PCIBus *bus, void *opaque) | |
422 | { | |
423 | unsigned *bsel_alloc = opaque; | |
424 | unsigned *bus_bsel; | |
425 | ||
39b888bd | 426 | if (qbus_is_hotpluggable(BUS(bus))) { |
99fd437d MT |
427 | bus_bsel = g_malloc(sizeof *bus_bsel); |
428 | ||
429 | *bus_bsel = (*bsel_alloc)++; | |
430 | object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, | |
431 | bus_bsel, NULL); | |
432 | } | |
433 | ||
434 | return bsel_alloc; | |
435 | } | |
436 | ||
437 | static void acpi_set_pci_info(void) | |
438 | { | |
439 | PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ | |
440 | unsigned bsel_alloc = 0; | |
441 | ||
442 | if (bus) { | |
443 | /* Scan all PCI buses. Set property to enable acpi based hotplug. */ | |
444 | pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); | |
445 | } | |
446 | } | |
447 | ||
62b52c26 | 448 | static void build_append_pcihp_notify_entry(Aml *method, int slot) |
99fd437d | 449 | { |
62b52c26 IM |
450 | Aml *if_ctx; |
451 | int32_t devfn = PCI_DEVFN(slot, 0); | |
452 | ||
453 | if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot))); | |
454 | aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); | |
455 | aml_append(method, if_ctx); | |
99fd437d MT |
456 | } |
457 | ||
62b52c26 | 458 | static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, |
b23046ab | 459 | bool pcihp_bridge_en) |
99fd437d | 460 | { |
62b52c26 | 461 | Aml *dev, *notify_method, *method; |
99fd437d | 462 | QObject *bsel; |
b23046ab IM |
463 | PCIBus *sec; |
464 | int i; | |
133a2da4 | 465 | |
99fd437d MT |
466 | bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); |
467 | if (bsel) { | |
62b52c26 IM |
468 | int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); |
469 | ||
470 | aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); | |
471 | notify_method = aml_method("DVNT", 2); | |
8dcf525a | 472 | } |
99fd437d | 473 | |
8dcf525a MT |
474 | for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { |
475 | DeviceClass *dc; | |
476 | PCIDeviceClass *pc; | |
477 | PCIDevice *pdev = bus->devices[i]; | |
478 | int slot = PCI_SLOT(i); | |
b23046ab | 479 | bool hotplug_enabled_dev; |
093a35e5 | 480 | bool bridge_in_acpi; |
99fd437d | 481 | |
8dcf525a | 482 | if (!pdev) { |
b23046ab | 483 | if (bsel) { /* add hotplug slots for non present devices */ |
62b52c26 IM |
484 | dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); |
485 | aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); | |
486 | aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); | |
487 | method = aml_method("_EJ0", 1); | |
488 | aml_append(method, | |
489 | aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) | |
490 | ); | |
491 | aml_append(dev, method); | |
492 | aml_append(parent_scope, dev); | |
493 | ||
494 | build_append_pcihp_notify_entry(notify_method, slot); | |
b23046ab | 495 | } |
8dcf525a MT |
496 | continue; |
497 | } | |
99fd437d | 498 | |
8dcf525a MT |
499 | pc = PCI_DEVICE_GET_CLASS(pdev); |
500 | dc = DEVICE_GET_CLASS(pdev); | |
99fd437d | 501 | |
093a35e5 MT |
502 | /* When hotplug for bridges is enabled, bridges are |
503 | * described in ACPI separately (see build_pci_bus_end). | |
504 | * In this case they aren't themselves hot-pluggable. | |
a20275fa | 505 | * Hotplugged bridges *are* hot-pluggable. |
093a35e5 | 506 | */ |
b23046ab IM |
507 | bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && |
508 | !DEVICE(pdev)->hotplugged; | |
509 | ||
510 | hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; | |
093a35e5 | 511 | |
b23046ab IM |
512 | if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { |
513 | continue; | |
99fd437d MT |
514 | } |
515 | ||
62b52c26 IM |
516 | /* start to compose PCI slot descriptor */ |
517 | dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); | |
518 | aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); | |
519 | ||
8dcf525a | 520 | if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { |
62b52c26 IM |
521 | /* add VGA specific AML methods */ |
522 | int s3d; | |
523 | ||
8dcf525a | 524 | if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { |
62b52c26 | 525 | s3d = 3; |
b23046ab | 526 | } else { |
62b52c26 | 527 | s3d = 0; |
99fd437d | 528 | } |
62b52c26 IM |
529 | |
530 | method = aml_method("_S1D", 0); | |
531 | aml_append(method, aml_return(aml_int(0))); | |
532 | aml_append(dev, method); | |
533 | ||
534 | method = aml_method("_S2D", 0); | |
535 | aml_append(method, aml_return(aml_int(0))); | |
536 | aml_append(dev, method); | |
537 | ||
538 | method = aml_method("_S3D", 0); | |
539 | aml_append(method, aml_return(aml_int(s3d))); | |
540 | aml_append(dev, method); | |
b23046ab | 541 | } else if (hotplug_enabled_dev) { |
62b52c26 IM |
542 | /* add _SUN/_EJ0 to make slot hotpluggable */ |
543 | aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); | |
99fd437d | 544 | |
62b52c26 IM |
545 | method = aml_method("_EJ0", 1); |
546 | aml_append(method, | |
547 | aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) | |
548 | ); | |
549 | aml_append(dev, method); | |
550 | ||
551 | if (bsel) { | |
552 | build_append_pcihp_notify_entry(notify_method, slot); | |
553 | } | |
b23046ab | 554 | } else if (bridge_in_acpi) { |
62b52c26 IM |
555 | /* |
556 | * device is coldplugged bridge, | |
557 | * add child device descriptions into its scope | |
558 | */ | |
b23046ab | 559 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); |
b23046ab | 560 | |
62b52c26 | 561 | build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); |
8dcf525a | 562 | } |
62b52c26 IM |
563 | /* slot descriptor has been composed, add it into parent context */ |
564 | aml_append(parent_scope, dev); | |
8dcf525a MT |
565 | } |
566 | ||
567 | if (bsel) { | |
62b52c26 | 568 | aml_append(parent_scope, notify_method); |
99fd437d MT |
569 | } |
570 | ||
571 | /* Append PCNT method to notify about events on local and child buses. | |
572 | * Add unconditionally for root since DSDT expects it. | |
72c194f7 | 573 | */ |
62b52c26 | 574 | method = aml_method("PCNT", 0); |
99fd437d | 575 | |
b23046ab IM |
576 | /* If bus supports hotplug select it and notify about local events */ |
577 | if (bsel) { | |
62b52c26 IM |
578 | int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); |
579 | aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); | |
580 | aml_append(method, | |
581 | aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) | |
582 | ); | |
583 | aml_append(method, | |
584 | aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) | |
585 | ); | |
b23046ab | 586 | } |
99fd437d | 587 | |
b23046ab IM |
588 | /* Notify about child bus events in any case */ |
589 | if (pcihp_bridge_en) { | |
590 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
62b52c26 IM |
591 | int32_t devfn = sec->parent_dev->devfn; |
592 | ||
593 | aml_append(method, aml_name("^S%.02X.PCNT", devfn)); | |
99fd437d | 594 | } |
72c194f7 | 595 | } |
62b52c26 | 596 | aml_append(parent_scope, method); |
72c194f7 MT |
597 | } |
598 | ||
72c194f7 MT |
599 | static void |
600 | build_ssdt(GArray *table_data, GArray *linker, | |
601 | AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, | |
602 | PcPciInfo *pci, PcGuestInfo *guest_info) | |
603 | { | |
bef3492d IM |
604 | MachineState *machine = MACHINE(qdev_get_machine()); |
605 | uint32_t nr_mem = machine->ram_slots; | |
2fd71f1b | 606 | unsigned acpi_cpus = guest_info->apic_id_limit; |
20843d16 | 607 | Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx; |
72c194f7 MT |
608 | int i; |
609 | ||
011bb749 | 610 | ssdt = init_aml_allocator(); |
2fd71f1b LE |
611 | /* The current AML generator can cover the APIC ID range [0..255], |
612 | * inclusive, for VCPU hotplug. */ | |
613 | QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); | |
614 | g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); | |
615 | ||
4ec8d2b3 IM |
616 | /* Reserve space for header */ |
617 | acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); | |
72c194f7 | 618 | |
500b11ea | 619 | scope = aml_scope("\\_SB.PCI0"); |
60efd429 IM |
620 | /* build PCI0._CRS */ |
621 | crs = aml_resource_template(); | |
622 | aml_append(crs, | |
ff80dc7f | 623 | aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, |
60efd429 | 624 | 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); |
ff80dc7f | 625 | aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); |
60efd429 IM |
626 | |
627 | aml_append(crs, | |
ff80dc7f SZ |
628 | aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, |
629 | AML_POS_DECODE, AML_ENTIRE_RANGE, | |
60efd429 | 630 | 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); |
d31c909e | 631 | aml_append(crs, |
ff80dc7f SZ |
632 | aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, |
633 | AML_POS_DECODE, AML_ENTIRE_RANGE, | |
d31c909e | 634 | 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); |
60efd429 | 635 | aml_append(crs, |
ff80dc7f SZ |
636 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, |
637 | AML_CACHEABLE, AML_READ_WRITE, | |
60efd429 IM |
638 | 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); |
639 | aml_append(crs, | |
ff80dc7f SZ |
640 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, |
641 | AML_NON_CACHEABLE, AML_READ_WRITE, | |
60efd429 IM |
642 | 0, pci->w32.begin, pci->w32.end - 1, 0, |
643 | pci->w32.end - pci->w32.begin)); | |
644 | if (pci->w64.begin) { | |
645 | aml_append(crs, | |
ff80dc7f SZ |
646 | aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, |
647 | AML_CACHEABLE, AML_READ_WRITE, | |
60efd429 IM |
648 | 0, pci->w64.begin, pci->w64.end - 1, 0, |
649 | pci->w64.end - pci->w64.begin)); | |
650 | } | |
651 | aml_append(scope, aml_name_decl("_CRS", crs)); | |
652 | ||
d31c909e IM |
653 | /* reserve GPE0 block resources */ |
654 | dev = aml_device("GPE0"); | |
655 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
656 | aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); | |
657 | /* device present, functioning, decoding, not shown in UI */ | |
658 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
659 | crs = aml_resource_template(); | |
660 | aml_append(crs, | |
ff80dc7f | 661 | aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) |
d31c909e IM |
662 | ); |
663 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
664 | aml_append(scope, dev); | |
665 | ||
500b11ea IM |
666 | /* reserve PCIHP resources */ |
667 | if (pm->pcihp_io_len) { | |
668 | dev = aml_device("PHPR"); | |
669 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
670 | aml_append(dev, | |
671 | aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); | |
672 | /* device present, functioning, decoding, not shown in UI */ | |
673 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
674 | crs = aml_resource_template(); | |
675 | aml_append(crs, | |
ff80dc7f | 676 | aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, |
500b11ea IM |
677 | pm->pcihp_io_len) |
678 | ); | |
679 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
680 | aml_append(scope, dev); | |
681 | } | |
682 | aml_append(ssdt, scope); | |
683 | ||
ebc3028f IM |
684 | /* create S3_ / S4_ / S5_ packages if necessary */ |
685 | scope = aml_scope("\\"); | |
686 | if (!pm->s3_disabled) { | |
687 | pkg = aml_package(4); | |
688 | aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ | |
689 | aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
690 | aml_append(pkg, aml_int(0)); /* reserved */ | |
691 | aml_append(pkg, aml_int(0)); /* reserved */ | |
692 | aml_append(scope, aml_name_decl("_S3", pkg)); | |
693 | } | |
694 | ||
695 | if (!pm->s4_disabled) { | |
696 | pkg = aml_package(4); | |
697 | aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ | |
698 | /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
699 | aml_append(pkg, aml_int(pm->s4_val)); | |
700 | aml_append(pkg, aml_int(0)); /* reserved */ | |
701 | aml_append(pkg, aml_int(0)); /* reserved */ | |
702 | aml_append(scope, aml_name_decl("_S4", pkg)); | |
703 | } | |
704 | ||
705 | pkg = aml_package(4); | |
706 | aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ | |
707 | aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ | |
708 | aml_append(pkg, aml_int(0)); /* reserved */ | |
709 | aml_append(pkg, aml_int(0)); /* reserved */ | |
710 | aml_append(scope, aml_name_decl("_S5", pkg)); | |
711 | aml_append(ssdt, scope); | |
712 | ||
8ac6f7a6 IM |
713 | if (misc->applesmc_io_base) { |
714 | scope = aml_scope("\\_SB.PCI0.ISA"); | |
715 | dev = aml_device("SMC"); | |
716 | ||
717 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); | |
718 | /* device present, functioning, decoding, not shown in UI */ | |
719 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
720 | ||
721 | crs = aml_resource_template(); | |
722 | aml_append(crs, | |
ff80dc7f | 723 | aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, |
8ac6f7a6 IM |
724 | 0x01, APPLESMC_MAX_DATA_LENGTH) |
725 | ); | |
726 | aml_append(crs, aml_irq_no_flags(6)); | |
727 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
728 | ||
729 | aml_append(scope, dev); | |
730 | aml_append(ssdt, scope); | |
731 | } | |
732 | ||
cd61cb2e IM |
733 | if (misc->pvpanic_port) { |
734 | scope = aml_scope("\\_SB.PCI0.ISA"); | |
735 | ||
2332333c | 736 | dev = aml_device("PEVT"); |
e65bef69 | 737 | aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); |
cd61cb2e IM |
738 | |
739 | crs = aml_resource_template(); | |
740 | aml_append(crs, | |
ff80dc7f | 741 | aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) |
cd61cb2e IM |
742 | ); |
743 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
744 | ||
ff80dc7f | 745 | aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, |
cd61cb2e | 746 | misc->pvpanic_port, 1)); |
ff80dc7f | 747 | field = aml_field("PEOR", AML_BYTE_ACC, AML_PRESERVE); |
cd61cb2e IM |
748 | aml_append(field, aml_named_field("PEPT", 8)); |
749 | aml_append(dev, field); | |
750 | ||
2332333c RK |
751 | /* device present, functioning, decoding, not shown in UI */ |
752 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
753 | ||
cd61cb2e IM |
754 | method = aml_method("RDPT", 0); |
755 | aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); | |
756 | aml_append(method, aml_return(aml_local(0))); | |
757 | aml_append(dev, method); | |
758 | ||
759 | method = aml_method("WRPT", 1); | |
760 | aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); | |
761 | aml_append(dev, method); | |
762 | ||
763 | aml_append(scope, dev); | |
764 | aml_append(ssdt, scope); | |
765 | } | |
766 | ||
7824df38 | 767 | sb_scope = aml_scope("\\_SB"); |
72c194f7 | 768 | { |
ddf1ec2f IM |
769 | /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ |
770 | dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); | |
771 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); | |
772 | aml_append(dev, | |
773 | aml_name_decl("_UID", aml_string("CPU Hotplug resources")) | |
774 | ); | |
775 | /* device present, functioning, decoding, not shown in UI */ | |
776 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
777 | crs = aml_resource_template(); | |
778 | aml_append(crs, | |
ff80dc7f | 779 | aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, |
ddf1ec2f IM |
780 | pm->cpu_hp_io_len) |
781 | ); | |
782 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
783 | aml_append(sb_scope, dev); | |
784 | /* declare CPU hotplug MMIO region and PRS field to access it */ | |
785 | aml_append(sb_scope, aml_operation_region( | |
ff80dc7f SZ |
786 | "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); |
787 | field = aml_field("PRST", AML_BYTE_ACC, AML_PRESERVE); | |
ddf1ec2f IM |
788 | aml_append(field, aml_named_field("PRS", 256)); |
789 | aml_append(sb_scope, field); | |
790 | ||
72c194f7 MT |
791 | /* build Processor object for each processor */ |
792 | for (i = 0; i < acpi_cpus; i++) { | |
20843d16 IM |
793 | dev = aml_processor(i, 0, 0, "CP%.02X", i); |
794 | ||
795 | method = aml_method("_MAT", 0); | |
796 | aml_append(method, aml_return(aml_call1("CPMA", aml_int(i)))); | |
797 | aml_append(dev, method); | |
798 | ||
799 | method = aml_method("_STA", 0); | |
800 | aml_append(method, aml_return(aml_call1("CPST", aml_int(i)))); | |
801 | aml_append(dev, method); | |
802 | ||
803 | method = aml_method("_EJ0", 1); | |
804 | aml_append(method, | |
805 | aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0))) | |
806 | ); | |
807 | aml_append(dev, method); | |
808 | ||
809 | aml_append(sb_scope, dev); | |
72c194f7 MT |
810 | } |
811 | ||
812 | /* build this code: | |
813 | * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} | |
814 | */ | |
815 | /* Arg0 = Processor ID = APIC ID */ | |
20843d16 IM |
816 | method = aml_method("NTFY", 2); |
817 | for (i = 0; i < acpi_cpus; i++) { | |
818 | ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); | |
819 | aml_append(ifctx, | |
820 | aml_notify(aml_name("CP%.02X", i), aml_arg(1)) | |
821 | ); | |
822 | aml_append(method, ifctx); | |
823 | } | |
824 | aml_append(sb_scope, method); | |
825 | ||
826 | /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" | |
827 | * | |
828 | * Note: The ability to create variable-sized packages was first | |
e71fd764 | 829 | * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages |
20843d16 IM |
830 | * ith up to 255 elements. Windows guests up to win2k8 fail when |
831 | * VarPackageOp is used. | |
832 | */ | |
833 | pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : | |
834 | aml_varpackage(acpi_cpus); | |
72c194f7 | 835 | |
20843d16 IM |
836 | for (i = 0; i < acpi_cpus; i++) { |
837 | uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; | |
838 | aml_append(pkg, aml_int(b)); | |
72c194f7 | 839 | } |
20843d16 | 840 | aml_append(sb_scope, aml_name_decl("CPON", pkg)); |
72c194f7 | 841 | |
8698c0c0 IM |
842 | /* build memory devices */ |
843 | assert(nr_mem <= ACPI_MAX_RAM_SLOTS); | |
2c6b94d8 IM |
844 | scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); |
845 | aml_append(scope, | |
846 | aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) | |
847 | ); | |
848 | ||
849 | crs = aml_resource_template(); | |
850 | aml_append(crs, | |
ff80dc7f | 851 | aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, |
2c6b94d8 IM |
852 | pm->mem_hp_io_len) |
853 | ); | |
854 | aml_append(scope, aml_name_decl("_CRS", crs)); | |
855 | ||
856 | aml_append(scope, aml_operation_region( | |
ff80dc7f | 857 | stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO, |
2c6b94d8 IM |
858 | pm->mem_hp_io_base, pm->mem_hp_io_len) |
859 | ); | |
860 | ||
ff80dc7f SZ |
861 | field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, |
862 | AML_PRESERVE); | |
2c6b94d8 IM |
863 | aml_append(field, /* read only */ |
864 | aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); | |
865 | aml_append(field, /* read only */ | |
866 | aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); | |
867 | aml_append(field, /* read only */ | |
868 | aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); | |
869 | aml_append(field, /* read only */ | |
870 | aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); | |
871 | aml_append(field, /* read only */ | |
872 | aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); | |
873 | aml_append(scope, field); | |
874 | ||
ff80dc7f SZ |
875 | field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC, |
876 | AML_WRITE_AS_ZEROS); | |
2c6b94d8 IM |
877 | aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); |
878 | aml_append(field, /* 1 if enabled, read only */ | |
879 | aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); | |
880 | aml_append(field, | |
881 | /*(read) 1 if has a insert event. (write) 1 to clear event */ | |
882 | aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); | |
c06b2ffb ZG |
883 | aml_append(field, |
884 | /* (read) 1 if has a remove event. (write) 1 to clear event */ | |
885 | aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1)); | |
886 | aml_append(field, | |
887 | /* initiates device eject, write only */ | |
888 | aml_named_field(stringify(MEMORY_SLOT_EJECT), 1)); | |
2c6b94d8 IM |
889 | aml_append(scope, field); |
890 | ||
ff80dc7f SZ |
891 | field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, |
892 | AML_PRESERVE); | |
2c6b94d8 IM |
893 | aml_append(field, /* DIMM selector, write only */ |
894 | aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); | |
895 | aml_append(field, /* _OST event code, write only */ | |
896 | aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); | |
897 | aml_append(field, /* _OST status code, write only */ | |
898 | aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); | |
899 | aml_append(scope, field); | |
900 | ||
901 | aml_append(sb_scope, scope); | |
8698c0c0 IM |
902 | |
903 | for (i = 0; i < nr_mem; i++) { | |
904 | #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "." | |
905 | const char *s; | |
906 | ||
907 | dev = aml_device("MP%02X", i); | |
908 | aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); | |
909 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); | |
bef3492d | 910 | |
8698c0c0 IM |
911 | method = aml_method("_CRS", 0); |
912 | s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD); | |
913 | aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); | |
914 | aml_append(dev, method); | |
915 | ||
916 | method = aml_method("_STA", 0); | |
917 | s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD); | |
918 | aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); | |
919 | aml_append(dev, method); | |
920 | ||
921 | method = aml_method("_PXM", 0); | |
922 | s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD); | |
923 | aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); | |
924 | aml_append(dev, method); | |
925 | ||
926 | method = aml_method("_OST", 3); | |
927 | s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD); | |
928 | aml_append(method, aml_return(aml_call4( | |
929 | s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) | |
930 | ))); | |
931 | aml_append(dev, method); | |
932 | ||
c06b2ffb ZG |
933 | method = aml_method("_EJ0", 1); |
934 | s = BASEPATH stringify(MEMORY_SLOT_EJECT_METHOD); | |
935 | aml_append(method, aml_return(aml_call2( | |
936 | s, aml_name("_UID"), aml_arg(0)))); | |
937 | aml_append(dev, method); | |
938 | ||
8698c0c0 | 939 | aml_append(sb_scope, dev); |
bef3492d IM |
940 | } |
941 | ||
8698c0c0 | 942 | /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { |
853cff8e | 943 | * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } |
8698c0c0 IM |
944 | */ |
945 | method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2); | |
946 | for (i = 0; i < nr_mem; i++) { | |
947 | ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); | |
948 | aml_append(ifctx, | |
949 | aml_notify(aml_name("MP%.02X", i), aml_arg(1)) | |
950 | ); | |
951 | aml_append(method, ifctx); | |
952 | } | |
953 | aml_append(sb_scope, method); | |
954 | ||
72c194f7 | 955 | { |
8dcf525a MT |
956 | Object *pci_host; |
957 | PCIBus *bus = NULL; | |
958 | bool ambiguous; | |
959 | ||
960 | pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); | |
961 | if (!ambiguous && pci_host) { | |
962 | bus = PCI_HOST_BRIDGE(pci_host)->bus; | |
963 | } | |
72c194f7 | 964 | |
99fd437d | 965 | if (bus) { |
62b52c26 | 966 | Aml *scope = aml_scope("PCI0"); |
99fd437d | 967 | /* Scan all PCI buses. Generate tables to support hotplug. */ |
62b52c26 IM |
968 | build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); |
969 | aml_append(sb_scope, scope); | |
72c194f7 | 970 | } |
72c194f7 | 971 | } |
011bb749 | 972 | aml_append(ssdt, sb_scope); |
72c194f7 MT |
973 | } |
974 | ||
011bb749 IM |
975 | /* copy AML table into ACPI tables blob and patch header there */ |
976 | g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); | |
72c194f7 | 977 | build_header(linker, table_data, |
011bb749 IM |
978 | (void *)(table_data->data + table_data->len - ssdt->buf->len), |
979 | "SSDT", ssdt->buf->len, 1); | |
980 | free_aml_allocator(); | |
72c194f7 MT |
981 | } |
982 | ||
983 | static void | |
984 | build_hpet(GArray *table_data, GArray *linker) | |
985 | { | |
986 | Acpi20Hpet *hpet; | |
987 | ||
988 | hpet = acpi_data_push(table_data, sizeof(*hpet)); | |
989 | /* Note timer_block_id value must be kept in sync with value advertised by | |
990 | * emulated hpet | |
991 | */ | |
992 | hpet->timer_block_id = cpu_to_le32(0x8086a201); | |
993 | hpet->addr.address = cpu_to_le64(HPET_BASE); | |
994 | build_header(linker, table_data, | |
821e3227 | 995 | (void *)hpet, "HPET", sizeof(*hpet), 1); |
72c194f7 MT |
996 | } |
997 | ||
711b20b4 | 998 | static void |
42a5b308 | 999 | build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) |
711b20b4 SB |
1000 | { |
1001 | Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); | |
42a5b308 | 1002 | uint64_t log_area_start_address = acpi_data_len(tcpalog); |
711b20b4 SB |
1003 | |
1004 | tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); | |
1005 | tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); | |
1006 | tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); | |
1007 | ||
42a5b308 SB |
1008 | bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, |
1009 | false /* high memory */); | |
1010 | ||
711b20b4 SB |
1011 | /* log area start address to be filled by Guest linker */ |
1012 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, | |
42a5b308 | 1013 | ACPI_BUILD_TPMLOG_FILE, |
711b20b4 SB |
1014 | table_data, &tcpa->log_area_start_address, |
1015 | sizeof(tcpa->log_area_start_address)); | |
1016 | ||
1017 | build_header(linker, table_data, | |
1018 | (void *)tcpa, "TCPA", sizeof(*tcpa), 2); | |
1019 | ||
42a5b308 | 1020 | acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); |
711b20b4 SB |
1021 | } |
1022 | ||
1023 | static void | |
1024 | build_tpm_ssdt(GArray *table_data, GArray *linker) | |
1025 | { | |
1026 | void *tpm_ptr; | |
1027 | ||
1028 | tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml)); | |
1029 | memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml)); | |
1030 | } | |
1031 | ||
04ed3ea8 IM |
1032 | typedef enum { |
1033 | MEM_AFFINITY_NOFLAGS = 0, | |
1034 | MEM_AFFINITY_ENABLED = (1 << 0), | |
1035 | MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), | |
1036 | MEM_AFFINITY_NON_VOLATILE = (1 << 2), | |
1037 | } MemoryAffinityFlags; | |
1038 | ||
72c194f7 | 1039 | static void |
04ed3ea8 IM |
1040 | acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, |
1041 | uint64_t len, int node, MemoryAffinityFlags flags) | |
72c194f7 MT |
1042 | { |
1043 | numamem->type = ACPI_SRAT_MEMORY; | |
1044 | numamem->length = sizeof(*numamem); | |
1045 | memset(numamem->proximity, 0, 4); | |
1046 | numamem->proximity[0] = node; | |
04ed3ea8 | 1047 | numamem->flags = cpu_to_le32(flags); |
72c194f7 MT |
1048 | numamem->base_addr = cpu_to_le64(base); |
1049 | numamem->range_length = cpu_to_le64(len); | |
1050 | } | |
1051 | ||
1052 | static void | |
dd0247e0 | 1053 | build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) |
72c194f7 MT |
1054 | { |
1055 | AcpiSystemResourceAffinityTable *srat; | |
1056 | AcpiSratProcessorAffinity *core; | |
1057 | AcpiSratMemoryAffinity *numamem; | |
1058 | ||
1059 | int i; | |
1060 | uint64_t curnode; | |
1061 | int srat_start, numa_start, slots; | |
1062 | uint64_t mem_len, mem_base, next_base; | |
cec65193 IM |
1063 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); |
1064 | ram_addr_t hotplugabble_address_space_size = | |
1065 | object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, | |
1066 | NULL); | |
72c194f7 MT |
1067 | |
1068 | srat_start = table_data->len; | |
1069 | ||
1070 | srat = acpi_data_push(table_data, sizeof *srat); | |
1071 | srat->reserved1 = cpu_to_le32(1); | |
1072 | core = (void *)(srat + 1); | |
1073 | ||
1074 | for (i = 0; i < guest_info->apic_id_limit; ++i) { | |
1075 | core = acpi_data_push(table_data, sizeof *core); | |
1076 | core->type = ACPI_SRAT_PROCESSOR; | |
1077 | core->length = sizeof(*core); | |
1078 | core->local_apic_id = i; | |
1079 | curnode = guest_info->node_cpu[i]; | |
1080 | core->proximity_lo = curnode; | |
1081 | memset(core->proximity_hi, 0, 3); | |
1082 | core->local_sapic_eid = 0; | |
dd0247e0 | 1083 | core->flags = cpu_to_le32(1); |
72c194f7 MT |
1084 | } |
1085 | ||
1086 | ||
1087 | /* the memory map is a bit tricky, it contains at least one hole | |
1088 | * from 640k-1M and possibly another one from 3.5G-4G. | |
1089 | */ | |
1090 | next_base = 0; | |
1091 | numa_start = table_data->len; | |
1092 | ||
1093 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
04ed3ea8 | 1094 | acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); |
72c194f7 MT |
1095 | next_base = 1024 * 1024; |
1096 | for (i = 1; i < guest_info->numa_nodes + 1; ++i) { | |
1097 | mem_base = next_base; | |
1098 | mem_len = guest_info->node_mem[i - 1]; | |
1099 | if (i == 1) { | |
1100 | mem_len -= 1024 * 1024; | |
1101 | } | |
1102 | next_base = mem_base + mem_len; | |
1103 | ||
1104 | /* Cut out the ACPI_PCI hole */ | |
4c8a949b EH |
1105 | if (mem_base <= guest_info->ram_size_below_4g && |
1106 | next_base > guest_info->ram_size_below_4g) { | |
1107 | mem_len -= next_base - guest_info->ram_size_below_4g; | |
72c194f7 MT |
1108 | if (mem_len > 0) { |
1109 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
04ed3ea8 IM |
1110 | acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, |
1111 | MEM_AFFINITY_ENABLED); | |
72c194f7 MT |
1112 | } |
1113 | mem_base = 1ULL << 32; | |
4c8a949b EH |
1114 | mem_len = next_base - guest_info->ram_size_below_4g; |
1115 | next_base += (1ULL << 32) - guest_info->ram_size_below_4g; | |
72c194f7 MT |
1116 | } |
1117 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
04ed3ea8 IM |
1118 | acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, |
1119 | MEM_AFFINITY_ENABLED); | |
72c194f7 MT |
1120 | } |
1121 | slots = (table_data->len - numa_start) / sizeof *numamem; | |
1122 | for (; slots < guest_info->numa_nodes + 2; slots++) { | |
1123 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
04ed3ea8 | 1124 | acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); |
72c194f7 MT |
1125 | } |
1126 | ||
cec65193 IM |
1127 | /* |
1128 | * Entry is required for Windows to enable memory hotplug in OS. | |
1129 | * Memory devices may override proximity set by this entry, | |
1130 | * providing _PXM method if necessary. | |
1131 | */ | |
1132 | if (hotplugabble_address_space_size) { | |
1133 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
1134 | acpi_build_srat_memory(numamem, pcms->hotplug_memory_base, | |
1135 | hotplugabble_address_space_size, 0, | |
1136 | MEM_AFFINITY_HOTPLUGGABLE | | |
1137 | MEM_AFFINITY_ENABLED); | |
1138 | } | |
1139 | ||
72c194f7 MT |
1140 | build_header(linker, table_data, |
1141 | (void *)(table_data->data + srat_start), | |
821e3227 | 1142 | "SRAT", |
72c194f7 MT |
1143 | table_data->len - srat_start, 1); |
1144 | } | |
1145 | ||
1146 | static void | |
1147 | build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) | |
1148 | { | |
1149 | AcpiTableMcfg *mcfg; | |
821e3227 | 1150 | const char *sig; |
72c194f7 MT |
1151 | int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); |
1152 | ||
1153 | mcfg = acpi_data_push(table_data, len); | |
1154 | mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); | |
1155 | /* Only a single allocation so no need to play with segments */ | |
1156 | mcfg->allocation[0].pci_segment = cpu_to_le16(0); | |
1157 | mcfg->allocation[0].start_bus_number = 0; | |
1158 | mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); | |
1159 | ||
1160 | /* MCFG is used for ECAM which can be enabled or disabled by guest. | |
1161 | * To avoid table size changes (which create migration issues), | |
1162 | * always create the table even if there are no allocations, | |
1163 | * but set the signature to a reserved value in this case. | |
1164 | * ACPI spec requires OSPMs to ignore such tables. | |
1165 | */ | |
1166 | if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { | |
821e3227 MT |
1167 | /* Reserved signature: ignored by OSPM */ |
1168 | sig = "QEMU"; | |
72c194f7 | 1169 | } else { |
821e3227 | 1170 | sig = "MCFG"; |
72c194f7 MT |
1171 | } |
1172 | build_header(linker, table_data, (void *)mcfg, sig, len, 1); | |
1173 | } | |
1174 | ||
d4eb9119 LT |
1175 | static void |
1176 | build_dmar_q35(GArray *table_data, GArray *linker) | |
1177 | { | |
1178 | int dmar_start = table_data->len; | |
1179 | ||
1180 | AcpiTableDmar *dmar; | |
1181 | AcpiDmarHardwareUnit *drhd; | |
1182 | ||
1183 | dmar = acpi_data_push(table_data, sizeof(*dmar)); | |
1184 | dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; | |
1185 | dmar->flags = 0; /* No intr_remap for now */ | |
1186 | ||
1187 | /* DMAR Remapping Hardware Unit Definition structure */ | |
1188 | drhd = acpi_data_push(table_data, sizeof(*drhd)); | |
1189 | drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); | |
1190 | drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ | |
1191 | drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; | |
1192 | drhd->pci_segment = cpu_to_le16(0); | |
1193 | drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); | |
1194 | ||
1195 | build_header(linker, table_data, (void *)(table_data->data + dmar_start), | |
1196 | "DMAR", table_data->len - dmar_start, 1); | |
1197 | } | |
1198 | ||
72c194f7 MT |
1199 | static void |
1200 | build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) | |
1201 | { | |
53db092a MT |
1202 | AcpiTableHeader *dsdt; |
1203 | ||
72c194f7 | 1204 | assert(misc->dsdt_code && misc->dsdt_size); |
53db092a | 1205 | |
72c194f7 MT |
1206 | dsdt = acpi_data_push(table_data, misc->dsdt_size); |
1207 | memcpy(dsdt, misc->dsdt_code, misc->dsdt_size); | |
53db092a MT |
1208 | |
1209 | memset(dsdt, 0, sizeof *dsdt); | |
821e3227 | 1210 | build_header(linker, table_data, dsdt, "DSDT", |
53db092a | 1211 | misc->dsdt_size, 1); |
72c194f7 MT |
1212 | } |
1213 | ||
72c194f7 MT |
1214 | static GArray * |
1215 | build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) | |
1216 | { | |
1217 | AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); | |
1218 | ||
d67aadcc | 1219 | bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, |
72c194f7 MT |
1220 | true /* fseg memory */); |
1221 | ||
821e3227 | 1222 | memcpy(&rsdp->signature, "RSD PTR ", 8); |
72c194f7 MT |
1223 | memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); |
1224 | rsdp->rsdt_physical_address = cpu_to_le32(rsdt); | |
1225 | /* Address to be filled by Guest linker */ | |
1226 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, | |
1227 | ACPI_BUILD_TABLE_FILE, | |
1228 | rsdp_table, &rsdp->rsdt_physical_address, | |
1229 | sizeof rsdp->rsdt_physical_address); | |
1230 | rsdp->checksum = 0; | |
1231 | /* Checksum to be filled by Guest linker */ | |
1232 | bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, | |
1233 | rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); | |
1234 | ||
1235 | return rsdp_table; | |
1236 | } | |
1237 | ||
72c194f7 MT |
1238 | typedef |
1239 | struct AcpiBuildState { | |
1240 | /* Copy of table in RAM (for patching). */ | |
339240b5 | 1241 | MemoryRegion *table_mr; |
72c194f7 MT |
1242 | /* Is table patched? */ |
1243 | uint8_t patched; | |
1244 | PcGuestInfo *guest_info; | |
d70414a5 | 1245 | void *rsdp; |
339240b5 PB |
1246 | MemoryRegion *rsdp_mr; |
1247 | MemoryRegion *linker_mr; | |
72c194f7 MT |
1248 | } AcpiBuildState; |
1249 | ||
1250 | static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) | |
1251 | { | |
1252 | Object *pci_host; | |
1253 | QObject *o; | |
1254 | bool ambiguous; | |
1255 | ||
1256 | pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); | |
1257 | g_assert(!ambiguous); | |
1258 | g_assert(pci_host); | |
1259 | ||
1260 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); | |
1261 | if (!o) { | |
1262 | return false; | |
1263 | } | |
1264 | mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); | |
097a97a6 | 1265 | qobject_decref(o); |
72c194f7 MT |
1266 | |
1267 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); | |
1268 | assert(o); | |
1269 | mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); | |
097a97a6 | 1270 | qobject_decref(o); |
72c194f7 MT |
1271 | return true; |
1272 | } | |
1273 | ||
d4eb9119 LT |
1274 | static bool acpi_has_iommu(void) |
1275 | { | |
1276 | bool ambiguous; | |
1277 | Object *intel_iommu; | |
1278 | ||
1279 | intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, | |
1280 | &ambiguous); | |
1281 | return intel_iommu && !ambiguous; | |
1282 | } | |
1283 | ||
72c194f7 MT |
1284 | static |
1285 | void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) | |
1286 | { | |
1287 | GArray *table_offsets; | |
07fb6176 | 1288 | unsigned facs, ssdt, dsdt, rsdt; |
72c194f7 MT |
1289 | AcpiCpuInfo cpu; |
1290 | AcpiPmInfo pm; | |
1291 | AcpiMiscInfo misc; | |
1292 | AcpiMcfgInfo mcfg; | |
1293 | PcPciInfo pci; | |
1294 | uint8_t *u; | |
07fb6176 | 1295 | size_t aml_len = 0; |
7c2c1fa5 | 1296 | GArray *tables_blob = tables->table_data; |
72c194f7 MT |
1297 | |
1298 | acpi_get_cpu_info(&cpu); | |
1299 | acpi_get_pm_info(&pm); | |
1300 | acpi_get_dsdt(&misc); | |
72c194f7 MT |
1301 | acpi_get_misc_info(&misc); |
1302 | acpi_get_pci_info(&pci); | |
1303 | ||
1304 | table_offsets = g_array_new(false, true /* clear */, | |
1305 | sizeof(uint32_t)); | |
8b310fc4 | 1306 | ACPI_BUILD_DPRINTF("init ACPI tables\n"); |
72c194f7 MT |
1307 | |
1308 | bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, | |
1309 | 64 /* Ensure FACS is aligned */, | |
1310 | false /* high memory */); | |
1311 | ||
1312 | /* | |
1313 | * FACS is pointed to by FADT. | |
1314 | * We place it first since it's the only table that has alignment | |
1315 | * requirements. | |
1316 | */ | |
7c2c1fa5 IM |
1317 | facs = tables_blob->len; |
1318 | build_facs(tables_blob, tables->linker, guest_info); | |
72c194f7 MT |
1319 | |
1320 | /* DSDT is pointed to by FADT */ | |
7c2c1fa5 IM |
1321 | dsdt = tables_blob->len; |
1322 | build_dsdt(tables_blob, tables->linker, &misc); | |
72c194f7 | 1323 | |
07fb6176 PB |
1324 | /* Count the size of the DSDT and SSDT, we will need it for legacy |
1325 | * sizing of ACPI tables. | |
1326 | */ | |
7c2c1fa5 | 1327 | aml_len += tables_blob->len - dsdt; |
07fb6176 | 1328 | |
72c194f7 | 1329 | /* ACPI tables pointed to by RSDT */ |
7c2c1fa5 IM |
1330 | acpi_add_table(table_offsets, tables_blob); |
1331 | build_fadt(tables_blob, tables->linker, &pm, facs, dsdt); | |
72c194f7 | 1332 | |
7c2c1fa5 IM |
1333 | ssdt = tables_blob->len; |
1334 | acpi_add_table(table_offsets, tables_blob); | |
1335 | build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, | |
72c194f7 | 1336 | guest_info); |
7c2c1fa5 | 1337 | aml_len += tables_blob->len - ssdt; |
72c194f7 | 1338 | |
7c2c1fa5 IM |
1339 | acpi_add_table(table_offsets, tables_blob); |
1340 | build_madt(tables_blob, tables->linker, &cpu, guest_info); | |
9ac1c4c0 | 1341 | |
72c194f7 | 1342 | if (misc.has_hpet) { |
7c2c1fa5 IM |
1343 | acpi_add_table(table_offsets, tables_blob); |
1344 | build_hpet(tables_blob, tables->linker); | |
711b20b4 SB |
1345 | } |
1346 | if (misc.has_tpm) { | |
7c2c1fa5 IM |
1347 | acpi_add_table(table_offsets, tables_blob); |
1348 | build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); | |
711b20b4 | 1349 | |
7c2c1fa5 IM |
1350 | acpi_add_table(table_offsets, tables_blob); |
1351 | build_tpm_ssdt(tables_blob, tables->linker); | |
72c194f7 MT |
1352 | } |
1353 | if (guest_info->numa_nodes) { | |
7c2c1fa5 IM |
1354 | acpi_add_table(table_offsets, tables_blob); |
1355 | build_srat(tables_blob, tables->linker, guest_info); | |
72c194f7 MT |
1356 | } |
1357 | if (acpi_get_mcfg(&mcfg)) { | |
7c2c1fa5 IM |
1358 | acpi_add_table(table_offsets, tables_blob); |
1359 | build_mcfg_q35(tables_blob, tables->linker, &mcfg); | |
72c194f7 | 1360 | } |
d4eb9119 | 1361 | if (acpi_has_iommu()) { |
7c2c1fa5 IM |
1362 | acpi_add_table(table_offsets, tables_blob); |
1363 | build_dmar_q35(tables_blob, tables->linker); | |
d4eb9119 | 1364 | } |
72c194f7 MT |
1365 | |
1366 | /* Add tables supplied by user (if any) */ | |
1367 | for (u = acpi_table_first(); u; u = acpi_table_next(u)) { | |
1368 | unsigned len = acpi_table_len(u); | |
1369 | ||
7c2c1fa5 IM |
1370 | acpi_add_table(table_offsets, tables_blob); |
1371 | g_array_append_vals(tables_blob, u, len); | |
72c194f7 MT |
1372 | } |
1373 | ||
1374 | /* RSDT is pointed to by RSDP */ | |
7c2c1fa5 IM |
1375 | rsdt = tables_blob->len; |
1376 | build_rsdt(tables_blob, tables->linker, table_offsets); | |
72c194f7 MT |
1377 | |
1378 | /* RSDP is in FSEG memory, so allocate it separately */ | |
1379 | build_rsdp(tables->rsdp, tables->linker, rsdt); | |
1380 | ||
07fb6176 | 1381 | /* We'll expose it all to Guest so we want to reduce |
72c194f7 | 1382 | * chance of size changes. |
07fb6176 PB |
1383 | * |
1384 | * We used to align the tables to 4k, but of course this would | |
1385 | * too simple to be enough. 4k turned out to be too small an | |
1386 | * alignment very soon, and in fact it is almost impossible to | |
1387 | * keep the table size stable for all (max_cpus, max_memory_slots) | |
1388 | * combinations. So the table size is always 64k for pc-i440fx-2.1 | |
1389 | * and we give an error if the table grows beyond that limit. | |
1390 | * | |
1391 | * We still have the problem of migrating from "-M pc-i440fx-2.0". For | |
1392 | * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables | |
1393 | * than 2.0 and we can always pad the smaller tables with zeros. We can | |
1394 | * then use the exact size of the 2.0 tables. | |
1395 | * | |
1396 | * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. | |
72c194f7 | 1397 | */ |
07fb6176 PB |
1398 | if (guest_info->legacy_acpi_table_size) { |
1399 | /* Subtracting aml_len gives the size of fixed tables. Then add the | |
1400 | * size of the PIIX4 DSDT/SSDT in QEMU 2.0. | |
1401 | */ | |
1402 | int legacy_aml_len = | |
1403 | guest_info->legacy_acpi_table_size + | |
1404 | ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; | |
1405 | int legacy_table_size = | |
7c2c1fa5 | 1406 | ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, |
07fb6176 | 1407 | ACPI_BUILD_ALIGN_SIZE); |
7c2c1fa5 | 1408 | if (tables_blob->len > legacy_table_size) { |
07fb6176 | 1409 | /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ |
868270f2 | 1410 | error_report("Warning: migration may not work."); |
07fb6176 | 1411 | } |
7c2c1fa5 | 1412 | g_array_set_size(tables_blob, legacy_table_size); |
07fb6176 | 1413 | } else { |
868270f2 | 1414 | /* Make sure we have a buffer in case we need to resize the tables. */ |
7c2c1fa5 | 1415 | if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { |
18045fb9 | 1416 | /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ |
868270f2 MT |
1417 | error_report("Warning: ACPI tables are larger than 64k."); |
1418 | error_report("Warning: migration may not work."); | |
1419 | error_report("Warning: please remove CPUs, NUMA nodes, " | |
1420 | "memory slots or PCI bridges."); | |
18045fb9 | 1421 | } |
7c2c1fa5 | 1422 | acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); |
07fb6176 | 1423 | } |
72c194f7 | 1424 | |
07fb6176 | 1425 | acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); |
72c194f7 MT |
1426 | |
1427 | /* Cleanup memory that's no longer used. */ | |
1428 | g_array_free(table_offsets, true); | |
1429 | } | |
1430 | ||
339240b5 | 1431 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) |
42d85900 MT |
1432 | { |
1433 | uint32_t size = acpi_data_len(data); | |
1434 | ||
1435 | /* Make sure RAM size is correct - in case it got changed e.g. by migration */ | |
339240b5 | 1436 | memory_region_ram_resize(mr, size, &error_abort); |
42d85900 | 1437 | |
339240b5 PB |
1438 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); |
1439 | memory_region_set_dirty(mr, 0, size); | |
42d85900 MT |
1440 | } |
1441 | ||
72c194f7 MT |
1442 | static void acpi_build_update(void *build_opaque, uint32_t offset) |
1443 | { | |
1444 | AcpiBuildState *build_state = build_opaque; | |
1445 | AcpiBuildTables tables; | |
1446 | ||
1447 | /* No state to update or already patched? Nothing to do. */ | |
1448 | if (!build_state || build_state->patched) { | |
1449 | return; | |
1450 | } | |
1451 | build_state->patched = 1; | |
1452 | ||
1453 | acpi_build_tables_init(&tables); | |
1454 | ||
1455 | acpi_build(build_state->guest_info, &tables); | |
1456 | ||
339240b5 | 1457 | acpi_ram_update(build_state->table_mr, tables.table_data); |
a1666142 | 1458 | |
42d85900 MT |
1459 | if (build_state->rsdp) { |
1460 | memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); | |
1461 | } else { | |
339240b5 | 1462 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); |
42d85900 | 1463 | } |
ad5b88b1 | 1464 | |
339240b5 | 1465 | acpi_ram_update(build_state->linker_mr, tables.linker); |
72c194f7 MT |
1466 | acpi_build_tables_cleanup(&tables, true); |
1467 | } | |
1468 | ||
1469 | static void acpi_build_reset(void *build_opaque) | |
1470 | { | |
1471 | AcpiBuildState *build_state = build_opaque; | |
1472 | build_state->patched = 0; | |
1473 | } | |
1474 | ||
339240b5 PB |
1475 | static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, |
1476 | GArray *blob, const char *name, | |
1477 | uint64_t max_size) | |
72c194f7 | 1478 | { |
a1666142 MT |
1479 | return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, |
1480 | name, acpi_build_update, build_state); | |
72c194f7 MT |
1481 | } |
1482 | ||
1483 | static const VMStateDescription vmstate_acpi_build = { | |
1484 | .name = "acpi_build", | |
1485 | .version_id = 1, | |
1486 | .minimum_version_id = 1, | |
d49805ae | 1487 | .fields = (VMStateField[]) { |
72c194f7 MT |
1488 | VMSTATE_UINT8(patched, AcpiBuildState), |
1489 | VMSTATE_END_OF_LIST() | |
1490 | }, | |
1491 | }; | |
1492 | ||
1493 | void acpi_setup(PcGuestInfo *guest_info) | |
1494 | { | |
1495 | AcpiBuildTables tables; | |
1496 | AcpiBuildState *build_state; | |
1497 | ||
1498 | if (!guest_info->fw_cfg) { | |
8b310fc4 | 1499 | ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); |
72c194f7 MT |
1500 | return; |
1501 | } | |
1502 | ||
1503 | if (!guest_info->has_acpi_build) { | |
8b310fc4 | 1504 | ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); |
72c194f7 MT |
1505 | return; |
1506 | } | |
1507 | ||
81adc513 | 1508 | if (!acpi_enabled) { |
8b310fc4 | 1509 | ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); |
81adc513 MT |
1510 | return; |
1511 | } | |
1512 | ||
72c194f7 MT |
1513 | build_state = g_malloc0(sizeof *build_state); |
1514 | ||
1515 | build_state->guest_info = guest_info; | |
1516 | ||
99fd437d MT |
1517 | acpi_set_pci_info(); |
1518 | ||
72c194f7 MT |
1519 | acpi_build_tables_init(&tables); |
1520 | acpi_build(build_state->guest_info, &tables); | |
1521 | ||
1522 | /* Now expose it all to Guest */ | |
339240b5 | 1523 | build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, |
a1666142 MT |
1524 | ACPI_BUILD_TABLE_FILE, |
1525 | ACPI_BUILD_TABLE_MAX_SIZE); | |
339240b5 | 1526 | assert(build_state->table_mr != NULL); |
72c194f7 | 1527 | |
339240b5 | 1528 | build_state->linker_mr = |
6e00619b | 1529 | acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); |
72c194f7 | 1530 | |
42a5b308 SB |
1531 | fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, |
1532 | tables.tcpalog->data, acpi_data_len(tables.tcpalog)); | |
1533 | ||
384fb32e | 1534 | if (!guest_info->rsdp_in_ram) { |
358774d7 IM |
1535 | /* |
1536 | * Keep for compatibility with old machine types. | |
1537 | * Though RSDP is small, its contents isn't immutable, so | |
afaa2e4b | 1538 | * we'll update it along with the rest of tables on guest access. |
358774d7 | 1539 | */ |
afaa2e4b MT |
1540 | uint32_t rsdp_size = acpi_data_len(tables.rsdp); |
1541 | ||
1542 | build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); | |
358774d7 IM |
1543 | fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE, |
1544 | acpi_build_update, build_state, | |
afaa2e4b | 1545 | build_state->rsdp, rsdp_size); |
339240b5 | 1546 | build_state->rsdp_mr = NULL; |
358774d7 | 1547 | } else { |
42d85900 | 1548 | build_state->rsdp = NULL; |
339240b5 | 1549 | build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, |
42d85900 | 1550 | ACPI_BUILD_RSDP_FILE, 0); |
358774d7 | 1551 | } |
72c194f7 MT |
1552 | |
1553 | qemu_register_reset(acpi_build_reset, build_state); | |
1554 | acpi_build_reset(build_state); | |
1555 | vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); | |
1556 | ||
1557 | /* Cleanup tables but don't free the memory: we track it | |
1558 | * in build_state. | |
1559 | */ | |
1560 | acpi_build_tables_cleanup(&tables, false); | |
1561 | } |