]> git.proxmox.com Git - mirror_qemu.git/blame - hw/i386/acpi-build.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pc: acpi: SRAT: create only valid processor lapic entries
[mirror_qemu.git] / hw / i386 / acpi-build.c
CommitLineData
72c194f7
MT		 1/* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
b6a0aa05 23#include "qemu/osdep.h"
72c194f7 24#include "acpi-build.h"
72c194f7
MT		 25#include <glib.h>
26#include "qemu-common.h"
27#include "qemu/bitmap.h"
07fb6176 28#include "qemu/error-report.h"
72c194f7
MT		 29#include "hw/pci/pci.h"
30#include "qom/cpu.h"
31#include "hw/i386/pc.h"
32#include "target-i386/cpu.h"
33#include "hw/timer/hpet.h"
395e5fb4 34#include "hw/acpi/acpi-defs.h"
72c194f7
MT		 35#include "hw/acpi/acpi.h"
36#include "hw/nvram/fw_cfg.h"
0058ae1d 37#include "hw/acpi/bios-linker-loader.h"
72c194f7 38#include "hw/loader.h"
15bce1b7 39#include "hw/isa/isa.h"
27b9fc54 40#include "hw/block/fdc.h"
bef3492d 41#include "hw/acpi/memory_hotplug.h"
711b20b4
SB		 42#include "sysemu/tpm.h"
43#include "hw/acpi/tpm.h"
5cb18b3d 44#include "sysemu/tpm_backend.h"
f070efa8 45#include "hw/timer/mc146818rtc_regs.h"
72c194f7
MT		 46
47/* Supported chipsets: */
48#include "hw/acpi/piix4.h"
99fd437d 49#include "hw/acpi/pcihp.h"
72c194f7
MT		 50#include "hw/i386/ich9.h"
51#include "hw/pci/pci_bus.h"
52#include "hw/pci-host/q35.h"
d4eb9119 53#include "hw/i386/intel_iommu.h"
a57d708d 54#include "hw/timer/hpet.h"
72c194f7 55
19934e0e
IM		 56#include "hw/acpi/aml-build.h"
57
72c194f7
MT		 58#include "qapi/qmp/qint.h"
59#include "qom/qom-qobject.h"
60
07fb6176
PB		 61/* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
62 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
63 * a little bit, there should be plenty of free space since the DSDT
64 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
65 */
66#define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
67#define ACPI_BUILD_ALIGN_SIZE 0x1000
68
868270f2 69#define ACPI_BUILD_TABLE_SIZE 0x20000
18045fb9 70
8b310fc4
GA		 71/* #define DEBUG_ACPI_BUILD */
72#ifdef DEBUG_ACPI_BUILD
73#define ACPI_BUILD_DPRINTF(fmt, ...) \
74 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
75#else
76#define ACPI_BUILD_DPRINTF(fmt, ...)
77#endif
78
72c194f7 79typedef struct AcpiCpuInfo {
798325ed 80 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
72c194f7
MT		 81} AcpiCpuInfo;
82
83typedef struct AcpiMcfgInfo {
84 uint64_t mcfg_base;
85 uint32_t mcfg_size;
86} AcpiMcfgInfo;
87
88typedef struct AcpiPmInfo {
89 bool s3_disabled;
90 bool s4_disabled;
133a2da4 91 bool pcihp_bridge_en;
72c194f7
MT		 92 uint8_t s4_val;
93 uint16_t sci_int;
94 uint8_t acpi_enable_cmd;
95 uint8_t acpi_disable_cmd;
96 uint32_t gpe0_blk;
97 uint32_t gpe0_blk_len;
98 uint32_t io_base;
ddf1ec2f
IM		 99 uint16_t cpu_hp_io_base;
100 uint16_t cpu_hp_io_len;
2c6b94d8
IM		 101 uint16_t mem_hp_io_base;
102 uint16_t mem_hp_io_len;
500b11ea
IM		 103 uint16_t pcihp_io_base;
104 uint16_t pcihp_io_len;
72c194f7
MT		 105} AcpiPmInfo;
106
107typedef struct AcpiMiscInfo {
e4db2798 108 bool is_piix4;
72c194f7 109 bool has_hpet;
5cb18b3d 110 TPMVersion tpm_version;
72c194f7
MT		 111 const unsigned char *dsdt_code;
112 unsigned dsdt_size;
113 uint16_t pvpanic_port;
8ac6f7a6 114 uint16_t applesmc_io_base;
72c194f7
MT		 115} AcpiMiscInfo;
116
99fd437d
MT		 117typedef struct AcpiBuildPciBusHotplugState {
118 GArray *device_table;
119 GArray *notify_table;
120 struct AcpiBuildPciBusHotplugState *parent;
133a2da4 121 bool pcihp_bridge_en;
99fd437d
MT		 122} AcpiBuildPciBusHotplugState;
123
72c194f7
MT		 124static
125int acpi_add_cpu_info(Object *o, void *opaque)
126{
127 AcpiCpuInfo *cpu = opaque;
128 uint64_t apic_id;
129
130 if (object_dynamic_cast(o, TYPE_CPU)) {
131 apic_id = object_property_get_int(o, "apic-id", NULL);
798325ed 132 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
72c194f7
MT		 133
134 set_bit(apic_id, cpu->found_cpus);
135 }
136
137 object_child_foreach(o, acpi_add_cpu_info, opaque);
138 return 0;
139}
140
141static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
142{
143 Object *root = object_get_root();
144
145 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
146 object_child_foreach(root, acpi_add_cpu_info, cpu);
147}
148
149static void acpi_get_pm_info(AcpiPmInfo *pm)
150{
151 Object *piix = piix4_pm_find();
152 Object *lpc = ich9_lpc_find();
153 Object *obj = NULL;
154 QObject *o;
155
94aaca64 156 pm->cpu_hp_io_base = 0;
500b11ea
IM		 157 pm->pcihp_io_base = 0;
158 pm->pcihp_io_len = 0;
72c194f7
MT		 159 if (piix) {
160 obj = piix;
ddf1ec2f 161 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
500b11ea
IM		 162 pm->pcihp_io_base =
163 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
164 pm->pcihp_io_len =
165 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
72c194f7
MT		 166 }
167 if (lpc) {
168 obj = lpc;
ddf1ec2f 169 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
72c194f7
MT		 170 }
171 assert(obj);
172
ddf1ec2f 173 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
2c6b94d8
IM		 174 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
175 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
176
72c194f7
MT		 177 /* Fill in optional s3/s4 related properties */
178 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
179 if (o) {
180 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
181 } else {
182 pm->s3_disabled = false;
183 }
097a97a6 184 qobject_decref(o);
72c194f7
MT		 185 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
186 if (o) {
187 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
188 } else {
189 pm->s4_disabled = false;
190 }
097a97a6 191 qobject_decref(o);
72c194f7
MT		 192 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
193 if (o) {
194 pm->s4_val = qint_get_int(qobject_to_qint(o));
195 } else {
196 pm->s4_val = false;
197 }
097a97a6 198 qobject_decref(o);
72c194f7
MT		 199
200 /* Fill in mandatory properties */
201 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
202
203 pm->acpi_enable_cmd = object_property_get_int(obj,
204 ACPI_PM_PROP_ACPI_ENABLE_CMD,
205 NULL);
206 pm->acpi_disable_cmd = object_property_get_int(obj,
207 ACPI_PM_PROP_ACPI_DISABLE_CMD,
208 NULL);
209 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
210 NULL);
211 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
212 NULL);
213 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
214 NULL);
133a2da4
IM		 215 pm->pcihp_bridge_en =
216 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
217 NULL);
72c194f7
MT		 218}
219
72c194f7
MT		 220static void acpi_get_misc_info(AcpiMiscInfo *info)
221{
3db119da
IM		 222 Object *piix = piix4_pm_find();
223 Object *lpc = ich9_lpc_find();
224 assert(!!piix != !!lpc);
225
226 if (piix) {
227 info->is_piix4 = true;
228 }
229 if (lpc) {
230 info->is_piix4 = false;
231 }
232
72c194f7 233 info->has_hpet = hpet_find();
5cb18b3d 234 info->tpm_version = tpm_get_version();
72c194f7 235 info->pvpanic_port = pvpanic_port();
8ac6f7a6 236 info->applesmc_io_base = applesmc_port();
72c194f7
MT		 237}
238
ca6c1855
MA		 239/*
240 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
241 * On i386 arch we only have two pci hosts, so we can look only for them.
242 */
243static Object *acpi_get_i386_pci_host(void)
244{
245 PCIHostState *host;
246
247 host = OBJECT_CHECK(PCIHostState,
248 object_resolve_path("/machine/i440fx", NULL),
249 TYPE_PCI_HOST_BRIDGE);
250 if (!host) {
251 host = OBJECT_CHECK(PCIHostState,
252 object_resolve_path("/machine/q35", NULL),
253 TYPE_PCI_HOST_BRIDGE);
254 }
255
256 return OBJECT(host);
257}
258
72c194f7
MT		 259static void acpi_get_pci_info(PcPciInfo *info)
260{
261 Object *pci_host;
72c194f7 262
ca6c1855
MA		 263
264 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 265 g_assert(pci_host);
266
267 info->w32.begin = object_property_get_int(pci_host,
268 PCI_HOST_PROP_PCI_HOLE_START,
269 NULL);
270 info->w32.end = object_property_get_int(pci_host,
271 PCI_HOST_PROP_PCI_HOLE_END,
272 NULL);
273 info->w64.begin = object_property_get_int(pci_host,
274 PCI_HOST_PROP_PCI_HOLE64_START,
275 NULL);
276 info->w64.end = object_property_get_int(pci_host,
277 PCI_HOST_PROP_PCI_HOLE64_END,
278 NULL);
279}
280
72c194f7
MT		 281#define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
282
72c194f7
MT		 283static void acpi_align_size(GArray *blob, unsigned align)
284{
285 /* Align size to multiple of given size. This reduces the chance
286 * we need to change size in the future (breaking cross version migration).
287 */
134d42d6 288 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
72c194f7
MT		 289}
290
72c194f7
MT		 291/* FACS */
292static void
fb306ffe 293build_facs(GArray *table_data, GArray *linker)
72c194f7
MT		 294{
295 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
821e3227 296 memcpy(&facs->signature, "FACS", 4);
72c194f7
MT		 297 facs->length = cpu_to_le32(sizeof(*facs));
298}
299
300/* Load chipset information in FADT */
301static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
302{
303 fadt->model = 1;
304 fadt->reserved1 = 0;
305 fadt->sci_int = cpu_to_le16(pm->sci_int);
306 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
307 fadt->acpi_enable = pm->acpi_enable_cmd;
308 fadt->acpi_disable = pm->acpi_disable_cmd;
309 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
310 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
311 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
312 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
313 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
314 /* EVT, CNT, TMR length matches hw/acpi/core.c */
315 fadt->pm1_evt_len = 4;
316 fadt->pm1_cnt_len = 2;
317 fadt->pm_tmr_len = 4;
318 fadt->gpe0_blk_len = pm->gpe0_blk_len;
319 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
320 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
321 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
322 (1 << ACPI_FADT_F_PROC_C1) |
323 (1 << ACPI_FADT_F_SLP_BUTTON) |
324 (1 << ACPI_FADT_F_RTC_S4));
325 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
07b81ed9
HZ		 326 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
327 * For more than 8 CPUs, "Clustered Logical" mode has to be used
328 */
329 if (max_cpus > 8) {
330 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
331 }
f070efa8 332 fadt->century = RTC_CENTURY;
72c194f7
MT		 333}
334
335
336/* FADT */
337static void
338build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
ae123749
LE		 339 unsigned facs, unsigned dsdt,
340 const char *oem_id, const char *oem_table_id)
72c194f7
MT		 341{
342 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
343
344 fadt->firmware_ctrl = cpu_to_le32(facs);
345 /* FACS address to be filled by Guest linker */
346 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
347 ACPI_BUILD_TABLE_FILE,
348 table_data, &fadt->firmware_ctrl,
349 sizeof fadt->firmware_ctrl);
350
351 fadt->dsdt = cpu_to_le32(dsdt);
352 /* DSDT address to be filled by Guest linker */
353 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
354 ACPI_BUILD_TABLE_FILE,
355 table_data, &fadt->dsdt,
356 sizeof fadt->dsdt);
357
358 fadt_setup(fadt, pm);
359
360 build_header(linker, table_data,
ae123749 361 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
72c194f7
MT		 362}
363
364static void
3d3ebcad
IM		 365build_madt(GArray *table_data, GArray *linker, PCMachineState *pcms,
366 AcpiCpuInfo *cpu)
72c194f7
MT		 367{
368 int madt_start = table_data->len;
369
370 AcpiMultipleApicTable *madt;
371 AcpiMadtIoApic *io_apic;
372 AcpiMadtIntsrcovr *intsrcovr;
373 AcpiMadtLocalNmi *local_nmi;
374 int i;
375
376 madt = acpi_data_push(table_data, sizeof *madt);
377 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
378 madt->flags = cpu_to_le32(1);
379
dd4c2f01 380 for (i = 0; i < pcms->apic_id_limit; i++) {
72c194f7
MT		 381 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
382 apic->type = ACPI_APIC_PROCESSOR;
383 apic->length = sizeof(*apic);
384 apic->processor_id = i;
385 apic->local_apic_id = i;
386 if (test_bit(i, cpu->found_cpus)) {
387 apic->flags = cpu_to_le32(1);
388 } else {
389 apic->flags = cpu_to_le32(0);
390 }
391 }
392 io_apic = acpi_data_push(table_data, sizeof *io_apic);
393 io_apic->type = ACPI_APIC_IO;
394 io_apic->length = sizeof(*io_apic);
395#define ACPI_BUILD_IOAPIC_ID 0x0
396 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
397 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
398 io_apic->interrupt = cpu_to_le32(0);
399
dd4c2f01 400 if (pcms->apic_xrupt_override) {
72c194f7
MT		 401 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
402 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
403 intsrcovr->length = sizeof(*intsrcovr);
404 intsrcovr->source = 0;
405 intsrcovr->gsi = cpu_to_le32(2);
406 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
407 }
408 for (i = 1; i < 16; i++) {
409#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
410 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
411 /* No need for a INT source override structure. */
412 continue;
413 }
414 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
415 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
416 intsrcovr->length = sizeof(*intsrcovr);
417 intsrcovr->source = i;
418 intsrcovr->gsi = cpu_to_le32(i);
419 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
420 }
421
422 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
423 local_nmi->type = ACPI_APIC_LOCAL_NMI;
424 local_nmi->length = sizeof(*local_nmi);
425 local_nmi->processor_id = 0xff; /* all processors */
426 local_nmi->flags = cpu_to_le16(0);
427 local_nmi->lint = 1; /* ACPI_LINT1 */
428
429 build_header(linker, table_data,
821e3227 430 (void *)(table_data->data + madt_start), "APIC",
37ad223c 431 table_data->len - madt_start, 1, NULL, NULL);
72c194f7
MT		 432}
433
99fd437d
MT		 434/* Assign BSEL property to all buses. In the future, this can be changed
435 * to only assign to buses that support hotplug.
436 */
437static void *acpi_set_bsel(PCIBus *bus, void *opaque)
438{
439 unsigned *bsel_alloc = opaque;
440 unsigned *bus_bsel;
441
39b888bd 442 if (qbus_is_hotpluggable(BUS(bus))) {
99fd437d
MT		 443 bus_bsel = g_malloc(sizeof *bus_bsel);
444
445 *bus_bsel = (*bsel_alloc)++;
446 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
447 bus_bsel, NULL);
448 }
449
450 return bsel_alloc;
451}
452
453static void acpi_set_pci_info(void)
454{
455 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
456 unsigned bsel_alloc = 0;
457
458 if (bus) {
459 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
460 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
461 }
462}
463
62b52c26 464static void build_append_pcihp_notify_entry(Aml *method, int slot)
99fd437d 465{
62b52c26
IM		 466 Aml *if_ctx;
467 int32_t devfn = PCI_DEVFN(slot, 0);
468
5530427f 469 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
62b52c26
IM		 470 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
471 aml_append(method, if_ctx);
99fd437d
MT		 472}
473
62b52c26 474static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
b23046ab 475 bool pcihp_bridge_en)
99fd437d 476{
62b52c26 477 Aml *dev, *notify_method, *method;
99fd437d 478 QObject *bsel;
b23046ab
IM		 479 PCIBus *sec;
480 int i;
133a2da4 481
99fd437d
MT		 482 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
483 if (bsel) {
62b52c26
IM		 484 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
485
486 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
4dbfc881 487 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
8dcf525a 488 }
99fd437d 489
8dcf525a
MT		 490 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
491 DeviceClass *dc;
492 PCIDeviceClass *pc;
493 PCIDevice *pdev = bus->devices[i];
494 int slot = PCI_SLOT(i);
b23046ab 495 bool hotplug_enabled_dev;
093a35e5 496 bool bridge_in_acpi;
99fd437d 497
8dcf525a 498 if (!pdev) {
b23046ab 499 if (bsel) { /* add hotplug slots for non present devices */
62b52c26
IM		 500 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
501 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
502 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
4dbfc881 503 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 504 aml_append(method,
505 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
506 );
507 aml_append(dev, method);
508 aml_append(parent_scope, dev);
509
510 build_append_pcihp_notify_entry(notify_method, slot);
b23046ab 511 }
8dcf525a
MT		 512 continue;
513 }
99fd437d 514
8dcf525a
MT		 515 pc = PCI_DEVICE_GET_CLASS(pdev);
516 dc = DEVICE_GET_CLASS(pdev);
99fd437d 517
093a35e5
MT		 518 /* When hotplug for bridges is enabled, bridges are
519 * described in ACPI separately (see build_pci_bus_end).
520 * In this case they aren't themselves hot-pluggable.
a20275fa 521 * Hotplugged bridges *are* hot-pluggable.
093a35e5 522 */
b23046ab
IM		 523 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
524 !DEVICE(pdev)->hotplugged;
525
526 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
093a35e5 527
b23046ab
IM		 528 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
529 continue;
99fd437d
MT		 530 }
531
62b52c26
IM		 532 /* start to compose PCI slot descriptor */
533 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
534 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
535
8dcf525a 536 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
62b52c26
IM		 537 /* add VGA specific AML methods */
538 int s3d;
539
8dcf525a 540 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
62b52c26 541 s3d = 3;
b23046ab 542 } else {
62b52c26 543 s3d = 0;
99fd437d 544 }
62b52c26 545
4dbfc881 546 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 547 aml_append(method, aml_return(aml_int(0)));
548 aml_append(dev, method);
549
4dbfc881 550 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 551 aml_append(method, aml_return(aml_int(0)));
552 aml_append(dev, method);
553
4dbfc881 554 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 555 aml_append(method, aml_return(aml_int(s3d)));
556 aml_append(dev, method);
b23046ab 557 } else if (hotplug_enabled_dev) {
62b52c26
IM		 558 /* add _SUN/_EJ0 to make slot hotpluggable */
559 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
99fd437d 560
4dbfc881 561 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 562 aml_append(method,
563 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
564 );
565 aml_append(dev, method);
566
567 if (bsel) {
568 build_append_pcihp_notify_entry(notify_method, slot);
569 }
b23046ab 570 } else if (bridge_in_acpi) {
62b52c26
IM		 571 /*
572 * device is coldplugged bridge,
573 * add child device descriptions into its scope
574 */
b23046ab 575 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
b23046ab 576
62b52c26 577 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
8dcf525a 578 }
62b52c26
IM		 579 /* slot descriptor has been composed, add it into parent context */
580 aml_append(parent_scope, dev);
8dcf525a
MT		 581 }
582
583 if (bsel) {
62b52c26 584 aml_append(parent_scope, notify_method);
99fd437d
MT		 585 }
586
587 /* Append PCNT method to notify about events on local and child buses.
588 * Add unconditionally for root since DSDT expects it.
72c194f7 589 */
4dbfc881 590 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
99fd437d 591
b23046ab
IM		 592 /* If bus supports hotplug select it and notify about local events */
593 if (bsel) {
62b52c26
IM		 594 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
595 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
596 aml_append(method,
597 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
598 );
599 aml_append(method,
600 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
601 );
b23046ab 602 }
99fd437d 603
b23046ab
IM		 604 /* Notify about child bus events in any case */
605 if (pcihp_bridge_en) {
606 QLIST_FOREACH(sec, &bus->child, sibling) {
62b52c26
IM		 607 int32_t devfn = sec->parent_dev->devfn;
608
609 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
99fd437d 610 }
72c194f7 611 }
62b52c26 612 aml_append(parent_scope, method);
d370dfa9 613 qobject_decref(bsel);
72c194f7
MT		 614}
615
196e2137
IM		 616/**
617 * build_prt_entry:
618 * @link_name: link name for PCI route entry
619 *
620 * build AML package containing a PCI route entry for @link_name
621 */
622static Aml *build_prt_entry(const char *link_name)
623{
624 Aml *a_zero = aml_int(0);
625 Aml *pkg = aml_package(4);
626 aml_append(pkg, a_zero);
627 aml_append(pkg, a_zero);
628 aml_append(pkg, aml_name("%s", link_name));
629 aml_append(pkg, a_zero);
630 return pkg;
631}
632
0d8935e3
MA		 633/*
634 * initialize_route - Initialize the interrupt routing rule
635 * through a specific LINK:
636 * if (lnk_idx == idx)
637 * route using link 'link_name'
638 */
639static Aml *initialize_route(Aml *route, const char *link_name,
640 Aml *lnk_idx, int idx)
641{
642 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
196e2137 643 Aml *pkg = build_prt_entry(link_name);
0d8935e3 644
0d8935e3
MA		 645 aml_append(if_ctx, aml_store(pkg, route));
646
647 return if_ctx;
648}
649
650/*
651 * build_prt - Define interrupt rounting rules
652 *
653 * Returns an array of 128 routes, one for each device,
654 * based on device location.
655 * The main goal is to equaly distribute the interrupts
656 * over the 4 existing ACPI links (works only for i440fx).
657 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
658 *
659 */
196e2137 660static Aml *build_prt(bool is_pci0_prt)
0d8935e3
MA		 661{
662 Aml *method, *while_ctx, *pin, *res;
663
4dbfc881 664 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
0d8935e3
MA		 665 res = aml_local(0);
666 pin = aml_local(1);
667 aml_append(method, aml_store(aml_package(128), res));
668 aml_append(method, aml_store(aml_int(0), pin));
669
670 /* while (pin < 128) */
671 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
672 {
673 Aml *slot = aml_local(2);
674 Aml *lnk_idx = aml_local(3);
675 Aml *route = aml_local(4);
676
677 /* slot = pin >> 2 */
678 aml_append(while_ctx,
c360639a 679 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
0d8935e3
MA		 680 /* lnk_idx = (slot + pin) & 3 */
681 aml_append(while_ctx,
5530427f
IM		 682 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
683 lnk_idx));
0d8935e3
MA		 684
685 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
686 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
196e2137
IM		 687 if (is_pci0_prt) {
688 Aml *if_device_1, *if_pin_4, *else_pin_4;
689
690 /* device 1 is the power-management device, needs SCI */
691 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
692 {
693 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
694 {
695 aml_append(if_pin_4,
696 aml_store(build_prt_entry("LNKS"), route));
697 }
698 aml_append(if_device_1, if_pin_4);
699 else_pin_4 = aml_else();
700 {
701 aml_append(else_pin_4,
702 aml_store(build_prt_entry("LNKA"), route));
703 }
704 aml_append(if_device_1, else_pin_4);
705 }
706 aml_append(while_ctx, if_device_1);
707 } else {
708 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
709 }
0d8935e3
MA		 710 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
711 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
712
713 /* route[0] = 0x[slot]FFFF */
714 aml_append(while_ctx,
ca3df95d
IM		 715 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
716 NULL),
0d8935e3
MA		 717 aml_index(route, aml_int(0))));
718 /* route[1] = pin & 3 */
719 aml_append(while_ctx,
5530427f
IM		 720 aml_store(aml_and(pin, aml_int(3), NULL),
721 aml_index(route, aml_int(1))));
0d8935e3
MA		 722 /* res[pin] = route */
723 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
724 /* pin++ */
725 aml_append(while_ctx, aml_increment(pin));
726 }
727 aml_append(method, while_ctx);
728 /* return res*/
729 aml_append(method, aml_return(res));
730
731 return method;
732}
733
a43c6e27
MA		 734typedef struct CrsRangeEntry {
735 uint64_t base;
736 uint64_t limit;
737} CrsRangeEntry;
738
739static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
740{
741 CrsRangeEntry *entry;
742
743 entry = g_malloc(sizeof(*entry));
744 entry->base = base;
745 entry->limit = limit;
746
747 g_ptr_array_add(ranges, entry);
748}
749
750static void crs_range_free(gpointer data)
751{
752 CrsRangeEntry *entry = (CrsRangeEntry *)data;
753 g_free(entry);
754}
755
dcdca296
MA		 756static gint crs_range_compare(gconstpointer a, gconstpointer b)
757{
758 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
759 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
760
761 return (int64_t)entry_a->base - (int64_t)entry_b->base;
762}
763
764/*
765 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
766 * interval, computes the 'free' ranges from the same interval.
767 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
768 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
769 */
770static void crs_replace_with_free_ranges(GPtrArray *ranges,
771 uint64_t start, uint64_t end)
772{
773 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
774 uint64_t free_base = start;
775 int i;
776
777 g_ptr_array_sort(ranges, crs_range_compare);
778 for (i = 0; i < ranges->len; i++) {
779 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
780
781 if (free_base < used->base) {
782 crs_range_insert(free_ranges, free_base, used->base - 1);
783 }
784
785 free_base = used->limit + 1;
786 }
787
788 if (free_base < end) {
789 crs_range_insert(free_ranges, free_base, end);
790 }
791
792 g_ptr_array_set_size(ranges, 0);
793 for (i = 0; i < free_ranges->len; i++) {
794 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
795 }
796
797 g_ptr_array_free(free_ranges, false);
798}
799
d7fd0e69
MA		 800/*
801 * crs_range_merge - merges adjacent ranges in the given array.
802 * Array elements are deleted and replaced with the merged ranges.
803 */
804static void crs_range_merge(GPtrArray *range)
805{
806 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
807 CrsRangeEntry *entry;
808 uint64_t range_base, range_limit;
809 int i;
810
811 if (!range->len) {
812 return;
813 }
814
815 g_ptr_array_sort(range, crs_range_compare);
816
817 entry = g_ptr_array_index(range, 0);
818 range_base = entry->base;
819 range_limit = entry->limit;
820 for (i = 1; i < range->len; i++) {
821 entry = g_ptr_array_index(range, i);
822 if (entry->base - 1 == range_limit) {
823 range_limit = entry->limit;
824 } else {
825 crs_range_insert(tmp, range_base, range_limit);
826 range_base = entry->base;
827 range_limit = entry->limit;
828 }
829 }
830 crs_range_insert(tmp, range_base, range_limit);
831
832 g_ptr_array_set_size(range, 0);
833 for (i = 0; i < tmp->len; i++) {
834 entry = g_ptr_array_index(tmp, i);
835 crs_range_insert(range, entry->base, entry->limit);
836 }
837 g_ptr_array_free(tmp, true);
838}
839
a43c6e27
MA		 840static Aml *build_crs(PCIHostState *host,
841 GPtrArray *io_ranges, GPtrArray *mem_ranges)
842{
843 Aml *crs = aml_resource_template();
d7fd0e69
MA		 844 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
845 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
846 CrsRangeEntry *entry;
a43c6e27
MA		 847 uint8_t max_bus = pci_bus_num(host->bus);
848 uint8_t type;
849 int devfn;
d7fd0e69 850 int i;
a43c6e27
MA		 851
852 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
a43c6e27
MA		 853 uint64_t range_base, range_limit;
854 PCIDevice *dev = host->bus->devices[devfn];
855
856 if (!dev) {
857 continue;
858 }
859
860 for (i = 0; i < PCI_NUM_REGIONS; i++) {
861 PCIIORegion *r = &dev->io_regions[i];
862
863 range_base = r->addr;
864 range_limit = r->addr + r->size - 1;
865
0f6dd8e1
MA		 866 /*
867 * Work-around for old bioses
868 * that do not support multiple root buses
869 */
870 if (!range_base || range_base > range_limit) {
871 continue;
872 }
873
a43c6e27 874 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
d7fd0e69 875 crs_range_insert(host_io_ranges, range_base, range_limit);
a43c6e27 876 } else { /* "memory" */
d7fd0e69 877 crs_range_insert(host_mem_ranges, range_base, range_limit);
a43c6e27
MA		 878 }
879 }
880
881 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
882 if (type == PCI_HEADER_TYPE_BRIDGE) {
883 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
884 if (subordinate > max_bus) {
885 max_bus = subordinate;
886 }
887
888 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
889 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
0f6dd8e1
MA		 890
891 /*
892 * Work-around for old bioses
893 * that do not support multiple root buses
894 */
4ebc736e 895 if (range_base && range_base <= range_limit) {
d7fd0e69 896 crs_range_insert(host_io_ranges, range_base, range_limit);
0f6dd8e1 897 }
a43c6e27
MA		 898
899 range_base =
900 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
901 range_limit =
902 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
0f6dd8e1
MA		 903
904 /*
905 * Work-around for old bioses
906 * that do not support multiple root buses
907 */
4ebc736e 908 if (range_base && range_base <= range_limit) {
d7fd0e69 909 crs_range_insert(host_mem_ranges, range_base, range_limit);
4ebc736e 910 }
a43c6e27
MA		 911
912 range_base =
913 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
914 range_limit =
915 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
0f6dd8e1
MA		 916
917 /*
918 * Work-around for old bioses
919 * that do not support multiple root buses
920 */
4ebc736e 921 if (range_base && range_base <= range_limit) {
d7fd0e69 922 crs_range_insert(host_mem_ranges, range_base, range_limit);
0f6dd8e1 923 }
a43c6e27
MA		 924 }
925 }
926
d7fd0e69
MA		 927 crs_range_merge(host_io_ranges);
928 for (i = 0; i < host_io_ranges->len; i++) {
929 entry = g_ptr_array_index(host_io_ranges, i);
930 aml_append(crs,
931 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
932 AML_POS_DECODE, AML_ENTIRE_RANGE,
933 0, entry->base, entry->limit, 0,
934 entry->limit - entry->base + 1));
935 crs_range_insert(io_ranges, entry->base, entry->limit);
936 }
937 g_ptr_array_free(host_io_ranges, true);
938
939 crs_range_merge(host_mem_ranges);
940 for (i = 0; i < host_mem_ranges->len; i++) {
941 entry = g_ptr_array_index(host_mem_ranges, i);
942 aml_append(crs,
943 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
944 AML_MAX_FIXED, AML_NON_CACHEABLE,
945 AML_READ_WRITE,
946 0, entry->base, entry->limit, 0,
947 entry->limit - entry->base + 1));
948 crs_range_insert(mem_ranges, entry->base, entry->limit);
949 }
950 g_ptr_array_free(host_mem_ranges, true);
951
a43c6e27 952 aml_append(crs,
dcdca296 953 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
a43c6e27
MA		 954 0,
955 pci_bus_num(host->bus),
956 max_bus,
957 0,
958 max_bus - pci_bus_num(host->bus) + 1));
959
960 return crs;
961}
962
5ca5efa4
IM		 963static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus,
964 AcpiCpuInfo *cpu, AcpiPmInfo *pm)
965{
966 int i;
967 Aml *dev;
968 Aml *crs;
969 Aml *pkg;
970 Aml *field;
971 Aml *ifctx;
972 Aml *method;
973
974 /* The current AML generator can cover the APIC ID range [0..255],
975 * inclusive, for VCPU hotplug. */
976 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
977 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
978
979 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
980 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
981 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
982 aml_append(dev,
983 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
984 );
985 /* device present, functioning, decoding, not shown in UI */
986 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
987 crs = aml_resource_template();
988 aml_append(crs,
989 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
990 pm->cpu_hp_io_len)
991 );
992 aml_append(dev, aml_name_decl("_CRS", crs));
993 aml_append(sb_scope, dev);
994 /* declare CPU hotplug MMIO region and PRS field to access it */
995 aml_append(sb_scope, aml_operation_region(
3f3009c0 996 "PRST", AML_SYSTEM_IO, aml_int(pm->cpu_hp_io_base), pm->cpu_hp_io_len));
5ca5efa4
IM		 997 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
998 aml_append(field, aml_named_field("PRS", 256));
999 aml_append(sb_scope, field);
1000
1001 /* build Processor object for each processor */
1002 for (i = 0; i < acpi_cpus; i++) {
1003 dev = aml_processor(i, 0, 0, "CP%.02X", i);
1004
1005 method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
1006 aml_append(method,
1007 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i))));
1008 aml_append(dev, method);
1009
1010 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1011 aml_append(method,
1012 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i))));
1013 aml_append(dev, method);
1014
1015 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1016 aml_append(method,
1017 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0)))
1018 );
1019 aml_append(dev, method);
1020
1021 aml_append(sb_scope, dev);
1022 }
1023
1024 /* build this code:
1025 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1026 */
1027 /* Arg0 = Processor ID = APIC ID */
1028 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1029 for (i = 0; i < acpi_cpus; i++) {
1030 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1031 aml_append(ifctx,
1032 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1033 );
1034 aml_append(method, ifctx);
1035 }
1036 aml_append(sb_scope, method);
1037
1038 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1039 *
1040 * Note: The ability to create variable-sized packages was first
1041 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1042 * ith up to 255 elements. Windows guests up to win2k8 fail when
1043 * VarPackageOp is used.
1044 */
1045 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1046 aml_varpackage(acpi_cpus);
1047
1048 for (i = 0; i < acpi_cpus; i++) {
1049 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1050 aml_append(pkg, aml_int(b));
1051 }
1052 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg));
1053}
1054
f177d40a
IM		 1055static void build_memory_devices(Aml *sb_scope, int nr_mem,
1056 uint16_t io_base, uint16_t io_len)
1057{
1058 int i;
1059 Aml *scope;
1060 Aml *crs;
1061 Aml *field;
1062 Aml *dev;
1063 Aml *method;
1064 Aml *ifctx;
1065
1066 /* build memory devices */
1067 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
f84548dd 1068 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
f177d40a 1069 aml_append(scope,
f84548dd 1070 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
f177d40a
IM		 1071 );
1072
1073 crs = aml_resource_template();
1074 aml_append(crs,
1075 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
1076 );
1077 aml_append(scope, aml_name_decl("_CRS", crs));
1078
1079 aml_append(scope, aml_operation_region(
f84548dd 1080 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
3f3009c0 1081 aml_int(io_base), io_len)
f177d40a
IM		 1082 );
1083
f84548dd 1084 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
f177d40a
IM		 1085 AML_NOLOCK, AML_PRESERVE);
1086 aml_append(field, /* read only */
f84548dd 1087 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
f177d40a 1088 aml_append(field, /* read only */
f84548dd 1089 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
f177d40a 1090 aml_append(field, /* read only */
f84548dd 1091 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
f177d40a 1092 aml_append(field, /* read only */
f84548dd 1093 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
f177d40a 1094 aml_append(field, /* read only */
f84548dd 1095 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
f177d40a
IM		 1096 aml_append(scope, field);
1097
f84548dd 1098 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
f177d40a
IM		 1099 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1100 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1101 aml_append(field, /* 1 if enabled, read only */
f84548dd 1102 aml_named_field(MEMORY_SLOT_ENABLED, 1));
f177d40a
IM		 1103 aml_append(field,
1104 /*(read) 1 if has a insert event. (write) 1 to clear event */
f84548dd 1105 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
f177d40a
IM		 1106 aml_append(field,
1107 /* (read) 1 if has a remove event. (write) 1 to clear event */
f84548dd 1108 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
f177d40a
IM		 1109 aml_append(field,
1110 /* initiates device eject, write only */
f84548dd 1111 aml_named_field(MEMORY_SLOT_EJECT, 1));
f177d40a
IM		 1112 aml_append(scope, field);
1113
f84548dd 1114 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
f177d40a
IM		 1115 AML_NOLOCK, AML_PRESERVE);
1116 aml_append(field, /* DIMM selector, write only */
f84548dd 1117 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
f177d40a 1118 aml_append(field, /* _OST event code, write only */
f84548dd 1119 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
f177d40a 1120 aml_append(field, /* _OST status code, write only */
f84548dd 1121 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
f177d40a
IM		 1122 aml_append(scope, field);
1123 aml_append(sb_scope, scope);
1124
1125 for (i = 0; i < nr_mem; i++) {
f84548dd 1126 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
f177d40a
IM		 1127 const char *s;
1128
1129 dev = aml_device("MP%02X", i);
1130 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1131 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1132
1133 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
f84548dd 1134 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
f177d40a
IM		 1135 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1136 aml_append(dev, method);
1137
1138 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
f84548dd 1139 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
f177d40a
IM		 1140 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1141 aml_append(dev, method);
1142
1143 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
f84548dd 1144 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
f177d40a
IM		 1145 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1146 aml_append(dev, method);
1147
1148 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
f84548dd
IM		 1149 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1150
f177d40a
IM		 1151 aml_append(method, aml_return(aml_call4(
1152 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1153 )));
1154 aml_append(dev, method);
1155
1156 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
f84548dd 1157 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
f177d40a
IM		 1158 aml_append(method, aml_return(aml_call2(
1159 s, aml_name("_UID"), aml_arg(0))));
1160 aml_append(dev, method);
1161
1162 aml_append(sb_scope, dev);
1163 }
1164
1165 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1166 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1167 */
f84548dd 1168 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
f177d40a
IM		 1169 for (i = 0; i < nr_mem; i++) {
1170 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1171 aml_append(ifctx,
1172 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1173 );
1174 aml_append(method, ifctx);
1175 }
1176 aml_append(sb_scope, method);
1177}
1178
a57d708d
IM		 1179static void build_hpet_aml(Aml *table)
1180{
1181 Aml *crs;
1182 Aml *field;
1183 Aml *method;
1184 Aml *if_ctx;
1185 Aml *scope = aml_scope("_SB");
1186 Aml *dev = aml_device("HPET");
1187 Aml *zero = aml_int(0);
1188 Aml *id = aml_local(0);
1189 Aml *period = aml_local(1);
1190
1191 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1192 aml_append(dev, aml_name_decl("_UID", zero));
1193
1194 aml_append(dev,
3f3009c0
XG		 1195 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1196 HPET_LEN));
a57d708d
IM		 1197 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1198 aml_append(field, aml_named_field("VEND", 32));
1199 aml_append(field, aml_named_field("PRD", 32));
1200 aml_append(dev, field);
1201
1202 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1203 aml_append(method, aml_store(aml_name("VEND"), id));
1204 aml_append(method, aml_store(aml_name("PRD"), period));
1205 aml_append(method, aml_shiftright(id, aml_int(16), id));
1206 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1207 aml_equal(id, aml_int(0xffff))));
1208 {
1209 aml_append(if_ctx, aml_return(zero));
1210 }
1211 aml_append(method, if_ctx);
1212
1213 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1214 aml_lgreater(period, aml_int(100000000))));
1215 {
1216 aml_append(if_ctx, aml_return(zero));
1217 }
1218 aml_append(method, if_ctx);
1219
1220 aml_append(method, aml_return(aml_int(0x0F)));
1221 aml_append(dev, method);
1222
1223 crs = aml_resource_template();
1224 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1225 aml_append(dev, aml_name_decl("_CRS", crs));
1226
1227 aml_append(scope, dev);
1228 aml_append(table, scope);
1229}
1230
27b9fc54 1231static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
95ed7e97 1232{
27b9fc54
RK		 1233 Aml *dev, *fdi;
1234 uint8_t maxc, maxh, maxs;
1235
1236 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1237
1238 dev = aml_device("FLP%c", 'A' + idx);
1239
1240 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1241
1242 fdi = aml_package(16);
1243 aml_append(fdi, aml_int(idx)); /* Drive Number */
1244 aml_append(fdi,
1245 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1246 /*
1247 * the values below are the limits of the drive, and are thus independent
1248 * of the inserted media
1249 */
1250 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1251 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1252 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1253 /*
1254 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1255 * the drive type, so shall we
1256 */
1257 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1258 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1259 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1260 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1261 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1262 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1263 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1264 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1265 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1266 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1267 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1268
1269 aml_append(dev, aml_name_decl("_FDI", fdi));
1270 return dev;
1271}
1272
1273static Aml *build_fdc_device_aml(ISADevice *fdc)
1274{
1275 int i;
95ed7e97
IM		 1276 Aml *dev;
1277 Aml *crs;
95ed7e97 1278
27b9fc54
RK		 1279#define ACPI_FDE_MAX_FD 4
1280 uint32_t fde_buf[5] = {
1281 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1282 cpu_to_le32(2) /* tape presence (2 == never present) */
1283 };
1284
95ed7e97
IM		 1285 dev = aml_device("FDC0");
1286 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1287
95ed7e97
IM		 1288 crs = aml_resource_template();
1289 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1290 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1291 aml_append(crs, aml_irq_no_flags(6));
1292 aml_append(crs,
1293 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1294 aml_append(dev, aml_name_decl("_CRS", crs));
1295
27b9fc54
RK		 1296 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1297 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1298
1299 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1300 fde_buf[i] = cpu_to_le32(1); /* drive present */
1301 aml_append(dev, build_fdinfo_aml(i, type));
1302 }
1303 }
1304 aml_append(dev, aml_name_decl("_FDE",
1305 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1306
95ed7e97
IM		 1307 return dev;
1308}
1309
ee135849
IM		 1310static Aml *build_rtc_device_aml(void)
1311{
1312 Aml *dev;
1313 Aml *crs;
1314
1315 dev = aml_device("RTC");
1316 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1317 crs = aml_resource_template();
1318 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1319 aml_append(crs, aml_irq_no_flags(8));
1320 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
95ed7e97 1321 aml_append(dev, aml_name_decl("_CRS", crs));
f58190e2
IM		 1322
1323 return dev;
1324}
1325
1326static Aml *build_kbd_device_aml(void)
1327{
1328 Aml *dev;
1329 Aml *crs;
1330 Aml *method;
1331
1332 dev = aml_device("KBD");
1333 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1334
1335 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1336 aml_append(method, aml_return(aml_int(0x0f)));
1337 aml_append(dev, method);
1338
1339 crs = aml_resource_template();
1340 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1341 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1342 aml_append(crs, aml_irq_no_flags(1));
ee135849
IM		 1343 aml_append(dev, aml_name_decl("_CRS", crs));
1344
1345 return dev;
1346}
1347
c355cb2c
IM		 1348static Aml *build_mouse_device_aml(void)
1349{
1350 Aml *dev;
1351 Aml *crs;
1352 Aml *method;
1353
1354 dev = aml_device("MOU");
1355 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1356
1357 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1358 aml_append(method, aml_return(aml_int(0x0f)));
1359 aml_append(dev, method);
1360
1361 crs = aml_resource_template();
1362 aml_append(crs, aml_irq_no_flags(12));
1363 aml_append(dev, aml_name_decl("_CRS", crs));
1364
1365 return dev;
1366}
1367
8b1da5f8
IM		 1368static Aml *build_lpt_device_aml(void)
1369{
1370 Aml *dev;
1371 Aml *crs;
1372 Aml *method;
1373 Aml *if_ctx;
1374 Aml *else_ctx;
1375 Aml *zero = aml_int(0);
1376 Aml *is_present = aml_local(0);
1377
1378 dev = aml_device("LPT");
1379 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1380
1381 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1382 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1383 if_ctx = aml_if(aml_equal(is_present, zero));
1384 {
1385 aml_append(if_ctx, aml_return(aml_int(0x00)));
1386 }
1387 aml_append(method, if_ctx);
1388 else_ctx = aml_else();
1389 {
1390 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1391 }
1392 aml_append(method, else_ctx);
1393 aml_append(dev, method);
1394
1395 crs = aml_resource_template();
1396 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1397 aml_append(crs, aml_irq_no_flags(7));
1398 aml_append(dev, aml_name_decl("_CRS", crs));
1399
1400 return dev;
1401}
1402
28f1f0e9
IM		 1403static Aml *build_com_device_aml(uint8_t uid)
1404{
1405 Aml *dev;
1406 Aml *crs;
1407 Aml *method;
1408 Aml *if_ctx;
1409 Aml *else_ctx;
1410 Aml *zero = aml_int(0);
1411 Aml *is_present = aml_local(0);
1412 const char *enabled_field = "CAEN";
1413 uint8_t irq = 4;
1414 uint16_t io_port = 0x03F8;
1415
1416 assert(uid == 1 || uid == 2);
1417 if (uid == 2) {
1418 enabled_field = "CBEN";
1419 irq = 3;
1420 io_port = 0x02F8;
1421 }
1422
1423 dev = aml_device("COM%d", uid);
1424 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1425 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1426
1427 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1428 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1429 if_ctx = aml_if(aml_equal(is_present, zero));
1430 {
1431 aml_append(if_ctx, aml_return(aml_int(0x00)));
1432 }
1433 aml_append(method, if_ctx);
1434 else_ctx = aml_else();
1435 {
1436 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1437 }
1438 aml_append(method, else_ctx);
1439 aml_append(dev, method);
1440
1441 crs = aml_resource_template();
1442 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1443 aml_append(crs, aml_irq_no_flags(irq));
1444 aml_append(dev, aml_name_decl("_CRS", crs));
1445
1446 return dev;
1447}
1448
ee135849
IM		 1449static void build_isa_devices_aml(Aml *table)
1450{
27b9fc54
RK		 1451 ISADevice *fdc = pc_find_fdc0();
1452
ee135849
IM		 1453 Aml *scope = aml_scope("_SB.PCI0.ISA");
1454
1455 aml_append(scope, build_rtc_device_aml());
f58190e2 1456 aml_append(scope, build_kbd_device_aml());
c355cb2c 1457 aml_append(scope, build_mouse_device_aml());
27b9fc54
RK		 1458 if (fdc) {
1459 aml_append(scope, build_fdc_device_aml(fdc));
9b613f4e 1460 }
8b1da5f8 1461 aml_append(scope, build_lpt_device_aml());
28f1f0e9
IM		 1462 aml_append(scope, build_com_device_aml(1));
1463 aml_append(scope, build_com_device_aml(2));
ee135849
IM		 1464
1465 aml_append(table, scope);
1466}
1467
3892a2b7
IM		 1468static void build_dbg_aml(Aml *table)
1469{
1470 Aml *field;
1471 Aml *method;
1472 Aml *while_ctx;
1473 Aml *scope = aml_scope("\\");
1474 Aml *buf = aml_local(0);
1475 Aml *len = aml_local(1);
1476 Aml *idx = aml_local(2);
1477
1478 aml_append(scope,
3f3009c0 1479 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
3892a2b7
IM		 1480 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1481 aml_append(field, aml_named_field("DBGB", 8));
1482 aml_append(scope, field);
1483
1484 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1485
1486 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1487 aml_append(method, aml_to_buffer(buf, buf));
1488 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1489 aml_append(method, aml_store(aml_int(0), idx));
1490
1491 while_ctx = aml_while(aml_lless(idx, len));
1492 aml_append(while_ctx,
1493 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1494 aml_append(while_ctx, aml_increment(idx));
1495 aml_append(method, while_ctx);
1496
1497 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1498 aml_append(scope, method);
1499
1500 aml_append(table, scope);
1501}
1502
c35b6e80
IM		 1503static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1504{
1505 Aml *dev;
1506 Aml *crs;
1507 Aml *method;
1508 uint32_t irqs[] = {5, 10, 11};
1509
1510 dev = aml_device("%s", name);
1511 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1512 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1513
1514 crs = aml_resource_template();
1515 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1516 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1517 aml_append(dev, aml_name_decl("_PRS", crs));
1518
1519 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1520 aml_append(method, aml_return(aml_call1("IQST", reg)));
1521 aml_append(dev, method);
1522
1523 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1524 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1525 aml_append(dev, method);
1526
1527 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1528 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1529 aml_append(dev, method);
1530
1531 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1532 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1533 aml_append(method, aml_store(aml_name("PRRI"), reg));
1534 aml_append(dev, method);
1535
1536 return dev;
1537 }
1538
80b32df5
IM		 1539static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1540{
1541 Aml *dev;
1542 Aml *crs;
1543 Aml *method;
1544 uint32_t irqs;
1545
1546 dev = aml_device("%s", name);
1547 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1548 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1549
1550 crs = aml_resource_template();
1551 irqs = gsi;
1552 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1553 AML_SHARED, &irqs, 1));
1554 aml_append(dev, aml_name_decl("_PRS", crs));
1555
1556 aml_append(dev, aml_name_decl("_CRS", crs));
1557
c82f503d
MA		 1558 /*
1559 * _DIS can be no-op because the interrupt cannot be disabled.
1560 */
1561 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1562 aml_append(dev, method);
1563
80b32df5
IM		 1564 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1565 aml_append(dev, method);
1566
1567 return dev;
1568}
1569
16682a9d
IM		 1570/* _CRS method - get current settings */
1571static Aml *build_iqcr_method(bool is_piix4)
1572{
1573 Aml *if_ctx;
1574 uint32_t irqs;
1575 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1576 Aml *crs = aml_resource_template();
1577
1578 irqs = 0;
1579 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1580 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1581 aml_append(method, aml_name_decl("PRR0", crs));
1582
1583 aml_append(method,
1584 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1585
1586 if (is_piix4) {
1587 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1588 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1589 aml_append(method, if_ctx);
1590 } else {
1591 aml_append(method,
1592 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1593 aml_name("PRRI")));
1594 }
1595
1596 aml_append(method, aml_return(aml_name("PRR0")));
1597 return method;
1598}
1599
78e1ad05
IM		 1600/* _STA method - get status */
1601static Aml *build_irq_status_method(void)
1602{
1603 Aml *if_ctx;
1604 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1605
1606 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1607 aml_append(if_ctx, aml_return(aml_int(0x09)));
1608 aml_append(method, if_ctx);
1609 aml_append(method, aml_return(aml_int(0x0B)));
1610 return method;
1611}
1612
e4db2798
IM		 1613static void build_piix4_pci0_int(Aml *table)
1614{
c35b6e80
IM		 1615 Aml *dev;
1616 Aml *crs;
e4db2798 1617 Aml *field;
c35b6e80
IM		 1618 Aml *method;
1619 uint32_t irqs;
e4db2798 1620 Aml *sb_scope = aml_scope("_SB");
196e2137
IM		 1621 Aml *pci0_scope = aml_scope("PCI0");
1622
1623 aml_append(pci0_scope, build_prt(true));
1624 aml_append(sb_scope, pci0_scope);
e4db2798
IM		 1625
1626 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1627 aml_append(field, aml_named_field("PRQ0", 8));
1628 aml_append(field, aml_named_field("PRQ1", 8));
1629 aml_append(field, aml_named_field("PRQ2", 8));
1630 aml_append(field, aml_named_field("PRQ3", 8));
1631 aml_append(sb_scope, field);
1632
78e1ad05 1633 aml_append(sb_scope, build_irq_status_method());
16682a9d 1634 aml_append(sb_scope, build_iqcr_method(true));
100681cc 1635
c35b6e80
IM		 1636 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1637 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1638 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1639 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1640
1641 dev = aml_device("LNKS");
1642 {
1643 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1644 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1645
1646 crs = aml_resource_template();
1647 irqs = 9;
1648 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1649 AML_ACTIVE_HIGH, AML_SHARED,
1650 &irqs, 1));
1651 aml_append(dev, aml_name_decl("_PRS", crs));
1652
1653 /* The SCI cannot be disabled and is always attached to GSI 9,
1654 * so these are no-ops. We only need this link to override the
1655 * polarity to active high and match the content of the MADT.
1656 */
1657 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1658 aml_append(method, aml_return(aml_int(0x0b)));
1659 aml_append(dev, method);
1660
1661 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1662 aml_append(dev, method);
1663
1664 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1665 aml_append(method, aml_return(aml_name("_PRS")));
1666 aml_append(dev, method);
1667
1668 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1669 aml_append(dev, method);
1670 }
1671 aml_append(sb_scope, dev);
1672
e4db2798
IM		 1673 aml_append(table, sb_scope);
1674}
1675
22b5b8bf
IM		 1676static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1677{
1678 int i;
1679 int head;
1680 Aml *pkg;
1681 char base = name[3] < 'E' ? 'A' : 'E';
1682 char *s = g_strdup(name);
1683 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1684
1685 assert(strlen(s) == 4);
1686
1687 head = name[3] - base;
1688 for (i = 0; i < 4; i++) {
1689 if (head + i > 3) {
1690 head = i * -1;
1691 }
1692 s[3] = base + head + i;
1693 pkg = aml_package(4);
1694 aml_append(pkg, a_nr);
1695 aml_append(pkg, aml_int(i));
1696 aml_append(pkg, aml_name("%s", s));
1697 aml_append(pkg, aml_int(0));
1698 aml_append(ctx, pkg);
1699 }
1700 g_free(s);
1701}
1702
1703static Aml *build_q35_routing_table(const char *str)
1704{
1705 int i;
1706 Aml *pkg;
1707 char *name = g_strdup_printf("%s ", str);
1708
1709 pkg = aml_package(128);
1710 for (i = 0; i < 0x18; i++) {
1711 name[3] = 'E' + (i & 0x3);
1712 append_q35_prt_entry(pkg, i, name);
1713 }
1714
1715 name[3] = 'E';
1716 append_q35_prt_entry(pkg, 0x18, name);
1717
1718 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1719 for (i = 0x0019; i < 0x1e; i++) {
1720 name[3] = 'A';
1721 append_q35_prt_entry(pkg, i, name);
1722 }
1723
1724 /* PCIe->PCI bridge. use PIRQ[E-H] */
1725 name[3] = 'E';
1726 append_q35_prt_entry(pkg, 0x1e, name);
1727 name[3] = 'A';
1728 append_q35_prt_entry(pkg, 0x1f, name);
1729
1730 g_free(name);
1731 return pkg;
1732}
1733
80b32df5
IM		 1734static void build_q35_pci0_int(Aml *table)
1735{
41f95a52 1736 Aml *field;
0dafe3b3 1737 Aml *method;
80b32df5 1738 Aml *sb_scope = aml_scope("_SB");
0dafe3b3
IM		 1739 Aml *pci0_scope = aml_scope("PCI0");
1740
e9fce798
IM		 1741 /* Zero => PIC mode, One => APIC Mode */
1742 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1743 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1744 {
1745 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1746 }
1747 aml_append(table, method);
1748
65aef4de
IM		 1749 aml_append(pci0_scope,
1750 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
22b5b8bf
IM		 1751 aml_append(pci0_scope,
1752 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1753
0dafe3b3
IM		 1754 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1755 {
1756 Aml *if_ctx;
1757 Aml *else_ctx;
1758
1759 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1760 section 6.2.8.1 */
1761 /* Note: we provide the same info as the PCI routing
1762 table of the Bochs BIOS */
1763 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1764 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1765 aml_append(method, if_ctx);
1766 else_ctx = aml_else();
1767 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1768 aml_append(method, else_ctx);
1769 }
1770 aml_append(pci0_scope, method);
1771 aml_append(sb_scope, pci0_scope);
80b32df5 1772
41f95a52
IM		 1773 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1774 aml_append(field, aml_named_field("PRQA", 8));
1775 aml_append(field, aml_named_field("PRQB", 8));
1776 aml_append(field, aml_named_field("PRQC", 8));
1777 aml_append(field, aml_named_field("PRQD", 8));
1778 aml_append(field, aml_reserved_field(0x20));
1779 aml_append(field, aml_named_field("PRQE", 8));
1780 aml_append(field, aml_named_field("PRQF", 8));
1781 aml_append(field, aml_named_field("PRQG", 8));
1782 aml_append(field, aml_named_field("PRQH", 8));
1783 aml_append(sb_scope, field);
1784
78e1ad05 1785 aml_append(sb_scope, build_irq_status_method());
16682a9d
IM		 1786 aml_append(sb_scope, build_iqcr_method(false));
1787
12e3b1f7
IM		 1788 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1789 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1790 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1791 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1792 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1793 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1794 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1795 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1796
80b32df5
IM		 1797 /*
1798 * TODO: UID probably shouldn't be the same for GSIx devices
1799 * but that's how it was in original ASL so keep it for now
1800 */
1801 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10));
1802 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11));
1803 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12));
1804 aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13));
1805 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14));
1806 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15));
1807 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16));
1808 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17));
1809
1810 aml_append(table, sb_scope);
1811}
1812
41f95a52
IM		 1813static void build_q35_isa_bridge(Aml *table)
1814{
1815 Aml *dev;
1816 Aml *scope;
1817 Aml *field;
1818
1819 scope = aml_scope("_SB.PCI0");
1820 dev = aml_device("ISA");
1821 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1822
1823 /* ICH9 PCI to ISA irq remapping */
1824 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
3f3009c0 1825 aml_int(0x60), 0x0C));
41f95a52
IM		 1826
1827 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
3f3009c0 1828 aml_int(0x80), 0x02));
41f95a52
IM		 1829 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1830 aml_append(field, aml_named_field("COMA", 3));
1831 aml_append(field, aml_reserved_field(1));
1832 aml_append(field, aml_named_field("COMB", 3));
1833 aml_append(field, aml_reserved_field(1));
1834 aml_append(field, aml_named_field("LPTD", 2));
41f95a52
IM		 1835 aml_append(dev, field);
1836
1837 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
3f3009c0 1838 aml_int(0x82), 0x02));
41f95a52
IM		 1839 /* enable bits */
1840 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1841 aml_append(field, aml_named_field("CAEN", 1));
1842 aml_append(field, aml_named_field("CBEN", 1));
1843 aml_append(field, aml_named_field("LPEN", 1));
41f95a52
IM		 1844 aml_append(dev, field);
1845
1846 aml_append(scope, dev);
1847 aml_append(table, scope);
1848}
1849
e4db2798
IM		 1850static void build_piix4_pm(Aml *table)
1851{
1852 Aml *dev;
1853 Aml *scope;
1854
1855 scope = aml_scope("_SB.PCI0");
1856 dev = aml_device("PX13");
1857 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1858
1859 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
3f3009c0 1860 aml_int(0x00), 0xff));
e4db2798
IM		 1861 aml_append(scope, dev);
1862 aml_append(table, scope);
1863}
1864
1865static void build_piix4_isa_bridge(Aml *table)
1866{
1867 Aml *dev;
1868 Aml *scope;
1869 Aml *field;
1870
1871 scope = aml_scope("_SB.PCI0");
1872 dev = aml_device("ISA");
1873 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1874
1875 /* PIIX PCI to ISA irq remapping */
1876 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
3f3009c0 1877 aml_int(0x60), 0x04));
e4db2798
IM		 1878 /* enable bits */
1879 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1880 /* Offset(0x5f),, 7, */
1881 aml_append(field, aml_reserved_field(0x2f8));
1882 aml_append(field, aml_reserved_field(7));
1883 aml_append(field, aml_named_field("LPEN", 1));
1884 /* Offset(0x67),, 3, */
1885 aml_append(field, aml_reserved_field(0x38));
1886 aml_append(field, aml_reserved_field(3));
1887 aml_append(field, aml_named_field("CAEN", 1));
1888 aml_append(field, aml_reserved_field(3));
1889 aml_append(field, aml_named_field("CBEN", 1));
1890 aml_append(dev, field);
e4db2798
IM		 1891
1892 aml_append(scope, dev);
1893 aml_append(table, scope);
1894}
1895
b616ec4d
IM		 1896static void build_piix4_pci_hotplug(Aml *table)
1897{
1898 Aml *scope;
1899 Aml *field;
1900 Aml *method;
1901
1902 scope = aml_scope("_SB.PCI0");
1903
1904 aml_append(scope,
3f3009c0 1905 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
b616ec4d
IM		 1906 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1907 aml_append(field, aml_named_field("PCIU", 32));
1908 aml_append(field, aml_named_field("PCID", 32));
1909 aml_append(scope, field);
1910
1911 aml_append(scope,
3f3009c0 1912 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
b616ec4d
IM		 1913 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1914 aml_append(field, aml_named_field("B0EJ", 32));
1915 aml_append(scope, field);
1916
1917 aml_append(scope,
3f3009c0 1918 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
b616ec4d
IM		 1919 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1920 aml_append(field, aml_named_field("BNUM", 32));
1921 aml_append(scope, field);
1922
1923 aml_append(scope, aml_mutex("BLCK", 0));
1924
1925 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1926 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1927 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1928 aml_append(method,
1929 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1930 aml_append(method, aml_release(aml_name("BLCK")));
1931 aml_append(method, aml_return(aml_int(0)));
1932 aml_append(scope, method);
1933
1934 aml_append(table, scope);
1935}
1936
f97a88a8
IM		 1937static Aml *build_q35_osc_method(void)
1938{
1939 Aml *if_ctx;
1940 Aml *if_ctx2;
1941 Aml *else_ctx;
1942 Aml *method;
1943 Aml *a_cwd1 = aml_name("CDW1");
1944 Aml *a_ctrl = aml_name("CTRL");
1945
1946 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1947 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1948
1949 if_ctx = aml_if(aml_equal(
1950 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1951 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1952 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1953
1954 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1955 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1956
1957 /*
1958 * Always allow native PME, AER (no dependencies)
1959 * Never allow SHPC (no SHPC controller in this system)
1960 */
1961 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1962
1963 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1964 /* Unknown revision */
1965 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1966 aml_append(if_ctx, if_ctx2);
1967
1968 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1969 /* Capabilities bits were masked */
1970 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1971 aml_append(if_ctx, if_ctx2);
1972
1973 /* Update DWORD3 in the buffer */
1974 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1975 aml_append(method, if_ctx);
1976
1977 else_ctx = aml_else();
1978 /* Unrecognized UUID */
1979 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1980 aml_append(method, else_ctx);
1981
1982 aml_append(method, aml_return(aml_arg(3)));
1983 return method;
1984}
b616ec4d 1985
72c194f7 1986static void
41fa5c04 1987build_dsdt(GArray *table_data, GArray *linker,
72c194f7 1988 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
3d3ebcad 1989 PcPciInfo *pci, MachineState *machine)
72c194f7 1990{
41fa5c04
IM		 1991 CrsRangeEntry *entry;
1992 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1993 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1994 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
fb306ffe 1995 PCMachineState *pcms = PC_MACHINE(machine);
bef3492d 1996 uint32_t nr_mem = machine->ram_slots;
dcdca296 1997 int root_bus_limit = 0xFF;
41fa5c04 1998 PCIBus *bus = NULL;
72c194f7
MT		 1999 int i;
2000
41fa5c04 2001 dsdt = init_aml_allocator();
2fd71f1b 2002
4ec8d2b3 2003 /* Reserve space for header */
41fa5c04
IM		 2004 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
2005
2006 build_dbg_aml(dsdt);
2007 if (misc->is_piix4) {
2008 sb_scope = aml_scope("_SB");
2009 dev = aml_device("PCI0");
2010 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2011 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2012 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2013 aml_append(sb_scope, dev);
2014 aml_append(dsdt, sb_scope);
2015
2016 build_hpet_aml(dsdt);
2017 build_piix4_pm(dsdt);
2018 build_piix4_isa_bridge(dsdt);
2019 build_isa_devices_aml(dsdt);
2020 build_piix4_pci_hotplug(dsdt);
2021 build_piix4_pci0_int(dsdt);
2022 } else {
2023 sb_scope = aml_scope("_SB");
2024 aml_append(sb_scope,
3f3009c0 2025 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
41fa5c04 2026 aml_append(sb_scope,
3f3009c0 2027 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
41fa5c04
IM		 2028 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
2029 aml_append(field, aml_named_field("PCIB", 8));
2030 aml_append(sb_scope, field);
2031 aml_append(dsdt, sb_scope);
2032
2033 sb_scope = aml_scope("_SB");
2034 dev = aml_device("PCI0");
2035 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
2036 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
2037 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2038 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2039 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
2040 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
2041 aml_append(dev, build_q35_osc_method());
2042 aml_append(sb_scope, dev);
2043 aml_append(dsdt, sb_scope);
2044
2045 build_hpet_aml(dsdt);
2046 build_q35_isa_bridge(dsdt);
2047 build_isa_devices_aml(dsdt);
2048 build_q35_pci0_int(dsdt);
2049 }
2050
2051 build_cpu_hotplug_aml(dsdt);
2052 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
2053 pm->mem_hp_io_len);
2054
2055 scope = aml_scope("_GPE");
2056 {
2057 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
2058
2059 aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED));
2060
2061 if (misc->is_piix4) {
2062 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
2063 aml_append(method,
2064 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
2065 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
2066 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
2067 aml_append(scope, method);
2068 } else {
2069 aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED));
2070 }
2071
2072 method = aml_method("_E02", 0, AML_NOTSERIALIZED);
2073 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD));
2074 aml_append(scope, method);
2075
2076 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
2077 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
2078 aml_append(scope, method);
2079
2080 aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED));
2081 aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED));
2082 aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED));
2083 aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED));
2084 aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED));
2085 aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED));
2086 aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED));
2087 aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED));
2088 aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED));
2089 aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED));
2090 aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED));
2091 aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED));
2092 }
2093 aml_append(dsdt, scope);
72c194f7 2094
81ed6482 2095 bus = PC_MACHINE(machine)->bus;
a4894206
MA		 2096 if (bus) {
2097 QLIST_FOREACH(bus, &bus->child, sibling) {
2098 uint8_t bus_num = pci_bus_num(bus);
0e79e51a 2099 uint8_t numa_node = pci_bus_numa_node(bus);
a4894206
MA		 2100
2101 /* look only for expander root buses */
2102 if (!pci_bus_is_root(bus)) {
2103 continue;
2104 }
2105
dcdca296
MA		 2106 if (bus_num < root_bus_limit) {
2107 root_bus_limit = bus_num - 1;
2108 }
2109
a4894206
MA		 2110 scope = aml_scope("\\_SB");
2111 dev = aml_device("PC%.02X", bus_num);
c96d9286
LE		 2112 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
2113 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
a4894206 2114 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
0e79e51a
MA		 2115
2116 if (numa_node != NUMA_NODE_UNASSIGNED) {
2117 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2118 }
2119
196e2137 2120 aml_append(dev, build_prt(false));
a43c6e27
MA		 2121 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
2122 io_ranges, mem_ranges);
2123 aml_append(dev, aml_name_decl("_CRS", crs));
a4894206 2124 aml_append(scope, dev);
41fa5c04 2125 aml_append(dsdt, scope);
a4894206
MA		 2126 }
2127 }
2128
500b11ea 2129 scope = aml_scope("\\_SB.PCI0");
60efd429
IM		 2130 /* build PCI0._CRS */
2131 crs = aml_resource_template();
2132 aml_append(crs,
ff80dc7f 2133 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
dcdca296
MA		 2134 0x0000, 0x0, root_bus_limit,
2135 0x0000, root_bus_limit + 1));
ff80dc7f 2136 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
60efd429
IM		 2137
2138 aml_append(crs,
ff80dc7f
SZ		 2139 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2140 AML_POS_DECODE, AML_ENTIRE_RANGE,
60efd429 2141 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
dcdca296
MA		 2142
2143 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
2144 for (i = 0; i < io_ranges->len; i++) {
2145 entry = g_ptr_array_index(io_ranges, i);
2146 aml_append(crs,
2147 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2148 AML_POS_DECODE, AML_ENTIRE_RANGE,
2149 0x0000, entry->base, entry->limit,
2150 0x0000, entry->limit - entry->base + 1));
2151 }
2152
60efd429 2153 aml_append(crs,
ff80dc7f
SZ		 2154 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2155 AML_CACHEABLE, AML_READ_WRITE,
60efd429 2156 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
dcdca296
MA		 2157
2158 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
2159 for (i = 0; i < mem_ranges->len; i++) {
2160 entry = g_ptr_array_index(mem_ranges, i);
2161 aml_append(crs,
2162 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2163 AML_NON_CACHEABLE, AML_READ_WRITE,
2164 0, entry->base, entry->limit,
2165 0, entry->limit - entry->base + 1));
2166 }
2167
60efd429
IM		 2168 if (pci->w64.begin) {
2169 aml_append(crs,
ff80dc7f
SZ		 2170 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2171 AML_CACHEABLE, AML_READ_WRITE,
60efd429
IM		 2172 0, pci->w64.begin, pci->w64.end - 1, 0,
2173 pci->w64.end - pci->w64.begin));
2174 }
2175 aml_append(scope, aml_name_decl("_CRS", crs));
2176
d31c909e
IM		 2177 /* reserve GPE0 block resources */
2178 dev = aml_device("GPE0");
2179 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2180 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2181 /* device present, functioning, decoding, not shown in UI */
2182 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2183 crs = aml_resource_template();
2184 aml_append(crs,
ff80dc7f 2185 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
d31c909e
IM		 2186 );
2187 aml_append(dev, aml_name_decl("_CRS", crs));
2188 aml_append(scope, dev);
2189
dcdca296
MA		 2190 g_ptr_array_free(io_ranges, true);
2191 g_ptr_array_free(mem_ranges, true);
2192
500b11ea
IM		 2193 /* reserve PCIHP resources */
2194 if (pm->pcihp_io_len) {
2195 dev = aml_device("PHPR");
2196 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2197 aml_append(dev,
2198 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2199 /* device present, functioning, decoding, not shown in UI */
2200 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2201 crs = aml_resource_template();
2202 aml_append(crs,
ff80dc7f 2203 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
500b11ea
IM		 2204 pm->pcihp_io_len)
2205 );
2206 aml_append(dev, aml_name_decl("_CRS", crs));
2207 aml_append(scope, dev);
2208 }
41fa5c04 2209 aml_append(dsdt, scope);
500b11ea 2210
ebc3028f
IM		 2211 /* create S3_ / S4_ / S5_ packages if necessary */
2212 scope = aml_scope("\\");
2213 if (!pm->s3_disabled) {
2214 pkg = aml_package(4);
2215 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2216 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2217 aml_append(pkg, aml_int(0)); /* reserved */
2218 aml_append(pkg, aml_int(0)); /* reserved */
2219 aml_append(scope, aml_name_decl("_S3", pkg));
2220 }
2221
2222 if (!pm->s4_disabled) {
2223 pkg = aml_package(4);
2224 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2225 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2226 aml_append(pkg, aml_int(pm->s4_val));
2227 aml_append(pkg, aml_int(0)); /* reserved */
2228 aml_append(pkg, aml_int(0)); /* reserved */
2229 aml_append(scope, aml_name_decl("_S4", pkg));
2230 }
2231
2232 pkg = aml_package(4);
2233 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2234 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2235 aml_append(pkg, aml_int(0)); /* reserved */
2236 aml_append(pkg, aml_int(0)); /* reserved */
2237 aml_append(scope, aml_name_decl("_S5", pkg));
41fa5c04 2238 aml_append(dsdt, scope);
ebc3028f 2239
e2ec7568
GS		 2240 /* create fw_cfg node, unconditionally */
2241 {
2242 /* when using port i/o, the 8-bit data register *always* overlaps
2243 * with half of the 16-bit control register. Hence, the total size
2244 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2245 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2246 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2247 "dma_enabled", NULL) ?
2248 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2249 FW_CFG_CTL_SIZE;
2250
2251 scope = aml_scope("\\_SB.PCI0");
2252 dev = aml_device("FWCF");
2253
2254 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2255
2256 /* device present, functioning, decoding, not shown in UI */
2257 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2258
2259 crs = aml_resource_template();
2260 aml_append(crs,
2261 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2262 );
2263 aml_append(dev, aml_name_decl("_CRS", crs));
2264
2265 aml_append(scope, dev);
2266 aml_append(dsdt, scope);
2267 }
2268
8ac6f7a6
IM		 2269 if (misc->applesmc_io_base) {
2270 scope = aml_scope("\\_SB.PCI0.ISA");
2271 dev = aml_device("SMC");
2272
2273 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2274 /* device present, functioning, decoding, not shown in UI */
2275 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2276
2277 crs = aml_resource_template();
2278 aml_append(crs,
ff80dc7f 2279 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
8ac6f7a6
IM		 2280 0x01, APPLESMC_MAX_DATA_LENGTH)
2281 );
2282 aml_append(crs, aml_irq_no_flags(6));
2283 aml_append(dev, aml_name_decl("_CRS", crs));
2284
2285 aml_append(scope, dev);
41fa5c04 2286 aml_append(dsdt, scope);
8ac6f7a6
IM		 2287 }
2288
cd61cb2e
IM		 2289 if (misc->pvpanic_port) {
2290 scope = aml_scope("\\_SB.PCI0.ISA");
2291
2332333c 2292 dev = aml_device("PEVT");
e65bef69 2293 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
cd61cb2e
IM		 2294
2295 crs = aml_resource_template();
2296 aml_append(crs,
ff80dc7f 2297 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
cd61cb2e
IM		 2298 );
2299 aml_append(dev, aml_name_decl("_CRS", crs));
2300
ff80dc7f 2301 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
3f3009c0 2302 aml_int(misc->pvpanic_port), 1));
36de884a 2303 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
cd61cb2e
IM		 2304 aml_append(field, aml_named_field("PEPT", 8));
2305 aml_append(dev, field);
2306
8ef3ea25
GH		 2307 /* device present, functioning, decoding, shown in UI */
2308 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2332333c 2309
4dbfc881 2310 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
cd61cb2e
IM		 2311 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2312 aml_append(method, aml_return(aml_local(0)));
2313 aml_append(dev, method);
2314
4dbfc881 2315 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
cd61cb2e
IM		 2316 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2317 aml_append(dev, method);
2318
2319 aml_append(scope, dev);
41fa5c04 2320 aml_append(dsdt, scope);
cd61cb2e
IM		 2321 }
2322
7824df38 2323 sb_scope = aml_scope("\\_SB");
72c194f7 2324 {
dd4c2f01 2325 build_processor_devices(sb_scope, pcms->apic_id_limit, cpu, pm);
72c194f7 2326
f177d40a
IM		 2327 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2328 pm->mem_hp_io_len);
8698c0c0 2329
72c194f7 2330 {
8dcf525a
MT		 2331 Object *pci_host;
2332 PCIBus *bus = NULL;
8dcf525a 2333
ca6c1855
MA		 2334 pci_host = acpi_get_i386_pci_host();
2335 if (pci_host) {
8dcf525a
MT		 2336 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2337 }
72c194f7 2338
99fd437d 2339 if (bus) {
62b52c26 2340 Aml *scope = aml_scope("PCI0");
99fd437d 2341 /* Scan all PCI buses. Generate tables to support hotplug. */
62b52c26 2342 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
72d97b3a
IM		 2343
2344 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2345 dev = aml_device("ISA.TPM");
2346 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2347 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2348 crs = aml_resource_template();
2349 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2350 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2351 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
2352 aml_append(dev, aml_name_decl("_CRS", crs));
2353 aml_append(scope, dev);
2354 }
2355
62b52c26 2356 aml_append(sb_scope, scope);
72c194f7 2357 }
72c194f7 2358 }
41fa5c04 2359 aml_append(dsdt, sb_scope);
72c194f7
MT		 2360 }
2361
011bb749 2362 /* copy AML table into ACPI tables blob and patch header there */
41fa5c04 2363 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
72c194f7 2364 build_header(linker, table_data,
41fa5c04 2365 (void *)(table_data->data + table_data->len - dsdt->buf->len),
37ad223c 2366 "DSDT", dsdt->buf->len, 1, NULL, NULL);
011bb749 2367 free_aml_allocator();
72c194f7
MT		 2368}
2369
2370static void
2371build_hpet(GArray *table_data, GArray *linker)
2372{
2373 Acpi20Hpet *hpet;
2374
2375 hpet = acpi_data_push(table_data, sizeof(*hpet));
2376 /* Note timer_block_id value must be kept in sync with value advertised by
2377 * emulated hpet
2378 */
2379 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2380 hpet->addr.address = cpu_to_le64(HPET_BASE);
2381 build_header(linker, table_data,
37ad223c 2382 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
72c194f7
MT		 2383}
2384
711b20b4 2385static void
42a5b308 2386build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
711b20b4
SB		 2387{
2388 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
42a5b308 2389 uint64_t log_area_start_address = acpi_data_len(tcpalog);
711b20b4
SB		 2390
2391 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2392 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2393 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
2394
42a5b308
SB		 2395 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
2396 false /* high memory */);
2397
711b20b4
SB		 2398 /* log area start address to be filled by Guest linker */
2399 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
42a5b308 2400 ACPI_BUILD_TPMLOG_FILE,
711b20b4
SB		 2401 table_data, &tcpa->log_area_start_address,
2402 sizeof(tcpa->log_area_start_address));
2403
2404 build_header(linker, table_data,
37ad223c 2405 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
711b20b4 2406
42a5b308 2407 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
711b20b4
SB		 2408}
2409
5cb18b3d
SB		 2410static void
2411build_tpm2(GArray *table_data, GArray *linker)
2412{
2413 Acpi20TPM2 *tpm2_ptr;
5cb18b3d
SB		 2414
2415 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2416
2417 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2418 tpm2_ptr->control_area_address = cpu_to_le64(0);
2419 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2420
2421 build_header(linker, table_data,
37ad223c 2422 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
5cb18b3d
SB		 2423}
2424
04ed3ea8
IM		 2425typedef enum {
2426 MEM_AFFINITY_NOFLAGS = 0,
2427 MEM_AFFINITY_ENABLED = (1 << 0),
2428 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
2429 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
2430} MemoryAffinityFlags;
2431
72c194f7 2432static void
04ed3ea8
IM		 2433acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
2434 uint64_t len, int node, MemoryAffinityFlags flags)
72c194f7
MT		 2435{
2436 numamem->type = ACPI_SRAT_MEMORY;
2437 numamem->length = sizeof(*numamem);
2438 memset(numamem->proximity, 0, 4);
2439 numamem->proximity[0] = node;
04ed3ea8 2440 numamem->flags = cpu_to_le32(flags);
72c194f7
MT		 2441 numamem->base_addr = cpu_to_le64(base);
2442 numamem->range_length = cpu_to_le64(len);
2443}
2444
2445static void
3d3ebcad 2446build_srat(GArray *table_data, GArray *linker, MachineState *machine)
72c194f7
MT		 2447{
2448 AcpiSystemResourceAffinityTable *srat;
2449 AcpiSratProcessorAffinity *core;
2450 AcpiSratMemoryAffinity *numamem;
2451
2452 int i;
2453 uint64_t curnode;
2454 int srat_start, numa_start, slots;
2455 uint64_t mem_len, mem_base, next_base;
5803fce3
IM		 2456 MachineClass *mc = MACHINE_GET_CLASS(machine);
2457 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
3d3ebcad 2458 PCMachineState *pcms = PC_MACHINE(machine);
cec65193
IM		 2459 ram_addr_t hotplugabble_address_space_size =
2460 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2461 NULL);
72c194f7
MT		 2462
2463 srat_start = table_data->len;
2464
2465 srat = acpi_data_push(table_data, sizeof *srat);
2466 srat->reserved1 = cpu_to_le32(1);
72c194f7 2467
5803fce3
IM		 2468 for (i = 0; i < apic_ids->len; i++) {
2469 int apic_id = apic_ids->cpus[i].arch_id;
2470
72c194f7
MT		 2471 core = acpi_data_push(table_data, sizeof *core);
2472 core->type = ACPI_SRAT_PROCESSOR;
2473 core->length = sizeof(*core);
5803fce3
IM		 2474 core->local_apic_id = apic_id;
2475 curnode = pcms->node_cpu[apic_id];
72c194f7
MT		 2476 core->proximity_lo = curnode;
2477 memset(core->proximity_hi, 0, 3);
2478 core->local_sapic_eid = 0;
dd0247e0 2479 core->flags = cpu_to_le32(1);
72c194f7
MT		 2480 }
2481
2482
2483 /* the memory map is a bit tricky, it contains at least one hole
2484 * from 640k-1M and possibly another one from 3.5G-4G.
2485 */
2486 next_base = 0;
2487 numa_start = table_data->len;
2488
2489 numamem = acpi_data_push(table_data, sizeof *numamem);
04ed3ea8 2490 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
72c194f7 2491 next_base = 1024 * 1024;
dd4c2f01 2492 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
72c194f7 2493 mem_base = next_base;
dd4c2f01 2494 mem_len = pcms->node_mem[i - 1];
72c194f7
MT		 2495 if (i == 1) {
2496 mem_len -= 1024 * 1024;
2497 }
2498 next_base = mem_base + mem_len;
2499
2500 /* Cut out the ACPI_PCI hole */
5299f1c7
EH		 2501 if (mem_base <= pcms->below_4g_mem_size &&
2502 next_base > pcms->below_4g_mem_size) {
2503 mem_len -= next_base - pcms->below_4g_mem_size;
72c194f7
MT		 2504 if (mem_len > 0) {
2505 numamem = acpi_data_push(table_data, sizeof *numamem);
04ed3ea8
IM		 2506 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2507 MEM_AFFINITY_ENABLED);
72c194f7
MT		 2508 }
2509 mem_base = 1ULL << 32;
5299f1c7
EH		 2510 mem_len = next_base - pcms->below_4g_mem_size;
2511 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
72c194f7
MT		 2512 }
2513 numamem = acpi_data_push(table_data, sizeof *numamem);
04ed3ea8
IM		 2514 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2515 MEM_AFFINITY_ENABLED);
72c194f7
MT		 2516 }
2517 slots = (table_data->len - numa_start) / sizeof *numamem;
dd4c2f01 2518 for (; slots < pcms->numa_nodes + 2; slots++) {
72c194f7 2519 numamem = acpi_data_push(table_data, sizeof *numamem);
04ed3ea8 2520 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
72c194f7
MT		 2521 }
2522
cec65193
IM		 2523 /*
2524 * Entry is required for Windows to enable memory hotplug in OS.
2525 * Memory devices may override proximity set by this entry,
2526 * providing _PXM method if necessary.
2527 */
2528 if (hotplugabble_address_space_size) {
2529 numamem = acpi_data_push(table_data, sizeof *numamem);
a7d69ff1 2530 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
cec65193
IM		 2531 hotplugabble_address_space_size, 0,
2532 MEM_AFFINITY_HOTPLUGGABLE |
2533 MEM_AFFINITY_ENABLED);
2534 }
2535
72c194f7
MT		 2536 build_header(linker, table_data,
2537 (void *)(table_data->data + srat_start),
821e3227 2538 "SRAT",
37ad223c 2539 table_data->len - srat_start, 1, NULL, NULL);
5803fce3 2540 g_free(apic_ids);
72c194f7
MT		 2541}
2542
2543static void
2544build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
2545{
2546 AcpiTableMcfg *mcfg;
821e3227 2547 const char *sig;
72c194f7
MT		 2548 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2549
2550 mcfg = acpi_data_push(table_data, len);
2551 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2552 /* Only a single allocation so no need to play with segments */
2553 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2554 mcfg->allocation[0].start_bus_number = 0;
2555 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2556
2557 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2558 * To avoid table size changes (which create migration issues),
2559 * always create the table even if there are no allocations,
2560 * but set the signature to a reserved value in this case.
2561 * ACPI spec requires OSPMs to ignore such tables.
2562 */
2563 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
821e3227
MT		 2564 /* Reserved signature: ignored by OSPM */
2565 sig = "QEMU";
72c194f7 2566 } else {
821e3227 2567 sig = "MCFG";
72c194f7 2568 }
37ad223c 2569 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
72c194f7
MT		 2570}
2571
d4eb9119
LT		 2572static void
2573build_dmar_q35(GArray *table_data, GArray *linker)
2574{
2575 int dmar_start = table_data->len;
2576
2577 AcpiTableDmar *dmar;
2578 AcpiDmarHardwareUnit *drhd;
2579
2580 dmar = acpi_data_push(table_data, sizeof(*dmar));
2581 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2582 dmar->flags = 0; /* No intr_remap for now */
2583
2584 /* DMAR Remapping Hardware Unit Definition structure */
2585 drhd = acpi_data_push(table_data, sizeof(*drhd));
2586 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2587 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
2588 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2589 drhd->pci_segment = cpu_to_le16(0);
2590 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2591
2592 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
37ad223c 2593 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
d4eb9119
LT		 2594}
2595
72c194f7
MT		 2596static GArray *
2597build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
2598{
2599 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2600
d67aadcc 2601 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
72c194f7
MT		 2602 true /* fseg memory */);
2603
821e3227 2604 memcpy(&rsdp->signature, "RSD PTR ", 8);
72c194f7
MT		 2605 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2606 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
2607 /* Address to be filled by Guest linker */
2608 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
2609 ACPI_BUILD_TABLE_FILE,
2610 rsdp_table, &rsdp->rsdt_physical_address,
2611 sizeof rsdp->rsdt_physical_address);
2612 rsdp->checksum = 0;
2613 /* Checksum to be filled by Guest linker */
2614 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
b54ca0c3
MT		 2615 rsdp_table, rsdp, sizeof *rsdp,
2616 &rsdp->checksum);
72c194f7
MT		 2617
2618 return rsdp_table;
2619}
2620
72c194f7
MT		 2621typedef
2622struct AcpiBuildState {
2623 /* Copy of table in RAM (for patching). */
339240b5 2624 MemoryRegion *table_mr;
72c194f7
MT		 2625 /* Is table patched? */
2626 uint8_t patched;
d70414a5 2627 void *rsdp;
339240b5
PB		 2628 MemoryRegion *rsdp_mr;
2629 MemoryRegion *linker_mr;
72c194f7
MT		 2630} AcpiBuildState;
2631
2632static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2633{
2634 Object *pci_host;
2635 QObject *o;
72c194f7 2636
ca6c1855 2637 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 2638 g_assert(pci_host);
2639
2640 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2641 if (!o) {
2642 return false;
2643 }
2644 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
097a97a6 2645 qobject_decref(o);
72c194f7
MT		 2646
2647 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2648 assert(o);
2649 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
097a97a6 2650 qobject_decref(o);
72c194f7
MT		 2651 return true;
2652}
2653
d4eb9119
LT		 2654static bool acpi_has_iommu(void)
2655{
2656 bool ambiguous;
2657 Object *intel_iommu;
2658
2659 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
2660 &ambiguous);
2661 return intel_iommu && !ambiguous;
2662}
2663
72c194f7 2664static
3d3ebcad 2665void acpi_build(AcpiBuildTables *tables, MachineState *machine)
72c194f7 2666{
3d3ebcad 2667 PCMachineState *pcms = PC_MACHINE(machine);
bb292f5a 2668 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72c194f7 2669 GArray *table_offsets;
41fa5c04 2670 unsigned facs, dsdt, rsdt, fadt;
72c194f7
MT		 2671 AcpiCpuInfo cpu;
2672 AcpiPmInfo pm;
2673 AcpiMiscInfo misc;
2674 AcpiMcfgInfo mcfg;
2675 PcPciInfo pci;
2676 uint8_t *u;
07fb6176 2677 size_t aml_len = 0;
7c2c1fa5 2678 GArray *tables_blob = tables->table_data;
ae123749 2679 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
72c194f7
MT		 2680
2681 acpi_get_cpu_info(&cpu);
2682 acpi_get_pm_info(&pm);
72c194f7
MT		 2683 acpi_get_misc_info(&misc);
2684 acpi_get_pci_info(&pci);
ae123749 2685 acpi_get_slic_oem(&slic_oem);
72c194f7
MT		 2686
2687 table_offsets = g_array_new(false, true /* clear */,
2688 sizeof(uint32_t));
8b310fc4 2689 ACPI_BUILD_DPRINTF("init ACPI tables\n");
72c194f7
MT		 2690
2691 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
2692 64 /* Ensure FACS is aligned */,
2693 false /* high memory */);
2694
2695 /*
2696 * FACS is pointed to by FADT.
2697 * We place it first since it's the only table that has alignment
2698 * requirements.
2699 */
7c2c1fa5 2700 facs = tables_blob->len;
fb306ffe 2701 build_facs(tables_blob, tables->linker);
72c194f7
MT		 2702
2703 /* DSDT is pointed to by FADT */
7c2c1fa5 2704 dsdt = tables_blob->len;
3d3ebcad 2705 build_dsdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, machine);
72c194f7 2706
07fb6176
PB		 2707 /* Count the size of the DSDT and SSDT, we will need it for legacy
2708 * sizing of ACPI tables.
2709 */
7c2c1fa5 2710 aml_len += tables_blob->len - dsdt;
07fb6176 2711
72c194f7 2712 /* ACPI tables pointed to by RSDT */
41fa5c04 2713 fadt = tables_blob->len;
7c2c1fa5 2714 acpi_add_table(table_offsets, tables_blob);
ae123749
LE		 2715 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2716 slic_oem.id, slic_oem.table_id);
41fa5c04 2717 aml_len += tables_blob->len - fadt;
72c194f7 2718
7c2c1fa5 2719 acpi_add_table(table_offsets, tables_blob);
3d3ebcad 2720 build_madt(tables_blob, tables->linker, pcms, &cpu);
9ac1c4c0 2721
72c194f7 2722 if (misc.has_hpet) {
7c2c1fa5
IM		 2723 acpi_add_table(table_offsets, tables_blob);
2724 build_hpet(tables_blob, tables->linker);
711b20b4 2725 }
5cb18b3d 2726 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
7c2c1fa5
IM		 2727 acpi_add_table(table_offsets, tables_blob);
2728 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
711b20b4 2729
72d97b3a
IM		 2730 if (misc.tpm_version == TPM_VERSION_2_0) {
2731 acpi_add_table(table_offsets, tables_blob);
5cb18b3d 2732 build_tpm2(tables_blob, tables->linker);
5cb18b3d 2733 }
72c194f7 2734 }
dd4c2f01 2735 if (pcms->numa_nodes) {
7c2c1fa5 2736 acpi_add_table(table_offsets, tables_blob);
3d3ebcad 2737 build_srat(tables_blob, tables->linker, machine);
72c194f7
MT		 2738 }
2739 if (acpi_get_mcfg(&mcfg)) {
7c2c1fa5
IM		 2740 acpi_add_table(table_offsets, tables_blob);
2741 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
72c194f7 2742 }
d4eb9119 2743 if (acpi_has_iommu()) {
7c2c1fa5
IM		 2744 acpi_add_table(table_offsets, tables_blob);
2745 build_dmar_q35(tables_blob, tables->linker);
d4eb9119 2746 }
5fe79386 2747 if (pcms->acpi_nvdimm_state.is_enabled) {
87252e1b
XG		 2748 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
2749 }
2750
72c194f7
MT		 2751 /* Add tables supplied by user (if any) */
2752 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2753 unsigned len = acpi_table_len(u);
2754
7c2c1fa5
IM		 2755 acpi_add_table(table_offsets, tables_blob);
2756 g_array_append_vals(tables_blob, u, len);
72c194f7
MT		 2757 }
2758
2759 /* RSDT is pointed to by RSDP */
7c2c1fa5 2760 rsdt = tables_blob->len;
ae123749
LE		 2761 build_rsdt(tables_blob, tables->linker, table_offsets,
2762 slic_oem.id, slic_oem.table_id);
72c194f7
MT		 2763
2764 /* RSDP is in FSEG memory, so allocate it separately */
2765 build_rsdp(tables->rsdp, tables->linker, rsdt);
2766
07fb6176 2767 /* We'll expose it all to Guest so we want to reduce
72c194f7 2768 * chance of size changes.
07fb6176
PB		 2769 *
2770 * We used to align the tables to 4k, but of course this would
2771 * too simple to be enough. 4k turned out to be too small an
2772 * alignment very soon, and in fact it is almost impossible to
2773 * keep the table size stable for all (max_cpus, max_memory_slots)
2774 * combinations. So the table size is always 64k for pc-i440fx-2.1
2775 * and we give an error if the table grows beyond that limit.
2776 *
2777 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2778 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2779 * than 2.0 and we can always pad the smaller tables with zeros. We can
2780 * then use the exact size of the 2.0 tables.
2781 *
2782 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
72c194f7 2783 */
bb292f5a 2784 if (pcmc->legacy_acpi_table_size) {
07fb6176
PB		 2785 /* Subtracting aml_len gives the size of fixed tables. Then add the
2786 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2787 */
2788 int legacy_aml_len =
bb292f5a 2789 pcmc->legacy_acpi_table_size +
07fb6176
PB		 2790 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2791 int legacy_table_size =
7c2c1fa5 2792 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
07fb6176 2793 ACPI_BUILD_ALIGN_SIZE);
7c2c1fa5 2794 if (tables_blob->len > legacy_table_size) {
07fb6176 2795 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
868270f2 2796 error_report("Warning: migration may not work.");
07fb6176 2797 }
7c2c1fa5 2798 g_array_set_size(tables_blob, legacy_table_size);
07fb6176 2799 } else {
868270f2 2800 /* Make sure we have a buffer in case we need to resize the tables. */
7c2c1fa5 2801 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
18045fb9 2802 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
868270f2
MT		 2803 error_report("Warning: ACPI tables are larger than 64k.");
2804 error_report("Warning: migration may not work.");
2805 error_report("Warning: please remove CPUs, NUMA nodes, "
2806 "memory slots or PCI bridges.");
18045fb9 2807 }
7c2c1fa5 2808 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
07fb6176 2809 }
72c194f7 2810
07fb6176 2811 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
72c194f7
MT		 2812
2813 /* Cleanup memory that's no longer used. */
2814 g_array_free(table_offsets, true);
2815}
2816
339240b5 2817static void acpi_ram_update(MemoryRegion *mr, GArray *data)
42d85900
MT		 2818{
2819 uint32_t size = acpi_data_len(data);
2820
2821 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
339240b5 2822 memory_region_ram_resize(mr, size, &error_abort);
42d85900 2823
339240b5
PB		 2824 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2825 memory_region_set_dirty(mr, 0, size);
42d85900
MT		 2826}
2827
3f8752b4 2828static void acpi_build_update(void *build_opaque)
72c194f7
MT		 2829{
2830 AcpiBuildState *build_state = build_opaque;
2831 AcpiBuildTables tables;
2832
2833 /* No state to update or already patched? Nothing to do. */
2834 if (!build_state || build_state->patched) {
2835 return;
2836 }
2837 build_state->patched = 1;
2838
2839 acpi_build_tables_init(&tables);
2840
3d3ebcad 2841 acpi_build(&tables, MACHINE(qdev_get_machine()));
72c194f7 2842
339240b5 2843 acpi_ram_update(build_state->table_mr, tables.table_data);
a1666142 2844
42d85900
MT		 2845 if (build_state->rsdp) {
2846 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2847 } else {
339240b5 2848 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
42d85900 2849 }
ad5b88b1 2850
339240b5 2851 acpi_ram_update(build_state->linker_mr, tables.linker);
72c194f7
MT		 2852 acpi_build_tables_cleanup(&tables, true);
2853}
2854
2855static void acpi_build_reset(void *build_opaque)
2856{
2857 AcpiBuildState *build_state = build_opaque;
2858 build_state->patched = 0;
2859}
2860
339240b5
PB		 2861static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2862 GArray *blob, const char *name,
2863 uint64_t max_size)
72c194f7 2864{
a1666142
MT		 2865 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2866 name, acpi_build_update, build_state);
72c194f7
MT		 2867}
2868
2869static const VMStateDescription vmstate_acpi_build = {
2870 .name = "acpi_build",
2871 .version_id = 1,
2872 .minimum_version_id = 1,
d49805ae 2873 .fields = (VMStateField[]) {
72c194f7
MT		 2874 VMSTATE_UINT8(patched, AcpiBuildState),
2875 VMSTATE_END_OF_LIST()
2876 },
2877};
2878
fb306ffe 2879void acpi_setup(void)
72c194f7 2880{
fb306ffe 2881 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
bb292f5a 2882 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72c194f7
MT		 2883 AcpiBuildTables tables;
2884 AcpiBuildState *build_state;
2885
f264d360 2886 if (!pcms->fw_cfg) {
8b310fc4 2887 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
72c194f7
MT		 2888 return;
2889 }
2890
bb292f5a 2891 if (!pcmc->has_acpi_build) {
8b310fc4 2892 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
72c194f7
MT		 2893 return;
2894 }
2895
81adc513 2896 if (!acpi_enabled) {
8b310fc4 2897 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
81adc513
MT		 2898 return;
2899 }
2900
72c194f7
MT		 2901 build_state = g_malloc0(sizeof *build_state);
2902
99fd437d
MT		 2903 acpi_set_pci_info();
2904
72c194f7 2905 acpi_build_tables_init(&tables);
3d3ebcad 2906 acpi_build(&tables, MACHINE(pcms));
72c194f7
MT		 2907
2908 /* Now expose it all to Guest */
339240b5 2909 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
a1666142
MT		 2910 ACPI_BUILD_TABLE_FILE,
2911 ACPI_BUILD_TABLE_MAX_SIZE);
339240b5 2912 assert(build_state->table_mr != NULL);
72c194f7 2913
339240b5 2914 build_state->linker_mr =
6e00619b 2915 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
72c194f7 2916
f264d360 2917 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
42a5b308
SB		 2918 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2919
bb292f5a 2920 if (!pcmc->rsdp_in_ram) {
358774d7
IM		 2921 /*
2922 * Keep for compatibility with old machine types.
2923 * Though RSDP is small, its contents isn't immutable, so
afaa2e4b 2924 * we'll update it along with the rest of tables on guest access.
358774d7 2925 */
afaa2e4b
MT		 2926 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2927
2928 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
f264d360 2929 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
358774d7 2930 acpi_build_update, build_state,
afaa2e4b 2931 build_state->rsdp, rsdp_size);
339240b5 2932 build_state->rsdp_mr = NULL;
358774d7 2933 } else {
42d85900 2934 build_state->rsdp = NULL;
339240b5 2935 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
42d85900 2936 ACPI_BUILD_RSDP_FILE, 0);
358774d7 2937 }
72c194f7
MT		 2938
2939 qemu_register_reset(acpi_build_reset, build_state);
2940 acpi_build_reset(build_state);
2941 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2942
2943 /* Cleanup tables but don't free the memory: we track it
2944 * in build_state.
2945 */
2946 acpi_build_tables_cleanup(&tables, false);
2947}
QEMU mirror