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72c194f7 MT |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
4 | * Copyright (C) 2006 Fabrice Bellard | |
5 | * Copyright (C) 2013 Red Hat Inc | |
6 | * | |
7 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | ||
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | ||
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
b6a0aa05 | 23 | #include "qemu/osdep.h" |
da34e65c | 24 | #include "qapi/error.h" |
15280c36 | 25 | #include "qapi/qmp/qnum.h" |
72c194f7 | 26 | #include "acpi-build.h" |
eb66ffab | 27 | #include "acpi-common.h" |
72c194f7 | 28 | #include "qemu/bitmap.h" |
07fb6176 | 29 | #include "qemu/error-report.h" |
72c194f7 | 30 | #include "hw/pci/pci.h" |
2e5b09fd | 31 | #include "hw/core/cpu.h" |
fcf5ef2a | 32 | #include "target/i386/cpu.h" |
0d5d8a3a | 33 | #include "hw/misc/pvpanic.h" |
72c194f7 | 34 | #include "hw/timer/hpet.h" |
395e5fb4 | 35 | #include "hw/acpi/acpi-defs.h" |
72c194f7 | 36 | #include "hw/acpi/acpi.h" |
679dd1a9 | 37 | #include "hw/acpi/cpu.h" |
72c194f7 | 38 | #include "hw/nvram/fw_cfg.h" |
0058ae1d | 39 | #include "hw/acpi/bios-linker-loader.h" |
15bce1b7 | 40 | #include "hw/isa/isa.h" |
27b9fc54 | 41 | #include "hw/block/fdc.h" |
bef3492d | 42 | #include "hw/acpi/memory_hotplug.h" |
711b20b4 SB |
43 | #include "sysemu/tpm.h" |
44 | #include "hw/acpi/tpm.h" | |
d03637bc | 45 | #include "hw/acpi/vmgenid.h" |
0e11fc69 | 46 | #include "hw/boards.h" |
5cb18b3d | 47 | #include "sysemu/tpm_backend.h" |
bcdb9064 | 48 | #include "hw/rtc/mc146818rtc_regs.h" |
d6454270 | 49 | #include "migration/vmstate.h" |
2cc0e2e8 | 50 | #include "hw/mem/memory-device.h" |
4b997690 | 51 | #include "hw/mem/nvdimm.h" |
1f3aba37 | 52 | #include "sysemu/numa.h" |
71e8a915 | 53 | #include "sysemu/reset.h" |
6775d15d | 54 | #include "hw/hyperv/vmbus-bridge.h" |
72c194f7 MT |
55 | |
56 | /* Supported chipsets: */ | |
fff123b8 | 57 | #include "hw/southbridge/piix.h" |
99fd437d | 58 | #include "hw/acpi/pcihp.h" |
89a289c7 | 59 | #include "hw/i386/fw_cfg.h" |
72c194f7 MT |
60 | #include "hw/i386/ich9.h" |
61 | #include "hw/pci/pci_bus.h" | |
62 | #include "hw/pci-host/q35.h" | |
1cf5fd57 | 63 | #include "hw/i386/x86-iommu.h" |
72c194f7 | 64 | |
19934e0e | 65 | #include "hw/acpi/aml-build.h" |
82f76c67 | 66 | #include "hw/acpi/utils.h" |
48cefd94 | 67 | #include "hw/acpi/pci.h" |
19934e0e | 68 | |
72c194f7 | 69 | #include "qom/qom-qobject.h" |
fb9f5926 DK |
70 | #include "hw/i386/amd_iommu.h" |
71 | #include "hw/i386/intel_iommu.h" | |
72c194f7 | 72 | |
86e91dd7 | 73 | #include "hw/acpi/ipmi.h" |
e6f123c3 | 74 | #include "hw/acpi/hmat.h" |
86e91dd7 | 75 | |
07fb6176 PB |
76 | /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and |
77 | * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows | |
78 | * a little bit, there should be plenty of free space since the DSDT | |
79 | * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. | |
80 | */ | |
81 | #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 | |
82 | #define ACPI_BUILD_ALIGN_SIZE 0x1000 | |
83 | ||
868270f2 | 84 | #define ACPI_BUILD_TABLE_SIZE 0x20000 |
18045fb9 | 85 | |
8b310fc4 GA |
86 | /* #define DEBUG_ACPI_BUILD */ |
87 | #ifdef DEBUG_ACPI_BUILD | |
88 | #define ACPI_BUILD_DPRINTF(fmt, ...) \ | |
89 | do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) | |
90 | #else | |
91 | #define ACPI_BUILD_DPRINTF(fmt, ...) | |
92 | #endif | |
93 | ||
72c194f7 MT |
94 | typedef struct AcpiPmInfo { |
95 | bool s3_disabled; | |
96 | bool s4_disabled; | |
133a2da4 | 97 | bool pcihp_bridge_en; |
6d837f1f | 98 | bool smi_on_cpuhp; |
892aae74 | 99 | bool smi_on_cpu_unplug; |
df4008c9 | 100 | bool pcihp_root_en; |
72c194f7 | 101 | uint8_t s4_val; |
937d1b58 | 102 | AcpiFadtData fadt; |
ddf1ec2f | 103 | uint16_t cpu_hp_io_base; |
500b11ea IM |
104 | uint16_t pcihp_io_base; |
105 | uint16_t pcihp_io_len; | |
72c194f7 MT |
106 | } AcpiPmInfo; |
107 | ||
108 | typedef struct AcpiMiscInfo { | |
e4db2798 | 109 | bool is_piix4; |
72c194f7 | 110 | bool has_hpet; |
5cb18b3d | 111 | TPMVersion tpm_version; |
72c194f7 MT |
112 | const unsigned char *dsdt_code; |
113 | unsigned dsdt_size; | |
114 | uint16_t pvpanic_port; | |
8ac6f7a6 | 115 | uint16_t applesmc_io_base; |
72c194f7 MT |
116 | } AcpiMiscInfo; |
117 | ||
99fd437d MT |
118 | typedef struct AcpiBuildPciBusHotplugState { |
119 | GArray *device_table; | |
120 | GArray *notify_table; | |
121 | struct AcpiBuildPciBusHotplugState *parent; | |
133a2da4 | 122 | bool pcihp_bridge_en; |
99fd437d MT |
123 | } AcpiBuildPciBusHotplugState; |
124 | ||
0fe24669 SB |
125 | typedef struct FwCfgTPMConfig { |
126 | uint32_t tpmppi_address; | |
127 | uint8_t tpm_version; | |
128 | uint8_t tpmppi_version; | |
129 | } QEMU_PACKED FwCfgTPMConfig; | |
130 | ||
4a441836 GH |
131 | static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); |
132 | ||
5c94b826 KL |
133 | const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { |
134 | .space_id = AML_AS_SYSTEM_IO, | |
135 | .address = NVDIMM_ACPI_IO_BASE, | |
136 | .bit_width = NVDIMM_ACPI_IO_LEN << 3 | |
137 | }; | |
138 | ||
0e11fc69 LX |
139 | static void init_common_fadt_data(MachineState *ms, Object *o, |
140 | AcpiFadtData *data) | |
937d1b58 | 141 | { |
33b44fda IY |
142 | X86MachineState *x86ms = X86_MACHINE(ms); |
143 | /* | |
144 | * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old | |
145 | * behavior for compatibility irrelevant to smm_enabled, which doesn't | |
146 | * comforms to ACPI spec. | |
147 | */ | |
148 | bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? | |
149 | true : x86_machine_is_smm_enabled(x86ms); | |
937d1b58 IM |
150 | uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); |
151 | AmlAddressSpace as = AML_AS_SYSTEM_IO; | |
152 | AcpiFadtData fadt = { | |
153 | .rev = 3, | |
154 | .flags = | |
155 | (1 << ACPI_FADT_F_WBINVD) | | |
156 | (1 << ACPI_FADT_F_PROC_C1) | | |
157 | (1 << ACPI_FADT_F_SLP_BUTTON) | | |
158 | (1 << ACPI_FADT_F_RTC_S4) | | |
159 | (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | | |
160 | /* APIC destination mode ("Flat Logical") has an upper limit of 8 | |
161 | * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be | |
162 | * used | |
163 | */ | |
0e11fc69 LX |
164 | ((ms->smp.max_cpus > 8) ? |
165 | (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), | |
937d1b58 IM |
166 | .int_model = 1 /* Multiple APIC */, |
167 | .rtc_century = RTC_CENTURY, | |
168 | .plvl2_lat = 0xfff /* C2 state not supported */, | |
169 | .plvl3_lat = 0xfff /* C3 state not supported */, | |
33b44fda | 170 | .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, |
937d1b58 IM |
171 | .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), |
172 | .acpi_enable_cmd = | |
33b44fda IY |
173 | smm_enabled ? |
174 | object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : | |
175 | 0, | |
937d1b58 | 176 | .acpi_disable_cmd = |
33b44fda IY |
177 | smm_enabled ? |
178 | object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : | |
179 | 0, | |
937d1b58 IM |
180 | .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, |
181 | .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, | |
182 | .address = io + 0x04 }, | |
183 | .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, | |
184 | .gpe0_blk = { .space_id = as, .bit_width = | |
185 | object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, | |
186 | .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) | |
187 | }, | |
188 | }; | |
189 | *data = fadt; | |
190 | } | |
191 | ||
81c48dd7 PMD |
192 | static Object *object_resolve_type_unambiguous(const char *typename) |
193 | { | |
194 | bool ambig; | |
195 | Object *o = object_resolve_path_type("", typename, &ambig); | |
196 | ||
197 | if (ambig || !o) { | |
198 | return NULL; | |
199 | } | |
200 | return o; | |
201 | } | |
202 | ||
0e11fc69 | 203 | static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) |
72c194f7 | 204 | { |
81c48dd7 PMD |
205 | Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); |
206 | Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); | |
697155cd | 207 | Object *obj = piix ? piix : lpc; |
72c194f7 | 208 | QObject *o; |
94aaca64 | 209 | pm->cpu_hp_io_base = 0; |
500b11ea IM |
210 | pm->pcihp_io_base = 0; |
211 | pm->pcihp_io_len = 0; | |
6d837f1f | 212 | pm->smi_on_cpuhp = false; |
892aae74 | 213 | pm->smi_on_cpu_unplug = false; |
937d1b58 | 214 | |
6fa5171f | 215 | assert(obj); |
a0628599 | 216 | init_common_fadt_data(machine, obj, &pm->fadt); |
72c194f7 | 217 | if (piix) { |
3a3fcc75 | 218 | /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ |
937d1b58 | 219 | pm->fadt.rev = 1; |
ddf1ec2f | 220 | pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; |
500b11ea | 221 | pm->pcihp_io_base = |
35f91e50 | 222 | object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); |
500b11ea | 223 | pm->pcihp_io_len = |
35f91e50 | 224 | object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); |
72c194f7 MT |
225 | } |
226 | if (lpc) { | |
6d837f1f IM |
227 | uint64_t smi_features = object_property_get_uint(lpc, |
228 | ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); | |
937d1b58 IM |
229 | struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, |
230 | .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; | |
231 | pm->fadt.reset_reg = r; | |
232 | pm->fadt.reset_val = 0xf; | |
233 | pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; | |
ddf1ec2f | 234 | pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; |
6d837f1f IM |
235 | pm->smi_on_cpuhp = |
236 | !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); | |
892aae74 IM |
237 | pm->smi_on_cpu_unplug = |
238 | !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); | |
72c194f7 | 239 | } |
72c194f7 | 240 | |
937d1b58 IM |
241 | /* The above need not be conditional on machine type because the reset port |
242 | * happens to be the same on PIIX (pc) and ICH9 (q35). */ | |
0063454a | 243 | QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); |
937d1b58 | 244 | |
72c194f7 MT |
245 | /* Fill in optional s3/s4 related properties */ |
246 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); | |
247 | if (o) { | |
7dc847eb | 248 | pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); |
72c194f7 MT |
249 | } else { |
250 | pm->s3_disabled = false; | |
251 | } | |
cb3e7f08 | 252 | qobject_unref(o); |
72c194f7 MT |
253 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); |
254 | if (o) { | |
7dc847eb | 255 | pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); |
72c194f7 MT |
256 | } else { |
257 | pm->s4_disabled = false; | |
258 | } | |
cb3e7f08 | 259 | qobject_unref(o); |
72c194f7 MT |
260 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); |
261 | if (o) { | |
7dc847eb | 262 | pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); |
72c194f7 MT |
263 | } else { |
264 | pm->s4_val = false; | |
265 | } | |
cb3e7f08 | 266 | qobject_unref(o); |
72c194f7 | 267 | |
133a2da4 IM |
268 | pm->pcihp_bridge_en = |
269 | object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", | |
270 | NULL); | |
df4008c9 AS |
271 | pm->pcihp_root_en = |
272 | object_property_get_bool(obj, "acpi-root-pci-hotplug", | |
273 | NULL); | |
72c194f7 MT |
274 | } |
275 | ||
72c194f7 MT |
276 | static void acpi_get_misc_info(AcpiMiscInfo *info) |
277 | { | |
81c48dd7 PMD |
278 | Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); |
279 | Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); | |
3db119da IM |
280 | assert(!!piix != !!lpc); |
281 | ||
282 | if (piix) { | |
283 | info->is_piix4 = true; | |
284 | } | |
285 | if (lpc) { | |
286 | info->is_piix4 = false; | |
287 | } | |
288 | ||
72c194f7 | 289 | info->has_hpet = hpet_find(); |
3dfd5a2a | 290 | info->tpm_version = tpm_get_version(tpm_find()); |
72c194f7 | 291 | info->pvpanic_port = pvpanic_port(); |
8ac6f7a6 | 292 | info->applesmc_io_base = applesmc_port(); |
72c194f7 MT |
293 | } |
294 | ||
ca6c1855 MA |
295 | /* |
296 | * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. | |
297 | * On i386 arch we only have two pci hosts, so we can look only for them. | |
298 | */ | |
299 | static Object *acpi_get_i386_pci_host(void) | |
300 | { | |
301 | PCIHostState *host; | |
302 | ||
303 | host = OBJECT_CHECK(PCIHostState, | |
304 | object_resolve_path("/machine/i440fx", NULL), | |
305 | TYPE_PCI_HOST_BRIDGE); | |
306 | if (!host) { | |
307 | host = OBJECT_CHECK(PCIHostState, | |
308 | object_resolve_path("/machine/q35", NULL), | |
309 | TYPE_PCI_HOST_BRIDGE); | |
310 | } | |
311 | ||
312 | return OBJECT(host); | |
313 | } | |
314 | ||
01c9742d | 315 | static void acpi_get_pci_holes(Range *hole, Range *hole64) |
72c194f7 MT |
316 | { |
317 | Object *pci_host; | |
72c194f7 | 318 | |
ca6c1855 | 319 | pci_host = acpi_get_i386_pci_host(); |
72c194f7 MT |
320 | g_assert(pci_host); |
321 | ||
a0efbf16 | 322 | range_set_bounds1(hole, |
60555365 MAL |
323 | object_property_get_uint(pci_host, |
324 | PCI_HOST_PROP_PCI_HOLE_START, | |
325 | NULL), | |
326 | object_property_get_uint(pci_host, | |
327 | PCI_HOST_PROP_PCI_HOLE_END, | |
328 | NULL)); | |
a0efbf16 | 329 | range_set_bounds1(hole64, |
60555365 MAL |
330 | object_property_get_uint(pci_host, |
331 | PCI_HOST_PROP_PCI_HOLE64_START, | |
332 | NULL), | |
333 | object_property_get_uint(pci_host, | |
334 | PCI_HOST_PROP_PCI_HOLE64_END, | |
335 | NULL)); | |
72c194f7 MT |
336 | } |
337 | ||
72c194f7 MT |
338 | static void acpi_align_size(GArray *blob, unsigned align) |
339 | { | |
340 | /* Align size to multiple of given size. This reduces the chance | |
341 | * we need to change size in the future (breaking cross version migration). | |
342 | */ | |
134d42d6 | 343 | g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); |
72c194f7 MT |
344 | } |
345 | ||
72c194f7 MT |
346 | /* FACS */ |
347 | static void | |
009180bd | 348 | build_facs(GArray *table_data) |
72c194f7 MT |
349 | { |
350 | AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); | |
821e3227 | 351 | memcpy(&facs->signature, "FACS", 4); |
72c194f7 MT |
352 | facs->length = cpu_to_le32(sizeof(*facs)); |
353 | } | |
354 | ||
62b52c26 | 355 | static void build_append_pcihp_notify_entry(Aml *method, int slot) |
99fd437d | 356 | { |
62b52c26 IM |
357 | Aml *if_ctx; |
358 | int32_t devfn = PCI_DEVFN(slot, 0); | |
359 | ||
5530427f | 360 | if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); |
62b52c26 IM |
361 | aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); |
362 | aml_append(method, if_ctx); | |
99fd437d MT |
363 | } |
364 | ||
62b52c26 | 365 | static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, |
b23046ab | 366 | bool pcihp_bridge_en) |
99fd437d | 367 | { |
7dc847eb | 368 | Aml *dev, *notify_method = NULL, *method; |
99fd437d | 369 | QObject *bsel; |
b23046ab IM |
370 | PCIBus *sec; |
371 | int i; | |
133a2da4 | 372 | |
99fd437d MT |
373 | bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); |
374 | if (bsel) { | |
7dc847eb | 375 | uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); |
62b52c26 IM |
376 | |
377 | aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); | |
4dbfc881 | 378 | notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); |
8dcf525a | 379 | } |
99fd437d | 380 | |
8dcf525a MT |
381 | for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { |
382 | DeviceClass *dc; | |
383 | PCIDeviceClass *pc; | |
384 | PCIDevice *pdev = bus->devices[i]; | |
385 | int slot = PCI_SLOT(i); | |
b23046ab | 386 | bool hotplug_enabled_dev; |
093a35e5 | 387 | bool bridge_in_acpi; |
15a5b254 | 388 | bool cold_plugged_bridge; |
99fd437d | 389 | |
8dcf525a | 390 | if (!pdev) { |
b23046ab | 391 | if (bsel) { /* add hotplug slots for non present devices */ |
62b52c26 IM |
392 | dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); |
393 | aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); | |
394 | aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); | |
4dbfc881 | 395 | method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); |
62b52c26 IM |
396 | aml_append(method, |
397 | aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) | |
398 | ); | |
399 | aml_append(dev, method); | |
b7f23f62 IM |
400 | method = aml_method("_DSM", 4, AML_SERIALIZED); |
401 | aml_append(method, | |
402 | aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1), | |
403 | aml_arg(2), aml_arg(3), | |
404 | aml_name("BSEL"), aml_name("_SUN"))) | |
405 | ); | |
406 | aml_append(dev, method); | |
62b52c26 IM |
407 | aml_append(parent_scope, dev); |
408 | ||
409 | build_append_pcihp_notify_entry(notify_method, slot); | |
b23046ab | 410 | } |
8dcf525a MT |
411 | continue; |
412 | } | |
99fd437d | 413 | |
8dcf525a MT |
414 | pc = PCI_DEVICE_GET_CLASS(pdev); |
415 | dc = DEVICE_GET_CLASS(pdev); | |
99fd437d | 416 | |
15a5b254 AS |
417 | /* |
418 | * Cold plugged bridges aren't themselves hot-pluggable. | |
a20275fa | 419 | * Hotplugged bridges *are* hot-pluggable. |
093a35e5 | 420 | */ |
15a5b254 AS |
421 | cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; |
422 | bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; | |
b23046ab | 423 | |
15a5b254 | 424 | hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; |
093a35e5 | 425 | |
b23046ab IM |
426 | if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { |
427 | continue; | |
99fd437d MT |
428 | } |
429 | ||
62b52c26 IM |
430 | /* start to compose PCI slot descriptor */ |
431 | dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); | |
432 | aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); | |
433 | ||
b7f23f62 IM |
434 | if (bsel) { |
435 | aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); | |
436 | method = aml_method("_DSM", 4, AML_SERIALIZED); | |
437 | aml_append(method, aml_return( | |
438 | aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2), | |
439 | aml_arg(3), aml_name("BSEL"), aml_name("_SUN")) | |
440 | )); | |
441 | aml_append(dev, method); | |
442 | } | |
443 | ||
8dcf525a | 444 | if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { |
62b52c26 IM |
445 | /* add VGA specific AML methods */ |
446 | int s3d; | |
447 | ||
8dcf525a | 448 | if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { |
62b52c26 | 449 | s3d = 3; |
b23046ab | 450 | } else { |
62b52c26 | 451 | s3d = 0; |
99fd437d | 452 | } |
62b52c26 | 453 | |
4dbfc881 | 454 | method = aml_method("_S1D", 0, AML_NOTSERIALIZED); |
62b52c26 IM |
455 | aml_append(method, aml_return(aml_int(0))); |
456 | aml_append(dev, method); | |
457 | ||
4dbfc881 | 458 | method = aml_method("_S2D", 0, AML_NOTSERIALIZED); |
62b52c26 IM |
459 | aml_append(method, aml_return(aml_int(0))); |
460 | aml_append(dev, method); | |
461 | ||
4dbfc881 | 462 | method = aml_method("_S3D", 0, AML_NOTSERIALIZED); |
62b52c26 IM |
463 | aml_append(method, aml_return(aml_int(s3d))); |
464 | aml_append(dev, method); | |
b23046ab | 465 | } else if (hotplug_enabled_dev) { |
b7f23f62 | 466 | /* add _EJ0 to make slot hotpluggable */ |
4dbfc881 | 467 | method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); |
62b52c26 IM |
468 | aml_append(method, |
469 | aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) | |
470 | ); | |
471 | aml_append(dev, method); | |
472 | ||
473 | if (bsel) { | |
474 | build_append_pcihp_notify_entry(notify_method, slot); | |
475 | } | |
b23046ab | 476 | } else if (bridge_in_acpi) { |
62b52c26 IM |
477 | /* |
478 | * device is coldplugged bridge, | |
479 | * add child device descriptions into its scope | |
480 | */ | |
b23046ab | 481 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); |
b23046ab | 482 | |
62b52c26 | 483 | build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); |
8dcf525a | 484 | } |
62b52c26 IM |
485 | /* slot descriptor has been composed, add it into parent context */ |
486 | aml_append(parent_scope, dev); | |
8dcf525a MT |
487 | } |
488 | ||
489 | if (bsel) { | |
62b52c26 | 490 | aml_append(parent_scope, notify_method); |
99fd437d MT |
491 | } |
492 | ||
493 | /* Append PCNT method to notify about events on local and child buses. | |
df4008c9 AS |
494 | * Add this method for root bus only when hotplug is enabled since DSDT |
495 | * expects it. | |
72c194f7 | 496 | */ |
df4008c9 AS |
497 | if (bsel || pcihp_bridge_en) { |
498 | method = aml_method("PCNT", 0, AML_NOTSERIALIZED); | |
01b2ffce | 499 | |
811c74fb PMD |
500 | /* If bus supports hotplug select it and notify about local events */ |
501 | if (bsel) { | |
502 | uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); | |
503 | ||
504 | aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); | |
505 | aml_append(method, aml_call2("DVNT", aml_name("PCIU"), | |
506 | aml_int(1))); /* Device Check */ | |
507 | aml_append(method, aml_call2("DVNT", aml_name("PCID"), | |
508 | aml_int(3))); /* Eject Request */ | |
509 | } | |
99fd437d | 510 | |
811c74fb PMD |
511 | /* Notify about child bus events in any case */ |
512 | if (pcihp_bridge_en) { | |
513 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
514 | int32_t devfn = sec->parent_dev->devfn; | |
62b52c26 | 515 | |
811c74fb PMD |
516 | if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { |
517 | continue; | |
518 | } | |
c99cb18e | 519 | |
811c74fb PMD |
520 | aml_append(method, aml_name("^S%.02X.PCNT", devfn)); |
521 | } | |
99fd437d | 522 | } |
df4008c9 | 523 | |
df4008c9 AS |
524 | aml_append(parent_scope, method); |
525 | } | |
cb3e7f08 | 526 | qobject_unref(bsel); |
72c194f7 MT |
527 | } |
528 | ||
b7f23f62 IM |
529 | Aml *aml_pci_device_dsm(void) |
530 | { | |
531 | Aml *method, *UUID, *ifctx, *ifctx1, *ifctx2, *ifctx3, *elsectx; | |
532 | Aml *acpi_index = aml_local(0); | |
533 | Aml *zero = aml_int(0); | |
534 | Aml *bnum = aml_arg(4); | |
535 | Aml *func = aml_arg(2); | |
536 | Aml *rev = aml_arg(1); | |
537 | Aml *sun = aml_arg(5); | |
538 | ||
539 | method = aml_method("PDSM", 6, AML_SERIALIZED); | |
540 | ||
541 | /* | |
542 | * PCI Firmware Specification 3.1 | |
543 | * 4.6. _DSM Definitions for PCI | |
544 | */ | |
545 | UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); | |
546 | ifctx = aml_if(aml_equal(aml_arg(0), UUID)); | |
547 | { | |
548 | aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index)); | |
549 | ifctx1 = aml_if(aml_equal(func, zero)); | |
550 | { | |
551 | uint8_t byte_list[1]; | |
552 | ||
553 | ifctx2 = aml_if(aml_equal(rev, aml_int(2))); | |
554 | { | |
555 | /* | |
556 | * advertise function 7 if device has acpi-index | |
557 | * acpi_index values: | |
558 | * 0: not present (default value) | |
559 | * FFFFFFFF: not supported (old QEMU without PIDX reg) | |
560 | * other: device's acpi-index | |
561 | */ | |
562 | ifctx3 = aml_if(aml_lnot( | |
563 | aml_or(aml_equal(acpi_index, zero), | |
564 | aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) | |
565 | )); | |
566 | { | |
567 | byte_list[0] = | |
568 | 1 /* have supported functions */ | | |
569 | 1 << 7 /* support for function 7 */ | |
570 | ; | |
571 | aml_append(ifctx3, aml_return(aml_buffer(1, byte_list))); | |
572 | } | |
573 | aml_append(ifctx2, ifctx3); | |
574 | } | |
575 | aml_append(ifctx1, ifctx2); | |
576 | ||
577 | byte_list[0] = 0; /* nothing supported */ | |
578 | aml_append(ifctx1, aml_return(aml_buffer(1, byte_list))); | |
579 | } | |
580 | aml_append(ifctx, ifctx1); | |
581 | elsectx = aml_else(); | |
582 | /* | |
583 | * PCI Firmware Specification 3.1 | |
584 | * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under | |
585 | * Operating Systems | |
586 | */ | |
587 | ifctx1 = aml_if(aml_equal(func, aml_int(7))); | |
588 | { | |
589 | Aml *pkg = aml_package(2); | |
590 | Aml *ret = aml_local(1); | |
591 | ||
592 | aml_append(pkg, zero); | |
593 | /* | |
594 | * optional, if not impl. should return null string | |
595 | */ | |
596 | aml_append(pkg, aml_string("%s", "")); | |
597 | aml_append(ifctx1, aml_store(pkg, ret)); | |
598 | /* | |
599 | * update acpi-index to actual value | |
600 | */ | |
601 | aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero))); | |
602 | aml_append(ifctx1, aml_return(ret)); | |
603 | } | |
604 | aml_append(elsectx, ifctx1); | |
605 | aml_append(ifctx, elsectx); | |
606 | } | |
607 | aml_append(method, ifctx); | |
608 | return method; | |
609 | } | |
610 | ||
196e2137 IM |
611 | /** |
612 | * build_prt_entry: | |
613 | * @link_name: link name for PCI route entry | |
614 | * | |
615 | * build AML package containing a PCI route entry for @link_name | |
616 | */ | |
617 | static Aml *build_prt_entry(const char *link_name) | |
618 | { | |
619 | Aml *a_zero = aml_int(0); | |
620 | Aml *pkg = aml_package(4); | |
621 | aml_append(pkg, a_zero); | |
622 | aml_append(pkg, a_zero); | |
623 | aml_append(pkg, aml_name("%s", link_name)); | |
624 | aml_append(pkg, a_zero); | |
625 | return pkg; | |
626 | } | |
627 | ||
0d8935e3 MA |
628 | /* |
629 | * initialize_route - Initialize the interrupt routing rule | |
630 | * through a specific LINK: | |
631 | * if (lnk_idx == idx) | |
632 | * route using link 'link_name' | |
633 | */ | |
634 | static Aml *initialize_route(Aml *route, const char *link_name, | |
635 | Aml *lnk_idx, int idx) | |
636 | { | |
637 | Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); | |
196e2137 | 638 | Aml *pkg = build_prt_entry(link_name); |
0d8935e3 | 639 | |
0d8935e3 MA |
640 | aml_append(if_ctx, aml_store(pkg, route)); |
641 | ||
642 | return if_ctx; | |
643 | } | |
644 | ||
645 | /* | |
646 | * build_prt - Define interrupt rounting rules | |
647 | * | |
648 | * Returns an array of 128 routes, one for each device, | |
649 | * based on device location. | |
650 | * The main goal is to equaly distribute the interrupts | |
651 | * over the 4 existing ACPI links (works only for i440fx). | |
652 | * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". | |
653 | * | |
654 | */ | |
196e2137 | 655 | static Aml *build_prt(bool is_pci0_prt) |
0d8935e3 MA |
656 | { |
657 | Aml *method, *while_ctx, *pin, *res; | |
658 | ||
4dbfc881 | 659 | method = aml_method("_PRT", 0, AML_NOTSERIALIZED); |
0d8935e3 MA |
660 | res = aml_local(0); |
661 | pin = aml_local(1); | |
662 | aml_append(method, aml_store(aml_package(128), res)); | |
663 | aml_append(method, aml_store(aml_int(0), pin)); | |
664 | ||
665 | /* while (pin < 128) */ | |
666 | while_ctx = aml_while(aml_lless(pin, aml_int(128))); | |
667 | { | |
668 | Aml *slot = aml_local(2); | |
669 | Aml *lnk_idx = aml_local(3); | |
670 | Aml *route = aml_local(4); | |
671 | ||
672 | /* slot = pin >> 2 */ | |
673 | aml_append(while_ctx, | |
c360639a | 674 | aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); |
0d8935e3 MA |
675 | /* lnk_idx = (slot + pin) & 3 */ |
676 | aml_append(while_ctx, | |
5530427f IM |
677 | aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), |
678 | lnk_idx)); | |
0d8935e3 MA |
679 | |
680 | /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ | |
681 | aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); | |
196e2137 IM |
682 | if (is_pci0_prt) { |
683 | Aml *if_device_1, *if_pin_4, *else_pin_4; | |
684 | ||
685 | /* device 1 is the power-management device, needs SCI */ | |
686 | if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); | |
687 | { | |
688 | if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); | |
689 | { | |
690 | aml_append(if_pin_4, | |
691 | aml_store(build_prt_entry("LNKS"), route)); | |
692 | } | |
693 | aml_append(if_device_1, if_pin_4); | |
694 | else_pin_4 = aml_else(); | |
695 | { | |
696 | aml_append(else_pin_4, | |
697 | aml_store(build_prt_entry("LNKA"), route)); | |
698 | } | |
699 | aml_append(if_device_1, else_pin_4); | |
700 | } | |
701 | aml_append(while_ctx, if_device_1); | |
702 | } else { | |
703 | aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); | |
704 | } | |
0d8935e3 MA |
705 | aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); |
706 | aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); | |
707 | ||
708 | /* route[0] = 0x[slot]FFFF */ | |
709 | aml_append(while_ctx, | |
ca3df95d IM |
710 | aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), |
711 | NULL), | |
0d8935e3 MA |
712 | aml_index(route, aml_int(0)))); |
713 | /* route[1] = pin & 3 */ | |
714 | aml_append(while_ctx, | |
5530427f IM |
715 | aml_store(aml_and(pin, aml_int(3), NULL), |
716 | aml_index(route, aml_int(1)))); | |
0d8935e3 MA |
717 | /* res[pin] = route */ |
718 | aml_append(while_ctx, aml_store(route, aml_index(res, pin))); | |
719 | /* pin++ */ | |
720 | aml_append(while_ctx, aml_increment(pin)); | |
721 | } | |
722 | aml_append(method, while_ctx); | |
723 | /* return res*/ | |
724 | aml_append(method, aml_return(res)); | |
725 | ||
726 | return method; | |
727 | } | |
728 | ||
a57d708d IM |
729 | static void build_hpet_aml(Aml *table) |
730 | { | |
731 | Aml *crs; | |
732 | Aml *field; | |
733 | Aml *method; | |
734 | Aml *if_ctx; | |
735 | Aml *scope = aml_scope("_SB"); | |
736 | Aml *dev = aml_device("HPET"); | |
737 | Aml *zero = aml_int(0); | |
738 | Aml *id = aml_local(0); | |
739 | Aml *period = aml_local(1); | |
740 | ||
741 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); | |
742 | aml_append(dev, aml_name_decl("_UID", zero)); | |
743 | ||
744 | aml_append(dev, | |
3f3009c0 XG |
745 | aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), |
746 | HPET_LEN)); | |
a57d708d IM |
747 | field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); |
748 | aml_append(field, aml_named_field("VEND", 32)); | |
749 | aml_append(field, aml_named_field("PRD", 32)); | |
750 | aml_append(dev, field); | |
751 | ||
752 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
753 | aml_append(method, aml_store(aml_name("VEND"), id)); | |
754 | aml_append(method, aml_store(aml_name("PRD"), period)); | |
755 | aml_append(method, aml_shiftright(id, aml_int(16), id)); | |
756 | if_ctx = aml_if(aml_lor(aml_equal(id, zero), | |
757 | aml_equal(id, aml_int(0xffff)))); | |
758 | { | |
759 | aml_append(if_ctx, aml_return(zero)); | |
760 | } | |
761 | aml_append(method, if_ctx); | |
762 | ||
763 | if_ctx = aml_if(aml_lor(aml_equal(period, zero), | |
764 | aml_lgreater(period, aml_int(100000000)))); | |
765 | { | |
766 | aml_append(if_ctx, aml_return(zero)); | |
767 | } | |
768 | aml_append(method, if_ctx); | |
769 | ||
770 | aml_append(method, aml_return(aml_int(0x0F))); | |
771 | aml_append(dev, method); | |
772 | ||
773 | crs = aml_resource_template(); | |
774 | aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); | |
775 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
776 | ||
777 | aml_append(scope, dev); | |
778 | aml_append(table, scope); | |
779 | } | |
780 | ||
6775d15d JD |
781 | static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) |
782 | { | |
783 | Aml *dev; | |
784 | Aml *method; | |
785 | Aml *crs; | |
786 | ||
787 | dev = aml_device("VMBS"); | |
788 | aml_append(dev, aml_name_decl("STA", aml_int(0xF))); | |
789 | aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); | |
790 | aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); | |
791 | aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); | |
792 | ||
793 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
794 | aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), | |
795 | aml_name("STA"))); | |
796 | aml_append(dev, method); | |
797 | ||
798 | method = aml_method("_PS0", 0, AML_NOTSERIALIZED); | |
799 | aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), | |
800 | aml_name("STA"))); | |
801 | aml_append(dev, method); | |
802 | ||
803 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
804 | aml_append(method, aml_return(aml_name("STA"))); | |
805 | aml_append(dev, method); | |
806 | ||
807 | aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); | |
808 | ||
809 | crs = aml_resource_template(); | |
8f06f22f | 810 | aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); |
6775d15d JD |
811 | aml_append(dev, aml_name_decl("_CRS", crs)); |
812 | ||
813 | return dev; | |
814 | } | |
815 | ||
ee135849 IM |
816 | static void build_isa_devices_aml(Aml *table) |
817 | { | |
86e91dd7 | 818 | bool ambiguous; |
86e91dd7 | 819 | Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); |
13371f9b | 820 | Aml *scope; |
ee135849 | 821 | |
13371f9b GH |
822 | assert(obj && !ambiguous); |
823 | ||
824 | scope = aml_scope("_SB.PCI0.ISA"); | |
825 | build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); | |
826 | isa_build_aml(ISA_BUS(obj), scope); | |
86e91dd7 | 827 | |
ee135849 IM |
828 | aml_append(table, scope); |
829 | } | |
830 | ||
3892a2b7 IM |
831 | static void build_dbg_aml(Aml *table) |
832 | { | |
833 | Aml *field; | |
834 | Aml *method; | |
835 | Aml *while_ctx; | |
836 | Aml *scope = aml_scope("\\"); | |
837 | Aml *buf = aml_local(0); | |
838 | Aml *len = aml_local(1); | |
839 | Aml *idx = aml_local(2); | |
840 | ||
841 | aml_append(scope, | |
3f3009c0 | 842 | aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); |
3892a2b7 IM |
843 | field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); |
844 | aml_append(field, aml_named_field("DBGB", 8)); | |
845 | aml_append(scope, field); | |
846 | ||
847 | method = aml_method("DBUG", 1, AML_NOTSERIALIZED); | |
848 | ||
849 | aml_append(method, aml_to_hexstring(aml_arg(0), buf)); | |
850 | aml_append(method, aml_to_buffer(buf, buf)); | |
851 | aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); | |
852 | aml_append(method, aml_store(aml_int(0), idx)); | |
853 | ||
854 | while_ctx = aml_while(aml_lless(idx, len)); | |
855 | aml_append(while_ctx, | |
856 | aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); | |
857 | aml_append(while_ctx, aml_increment(idx)); | |
858 | aml_append(method, while_ctx); | |
859 | ||
860 | aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); | |
861 | aml_append(scope, method); | |
862 | ||
863 | aml_append(table, scope); | |
864 | } | |
865 | ||
c35b6e80 IM |
866 | static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) |
867 | { | |
868 | Aml *dev; | |
869 | Aml *crs; | |
870 | Aml *method; | |
871 | uint32_t irqs[] = {5, 10, 11}; | |
872 | ||
873 | dev = aml_device("%s", name); | |
874 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); | |
875 | aml_append(dev, aml_name_decl("_UID", aml_int(uid))); | |
876 | ||
877 | crs = aml_resource_template(); | |
878 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
879 | AML_SHARED, irqs, ARRAY_SIZE(irqs))); | |
880 | aml_append(dev, aml_name_decl("_PRS", crs)); | |
881 | ||
882 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
883 | aml_append(method, aml_return(aml_call1("IQST", reg))); | |
884 | aml_append(dev, method); | |
885 | ||
886 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
887 | aml_append(method, aml_or(reg, aml_int(0x80), reg)); | |
888 | aml_append(dev, method); | |
889 | ||
890 | method = aml_method("_CRS", 0, AML_NOTSERIALIZED); | |
891 | aml_append(method, aml_return(aml_call1("IQCR", reg))); | |
892 | aml_append(dev, method); | |
893 | ||
894 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); | |
895 | aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); | |
896 | aml_append(method, aml_store(aml_name("PRRI"), reg)); | |
897 | aml_append(dev, method); | |
898 | ||
899 | return dev; | |
900 | } | |
901 | ||
80b32df5 IM |
902 | static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) |
903 | { | |
904 | Aml *dev; | |
905 | Aml *crs; | |
906 | Aml *method; | |
907 | uint32_t irqs; | |
908 | ||
909 | dev = aml_device("%s", name); | |
910 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); | |
911 | aml_append(dev, aml_name_decl("_UID", aml_int(uid))); | |
912 | ||
913 | crs = aml_resource_template(); | |
914 | irqs = gsi; | |
915 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
916 | AML_SHARED, &irqs, 1)); | |
917 | aml_append(dev, aml_name_decl("_PRS", crs)); | |
918 | ||
919 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
920 | ||
c82f503d MA |
921 | /* |
922 | * _DIS can be no-op because the interrupt cannot be disabled. | |
923 | */ | |
924 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
925 | aml_append(dev, method); | |
926 | ||
80b32df5 IM |
927 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); |
928 | aml_append(dev, method); | |
929 | ||
930 | return dev; | |
931 | } | |
932 | ||
16682a9d IM |
933 | /* _CRS method - get current settings */ |
934 | static Aml *build_iqcr_method(bool is_piix4) | |
935 | { | |
936 | Aml *if_ctx; | |
937 | uint32_t irqs; | |
938 | Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); | |
939 | Aml *crs = aml_resource_template(); | |
940 | ||
941 | irqs = 0; | |
942 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, | |
943 | AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); | |
944 | aml_append(method, aml_name_decl("PRR0", crs)); | |
945 | ||
946 | aml_append(method, | |
947 | aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); | |
948 | ||
949 | if (is_piix4) { | |
950 | if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); | |
951 | aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); | |
952 | aml_append(method, if_ctx); | |
953 | } else { | |
954 | aml_append(method, | |
955 | aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), | |
956 | aml_name("PRRI"))); | |
957 | } | |
958 | ||
959 | aml_append(method, aml_return(aml_name("PRR0"))); | |
960 | return method; | |
961 | } | |
962 | ||
78e1ad05 IM |
963 | /* _STA method - get status */ |
964 | static Aml *build_irq_status_method(void) | |
965 | { | |
966 | Aml *if_ctx; | |
967 | Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); | |
968 | ||
969 | if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); | |
970 | aml_append(if_ctx, aml_return(aml_int(0x09))); | |
971 | aml_append(method, if_ctx); | |
972 | aml_append(method, aml_return(aml_int(0x0B))); | |
973 | return method; | |
974 | } | |
975 | ||
e4db2798 IM |
976 | static void build_piix4_pci0_int(Aml *table) |
977 | { | |
c35b6e80 IM |
978 | Aml *dev; |
979 | Aml *crs; | |
e4db2798 | 980 | Aml *field; |
c35b6e80 IM |
981 | Aml *method; |
982 | uint32_t irqs; | |
e4db2798 | 983 | Aml *sb_scope = aml_scope("_SB"); |
196e2137 IM |
984 | Aml *pci0_scope = aml_scope("PCI0"); |
985 | ||
986 | aml_append(pci0_scope, build_prt(true)); | |
987 | aml_append(sb_scope, pci0_scope); | |
e4db2798 IM |
988 | |
989 | field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); | |
990 | aml_append(field, aml_named_field("PRQ0", 8)); | |
991 | aml_append(field, aml_named_field("PRQ1", 8)); | |
992 | aml_append(field, aml_named_field("PRQ2", 8)); | |
993 | aml_append(field, aml_named_field("PRQ3", 8)); | |
994 | aml_append(sb_scope, field); | |
995 | ||
78e1ad05 | 996 | aml_append(sb_scope, build_irq_status_method()); |
16682a9d | 997 | aml_append(sb_scope, build_iqcr_method(true)); |
100681cc | 998 | |
c35b6e80 IM |
999 | aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); |
1000 | aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); | |
1001 | aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); | |
1002 | aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); | |
1003 | ||
1004 | dev = aml_device("LNKS"); | |
1005 | { | |
1006 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); | |
1007 | aml_append(dev, aml_name_decl("_UID", aml_int(4))); | |
1008 | ||
1009 | crs = aml_resource_template(); | |
1010 | irqs = 9; | |
1011 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, | |
1012 | AML_ACTIVE_HIGH, AML_SHARED, | |
1013 | &irqs, 1)); | |
1014 | aml_append(dev, aml_name_decl("_PRS", crs)); | |
1015 | ||
1016 | /* The SCI cannot be disabled and is always attached to GSI 9, | |
1017 | * so these are no-ops. We only need this link to override the | |
1018 | * polarity to active high and match the content of the MADT. | |
1019 | */ | |
1020 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
1021 | aml_append(method, aml_return(aml_int(0x0b))); | |
1022 | aml_append(dev, method); | |
1023 | ||
1024 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
1025 | aml_append(dev, method); | |
1026 | ||
1027 | method = aml_method("_CRS", 0, AML_NOTSERIALIZED); | |
1028 | aml_append(method, aml_return(aml_name("_PRS"))); | |
1029 | aml_append(dev, method); | |
1030 | ||
1031 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); | |
1032 | aml_append(dev, method); | |
1033 | } | |
1034 | aml_append(sb_scope, dev); | |
1035 | ||
e4db2798 IM |
1036 | aml_append(table, sb_scope); |
1037 | } | |
1038 | ||
22b5b8bf IM |
1039 | static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) |
1040 | { | |
1041 | int i; | |
1042 | int head; | |
1043 | Aml *pkg; | |
1044 | char base = name[3] < 'E' ? 'A' : 'E'; | |
1045 | char *s = g_strdup(name); | |
1046 | Aml *a_nr = aml_int((nr << 16) | 0xffff); | |
1047 | ||
1048 | assert(strlen(s) == 4); | |
1049 | ||
1050 | head = name[3] - base; | |
1051 | for (i = 0; i < 4; i++) { | |
1052 | if (head + i > 3) { | |
1053 | head = i * -1; | |
1054 | } | |
1055 | s[3] = base + head + i; | |
1056 | pkg = aml_package(4); | |
1057 | aml_append(pkg, a_nr); | |
1058 | aml_append(pkg, aml_int(i)); | |
1059 | aml_append(pkg, aml_name("%s", s)); | |
1060 | aml_append(pkg, aml_int(0)); | |
1061 | aml_append(ctx, pkg); | |
1062 | } | |
1063 | g_free(s); | |
1064 | } | |
1065 | ||
1066 | static Aml *build_q35_routing_table(const char *str) | |
1067 | { | |
1068 | int i; | |
1069 | Aml *pkg; | |
1070 | char *name = g_strdup_printf("%s ", str); | |
1071 | ||
1072 | pkg = aml_package(128); | |
1073 | for (i = 0; i < 0x18; i++) { | |
1074 | name[3] = 'E' + (i & 0x3); | |
1075 | append_q35_prt_entry(pkg, i, name); | |
1076 | } | |
1077 | ||
1078 | name[3] = 'E'; | |
1079 | append_q35_prt_entry(pkg, 0x18, name); | |
1080 | ||
1081 | /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ | |
1082 | for (i = 0x0019; i < 0x1e; i++) { | |
1083 | name[3] = 'A'; | |
1084 | append_q35_prt_entry(pkg, i, name); | |
1085 | } | |
1086 | ||
1087 | /* PCIe->PCI bridge. use PIRQ[E-H] */ | |
1088 | name[3] = 'E'; | |
1089 | append_q35_prt_entry(pkg, 0x1e, name); | |
1090 | name[3] = 'A'; | |
1091 | append_q35_prt_entry(pkg, 0x1f, name); | |
1092 | ||
1093 | g_free(name); | |
1094 | return pkg; | |
1095 | } | |
1096 | ||
80b32df5 IM |
1097 | static void build_q35_pci0_int(Aml *table) |
1098 | { | |
41f95a52 | 1099 | Aml *field; |
0dafe3b3 | 1100 | Aml *method; |
80b32df5 | 1101 | Aml *sb_scope = aml_scope("_SB"); |
0dafe3b3 IM |
1102 | Aml *pci0_scope = aml_scope("PCI0"); |
1103 | ||
e9fce798 IM |
1104 | /* Zero => PIC mode, One => APIC Mode */ |
1105 | aml_append(table, aml_name_decl("PICF", aml_int(0))); | |
1106 | method = aml_method("_PIC", 1, AML_NOTSERIALIZED); | |
1107 | { | |
1108 | aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); | |
1109 | } | |
1110 | aml_append(table, method); | |
1111 | ||
65aef4de IM |
1112 | aml_append(pci0_scope, |
1113 | aml_name_decl("PRTP", build_q35_routing_table("LNK"))); | |
22b5b8bf IM |
1114 | aml_append(pci0_scope, |
1115 | aml_name_decl("PRTA", build_q35_routing_table("GSI"))); | |
1116 | ||
0dafe3b3 IM |
1117 | method = aml_method("_PRT", 0, AML_NOTSERIALIZED); |
1118 | { | |
1119 | Aml *if_ctx; | |
1120 | Aml *else_ctx; | |
1121 | ||
1122 | /* PCI IRQ routing table, example from ACPI 2.0a specification, | |
1123 | section 6.2.8.1 */ | |
1124 | /* Note: we provide the same info as the PCI routing | |
1125 | table of the Bochs BIOS */ | |
1126 | if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); | |
1127 | aml_append(if_ctx, aml_return(aml_name("PRTP"))); | |
1128 | aml_append(method, if_ctx); | |
1129 | else_ctx = aml_else(); | |
1130 | aml_append(else_ctx, aml_return(aml_name("PRTA"))); | |
1131 | aml_append(method, else_ctx); | |
1132 | } | |
1133 | aml_append(pci0_scope, method); | |
1134 | aml_append(sb_scope, pci0_scope); | |
80b32df5 | 1135 | |
41f95a52 IM |
1136 | field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); |
1137 | aml_append(field, aml_named_field("PRQA", 8)); | |
1138 | aml_append(field, aml_named_field("PRQB", 8)); | |
1139 | aml_append(field, aml_named_field("PRQC", 8)); | |
1140 | aml_append(field, aml_named_field("PRQD", 8)); | |
1141 | aml_append(field, aml_reserved_field(0x20)); | |
1142 | aml_append(field, aml_named_field("PRQE", 8)); | |
1143 | aml_append(field, aml_named_field("PRQF", 8)); | |
1144 | aml_append(field, aml_named_field("PRQG", 8)); | |
1145 | aml_append(field, aml_named_field("PRQH", 8)); | |
1146 | aml_append(sb_scope, field); | |
1147 | ||
78e1ad05 | 1148 | aml_append(sb_scope, build_irq_status_method()); |
16682a9d IM |
1149 | aml_append(sb_scope, build_iqcr_method(false)); |
1150 | ||
12e3b1f7 IM |
1151 | aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); |
1152 | aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); | |
1153 | aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); | |
1154 | aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); | |
1155 | aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); | |
1156 | aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); | |
1157 | aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); | |
1158 | aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); | |
1159 | ||
6a991e07 MA |
1160 | aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); |
1161 | aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); | |
1162 | aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); | |
1163 | aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); | |
1164 | aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); | |
1165 | aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); | |
1166 | aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); | |
1167 | aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); | |
80b32df5 IM |
1168 | |
1169 | aml_append(table, sb_scope); | |
1170 | } | |
1171 | ||
e3fb55f0 IY |
1172 | static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) |
1173 | { | |
1174 | Aml *dev; | |
1175 | Aml *resource_template; | |
1176 | ||
1177 | /* DRAM controller */ | |
1178 | dev = aml_device("DRAC"); | |
1179 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); | |
1180 | ||
1181 | resource_template = aml_resource_template(); | |
1182 | if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { | |
1183 | aml_append(resource_template, | |
1184 | aml_qword_memory(AML_POS_DECODE, | |
1185 | AML_MIN_FIXED, | |
1186 | AML_MAX_FIXED, | |
1187 | AML_NON_CACHEABLE, | |
1188 | AML_READ_WRITE, | |
1189 | 0x0000000000000000, | |
1190 | mcfg->base, | |
1191 | mcfg->base + mcfg->size - 1, | |
1192 | 0x0000000000000000, | |
1193 | mcfg->size)); | |
1194 | } else { | |
1195 | aml_append(resource_template, | |
1196 | aml_dword_memory(AML_POS_DECODE, | |
1197 | AML_MIN_FIXED, | |
1198 | AML_MAX_FIXED, | |
1199 | AML_NON_CACHEABLE, | |
1200 | AML_READ_WRITE, | |
1201 | 0x0000000000000000, | |
1202 | mcfg->base, | |
1203 | mcfg->base + mcfg->size - 1, | |
1204 | 0x0000000000000000, | |
1205 | mcfg->size)); | |
1206 | } | |
1207 | aml_append(dev, aml_name_decl("_CRS", resource_template)); | |
1208 | ||
1209 | return dev; | |
1210 | } | |
1211 | ||
41f95a52 IM |
1212 | static void build_q35_isa_bridge(Aml *table) |
1213 | { | |
1214 | Aml *dev; | |
1215 | Aml *scope; | |
41f95a52 IM |
1216 | |
1217 | scope = aml_scope("_SB.PCI0"); | |
1218 | dev = aml_device("ISA"); | |
1219 | aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); | |
1220 | ||
1221 | /* ICH9 PCI to ISA irq remapping */ | |
1222 | aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, | |
3f3009c0 | 1223 | aml_int(0x60), 0x0C)); |
41f95a52 | 1224 | |
41f95a52 IM |
1225 | aml_append(scope, dev); |
1226 | aml_append(table, scope); | |
1227 | } | |
1228 | ||
e4db2798 IM |
1229 | static void build_piix4_isa_bridge(Aml *table) |
1230 | { | |
1231 | Aml *dev; | |
1232 | Aml *scope; | |
e4db2798 IM |
1233 | |
1234 | scope = aml_scope("_SB.PCI0"); | |
1235 | dev = aml_device("ISA"); | |
1236 | aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); | |
1237 | ||
1238 | /* PIIX PCI to ISA irq remapping */ | |
1239 | aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, | |
3f3009c0 | 1240 | aml_int(0x60), 0x04)); |
e4db2798 IM |
1241 | |
1242 | aml_append(scope, dev); | |
1243 | aml_append(table, scope); | |
1244 | } | |
1245 | ||
b616ec4d IM |
1246 | static void build_piix4_pci_hotplug(Aml *table) |
1247 | { | |
1248 | Aml *scope; | |
1249 | Aml *field; | |
1250 | Aml *method; | |
1251 | ||
1252 | scope = aml_scope("_SB.PCI0"); | |
1253 | ||
1254 | aml_append(scope, | |
3f3009c0 | 1255 | aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); |
b616ec4d IM |
1256 | field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); |
1257 | aml_append(field, aml_named_field("PCIU", 32)); | |
1258 | aml_append(field, aml_named_field("PCID", 32)); | |
1259 | aml_append(scope, field); | |
1260 | ||
1261 | aml_append(scope, | |
3f3009c0 | 1262 | aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); |
b616ec4d IM |
1263 | field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); |
1264 | aml_append(field, aml_named_field("B0EJ", 32)); | |
1265 | aml_append(scope, field); | |
1266 | ||
1267 | aml_append(scope, | |
b32bd763 | 1268 | aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x08)); |
b616ec4d IM |
1269 | field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); |
1270 | aml_append(field, aml_named_field("BNUM", 32)); | |
b32bd763 | 1271 | aml_append(field, aml_named_field("PIDX", 32)); |
b616ec4d IM |
1272 | aml_append(scope, field); |
1273 | ||
1274 | aml_append(scope, aml_mutex("BLCK", 0)); | |
1275 | ||
1276 | method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); | |
1277 | aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); | |
1278 | aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); | |
1279 | aml_append(method, | |
1280 | aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); | |
1281 | aml_append(method, aml_release(aml_name("BLCK"))); | |
1282 | aml_append(method, aml_return(aml_int(0))); | |
1283 | aml_append(scope, method); | |
1284 | ||
b32bd763 IM |
1285 | method = aml_method("AIDX", 2, AML_NOTSERIALIZED); |
1286 | aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); | |
1287 | aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); | |
1288 | aml_append(method, | |
1289 | aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); | |
1290 | aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); | |
1291 | aml_append(method, aml_release(aml_name("BLCK"))); | |
1292 | aml_append(method, aml_return(aml_local(0))); | |
1293 | aml_append(scope, method); | |
1294 | ||
b7f23f62 IM |
1295 | aml_append(scope, aml_pci_device_dsm()); |
1296 | ||
b616ec4d IM |
1297 | aml_append(table, scope); |
1298 | } | |
1299 | ||
f97a88a8 IM |
1300 | static Aml *build_q35_osc_method(void) |
1301 | { | |
1302 | Aml *if_ctx; | |
1303 | Aml *if_ctx2; | |
1304 | Aml *else_ctx; | |
1305 | Aml *method; | |
1306 | Aml *a_cwd1 = aml_name("CDW1"); | |
b3c782db | 1307 | Aml *a_ctrl = aml_local(0); |
f97a88a8 IM |
1308 | |
1309 | method = aml_method("_OSC", 4, AML_NOTSERIALIZED); | |
1310 | aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); | |
1311 | ||
1312 | if_ctx = aml_if(aml_equal( | |
1313 | aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); | |
1314 | aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); | |
1315 | aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); | |
1316 | ||
f97a88a8 IM |
1317 | aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); |
1318 | ||
1319 | /* | |
1320 | * Always allow native PME, AER (no dependencies) | |
a41c78c1 | 1321 | * Allow SHPC (PCI bridges can have SHPC controller) |
f97a88a8 | 1322 | */ |
a41c78c1 | 1323 | aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); |
f97a88a8 IM |
1324 | |
1325 | if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); | |
1326 | /* Unknown revision */ | |
1327 | aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); | |
1328 | aml_append(if_ctx, if_ctx2); | |
1329 | ||
1330 | if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); | |
1331 | /* Capabilities bits were masked */ | |
1332 | aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); | |
1333 | aml_append(if_ctx, if_ctx2); | |
1334 | ||
1335 | /* Update DWORD3 in the buffer */ | |
1336 | aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); | |
1337 | aml_append(method, if_ctx); | |
1338 | ||
1339 | else_ctx = aml_else(); | |
1340 | /* Unrecognized UUID */ | |
1341 | aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); | |
1342 | aml_append(method, else_ctx); | |
1343 | ||
1344 | aml_append(method, aml_return(aml_arg(3))); | |
1345 | return method; | |
1346 | } | |
b616ec4d | 1347 | |
ebe15582 CM |
1348 | static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) |
1349 | { | |
1350 | Aml *scope = aml_scope("_SB.PCI0"); | |
1351 | Aml *dev = aml_device("SMB0"); | |
1352 | ||
ebe15582 CM |
1353 | aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); |
1354 | build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); | |
1355 | aml_append(scope, dev); | |
1356 | aml_append(table, scope); | |
1357 | } | |
1358 | ||
72c194f7 | 1359 | static void |
0e9b9eda | 1360 | build_dsdt(GArray *table_data, BIOSLinker *linker, |
adcb89d5 | 1361 | AcpiPmInfo *pm, AcpiMiscInfo *misc, |
01c9742d | 1362 | Range *pci_hole, Range *pci_hole64, MachineState *machine) |
72c194f7 | 1363 | { |
41fa5c04 IM |
1364 | CrsRangeEntry *entry; |
1365 | Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; | |
2df5a7b5 | 1366 | CrsRangeSet crs_range_set; |
fb306ffe | 1367 | PCMachineState *pcms = PC_MACHINE(machine); |
679dd1a9 | 1368 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); |
f0bb276b | 1369 | X86MachineState *x86ms = X86_MACHINE(machine); |
4a441836 | 1370 | AcpiMcfgInfo mcfg; |
e3fb55f0 | 1371 | bool mcfg_valid = !!acpi_get_mcfg(&mcfg); |
bef3492d | 1372 | uint32_t nr_mem = machine->ram_slots; |
dcdca296 | 1373 | int root_bus_limit = 0xFF; |
41fa5c04 | 1374 | PCIBus *bus = NULL; |
ac6dd31e | 1375 | TPMIf *tpm = tpm_find(); |
72c194f7 | 1376 | int i; |
8f814ea1 | 1377 | VMBusBridge *vmbus_bridge = vmbus_bridge_find(); |
72c194f7 | 1378 | |
41fa5c04 | 1379 | dsdt = init_aml_allocator(); |
2fd71f1b | 1380 | |
4ec8d2b3 | 1381 | /* Reserve space for header */ |
41fa5c04 IM |
1382 | acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); |
1383 | ||
1384 | build_dbg_aml(dsdt); | |
1385 | if (misc->is_piix4) { | |
1386 | sb_scope = aml_scope("_SB"); | |
1387 | dev = aml_device("PCI0"); | |
1388 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); | |
1389 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
0a343a5a | 1390 | aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); |
41fa5c04 IM |
1391 | aml_append(sb_scope, dev); |
1392 | aml_append(dsdt, sb_scope); | |
1393 | ||
51124bbf SC |
1394 | if (misc->has_hpet) { |
1395 | build_hpet_aml(dsdt); | |
1396 | } | |
41fa5c04 IM |
1397 | build_piix4_isa_bridge(dsdt); |
1398 | build_isa_devices_aml(dsdt); | |
df4008c9 AS |
1399 | if (pm->pcihp_bridge_en || pm->pcihp_root_en) { |
1400 | build_piix4_pci_hotplug(dsdt); | |
1401 | } | |
41fa5c04 IM |
1402 | build_piix4_pci0_int(dsdt); |
1403 | } else { | |
41fa5c04 IM |
1404 | sb_scope = aml_scope("_SB"); |
1405 | dev = aml_device("PCI0"); | |
1406 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); | |
1407 | aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); | |
1408 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
0a343a5a | 1409 | aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); |
41fa5c04 IM |
1410 | aml_append(dev, build_q35_osc_method()); |
1411 | aml_append(sb_scope, dev); | |
e3fb55f0 IY |
1412 | if (mcfg_valid) { |
1413 | aml_append(sb_scope, build_q35_dram_controller(&mcfg)); | |
1414 | } | |
998ba950 IM |
1415 | |
1416 | if (pm->smi_on_cpuhp) { | |
1417 | /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ | |
1418 | dev = aml_device("PCI0.SMI0"); | |
1419 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); | |
1420 | aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); | |
1421 | crs = aml_resource_template(); | |
1422 | aml_append(crs, | |
1423 | aml_io( | |
1424 | AML_DECODE16, | |
1425 | ACPI_PORT_SMI_CMD, | |
1426 | ACPI_PORT_SMI_CMD, | |
1427 | 1, | |
1428 | 2) | |
1429 | ); | |
1430 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1431 | aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, | |
1432 | aml_int(ACPI_PORT_SMI_CMD), 2)); | |
1433 | field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, | |
1434 | AML_WRITE_AS_ZEROS); | |
1435 | aml_append(field, aml_named_field("SMIC", 8)); | |
1436 | aml_append(field, aml_reserved_field(8)); | |
1437 | aml_append(dev, field); | |
1438 | aml_append(sb_scope, dev); | |
1439 | } | |
1440 | ||
41fa5c04 IM |
1441 | aml_append(dsdt, sb_scope); |
1442 | ||
51124bbf SC |
1443 | if (misc->has_hpet) { |
1444 | build_hpet_aml(dsdt); | |
1445 | } | |
41fa5c04 IM |
1446 | build_q35_isa_bridge(dsdt); |
1447 | build_isa_devices_aml(dsdt); | |
1448 | build_q35_pci0_int(dsdt); | |
ebe15582 CM |
1449 | if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { |
1450 | build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); | |
1451 | } | |
41fa5c04 IM |
1452 | } |
1453 | ||
8f814ea1 JD |
1454 | if (vmbus_bridge) { |
1455 | sb_scope = aml_scope("_SB"); | |
1456 | aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); | |
1457 | aml_append(dsdt, sb_scope); | |
1458 | } | |
1459 | ||
679dd1a9 IM |
1460 | if (pcmc->legacy_cpu_hotplug) { |
1461 | build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); | |
1462 | } else { | |
1463 | CPUHotplugFeatures opts = { | |
998ba950 IM |
1464 | .acpi_1_compatible = true, .has_legacy_cphp = true, |
1465 | .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, | |
69dea9d6 | 1466 | .fw_unplugs_cpu = pm->smi_on_cpu_unplug, |
679dd1a9 IM |
1467 | }; |
1468 | build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, | |
1469 | "\\_SB.PCI0", "\\_GPE._E02"); | |
1470 | } | |
091c466e SK |
1471 | |
1472 | if (pcms->memhp_io_base && nr_mem) { | |
1473 | build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", | |
1474 | "\\_GPE._E03", AML_SYSTEM_IO, | |
1475 | pcms->memhp_io_base); | |
1476 | } | |
41fa5c04 IM |
1477 | |
1478 | scope = aml_scope("_GPE"); | |
1479 | { | |
1480 | aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); | |
1481 | ||
df4008c9 | 1482 | if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { |
41fa5c04 IM |
1483 | method = aml_method("_E01", 0, AML_NOTSERIALIZED); |
1484 | aml_append(method, | |
1485 | aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); | |
1486 | aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); | |
1487 | aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); | |
1488 | aml_append(scope, method); | |
41fa5c04 IM |
1489 | } |
1490 | ||
f6a0d06b | 1491 | if (machine->nvdimms_state->is_enabled) { |
b097cc52 XG |
1492 | method = aml_method("_E04", 0, AML_NOTSERIALIZED); |
1493 | aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), | |
1494 | aml_int(0x80))); | |
1495 | aml_append(scope, method); | |
1496 | } | |
41fa5c04 IM |
1497 | } |
1498 | aml_append(dsdt, scope); | |
72c194f7 | 1499 | |
2df5a7b5 | 1500 | crs_range_set_init(&crs_range_set); |
81ed6482 | 1501 | bus = PC_MACHINE(machine)->bus; |
a4894206 MA |
1502 | if (bus) { |
1503 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1504 | uint8_t bus_num = pci_bus_num(bus); | |
0e79e51a | 1505 | uint8_t numa_node = pci_bus_numa_node(bus); |
a4894206 MA |
1506 | |
1507 | /* look only for expander root buses */ | |
1508 | if (!pci_bus_is_root(bus)) { | |
1509 | continue; | |
1510 | } | |
1511 | ||
dcdca296 MA |
1512 | if (bus_num < root_bus_limit) { |
1513 | root_bus_limit = bus_num - 1; | |
1514 | } | |
1515 | ||
a4894206 MA |
1516 | scope = aml_scope("\\_SB"); |
1517 | dev = aml_device("PC%.02X", bus_num); | |
c96d9286 | 1518 | aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); |
a4894206 | 1519 | aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); |
077dd742 | 1520 | if (pci_bus_is_express(bus)) { |
ee4b0c86 EY |
1521 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); |
1522 | aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); | |
077dd742 | 1523 | aml_append(dev, build_q35_osc_method()); |
ee4b0c86 EY |
1524 | } else { |
1525 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); | |
077dd742 | 1526 | } |
0e79e51a MA |
1527 | |
1528 | if (numa_node != NUMA_NODE_UNASSIGNED) { | |
1529 | aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); | |
1530 | } | |
1531 | ||
196e2137 | 1532 | aml_append(dev, build_prt(false)); |
e41ee855 JC |
1533 | crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, |
1534 | 0, 0, 0, 0); | |
a43c6e27 | 1535 | aml_append(dev, aml_name_decl("_CRS", crs)); |
a4894206 | 1536 | aml_append(scope, dev); |
41fa5c04 | 1537 | aml_append(dsdt, scope); |
a4894206 MA |
1538 | } |
1539 | } | |
1540 | ||
4a441836 GH |
1541 | /* |
1542 | * At this point crs_range_set has all the ranges used by pci | |
1543 | * busses *other* than PCI0. These ranges will be excluded from | |
1544 | * the PCI0._CRS. Add mmconfig to the set so it will be excluded | |
1545 | * too. | |
1546 | */ | |
e3fb55f0 | 1547 | if (mcfg_valid) { |
4a441836 GH |
1548 | crs_range_insert(crs_range_set.mem_ranges, |
1549 | mcfg.base, mcfg.base + mcfg.size - 1); | |
1550 | } | |
1551 | ||
500b11ea | 1552 | scope = aml_scope("\\_SB.PCI0"); |
60efd429 IM |
1553 | /* build PCI0._CRS */ |
1554 | crs = aml_resource_template(); | |
1555 | aml_append(crs, | |
ff80dc7f | 1556 | aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, |
dcdca296 MA |
1557 | 0x0000, 0x0, root_bus_limit, |
1558 | 0x0000, root_bus_limit + 1)); | |
ff80dc7f | 1559 | aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); |
60efd429 IM |
1560 | |
1561 | aml_append(crs, | |
ff80dc7f SZ |
1562 | aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, |
1563 | AML_POS_DECODE, AML_ENTIRE_RANGE, | |
60efd429 | 1564 | 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); |
dcdca296 | 1565 | |
2df5a7b5 MA |
1566 | crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); |
1567 | for (i = 0; i < crs_range_set.io_ranges->len; i++) { | |
1568 | entry = g_ptr_array_index(crs_range_set.io_ranges, i); | |
dcdca296 MA |
1569 | aml_append(crs, |
1570 | aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, | |
1571 | AML_POS_DECODE, AML_ENTIRE_RANGE, | |
1572 | 0x0000, entry->base, entry->limit, | |
1573 | 0x0000, entry->limit - entry->base + 1)); | |
1574 | } | |
1575 | ||
60efd429 | 1576 | aml_append(crs, |
ff80dc7f SZ |
1577 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, |
1578 | AML_CACHEABLE, AML_READ_WRITE, | |
60efd429 | 1579 | 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); |
dcdca296 | 1580 | |
2df5a7b5 | 1581 | crs_replace_with_free_ranges(crs_range_set.mem_ranges, |
a0efbf16 MA |
1582 | range_lob(pci_hole), |
1583 | range_upb(pci_hole)); | |
2df5a7b5 MA |
1584 | for (i = 0; i < crs_range_set.mem_ranges->len; i++) { |
1585 | entry = g_ptr_array_index(crs_range_set.mem_ranges, i); | |
dcdca296 MA |
1586 | aml_append(crs, |
1587 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, | |
1588 | AML_NON_CACHEABLE, AML_READ_WRITE, | |
1589 | 0, entry->base, entry->limit, | |
1590 | 0, entry->limit - entry->base + 1)); | |
1591 | } | |
1592 | ||
a0efbf16 | 1593 | if (!range_is_empty(pci_hole64)) { |
16de88a4 MA |
1594 | crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, |
1595 | range_lob(pci_hole64), | |
1596 | range_upb(pci_hole64)); | |
1597 | for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { | |
1598 | entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); | |
1599 | aml_append(crs, | |
1600 | aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, | |
1601 | AML_MAX_FIXED, | |
1602 | AML_CACHEABLE, AML_READ_WRITE, | |
1603 | 0, entry->base, entry->limit, | |
1604 | 0, entry->limit - entry->base + 1)); | |
1605 | } | |
60efd429 | 1606 | } |
2b1c2e8e | 1607 | |
43bc7f84 | 1608 | if (TPM_IS_TIS_ISA(tpm_find())) { |
2b1c2e8e IM |
1609 | aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, |
1610 | TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); | |
1611 | } | |
60efd429 IM |
1612 | aml_append(scope, aml_name_decl("_CRS", crs)); |
1613 | ||
d31c909e IM |
1614 | /* reserve GPE0 block resources */ |
1615 | dev = aml_device("GPE0"); | |
1616 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
1617 | aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); | |
1618 | /* device present, functioning, decoding, not shown in UI */ | |
1619 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1620 | crs = aml_resource_template(); | |
1621 | aml_append(crs, | |
937d1b58 IM |
1622 | aml_io( |
1623 | AML_DECODE16, | |
1624 | pm->fadt.gpe0_blk.address, | |
1625 | pm->fadt.gpe0_blk.address, | |
1626 | 1, | |
1627 | pm->fadt.gpe0_blk.bit_width / 8) | |
d31c909e IM |
1628 | ); |
1629 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1630 | aml_append(scope, dev); | |
1631 | ||
2df5a7b5 | 1632 | crs_range_set_free(&crs_range_set); |
dcdca296 | 1633 | |
500b11ea | 1634 | /* reserve PCIHP resources */ |
df4008c9 | 1635 | if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { |
500b11ea IM |
1636 | dev = aml_device("PHPR"); |
1637 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
1638 | aml_append(dev, | |
1639 | aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); | |
1640 | /* device present, functioning, decoding, not shown in UI */ | |
1641 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1642 | crs = aml_resource_template(); | |
1643 | aml_append(crs, | |
ff80dc7f | 1644 | aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, |
500b11ea IM |
1645 | pm->pcihp_io_len) |
1646 | ); | |
1647 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1648 | aml_append(scope, dev); | |
1649 | } | |
41fa5c04 | 1650 | aml_append(dsdt, scope); |
500b11ea | 1651 | |
ebc3028f IM |
1652 | /* create S3_ / S4_ / S5_ packages if necessary */ |
1653 | scope = aml_scope("\\"); | |
1654 | if (!pm->s3_disabled) { | |
1655 | pkg = aml_package(4); | |
1656 | aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ | |
1657 | aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
1658 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1659 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1660 | aml_append(scope, aml_name_decl("_S3", pkg)); | |
1661 | } | |
1662 | ||
1663 | if (!pm->s4_disabled) { | |
1664 | pkg = aml_package(4); | |
1665 | aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ | |
1666 | /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
1667 | aml_append(pkg, aml_int(pm->s4_val)); | |
1668 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1669 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1670 | aml_append(scope, aml_name_decl("_S4", pkg)); | |
1671 | } | |
1672 | ||
1673 | pkg = aml_package(4); | |
1674 | aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ | |
1675 | aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ | |
1676 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1677 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1678 | aml_append(scope, aml_name_decl("_S5", pkg)); | |
41fa5c04 | 1679 | aml_append(dsdt, scope); |
ebc3028f | 1680 | |
e2ec7568 GS |
1681 | /* create fw_cfg node, unconditionally */ |
1682 | { | |
e2ec7568 | 1683 | scope = aml_scope("\\_SB.PCI0"); |
0575c2fd | 1684 | fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); |
e2ec7568 GS |
1685 | aml_append(dsdt, scope); |
1686 | } | |
1687 | ||
8ac6f7a6 IM |
1688 | if (misc->applesmc_io_base) { |
1689 | scope = aml_scope("\\_SB.PCI0.ISA"); | |
1690 | dev = aml_device("SMC"); | |
1691 | ||
1692 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); | |
1693 | /* device present, functioning, decoding, not shown in UI */ | |
1694 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1695 | ||
1696 | crs = aml_resource_template(); | |
1697 | aml_append(crs, | |
ff80dc7f | 1698 | aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, |
8ac6f7a6 IM |
1699 | 0x01, APPLESMC_MAX_DATA_LENGTH) |
1700 | ); | |
1701 | aml_append(crs, aml_irq_no_flags(6)); | |
1702 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1703 | ||
1704 | aml_append(scope, dev); | |
41fa5c04 | 1705 | aml_append(dsdt, scope); |
8ac6f7a6 IM |
1706 | } |
1707 | ||
cd61cb2e IM |
1708 | if (misc->pvpanic_port) { |
1709 | scope = aml_scope("\\_SB.PCI0.ISA"); | |
1710 | ||
2332333c | 1711 | dev = aml_device("PEVT"); |
e65bef69 | 1712 | aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); |
cd61cb2e IM |
1713 | |
1714 | crs = aml_resource_template(); | |
1715 | aml_append(crs, | |
ff80dc7f | 1716 | aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) |
cd61cb2e IM |
1717 | ); |
1718 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1719 | ||
ff80dc7f | 1720 | aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, |
3f3009c0 | 1721 | aml_int(misc->pvpanic_port), 1)); |
36de884a | 1722 | field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); |
cd61cb2e IM |
1723 | aml_append(field, aml_named_field("PEPT", 8)); |
1724 | aml_append(dev, field); | |
1725 | ||
8ef3ea25 GH |
1726 | /* device present, functioning, decoding, shown in UI */ |
1727 | aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); | |
2332333c | 1728 | |
4dbfc881 | 1729 | method = aml_method("RDPT", 0, AML_NOTSERIALIZED); |
cd61cb2e IM |
1730 | aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); |
1731 | aml_append(method, aml_return(aml_local(0))); | |
1732 | aml_append(dev, method); | |
1733 | ||
4dbfc881 | 1734 | method = aml_method("WRPT", 1, AML_NOTSERIALIZED); |
cd61cb2e IM |
1735 | aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); |
1736 | aml_append(dev, method); | |
1737 | ||
1738 | aml_append(scope, dev); | |
41fa5c04 | 1739 | aml_append(dsdt, scope); |
cd61cb2e IM |
1740 | } |
1741 | ||
7824df38 | 1742 | sb_scope = aml_scope("\\_SB"); |
72c194f7 | 1743 | { |
8b35ab27 IM |
1744 | Object *pci_host; |
1745 | PCIBus *bus = NULL; | |
8698c0c0 | 1746 | |
8b35ab27 IM |
1747 | pci_host = acpi_get_i386_pci_host(); |
1748 | if (pci_host) { | |
1749 | bus = PCI_HOST_BRIDGE(pci_host)->bus; | |
1750 | } | |
8dcf525a | 1751 | |
8b35ab27 IM |
1752 | if (bus) { |
1753 | Aml *scope = aml_scope("PCI0"); | |
1754 | /* Scan all PCI buses. Generate tables to support hotplug. */ | |
1755 | build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); | |
1756 | ||
43bc7f84 | 1757 | if (TPM_IS_TIS_ISA(tpm)) { |
24cf5413 SB |
1758 | if (misc->tpm_version == TPM_VERSION_2_0) { |
1759 | dev = aml_device("TPM"); | |
1760 | aml_append(dev, aml_name_decl("_HID", | |
1761 | aml_string("MSFT0101"))); | |
1762 | } else { | |
1763 | dev = aml_device("ISA.TPM"); | |
1764 | aml_append(dev, aml_name_decl("_HID", | |
1765 | aml_eisaid("PNP0C31"))); | |
1766 | } | |
1767 | ||
8b35ab27 IM |
1768 | aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); |
1769 | crs = aml_resource_template(); | |
1770 | aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, | |
1771 | TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); | |
1772 | /* | |
1773 | FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, | |
1774 | Rewrite to take IRQ from TPM device model and | |
1775 | fix default IRQ value there to use some unused IRQ | |
1776 | */ | |
1777 | /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ | |
1778 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
ac6dd31e SB |
1779 | |
1780 | tpm_build_ppi_acpi(tpm, dev); | |
1781 | ||
8b35ab27 | 1782 | aml_append(scope, dev); |
8dcf525a | 1783 | } |
72c194f7 | 1784 | |
8b35ab27 | 1785 | aml_append(sb_scope, scope); |
72c194f7 | 1786 | } |
72c194f7 | 1787 | } |
4ab6cb4c | 1788 | |
ac6dd31e | 1789 | if (TPM_IS_CRB(tpm)) { |
4ab6cb4c MAL |
1790 | dev = aml_device("TPM"); |
1791 | aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); | |
1792 | crs = aml_resource_template(); | |
1793 | aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, | |
1794 | TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); | |
1795 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1796 | ||
88b3648f | 1797 | aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); |
4ab6cb4c | 1798 | |
ac6dd31e SB |
1799 | tpm_build_ppi_acpi(tpm, dev); |
1800 | ||
4ab6cb4c MAL |
1801 | aml_append(sb_scope, dev); |
1802 | } | |
1803 | ||
8b35ab27 | 1804 | aml_append(dsdt, sb_scope); |
72c194f7 | 1805 | |
011bb749 | 1806 | /* copy AML table into ACPI tables blob and patch header there */ |
41fa5c04 | 1807 | g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); |
72c194f7 | 1808 | build_header(linker, table_data, |
41fa5c04 | 1809 | (void *)(table_data->data + table_data->len - dsdt->buf->len), |
d07b2286 | 1810 | "DSDT", dsdt->buf->len, 1, x86ms->oem_id, x86ms->oem_table_id); |
011bb749 | 1811 | free_aml_allocator(); |
72c194f7 MT |
1812 | } |
1813 | ||
1814 | static void | |
602b4582 MP |
1815 | build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, |
1816 | const char *oem_table_id) | |
72c194f7 MT |
1817 | { |
1818 | Acpi20Hpet *hpet; | |
1819 | ||
1820 | hpet = acpi_data_push(table_data, sizeof(*hpet)); | |
1821 | /* Note timer_block_id value must be kept in sync with value advertised by | |
1822 | * emulated hpet | |
1823 | */ | |
1824 | hpet->timer_block_id = cpu_to_le32(0x8086a201); | |
1825 | hpet->addr.address = cpu_to_le64(HPET_BASE); | |
1826 | build_header(linker, table_data, | |
602b4582 | 1827 | (void *)hpet, "HPET", sizeof(*hpet), 1, oem_id, oem_table_id); |
72c194f7 MT |
1828 | } |
1829 | ||
711b20b4 | 1830 | static void |
602b4582 MP |
1831 | build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, |
1832 | const char *oem_id, const char *oem_table_id) | |
711b20b4 SB |
1833 | { |
1834 | Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); | |
4678124b IM |
1835 | unsigned log_addr_size = sizeof(tcpa->log_area_start_address); |
1836 | unsigned log_addr_offset = | |
1837 | (char *)&tcpa->log_area_start_address - table_data->data; | |
711b20b4 SB |
1838 | |
1839 | tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); | |
1840 | tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); | |
9774ccf7 | 1841 | acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); |
711b20b4 | 1842 | |
ad9671b8 | 1843 | bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, |
42a5b308 SB |
1844 | false /* high memory */); |
1845 | ||
711b20b4 | 1846 | /* log area start address to be filled by Guest linker */ |
4678124b IM |
1847 | bios_linker_loader_add_pointer(linker, |
1848 | ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, | |
1849 | ACPI_BUILD_TPMLOG_FILE, 0); | |
711b20b4 SB |
1850 | |
1851 | build_header(linker, table_data, | |
602b4582 | 1852 | (void *)tcpa, "TCPA", sizeof(*tcpa), 2, oem_id, oem_table_id); |
711b20b4 SB |
1853 | } |
1854 | ||
d471bf3e PB |
1855 | #define HOLE_640K_START (640 * KiB) |
1856 | #define HOLE_640K_END (1 * MiB) | |
4926403c | 1857 | |
72c194f7 | 1858 | static void |
0e9b9eda | 1859 | build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) |
72c194f7 MT |
1860 | { |
1861 | AcpiSystemResourceAffinityTable *srat; | |
72c194f7 MT |
1862 | AcpiSratMemoryAffinity *numamem; |
1863 | ||
1864 | int i; | |
72c194f7 MT |
1865 | int srat_start, numa_start, slots; |
1866 | uint64_t mem_len, mem_base, next_base; | |
5803fce3 | 1867 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
f0bb276b | 1868 | X86MachineState *x86ms = X86_MACHINE(machine); |
80e5db30 | 1869 | const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); |
3d3ebcad | 1870 | PCMachineState *pcms = PC_MACHINE(machine); |
cec65193 | 1871 | ram_addr_t hotplugabble_address_space_size = |
f2ffbe2b | 1872 | object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, |
cec65193 | 1873 | NULL); |
72c194f7 MT |
1874 | |
1875 | srat_start = table_data->len; | |
1876 | ||
1877 | srat = acpi_data_push(table_data, sizeof *srat); | |
1878 | srat->reserved1 = cpu_to_le32(1); | |
72c194f7 | 1879 | |
5803fce3 | 1880 | for (i = 0; i < apic_ids->len; i++) { |
d41f3e75 | 1881 | int node_id = apic_ids->cpus[i].props.node_id; |
5eff33a2 | 1882 | uint32_t apic_id = apic_ids->cpus[i].arch_id; |
5803fce3 | 1883 | |
5eff33a2 IM |
1884 | if (apic_id < 255) { |
1885 | AcpiSratProcessorAffinity *core; | |
1886 | ||
1887 | core = acpi_data_push(table_data, sizeof *core); | |
1888 | core->type = ACPI_SRAT_PROCESSOR_APIC; | |
1889 | core->length = sizeof(*core); | |
1890 | core->local_apic_id = apic_id; | |
ea265072 | 1891 | core->proximity_lo = node_id; |
5eff33a2 IM |
1892 | memset(core->proximity_hi, 0, 3); |
1893 | core->local_sapic_eid = 0; | |
1894 | core->flags = cpu_to_le32(1); | |
1895 | } else { | |
1896 | AcpiSratProcessorX2ApicAffinity *core; | |
1897 | ||
1898 | core = acpi_data_push(table_data, sizeof *core); | |
1899 | core->type = ACPI_SRAT_PROCESSOR_x2APIC; | |
1900 | core->length = sizeof(*core); | |
1901 | core->x2apic_id = cpu_to_le32(apic_id); | |
ea265072 | 1902 | core->proximity_domain = cpu_to_le32(node_id); |
5eff33a2 | 1903 | core->flags = cpu_to_le32(1); |
1f3aba37 | 1904 | } |
72c194f7 MT |
1905 | } |
1906 | ||
1907 | ||
1908 | /* the memory map is a bit tricky, it contains at least one hole | |
1909 | * from 640k-1M and possibly another one from 3.5G-4G. | |
1910 | */ | |
1911 | next_base = 0; | |
1912 | numa_start = table_data->len; | |
1913 | ||
dd4c2f01 | 1914 | for (i = 1; i < pcms->numa_nodes + 1; ++i) { |
72c194f7 | 1915 | mem_base = next_base; |
dd4c2f01 | 1916 | mem_len = pcms->node_mem[i - 1]; |
72c194f7 MT |
1917 | next_base = mem_base + mem_len; |
1918 | ||
4926403c EH |
1919 | /* Cut out the 640K hole */ |
1920 | if (mem_base <= HOLE_640K_START && | |
1921 | next_base > HOLE_640K_START) { | |
1922 | mem_len -= next_base - HOLE_640K_START; | |
1923 | if (mem_len > 0) { | |
1924 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
1925 | build_srat_memory(numamem, mem_base, mem_len, i - 1, | |
1926 | MEM_AFFINITY_ENABLED); | |
1927 | } | |
1928 | ||
1929 | /* Check for the rare case: 640K < RAM < 1M */ | |
1930 | if (next_base <= HOLE_640K_END) { | |
1931 | next_base = HOLE_640K_END; | |
1932 | continue; | |
1933 | } | |
1934 | mem_base = HOLE_640K_END; | |
1935 | mem_len = next_base - HOLE_640K_END; | |
1936 | } | |
1937 | ||
72c194f7 | 1938 | /* Cut out the ACPI_PCI hole */ |
f0bb276b PB |
1939 | if (mem_base <= x86ms->below_4g_mem_size && |
1940 | next_base > x86ms->below_4g_mem_size) { | |
1941 | mem_len -= next_base - x86ms->below_4g_mem_size; | |
72c194f7 MT |
1942 | if (mem_len > 0) { |
1943 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
64b83136 SZ |
1944 | build_srat_memory(numamem, mem_base, mem_len, i - 1, |
1945 | MEM_AFFINITY_ENABLED); | |
72c194f7 MT |
1946 | } |
1947 | mem_base = 1ULL << 32; | |
f0bb276b | 1948 | mem_len = next_base - x86ms->below_4g_mem_size; |
6cf6fe39 | 1949 | next_base = mem_base + mem_len; |
72c194f7 | 1950 | } |
16b42263 DL |
1951 | |
1952 | if (mem_len > 0) { | |
1953 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
1954 | build_srat_memory(numamem, mem_base, mem_len, i - 1, | |
1955 | MEM_AFFINITY_ENABLED); | |
1956 | } | |
72c194f7 | 1957 | } |
c3b0cf6e VV |
1958 | |
1959 | if (machine->nvdimms_state->is_enabled) { | |
1960 | nvdimm_build_srat(table_data); | |
1961 | } | |
1962 | ||
72c194f7 | 1963 | slots = (table_data->len - numa_start) / sizeof *numamem; |
dd4c2f01 | 1964 | for (; slots < pcms->numa_nodes + 2; slots++) { |
72c194f7 | 1965 | numamem = acpi_data_push(table_data, sizeof *numamem); |
64b83136 | 1966 | build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); |
72c194f7 MT |
1967 | } |
1968 | ||
dbb6da8b IM |
1969 | /* |
1970 | * Entry is required for Windows to enable memory hotplug in OS | |
1971 | * and for Linux to enable SWIOTLB when booted with less than | |
1972 | * 4G of RAM. Windows works better if the entry sets proximity | |
1973 | * to the highest NUMA node in the machine. | |
1974 | * Memory devices may override proximity set by this entry, | |
1975 | * providing _PXM method if necessary. | |
1976 | */ | |
cec65193 | 1977 | if (hotplugabble_address_space_size) { |
dbb6da8b IM |
1978 | numamem = acpi_data_push(table_data, sizeof *numamem); |
1979 | build_srat_memory(numamem, machine->device_memory->base, | |
1980 | hotplugabble_address_space_size, pcms->numa_nodes - 1, | |
1981 | MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); | |
cec65193 IM |
1982 | } |
1983 | ||
72c194f7 MT |
1984 | build_header(linker, table_data, |
1985 | (void *)(table_data->data + srat_start), | |
821e3227 | 1986 | "SRAT", |
d07b2286 MP |
1987 | table_data->len - srat_start, 1, x86ms->oem_id, |
1988 | x86ms->oem_table_id); | |
72c194f7 MT |
1989 | } |
1990 | ||
d46114f9 PX |
1991 | /* |
1992 | * VT-d spec 8.1 DMA Remapping Reporting Structure | |
1993 | * (version Oct. 2014 or later) | |
1994 | */ | |
d4eb9119 | 1995 | static void |
602b4582 MP |
1996 | build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, |
1997 | const char *oem_table_id) | |
d4eb9119 LT |
1998 | { |
1999 | int dmar_start = table_data->len; | |
2000 | ||
2001 | AcpiTableDmar *dmar; | |
2002 | AcpiDmarHardwareUnit *drhd; | |
bd2baacc | 2003 | AcpiDmarRootPortATS *atsr; |
d46114f9 PX |
2004 | uint8_t dmar_flags = 0; |
2005 | X86IOMMUState *iommu = x86_iommu_get_default(); | |
cfc13df4 PX |
2006 | AcpiDmarDeviceScope *scope = NULL; |
2007 | /* Root complex IOAPIC use one path[0] only */ | |
2008 | size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); | |
37f51384 | 2009 | IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); |
d46114f9 PX |
2010 | |
2011 | assert(iommu); | |
a924b3d8 | 2012 | if (x86_iommu_ir_supported(iommu)) { |
d46114f9 PX |
2013 | dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ |
2014 | } | |
d4eb9119 LT |
2015 | |
2016 | dmar = acpi_data_push(table_data, sizeof(*dmar)); | |
37f51384 | 2017 | dmar->host_address_width = intel_iommu->aw_bits - 1; |
d46114f9 | 2018 | dmar->flags = dmar_flags; |
d4eb9119 LT |
2019 | |
2020 | /* DMAR Remapping Hardware Unit Definition structure */ | |
cfc13df4 | 2021 | drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); |
d4eb9119 | 2022 | drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); |
cfc13df4 | 2023 | drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); |
d4eb9119 LT |
2024 | drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; |
2025 | drhd->pci_segment = cpu_to_le16(0); | |
2026 | drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); | |
2027 | ||
cfc13df4 PX |
2028 | /* Scope definition for the root-complex IOAPIC. See VT-d spec |
2029 | * 8.3.1 (version Oct. 2014 or later). */ | |
2030 | scope = &drhd->scope[0]; | |
2031 | scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ | |
2032 | scope->length = ioapic_scope_size; | |
2033 | scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; | |
2034 | scope->bus = Q35_PSEUDO_BUS_PLATFORM; | |
1b39bc1c PX |
2035 | scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); |
2036 | scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); | |
cfc13df4 | 2037 | |
bd2baacc JW |
2038 | if (iommu->dt_supported) { |
2039 | atsr = acpi_data_push(table_data, sizeof(*atsr)); | |
2040 | atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); | |
2041 | atsr->length = cpu_to_le16(sizeof(*atsr)); | |
2042 | atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; | |
2043 | atsr->pci_segment = cpu_to_le16(0); | |
2044 | } | |
2045 | ||
d4eb9119 | 2046 | build_header(linker, table_data, (void *)(table_data->data + dmar_start), |
602b4582 | 2047 | "DMAR", table_data->len - dmar_start, 1, oem_id, oem_table_id); |
d4eb9119 | 2048 | } |
14cda350 LA |
2049 | |
2050 | /* | |
2051 | * Windows ACPI Emulated Devices Table | |
2052 | * (Version 1.0 - April 6, 2009) | |
2053 | * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx | |
2054 | * | |
2055 | * Helpful to speedup Windows guests and ignored by others. | |
2056 | */ | |
2057 | static void | |
602b4582 MP |
2058 | build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, |
2059 | const char *oem_table_id) | |
14cda350 LA |
2060 | { |
2061 | int waet_start = table_data->len; | |
2062 | ||
2063 | /* WAET header */ | |
2064 | acpi_data_push(table_data, sizeof(AcpiTableHeader)); | |
2065 | /* | |
2066 | * Set "ACPI PM timer good" flag. | |
2067 | * | |
2068 | * Tells Windows guests that our ACPI PM timer is reliable in the | |
2069 | * sense that guest can read it only once to obtain a reliable value. | |
2070 | * Which avoids costly VMExits caused by guest re-reading it unnecessarily. | |
2071 | */ | |
2072 | build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); | |
2073 | ||
2074 | build_header(linker, table_data, (void *)(table_data->data + waet_start), | |
602b4582 | 2075 | "WAET", table_data->len - waet_start, 1, oem_id, oem_table_id); |
14cda350 LA |
2076 | } |
2077 | ||
fb9f5926 DK |
2078 | /* |
2079 | * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 | |
2080 | * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf | |
2081 | */ | |
c028818d BS |
2082 | #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) |
2083 | ||
977aff10 AW |
2084 | /* |
2085 | * Insert IVHD entry for device and recurse, insert alias, or insert range as | |
2086 | * necessary for the PCI topology. | |
2087 | */ | |
2088 | static void | |
2089 | insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) | |
2090 | { | |
2091 | GArray *table_data = opaque; | |
2092 | uint32_t entry; | |
2093 | ||
2094 | /* "Select" IVHD entry, type 0x2 */ | |
2095 | entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; | |
2096 | build_append_int_noprefix(table_data, entry, 4); | |
2097 | ||
2098 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { | |
2099 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); | |
2100 | uint8_t sec = pci_bus_num(sec_bus); | |
2101 | uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; | |
2102 | ||
2103 | if (pci_bus_is_express(sec_bus)) { | |
2104 | /* | |
2105 | * Walk the bus if there are subordinates, otherwise use a range | |
2106 | * to cover an entire leaf bus. We could potentially also use a | |
2107 | * range for traversed buses, but we'd need to take care not to | |
2108 | * create both Select and Range entries covering the same device. | |
2109 | * This is easier and potentially more compact. | |
2110 | * | |
2111 | * An example bare metal system seems to use Select entries for | |
2112 | * root ports without a slot (ie. built-ins) and Range entries | |
2113 | * when there is a slot. The same system also only hard-codes | |
2114 | * the alias range for an onboard PCIe-to-PCI bridge, apparently | |
2115 | * making no effort to support nested bridges. We attempt to | |
2116 | * be more thorough here. | |
2117 | */ | |
2118 | if (sec == sub) { /* leaf bus */ | |
2119 | /* "Start of Range" IVHD entry, type 0x3 */ | |
2120 | entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; | |
2121 | build_append_int_noprefix(table_data, entry, 4); | |
2122 | /* "End of Range" IVHD entry, type 0x4 */ | |
2123 | entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; | |
2124 | build_append_int_noprefix(table_data, entry, 4); | |
2125 | } else { | |
2126 | pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); | |
2127 | } | |
2128 | } else { | |
2129 | /* | |
2130 | * If the secondary bus is conventional, then we need to create an | |
2131 | * Alias range for everything downstream. The range covers the | |
2132 | * first devfn on the secondary bus to the last devfn on the | |
2133 | * subordinate bus. The alias target depends on legacy versus | |
2134 | * express bridges, just as in pci_device_iommu_address_space(). | |
2135 | * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. | |
2136 | */ | |
2137 | uint16_t dev_id_a, dev_id_b; | |
2138 | ||
2139 | dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); | |
2140 | ||
2141 | if (pci_is_express(dev) && | |
2142 | pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
2143 | dev_id_b = dev_id_a; | |
2144 | } else { | |
2145 | dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); | |
2146 | } | |
2147 | ||
2148 | /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ | |
2149 | build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); | |
2150 | build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); | |
2151 | ||
2152 | /* "End of Range" IVHD entry, type 0x4 */ | |
2153 | entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; | |
2154 | build_append_int_noprefix(table_data, entry, 4); | |
2155 | } | |
2156 | } | |
2157 | } | |
2158 | ||
2159 | /* For all PCI host bridges, walk and insert IVHD entries */ | |
2160 | static int | |
2161 | ivrs_host_bridges(Object *obj, void *opaque) | |
2162 | { | |
2163 | GArray *ivhd_blob = opaque; | |
2164 | ||
2165 | if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { | |
2166 | PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; | |
2167 | ||
2168 | if (bus) { | |
2169 | pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob); | |
2170 | } | |
2171 | } | |
2172 | ||
2173 | return 0; | |
2174 | } | |
2175 | ||
fb9f5926 | 2176 | static void |
602b4582 MP |
2177 | build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, |
2178 | const char *oem_table_id) | |
fb9f5926 | 2179 | { |
977aff10 | 2180 | int ivhd_table_len = 24; |
fb9f5926 DK |
2181 | int iommu_start = table_data->len; |
2182 | AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); | |
977aff10 | 2183 | GArray *ivhd_blob = g_array_new(false, true, 1); |
fb9f5926 DK |
2184 | |
2185 | /* IVRS header */ | |
2186 | acpi_data_push(table_data, sizeof(AcpiTableHeader)); | |
2187 | /* IVinfo - IO virtualization information common to all | |
2188 | * IOMMU units in a system | |
2189 | */ | |
2190 | build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); | |
2191 | /* reserved */ | |
2192 | build_append_int_noprefix(table_data, 0, 8); | |
2193 | ||
2194 | /* IVHD definition - type 10h */ | |
2195 | build_append_int_noprefix(table_data, 0x10, 1); | |
2196 | /* virtualization flags */ | |
2197 | build_append_int_noprefix(table_data, | |
2198 | (1UL << 0) | /* HtTunEn */ | |
2199 | (1UL << 4) | /* iotblSup */ | |
2200 | (1UL << 6) | /* PrefSup */ | |
2201 | (1UL << 7), /* PPRSup */ | |
2202 | 1); | |
c028818d | 2203 | |
977aff10 AW |
2204 | /* |
2205 | * A PCI bus walk, for each PCI host bridge, is necessary to create a | |
2206 | * complete set of IVHD entries. Do this into a separate blob so that we | |
2207 | * can calculate the total IVRS table length here and then append the new | |
2208 | * blob further below. Fall back to an entry covering all devices, which | |
2209 | * is sufficient when no aliases are present. | |
2210 | */ | |
2211 | object_child_foreach_recursive(object_get_root(), | |
2212 | ivrs_host_bridges, ivhd_blob); | |
2213 | ||
2214 | if (!ivhd_blob->len) { | |
2215 | /* | |
2216 | * Type 1 device entry reporting all devices | |
2217 | * These are 4-byte device entries currently reporting the range of | |
2218 | * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) | |
2219 | */ | |
2220 | build_append_int_noprefix(ivhd_blob, 0x0000001, 4); | |
2221 | } | |
2222 | ||
2223 | ivhd_table_len += ivhd_blob->len; | |
2224 | ||
c028818d BS |
2225 | /* |
2226 | * When interrupt remapping is supported, we add a special IVHD device | |
2227 | * for type IO-APIC. | |
2228 | */ | |
a924b3d8 | 2229 | if (x86_iommu_ir_supported(x86_iommu_get_default())) { |
c028818d BS |
2230 | ivhd_table_len += 8; |
2231 | } | |
977aff10 | 2232 | |
fb9f5926 | 2233 | /* IVHD length */ |
c028818d | 2234 | build_append_int_noprefix(table_data, ivhd_table_len, 2); |
fb9f5926 DK |
2235 | /* DeviceID */ |
2236 | build_append_int_noprefix(table_data, s->devid, 2); | |
2237 | /* Capability offset */ | |
2238 | build_append_int_noprefix(table_data, s->capab_offset, 2); | |
2239 | /* IOMMU base address */ | |
2240 | build_append_int_noprefix(table_data, s->mmio.addr, 8); | |
2241 | /* PCI Segment Group */ | |
2242 | build_append_int_noprefix(table_data, 0, 2); | |
2243 | /* IOMMU info */ | |
2244 | build_append_int_noprefix(table_data, 0, 2); | |
2245 | /* IOMMU Feature Reporting */ | |
2246 | build_append_int_noprefix(table_data, | |
2247 | (48UL << 30) | /* HATS */ | |
2248 | (48UL << 28) | /* GATS */ | |
12499b23 BS |
2249 | (1UL << 2) | /* GTSup */ |
2250 | (1UL << 6), /* GASup */ | |
fb9f5926 | 2251 | 4); |
977aff10 AW |
2252 | |
2253 | /* IVHD entries as found above */ | |
2254 | g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); | |
2255 | g_array_free(ivhd_blob, TRUE); | |
fb9f5926 | 2256 | |
c028818d BS |
2257 | /* |
2258 | * Add a special IVHD device type. | |
2259 | * Refer to spec - Table 95: IVHD device entry type codes | |
2260 | * | |
2261 | * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). | |
2262 | * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' | |
2263 | */ | |
a924b3d8 | 2264 | if (x86_iommu_ir_supported(x86_iommu_get_default())) { |
c028818d BS |
2265 | build_append_int_noprefix(table_data, |
2266 | (0x1ull << 56) | /* type IOAPIC */ | |
2267 | (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ | |
2268 | 0x48, /* special device */ | |
2269 | 8); | |
2270 | } | |
2271 | ||
fb9f5926 | 2272 | build_header(linker, table_data, (void *)(table_data->data + iommu_start), |
602b4582 MP |
2273 | "IVRS", table_data->len - iommu_start, 1, oem_id, |
2274 | oem_table_id); | |
fb9f5926 | 2275 | } |
d4eb9119 | 2276 | |
72c194f7 MT |
2277 | typedef |
2278 | struct AcpiBuildState { | |
2279 | /* Copy of table in RAM (for patching). */ | |
339240b5 | 2280 | MemoryRegion *table_mr; |
72c194f7 MT |
2281 | /* Is table patched? */ |
2282 | uint8_t patched; | |
d70414a5 | 2283 | void *rsdp; |
339240b5 PB |
2284 | MemoryRegion *rsdp_mr; |
2285 | MemoryRegion *linker_mr; | |
72c194f7 MT |
2286 | } AcpiBuildState; |
2287 | ||
2288 | static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) | |
2289 | { | |
2290 | Object *pci_host; | |
2291 | QObject *o; | |
72c194f7 | 2292 | |
ca6c1855 | 2293 | pci_host = acpi_get_i386_pci_host(); |
72c194f7 MT |
2294 | g_assert(pci_host); |
2295 | ||
2296 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); | |
2297 | if (!o) { | |
2298 | return false; | |
2299 | } | |
c309434e | 2300 | mcfg->base = qnum_get_uint(qobject_to(QNum, o)); |
cb3e7f08 | 2301 | qobject_unref(o); |
c309434e | 2302 | if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { |
fe4970ad IM |
2303 | return false; |
2304 | } | |
72c194f7 MT |
2305 | |
2306 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); | |
2307 | assert(o); | |
c309434e | 2308 | mcfg->size = qnum_get_uint(qobject_to(QNum, o)); |
cb3e7f08 | 2309 | qobject_unref(o); |
72c194f7 MT |
2310 | return true; |
2311 | } | |
2312 | ||
2313 | static | |
3d3ebcad | 2314 | void acpi_build(AcpiBuildTables *tables, MachineState *machine) |
72c194f7 | 2315 | { |
3d3ebcad | 2316 | PCMachineState *pcms = PC_MACHINE(machine); |
bb292f5a | 2317 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 2318 | X86MachineState *x86ms = X86_MACHINE(machine); |
72c194f7 | 2319 | GArray *table_offsets; |
41fa5c04 | 2320 | unsigned facs, dsdt, rsdt, fadt; |
72c194f7 MT |
2321 | AcpiPmInfo pm; |
2322 | AcpiMiscInfo misc; | |
2323 | AcpiMcfgInfo mcfg; | |
01c9742d | 2324 | Range pci_hole, pci_hole64; |
72c194f7 | 2325 | uint8_t *u; |
07fb6176 | 2326 | size_t aml_len = 0; |
7c2c1fa5 | 2327 | GArray *tables_blob = tables->table_data; |
ae123749 | 2328 | AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; |
d03637bc | 2329 | Object *vmgenid_dev; |
602b4582 MP |
2330 | char *oem_id; |
2331 | char *oem_table_id; | |
72c194f7 | 2332 | |
0e11fc69 | 2333 | acpi_get_pm_info(machine, &pm); |
72c194f7 | 2334 | acpi_get_misc_info(&misc); |
01c9742d | 2335 | acpi_get_pci_holes(&pci_hole, &pci_hole64); |
ae123749 | 2336 | acpi_get_slic_oem(&slic_oem); |
72c194f7 | 2337 | |
602b4582 MP |
2338 | if (slic_oem.id) { |
2339 | oem_id = slic_oem.id; | |
2340 | } else { | |
d07b2286 | 2341 | oem_id = x86ms->oem_id; |
602b4582 MP |
2342 | } |
2343 | ||
2344 | if (slic_oem.table_id) { | |
2345 | oem_table_id = slic_oem.table_id; | |
2346 | } else { | |
d07b2286 | 2347 | oem_table_id = x86ms->oem_table_id; |
602b4582 MP |
2348 | } |
2349 | ||
72c194f7 MT |
2350 | table_offsets = g_array_new(false, true /* clear */, |
2351 | sizeof(uint32_t)); | |
8b310fc4 | 2352 | ACPI_BUILD_DPRINTF("init ACPI tables\n"); |
72c194f7 | 2353 | |
ad9671b8 IM |
2354 | bios_linker_loader_alloc(tables->linker, |
2355 | ACPI_BUILD_TABLE_FILE, tables_blob, | |
72c194f7 MT |
2356 | 64 /* Ensure FACS is aligned */, |
2357 | false /* high memory */); | |
2358 | ||
2359 | /* | |
2360 | * FACS is pointed to by FADT. | |
2361 | * We place it first since it's the only table that has alignment | |
2362 | * requirements. | |
2363 | */ | |
7c2c1fa5 | 2364 | facs = tables_blob->len; |
009180bd | 2365 | build_facs(tables_blob); |
72c194f7 MT |
2366 | |
2367 | /* DSDT is pointed to by FADT */ | |
7c2c1fa5 | 2368 | dsdt = tables_blob->len; |
01c9742d MA |
2369 | build_dsdt(tables_blob, tables->linker, &pm, &misc, |
2370 | &pci_hole, &pci_hole64, machine); | |
72c194f7 | 2371 | |
07fb6176 PB |
2372 | /* Count the size of the DSDT and SSDT, we will need it for legacy |
2373 | * sizing of ACPI tables. | |
2374 | */ | |
7c2c1fa5 | 2375 | aml_len += tables_blob->len - dsdt; |
07fb6176 | 2376 | |
72c194f7 | 2377 | /* ACPI tables pointed to by RSDT */ |
41fa5c04 | 2378 | fadt = tables_blob->len; |
7c2c1fa5 | 2379 | acpi_add_table(table_offsets, tables_blob); |
937d1b58 IM |
2380 | pm.fadt.facs_tbl_offset = &facs; |
2381 | pm.fadt.dsdt_tbl_offset = &dsdt; | |
2382 | pm.fadt.xdsdt_tbl_offset = &dsdt; | |
602b4582 | 2383 | build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); |
41fa5c04 | 2384 | aml_len += tables_blob->len - fadt; |
72c194f7 | 2385 | |
7c2c1fa5 | 2386 | acpi_add_table(table_offsets, tables_blob); |
eb66ffab | 2387 | acpi_build_madt(tables_blob, tables->linker, x86ms, |
d07b2286 MP |
2388 | ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, |
2389 | x86ms->oem_table_id); | |
9ac1c4c0 | 2390 | |
d03637bc BW |
2391 | vmgenid_dev = find_vmgenid_dev(); |
2392 | if (vmgenid_dev) { | |
2393 | acpi_add_table(table_offsets, tables_blob); | |
2394 | vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, | |
d07b2286 | 2395 | tables->vmgenid, tables->linker, x86ms->oem_id); |
d03637bc BW |
2396 | } |
2397 | ||
72c194f7 | 2398 | if (misc.has_hpet) { |
7c2c1fa5 | 2399 | acpi_add_table(table_offsets, tables_blob); |
d07b2286 MP |
2400 | build_hpet(tables_blob, tables->linker, x86ms->oem_id, |
2401 | x86ms->oem_table_id); | |
711b20b4 | 2402 | } |
5cb18b3d | 2403 | if (misc.tpm_version != TPM_VERSION_UNSPEC) { |
7e7c1b84 SB |
2404 | if (misc.tpm_version == TPM_VERSION_1_2) { |
2405 | acpi_add_table(table_offsets, tables_blob); | |
602b4582 | 2406 | build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, |
d07b2286 | 2407 | x86ms->oem_id, x86ms->oem_table_id); |
7e7c1b84 | 2408 | } else { /* TPM_VERSION_2_0 */ |
72d97b3a | 2409 | acpi_add_table(table_offsets, tables_blob); |
602b4582 | 2410 | build_tpm2(tables_blob, tables->linker, tables->tcpalog, |
d07b2286 | 2411 | x86ms->oem_id, x86ms->oem_table_id); |
5cb18b3d | 2412 | } |
72c194f7 | 2413 | } |
dd4c2f01 | 2414 | if (pcms->numa_nodes) { |
7c2c1fa5 | 2415 | acpi_add_table(table_offsets, tables_blob); |
3d3ebcad | 2416 | build_srat(tables_blob, tables->linker, machine); |
118154b7 | 2417 | if (machine->numa_state->have_numa_distance) { |
0f203430 | 2418 | acpi_add_table(table_offsets, tables_blob); |
d07b2286 MP |
2419 | build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, |
2420 | x86ms->oem_table_id); | |
0f203430 | 2421 | } |
e6f123c3 LJ |
2422 | if (machine->numa_state->hmat_enabled) { |
2423 | acpi_add_table(table_offsets, tables_blob); | |
602b4582 | 2424 | build_hmat(tables_blob, tables->linker, machine->numa_state, |
d07b2286 | 2425 | x86ms->oem_id, x86ms->oem_table_id); |
e6f123c3 | 2426 | } |
72c194f7 MT |
2427 | } |
2428 | if (acpi_get_mcfg(&mcfg)) { | |
7c2c1fa5 | 2429 | acpi_add_table(table_offsets, tables_blob); |
d07b2286 MP |
2430 | build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, |
2431 | x86ms->oem_table_id); | |
72c194f7 | 2432 | } |
fb9f5926 DK |
2433 | if (x86_iommu_get_default()) { |
2434 | IommuType IOMMUType = x86_iommu_get_type(); | |
2435 | if (IOMMUType == TYPE_AMD) { | |
2436 | acpi_add_table(table_offsets, tables_blob); | |
d07b2286 MP |
2437 | build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, |
2438 | x86ms->oem_table_id); | |
fb9f5926 DK |
2439 | } else if (IOMMUType == TYPE_INTEL) { |
2440 | acpi_add_table(table_offsets, tables_blob); | |
d07b2286 MP |
2441 | build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, |
2442 | x86ms->oem_table_id); | |
fb9f5926 | 2443 | } |
d4eb9119 | 2444 | } |
f6a0d06b | 2445 | if (machine->nvdimms_state->is_enabled) { |
ad9671b8 | 2446 | nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, |
602b4582 | 2447 | machine->nvdimms_state, machine->ram_slots, |
d07b2286 | 2448 | x86ms->oem_id, x86ms->oem_table_id); |
87252e1b XG |
2449 | } |
2450 | ||
14cda350 | 2451 | acpi_add_table(table_offsets, tables_blob); |
d07b2286 | 2452 | build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); |
14cda350 | 2453 | |
72c194f7 MT |
2454 | /* Add tables supplied by user (if any) */ |
2455 | for (u = acpi_table_first(); u; u = acpi_table_next(u)) { | |
2456 | unsigned len = acpi_table_len(u); | |
2457 | ||
7c2c1fa5 IM |
2458 | acpi_add_table(table_offsets, tables_blob); |
2459 | g_array_append_vals(tables_blob, u, len); | |
72c194f7 MT |
2460 | } |
2461 | ||
2462 | /* RSDT is pointed to by RSDP */ | |
7c2c1fa5 | 2463 | rsdt = tables_blob->len; |
ae123749 | 2464 | build_rsdt(tables_blob, tables->linker, table_offsets, |
602b4582 | 2465 | oem_id, oem_table_id); |
72c194f7 MT |
2466 | |
2467 | /* RSDP is in FSEG memory, so allocate it separately */ | |
a46ce1c2 SO |
2468 | { |
2469 | AcpiRsdpData rsdp_data = { | |
2470 | .revision = 0, | |
d07b2286 | 2471 | .oem_id = x86ms->oem_id, |
a46ce1c2 SO |
2472 | .xsdt_tbl_offset = NULL, |
2473 | .rsdt_tbl_offset = &rsdt, | |
2474 | }; | |
2475 | build_rsdp(tables->rsdp, tables->linker, &rsdp_data); | |
2476 | if (!pcmc->rsdp_in_ram) { | |
2477 | /* We used to allocate some extra space for RSDP revision 2 but | |
2478 | * only used the RSDP revision 0 space. The extra bytes were | |
2479 | * zeroed out and not used. | |
2480 | * Here we continue wasting those extra 16 bytes to make sure we | |
2481 | * don't break migration for machine types 2.2 and older due to | |
2482 | * RSDP blob size mismatch. | |
2483 | */ | |
2484 | build_append_int_noprefix(tables->rsdp, 0, 16); | |
2485 | } | |
2486 | } | |
72c194f7 | 2487 | |
07fb6176 | 2488 | /* We'll expose it all to Guest so we want to reduce |
72c194f7 | 2489 | * chance of size changes. |
07fb6176 PB |
2490 | * |
2491 | * We used to align the tables to 4k, but of course this would | |
2492 | * too simple to be enough. 4k turned out to be too small an | |
2493 | * alignment very soon, and in fact it is almost impossible to | |
2494 | * keep the table size stable for all (max_cpus, max_memory_slots) | |
2495 | * combinations. So the table size is always 64k for pc-i440fx-2.1 | |
2496 | * and we give an error if the table grows beyond that limit. | |
2497 | * | |
2498 | * We still have the problem of migrating from "-M pc-i440fx-2.0". For | |
2499 | * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables | |
2500 | * than 2.0 and we can always pad the smaller tables with zeros. We can | |
2501 | * then use the exact size of the 2.0 tables. | |
2502 | * | |
2503 | * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. | |
72c194f7 | 2504 | */ |
bb292f5a | 2505 | if (pcmc->legacy_acpi_table_size) { |
07fb6176 PB |
2506 | /* Subtracting aml_len gives the size of fixed tables. Then add the |
2507 | * size of the PIIX4 DSDT/SSDT in QEMU 2.0. | |
2508 | */ | |
2509 | int legacy_aml_len = | |
bb292f5a | 2510 | pcmc->legacy_acpi_table_size + |
f0bb276b | 2511 | ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; |
07fb6176 | 2512 | int legacy_table_size = |
7c2c1fa5 | 2513 | ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, |
07fb6176 | 2514 | ACPI_BUILD_ALIGN_SIZE); |
7c2c1fa5 | 2515 | if (tables_blob->len > legacy_table_size) { |
07fb6176 | 2516 | /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ |
9e5d2c52 AF |
2517 | warn_report("ACPI table size %u exceeds %d bytes," |
2518 | " migration may not work", | |
2519 | tables_blob->len, legacy_table_size); | |
2520 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
2521 | " or PCI bridges."); | |
07fb6176 | 2522 | } |
7c2c1fa5 | 2523 | g_array_set_size(tables_blob, legacy_table_size); |
07fb6176 | 2524 | } else { |
868270f2 | 2525 | /* Make sure we have a buffer in case we need to resize the tables. */ |
7c2c1fa5 | 2526 | if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { |
18045fb9 | 2527 | /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ |
9e5d2c52 AF |
2528 | warn_report("ACPI table size %u exceeds %d bytes," |
2529 | " migration may not work", | |
2530 | tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); | |
2531 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
2532 | " or PCI bridges."); | |
18045fb9 | 2533 | } |
7c2c1fa5 | 2534 | acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); |
07fb6176 | 2535 | } |
72c194f7 | 2536 | |
0e9b9eda | 2537 | acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); |
72c194f7 MT |
2538 | |
2539 | /* Cleanup memory that's no longer used. */ | |
2540 | g_array_free(table_offsets, true); | |
2541 | } | |
2542 | ||
339240b5 | 2543 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) |
42d85900 MT |
2544 | { |
2545 | uint32_t size = acpi_data_len(data); | |
2546 | ||
2547 | /* Make sure RAM size is correct - in case it got changed e.g. by migration */ | |
339240b5 | 2548 | memory_region_ram_resize(mr, size, &error_abort); |
42d85900 | 2549 | |
339240b5 PB |
2550 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); |
2551 | memory_region_set_dirty(mr, 0, size); | |
42d85900 MT |
2552 | } |
2553 | ||
3f8752b4 | 2554 | static void acpi_build_update(void *build_opaque) |
72c194f7 MT |
2555 | { |
2556 | AcpiBuildState *build_state = build_opaque; | |
2557 | AcpiBuildTables tables; | |
2558 | ||
2559 | /* No state to update or already patched? Nothing to do. */ | |
2560 | if (!build_state || build_state->patched) { | |
2561 | return; | |
2562 | } | |
2563 | build_state->patched = 1; | |
2564 | ||
2565 | acpi_build_tables_init(&tables); | |
2566 | ||
3d3ebcad | 2567 | acpi_build(&tables, MACHINE(qdev_get_machine())); |
72c194f7 | 2568 | |
339240b5 | 2569 | acpi_ram_update(build_state->table_mr, tables.table_data); |
a1666142 | 2570 | |
42d85900 MT |
2571 | if (build_state->rsdp) { |
2572 | memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); | |
2573 | } else { | |
339240b5 | 2574 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); |
42d85900 | 2575 | } |
ad5b88b1 | 2576 | |
0e9b9eda | 2577 | acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); |
72c194f7 MT |
2578 | acpi_build_tables_cleanup(&tables, true); |
2579 | } | |
2580 | ||
2581 | static void acpi_build_reset(void *build_opaque) | |
2582 | { | |
2583 | AcpiBuildState *build_state = build_opaque; | |
2584 | build_state->patched = 0; | |
2585 | } | |
2586 | ||
72c194f7 MT |
2587 | static const VMStateDescription vmstate_acpi_build = { |
2588 | .name = "acpi_build", | |
2589 | .version_id = 1, | |
2590 | .minimum_version_id = 1, | |
d49805ae | 2591 | .fields = (VMStateField[]) { |
72c194f7 MT |
2592 | VMSTATE_UINT8(patched, AcpiBuildState), |
2593 | VMSTATE_END_OF_LIST() | |
2594 | }, | |
2595 | }; | |
2596 | ||
fb306ffe | 2597 | void acpi_setup(void) |
72c194f7 | 2598 | { |
fb306ffe | 2599 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); |
bb292f5a | 2600 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 2601 | X86MachineState *x86ms = X86_MACHINE(pcms); |
72c194f7 MT |
2602 | AcpiBuildTables tables; |
2603 | AcpiBuildState *build_state; | |
d03637bc | 2604 | Object *vmgenid_dev; |
0fe24669 SB |
2605 | TPMIf *tpm; |
2606 | static FwCfgTPMConfig tpm_config; | |
72c194f7 | 2607 | |
f0bb276b | 2608 | if (!x86ms->fw_cfg) { |
8b310fc4 | 2609 | ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); |
72c194f7 MT |
2610 | return; |
2611 | } | |
2612 | ||
021746c1 | 2613 | if (!pcms->acpi_build_enabled) { |
8b310fc4 | 2614 | ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); |
72c194f7 MT |
2615 | return; |
2616 | } | |
2617 | ||
17e89077 | 2618 | if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { |
8b310fc4 | 2619 | ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); |
81adc513 MT |
2620 | return; |
2621 | } | |
2622 | ||
72c194f7 MT |
2623 | build_state = g_malloc0(sizeof *build_state); |
2624 | ||
72c194f7 | 2625 | acpi_build_tables_init(&tables); |
3d3ebcad | 2626 | acpi_build(&tables, MACHINE(pcms)); |
72c194f7 MT |
2627 | |
2628 | /* Now expose it all to Guest */ | |
82f76c67 WY |
2629 | build_state->table_mr = acpi_add_rom_blob(acpi_build_update, |
2630 | build_state, tables.table_data, | |
6930ba0d | 2631 | ACPI_BUILD_TABLE_FILE); |
339240b5 | 2632 | assert(build_state->table_mr != NULL); |
72c194f7 | 2633 | |
339240b5 | 2634 | build_state->linker_mr = |
82f76c67 | 2635 | acpi_add_rom_blob(acpi_build_update, build_state, |
6930ba0d | 2636 | tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); |
72c194f7 | 2637 | |
f0bb276b | 2638 | fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, |
42a5b308 SB |
2639 | tables.tcpalog->data, acpi_data_len(tables.tcpalog)); |
2640 | ||
0fe24669 SB |
2641 | tpm = tpm_find(); |
2642 | if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { | |
2643 | tpm_config = (FwCfgTPMConfig) { | |
2644 | .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), | |
2645 | .tpm_version = tpm_get_version(tpm), | |
ac6dd31e | 2646 | .tpmppi_version = TPM_PPI_VERSION_1_30 |
0fe24669 | 2647 | }; |
f0bb276b | 2648 | fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", |
0fe24669 SB |
2649 | &tpm_config, sizeof tpm_config); |
2650 | } | |
2651 | ||
d03637bc BW |
2652 | vmgenid_dev = find_vmgenid_dev(); |
2653 | if (vmgenid_dev) { | |
f0bb276b | 2654 | vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, |
d03637bc BW |
2655 | tables.vmgenid); |
2656 | } | |
2657 | ||
bb292f5a | 2658 | if (!pcmc->rsdp_in_ram) { |
358774d7 IM |
2659 | /* |
2660 | * Keep for compatibility with old machine types. | |
2661 | * Though RSDP is small, its contents isn't immutable, so | |
afaa2e4b | 2662 | * we'll update it along with the rest of tables on guest access. |
358774d7 | 2663 | */ |
afaa2e4b MT |
2664 | uint32_t rsdp_size = acpi_data_len(tables.rsdp); |
2665 | ||
2666 | build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); | |
f0bb276b | 2667 | fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, |
5f9252f7 | 2668 | acpi_build_update, NULL, build_state, |
baf2d5bf | 2669 | build_state->rsdp, rsdp_size, true); |
339240b5 | 2670 | build_state->rsdp_mr = NULL; |
358774d7 | 2671 | } else { |
42d85900 | 2672 | build_state->rsdp = NULL; |
82f76c67 WY |
2673 | build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, |
2674 | build_state, tables.rsdp, | |
6930ba0d | 2675 | ACPI_BUILD_RSDP_FILE); |
358774d7 | 2676 | } |
72c194f7 MT |
2677 | |
2678 | qemu_register_reset(acpi_build_reset, build_state); | |
2679 | acpi_build_reset(build_state); | |
2680 | vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); | |
2681 | ||
2682 | /* Cleanup tables but don't free the memory: we track it | |
2683 | * in build_state. | |
2684 | */ | |
2685 | acpi_build_tables_cleanup(&tables, false); | |
2686 | } |