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numa: reduce code duplication by adding helper numa_get_node_for_cpu()
[mirror_qemu.git] / hw / i386 / acpi-build.c
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72c194f7
MT		 1/* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
b6a0aa05 23#include "qemu/osdep.h"
da34e65c 24#include "qapi/error.h"
72c194f7 25#include "acpi-build.h"
72c194f7
MT		 26#include "qemu-common.h"
27#include "qemu/bitmap.h"
07fb6176 28#include "qemu/error-report.h"
72c194f7
MT		 29#include "hw/pci/pci.h"
30#include "qom/cpu.h"
31#include "hw/i386/pc.h"
32#include "target-i386/cpu.h"
33#include "hw/timer/hpet.h"
395e5fb4 34#include "hw/acpi/acpi-defs.h"
72c194f7 35#include "hw/acpi/acpi.h"
679dd1a9 36#include "hw/acpi/cpu.h"
72c194f7 37#include "hw/nvram/fw_cfg.h"
0058ae1d 38#include "hw/acpi/bios-linker-loader.h"
72c194f7 39#include "hw/loader.h"
15bce1b7 40#include "hw/isa/isa.h"
27b9fc54 41#include "hw/block/fdc.h"
bef3492d 42#include "hw/acpi/memory_hotplug.h"
711b20b4
SB		 43#include "sysemu/tpm.h"
44#include "hw/acpi/tpm.h"
5cb18b3d 45#include "sysemu/tpm_backend.h"
f070efa8 46#include "hw/timer/mc146818rtc_regs.h"
1f3aba37 47#include "sysemu/numa.h"
72c194f7
MT		 48
49/* Supported chipsets: */
50#include "hw/acpi/piix4.h"
99fd437d 51#include "hw/acpi/pcihp.h"
72c194f7
MT		 52#include "hw/i386/ich9.h"
53#include "hw/pci/pci_bus.h"
54#include "hw/pci-host/q35.h"
1cf5fd57 55#include "hw/i386/x86-iommu.h"
a57d708d 56#include "hw/timer/hpet.h"
72c194f7 57
19934e0e
IM		 58#include "hw/acpi/aml-build.h"
59
72c194f7
MT		 60#include "qapi/qmp/qint.h"
61#include "qom/qom-qobject.h"
fb9f5926
DK		 62#include "hw/i386/amd_iommu.h"
63#include "hw/i386/intel_iommu.h"
72c194f7 64
86e91dd7
CM		 65#include "hw/acpi/ipmi.h"
66
07fb6176
PB		 67/* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
68 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
69 * a little bit, there should be plenty of free space since the DSDT
70 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
71 */
72#define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
73#define ACPI_BUILD_ALIGN_SIZE 0x1000
74
868270f2 75#define ACPI_BUILD_TABLE_SIZE 0x20000
18045fb9 76
8b310fc4
GA		 77/* #define DEBUG_ACPI_BUILD */
78#ifdef DEBUG_ACPI_BUILD
79#define ACPI_BUILD_DPRINTF(fmt, ...) \
80 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
81#else
82#define ACPI_BUILD_DPRINTF(fmt, ...)
83#endif
84
cfc13df4
PX		 85/* Default IOAPIC ID */
86#define ACPI_BUILD_IOAPIC_ID 0x0
87
72c194f7
MT		 88typedef struct AcpiMcfgInfo {
89 uint64_t mcfg_base;
90 uint32_t mcfg_size;
91} AcpiMcfgInfo;
92
93typedef struct AcpiPmInfo {
94 bool s3_disabled;
95 bool s4_disabled;
133a2da4 96 bool pcihp_bridge_en;
72c194f7
MT		 97 uint8_t s4_val;
98 uint16_t sci_int;
99 uint8_t acpi_enable_cmd;
100 uint8_t acpi_disable_cmd;
101 uint32_t gpe0_blk;
102 uint32_t gpe0_blk_len;
103 uint32_t io_base;
ddf1ec2f 104 uint16_t cpu_hp_io_base;
2c6b94d8
IM		 105 uint16_t mem_hp_io_base;
106 uint16_t mem_hp_io_len;
500b11ea
IM		 107 uint16_t pcihp_io_base;
108 uint16_t pcihp_io_len;
72c194f7
MT		 109} AcpiPmInfo;
110
111typedef struct AcpiMiscInfo {
e4db2798 112 bool is_piix4;
72c194f7 113 bool has_hpet;
5cb18b3d 114 TPMVersion tpm_version;
72c194f7
MT		 115 const unsigned char *dsdt_code;
116 unsigned dsdt_size;
117 uint16_t pvpanic_port;
8ac6f7a6 118 uint16_t applesmc_io_base;
72c194f7
MT		 119} AcpiMiscInfo;
120
99fd437d
MT		 121typedef struct AcpiBuildPciBusHotplugState {
122 GArray *device_table;
123 GArray *notify_table;
124 struct AcpiBuildPciBusHotplugState *parent;
133a2da4 125 bool pcihp_bridge_en;
99fd437d
MT		 126} AcpiBuildPciBusHotplugState;
127
72c194f7
MT		 128static void acpi_get_pm_info(AcpiPmInfo *pm)
129{
130 Object *piix = piix4_pm_find();
131 Object *lpc = ich9_lpc_find();
132 Object *obj = NULL;
133 QObject *o;
134
94aaca64 135 pm->cpu_hp_io_base = 0;
500b11ea
IM		 136 pm->pcihp_io_base = 0;
137 pm->pcihp_io_len = 0;
72c194f7
MT		 138 if (piix) {
139 obj = piix;
ddf1ec2f 140 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
500b11ea
IM		 141 pm->pcihp_io_base =
142 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
143 pm->pcihp_io_len =
144 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
72c194f7
MT		 145 }
146 if (lpc) {
147 obj = lpc;
ddf1ec2f 148 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
72c194f7
MT		 149 }
150 assert(obj);
151
2c6b94d8
IM		 152 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
153 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
154
72c194f7
MT		 155 /* Fill in optional s3/s4 related properties */
156 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
157 if (o) {
158 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
159 } else {
160 pm->s3_disabled = false;
161 }
097a97a6 162 qobject_decref(o);
72c194f7
MT		 163 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
164 if (o) {
165 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
166 } else {
167 pm->s4_disabled = false;
168 }
097a97a6 169 qobject_decref(o);
72c194f7
MT		 170 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
171 if (o) {
172 pm->s4_val = qint_get_int(qobject_to_qint(o));
173 } else {
174 pm->s4_val = false;
175 }
097a97a6 176 qobject_decref(o);
72c194f7
MT		 177
178 /* Fill in mandatory properties */
179 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
180
181 pm->acpi_enable_cmd = object_property_get_int(obj,
182 ACPI_PM_PROP_ACPI_ENABLE_CMD,
183 NULL);
184 pm->acpi_disable_cmd = object_property_get_int(obj,
185 ACPI_PM_PROP_ACPI_DISABLE_CMD,
186 NULL);
187 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
188 NULL);
189 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
190 NULL);
191 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
192 NULL);
133a2da4
IM		 193 pm->pcihp_bridge_en =
194 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
195 NULL);
72c194f7
MT		 196}
197
72c194f7
MT		 198static void acpi_get_misc_info(AcpiMiscInfo *info)
199{
3db119da
IM		 200 Object *piix = piix4_pm_find();
201 Object *lpc = ich9_lpc_find();
202 assert(!!piix != !!lpc);
203
204 if (piix) {
205 info->is_piix4 = true;
206 }
207 if (lpc) {
208 info->is_piix4 = false;
209 }
210
72c194f7 211 info->has_hpet = hpet_find();
5cb18b3d 212 info->tpm_version = tpm_get_version();
72c194f7 213 info->pvpanic_port = pvpanic_port();
8ac6f7a6 214 info->applesmc_io_base = applesmc_port();
72c194f7
MT		 215}
216
ca6c1855
MA		 217/*
218 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
219 * On i386 arch we only have two pci hosts, so we can look only for them.
220 */
221static Object *acpi_get_i386_pci_host(void)
222{
223 PCIHostState *host;
224
225 host = OBJECT_CHECK(PCIHostState,
226 object_resolve_path("/machine/i440fx", NULL),
227 TYPE_PCI_HOST_BRIDGE);
228 if (!host) {
229 host = OBJECT_CHECK(PCIHostState,
230 object_resolve_path("/machine/q35", NULL),
231 TYPE_PCI_HOST_BRIDGE);
232 }
233
234 return OBJECT(host);
235}
236
01c9742d 237static void acpi_get_pci_holes(Range *hole, Range *hole64)
72c194f7
MT		 238{
239 Object *pci_host;
72c194f7 240
ca6c1855 241 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 242 g_assert(pci_host);
243
a0efbf16
MA		 244 range_set_bounds1(hole,
245 object_property_get_int(pci_host,
246 PCI_HOST_PROP_PCI_HOLE_START,
247 NULL),
248 object_property_get_int(pci_host,
249 PCI_HOST_PROP_PCI_HOLE_END,
250 NULL));
251 range_set_bounds1(hole64,
252 object_property_get_int(pci_host,
253 PCI_HOST_PROP_PCI_HOLE64_START,
254 NULL),
255 object_property_get_int(pci_host,
256 PCI_HOST_PROP_PCI_HOLE64_END,
257 NULL));
72c194f7
MT		 258}
259
72c194f7
MT		 260#define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
261
72c194f7
MT		 262static void acpi_align_size(GArray *blob, unsigned align)
263{
264 /* Align size to multiple of given size. This reduces the chance
265 * we need to change size in the future (breaking cross version migration).
266 */
134d42d6 267 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
72c194f7
MT		 268}
269
72c194f7
MT		 270/* FACS */
271static void
0e9b9eda 272build_facs(GArray *table_data, BIOSLinker *linker)
72c194f7
MT		 273{
274 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
821e3227 275 memcpy(&facs->signature, "FACS", 4);
72c194f7
MT		 276 facs->length = cpu_to_le32(sizeof(*facs));
277}
278
279/* Load chipset information in FADT */
280static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
281{
282 fadt->model = 1;
283 fadt->reserved1 = 0;
284 fadt->sci_int = cpu_to_le16(pm->sci_int);
285 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
286 fadt->acpi_enable = pm->acpi_enable_cmd;
287 fadt->acpi_disable = pm->acpi_disable_cmd;
288 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
289 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
290 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
291 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
292 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
293 /* EVT, CNT, TMR length matches hw/acpi/core.c */
294 fadt->pm1_evt_len = 4;
295 fadt->pm1_cnt_len = 2;
296 fadt->pm_tmr_len = 4;
297 fadt->gpe0_blk_len = pm->gpe0_blk_len;
298 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
299 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
300 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
301 (1 << ACPI_FADT_F_PROC_C1) |
302 (1 << ACPI_FADT_F_SLP_BUTTON) |
303 (1 << ACPI_FADT_F_RTC_S4));
304 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
07b81ed9
HZ		 305 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
306 * For more than 8 CPUs, "Clustered Logical" mode has to be used
307 */
308 if (max_cpus > 8) {
309 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
310 }
f070efa8 311 fadt->century = RTC_CENTURY;
72c194f7
MT		 312}
313
314
315/* FADT */
316static void
0e9b9eda 317build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
4678124b 318 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset,
ae123749 319 const char *oem_id, const char *oem_table_id)
72c194f7
MT		 320{
321 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
4678124b
IM		 322 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data;
323 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
72c194f7 324
72c194f7 325 /* FACS address to be filled by Guest linker */
4678124b
IM		 326 bios_linker_loader_add_pointer(linker,
327 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
328 ACPI_BUILD_TABLE_FILE, facs_tbl_offset);
72c194f7 329
72c194f7 330 /* DSDT address to be filled by Guest linker */
72c194f7 331 fadt_setup(fadt, pm);
4678124b
IM		 332 bios_linker_loader_add_pointer(linker,
333 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
334 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
72c194f7
MT		 335
336 build_header(linker, table_data,
ae123749 337 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
72c194f7
MT		 338}
339
ac35f13b
IM		 340void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
341 CPUArchIdList *apic_ids, GArray *entry)
342{
343 int apic_id;
344 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
345
346 apic_id = apic_ids->cpus[uid].arch_id;
347 apic->type = ACPI_APIC_PROCESSOR;
348 apic->length = sizeof(*apic);
349 apic->processor_id = uid;
350 apic->local_apic_id = apic_id;
351 if (apic_ids->cpus[uid].cpu != NULL) {
352 apic->flags = cpu_to_le32(1);
353 } else {
354 /* ACPI spec says that LAPIC entry for non present
355 * CPU may be omitted from MADT or it must be marked
356 * as disabled. However omitting non present CPU from
357 * MADT breaks hotplug on linux. So possible CPUs
358 * should be put in MADT but kept disabled.
359 */
360 apic->flags = cpu_to_le32(0);
361 }
362}
363
72c194f7 364static void
0e9b9eda 365build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
72c194f7 366{
907e7c94
IM		 367 MachineClass *mc = MACHINE_GET_CLASS(pcms);
368 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
72c194f7 369 int madt_start = table_data->len;
ac35f13b
IM		 370 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
371 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
72c194f7
MT		 372
373 AcpiMultipleApicTable *madt;
374 AcpiMadtIoApic *io_apic;
375 AcpiMadtIntsrcovr *intsrcovr;
376 AcpiMadtLocalNmi *local_nmi;
377 int i;
378
379 madt = acpi_data_push(table_data, sizeof *madt);
380 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
381 madt->flags = cpu_to_le32(1);
382
907e7c94 383 for (i = 0; i < apic_ids->len; i++) {
ac35f13b 384 adevc->madt_cpu(adev, i, apic_ids, table_data);
72c194f7 385 }
907e7c94
IM		 386 g_free(apic_ids);
387
72c194f7
MT		 388 io_apic = acpi_data_push(table_data, sizeof *io_apic);
389 io_apic->type = ACPI_APIC_IO;
390 io_apic->length = sizeof(*io_apic);
72c194f7
MT		 391 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
392 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
393 io_apic->interrupt = cpu_to_le32(0);
394
dd4c2f01 395 if (pcms->apic_xrupt_override) {
72c194f7
MT		 396 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
397 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
398 intsrcovr->length = sizeof(*intsrcovr);
399 intsrcovr->source = 0;
400 intsrcovr->gsi = cpu_to_le32(2);
401 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
402 }
403 for (i = 1; i < 16; i++) {
404#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
405 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
406 /* No need for a INT source override structure. */
407 continue;
408 }
409 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
410 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
411 intsrcovr->length = sizeof(*intsrcovr);
412 intsrcovr->source = i;
413 intsrcovr->gsi = cpu_to_le32(i);
414 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
415 }
416
417 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
418 local_nmi->type = ACPI_APIC_LOCAL_NMI;
419 local_nmi->length = sizeof(*local_nmi);
420 local_nmi->processor_id = 0xff; /* all processors */
421 local_nmi->flags = cpu_to_le16(0);
422 local_nmi->lint = 1; /* ACPI_LINT1 */
423
424 build_header(linker, table_data,
821e3227 425 (void *)(table_data->data + madt_start), "APIC",
37ad223c 426 table_data->len - madt_start, 1, NULL, NULL);
72c194f7
MT		 427}
428
99fd437d
MT		 429/* Assign BSEL property to all buses. In the future, this can be changed
430 * to only assign to buses that support hotplug.
431 */
432static void *acpi_set_bsel(PCIBus *bus, void *opaque)
433{
434 unsigned *bsel_alloc = opaque;
435 unsigned *bus_bsel;
436
39b888bd 437 if (qbus_is_hotpluggable(BUS(bus))) {
99fd437d
MT		 438 bus_bsel = g_malloc(sizeof *bus_bsel);
439
440 *bus_bsel = (*bsel_alloc)++;
441 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
442 bus_bsel, NULL);
443 }
444
445 return bsel_alloc;
446}
447
448static void acpi_set_pci_info(void)
449{
450 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
451 unsigned bsel_alloc = 0;
452
453 if (bus) {
454 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
455 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
456 }
457}
458
62b52c26 459static void build_append_pcihp_notify_entry(Aml *method, int slot)
99fd437d 460{
62b52c26
IM		 461 Aml *if_ctx;
462 int32_t devfn = PCI_DEVFN(slot, 0);
463
5530427f 464 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
62b52c26
IM		 465 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
466 aml_append(method, if_ctx);
99fd437d
MT		 467}
468
62b52c26 469static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
b23046ab 470 bool pcihp_bridge_en)
99fd437d 471{
62b52c26 472 Aml *dev, *notify_method, *method;
99fd437d 473 QObject *bsel;
b23046ab
IM		 474 PCIBus *sec;
475 int i;
133a2da4 476
99fd437d
MT		 477 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
478 if (bsel) {
62b52c26
IM		 479 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
480
481 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
4dbfc881 482 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
8dcf525a 483 }
99fd437d 484
8dcf525a
MT		 485 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
486 DeviceClass *dc;
487 PCIDeviceClass *pc;
488 PCIDevice *pdev = bus->devices[i];
489 int slot = PCI_SLOT(i);
b23046ab 490 bool hotplug_enabled_dev;
093a35e5 491 bool bridge_in_acpi;
99fd437d 492
8dcf525a 493 if (!pdev) {
b23046ab 494 if (bsel) { /* add hotplug slots for non present devices */
62b52c26
IM		 495 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
496 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
497 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
4dbfc881 498 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 499 aml_append(method,
500 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
501 );
502 aml_append(dev, method);
503 aml_append(parent_scope, dev);
504
505 build_append_pcihp_notify_entry(notify_method, slot);
b23046ab 506 }
8dcf525a
MT		 507 continue;
508 }
99fd437d 509
8dcf525a
MT		 510 pc = PCI_DEVICE_GET_CLASS(pdev);
511 dc = DEVICE_GET_CLASS(pdev);
99fd437d 512
093a35e5
MT		 513 /* When hotplug for bridges is enabled, bridges are
514 * described in ACPI separately (see build_pci_bus_end).
515 * In this case they aren't themselves hot-pluggable.
a20275fa 516 * Hotplugged bridges *are* hot-pluggable.
093a35e5 517 */
b23046ab
IM		 518 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
519 !DEVICE(pdev)->hotplugged;
520
521 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
093a35e5 522
b23046ab
IM		 523 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
524 continue;
99fd437d
MT		 525 }
526
62b52c26
IM		 527 /* start to compose PCI slot descriptor */
528 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
529 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
530
8dcf525a 531 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
62b52c26
IM		 532 /* add VGA specific AML methods */
533 int s3d;
534
8dcf525a 535 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
62b52c26 536 s3d = 3;
b23046ab 537 } else {
62b52c26 538 s3d = 0;
99fd437d 539 }
62b52c26 540
4dbfc881 541 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 542 aml_append(method, aml_return(aml_int(0)));
543 aml_append(dev, method);
544
4dbfc881 545 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 546 aml_append(method, aml_return(aml_int(0)));
547 aml_append(dev, method);
548
4dbfc881 549 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 550 aml_append(method, aml_return(aml_int(s3d)));
551 aml_append(dev, method);
b23046ab 552 } else if (hotplug_enabled_dev) {
62b52c26
IM		 553 /* add _SUN/_EJ0 to make slot hotpluggable */
554 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
99fd437d 555
4dbfc881 556 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 557 aml_append(method,
558 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
559 );
560 aml_append(dev, method);
561
562 if (bsel) {
563 build_append_pcihp_notify_entry(notify_method, slot);
564 }
b23046ab 565 } else if (bridge_in_acpi) {
62b52c26
IM		 566 /*
567 * device is coldplugged bridge,
568 * add child device descriptions into its scope
569 */
b23046ab 570 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
b23046ab 571
62b52c26 572 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
8dcf525a 573 }
62b52c26
IM		 574 /* slot descriptor has been composed, add it into parent context */
575 aml_append(parent_scope, dev);
8dcf525a
MT		 576 }
577
578 if (bsel) {
62b52c26 579 aml_append(parent_scope, notify_method);
99fd437d
MT		 580 }
581
582 /* Append PCNT method to notify about events on local and child buses.
583 * Add unconditionally for root since DSDT expects it.
72c194f7 584 */
4dbfc881 585 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
99fd437d 586
b23046ab
IM		 587 /* If bus supports hotplug select it and notify about local events */
588 if (bsel) {
62b52c26
IM		 589 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
590 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
591 aml_append(method,
592 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
593 );
594 aml_append(method,
595 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
596 );
b23046ab 597 }
99fd437d 598
b23046ab
IM		 599 /* Notify about child bus events in any case */
600 if (pcihp_bridge_en) {
601 QLIST_FOREACH(sec, &bus->child, sibling) {
62b52c26
IM		 602 int32_t devfn = sec->parent_dev->devfn;
603
c99cb18e
MA		 604 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
605 continue;
606 }
607
62b52c26 608 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
99fd437d 609 }
72c194f7 610 }
62b52c26 611 aml_append(parent_scope, method);
d370dfa9 612 qobject_decref(bsel);
72c194f7
MT		 613}
614
196e2137
IM		 615/**
616 * build_prt_entry:
617 * @link_name: link name for PCI route entry
618 *
619 * build AML package containing a PCI route entry for @link_name
620 */
621static Aml *build_prt_entry(const char *link_name)
622{
623 Aml *a_zero = aml_int(0);
624 Aml *pkg = aml_package(4);
625 aml_append(pkg, a_zero);
626 aml_append(pkg, a_zero);
627 aml_append(pkg, aml_name("%s", link_name));
628 aml_append(pkg, a_zero);
629 return pkg;
630}
631
0d8935e3
MA		 632/*
633 * initialize_route - Initialize the interrupt routing rule
634 * through a specific LINK:
635 * if (lnk_idx == idx)
636 * route using link 'link_name'
637 */
638static Aml *initialize_route(Aml *route, const char *link_name,
639 Aml *lnk_idx, int idx)
640{
641 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
196e2137 642 Aml *pkg = build_prt_entry(link_name);
0d8935e3 643
0d8935e3
MA		 644 aml_append(if_ctx, aml_store(pkg, route));
645
646 return if_ctx;
647}
648
649/*
650 * build_prt - Define interrupt rounting rules
651 *
652 * Returns an array of 128 routes, one for each device,
653 * based on device location.
654 * The main goal is to equaly distribute the interrupts
655 * over the 4 existing ACPI links (works only for i440fx).
656 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
657 *
658 */
196e2137 659static Aml *build_prt(bool is_pci0_prt)
0d8935e3
MA		 660{
661 Aml *method, *while_ctx, *pin, *res;
662
4dbfc881 663 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
0d8935e3
MA		 664 res = aml_local(0);
665 pin = aml_local(1);
666 aml_append(method, aml_store(aml_package(128), res));
667 aml_append(method, aml_store(aml_int(0), pin));
668
669 /* while (pin < 128) */
670 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
671 {
672 Aml *slot = aml_local(2);
673 Aml *lnk_idx = aml_local(3);
674 Aml *route = aml_local(4);
675
676 /* slot = pin >> 2 */
677 aml_append(while_ctx,
c360639a 678 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
0d8935e3
MA		 679 /* lnk_idx = (slot + pin) & 3 */
680 aml_append(while_ctx,
5530427f
IM		 681 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
682 lnk_idx));
0d8935e3
MA		 683
684 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
685 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
196e2137
IM		 686 if (is_pci0_prt) {
687 Aml *if_device_1, *if_pin_4, *else_pin_4;
688
689 /* device 1 is the power-management device, needs SCI */
690 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
691 {
692 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
693 {
694 aml_append(if_pin_4,
695 aml_store(build_prt_entry("LNKS"), route));
696 }
697 aml_append(if_device_1, if_pin_4);
698 else_pin_4 = aml_else();
699 {
700 aml_append(else_pin_4,
701 aml_store(build_prt_entry("LNKA"), route));
702 }
703 aml_append(if_device_1, else_pin_4);
704 }
705 aml_append(while_ctx, if_device_1);
706 } else {
707 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
708 }
0d8935e3
MA		 709 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
710 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
711
712 /* route[0] = 0x[slot]FFFF */
713 aml_append(while_ctx,
ca3df95d
IM		 714 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
715 NULL),
0d8935e3
MA		 716 aml_index(route, aml_int(0))));
717 /* route[1] = pin & 3 */
718 aml_append(while_ctx,
5530427f
IM		 719 aml_store(aml_and(pin, aml_int(3), NULL),
720 aml_index(route, aml_int(1))));
0d8935e3
MA		 721 /* res[pin] = route */
722 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
723 /* pin++ */
724 aml_append(while_ctx, aml_increment(pin));
725 }
726 aml_append(method, while_ctx);
727 /* return res*/
728 aml_append(method, aml_return(res));
729
730 return method;
731}
732
a43c6e27
MA		 733typedef struct CrsRangeEntry {
734 uint64_t base;
735 uint64_t limit;
736} CrsRangeEntry;
737
738static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
739{
740 CrsRangeEntry *entry;
741
742 entry = g_malloc(sizeof(*entry));
743 entry->base = base;
744 entry->limit = limit;
745
746 g_ptr_array_add(ranges, entry);
747}
748
749static void crs_range_free(gpointer data)
750{
751 CrsRangeEntry *entry = (CrsRangeEntry *)data;
752 g_free(entry);
753}
754
2df5a7b5
MA		 755typedef struct CrsRangeSet {
756 GPtrArray *io_ranges;
757 GPtrArray *mem_ranges;
16de88a4 758 GPtrArray *mem_64bit_ranges;
2df5a7b5
MA		 759 } CrsRangeSet;
760
761static void crs_range_set_init(CrsRangeSet *range_set)
762{
763 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
764 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
16de88a4
MA		 765 range_set->mem_64bit_ranges =
766 g_ptr_array_new_with_free_func(crs_range_free);
2df5a7b5
MA		 767}
768
769static void crs_range_set_free(CrsRangeSet *range_set)
770{
771 g_ptr_array_free(range_set->io_ranges, true);
772 g_ptr_array_free(range_set->mem_ranges, true);
16de88a4 773 g_ptr_array_free(range_set->mem_64bit_ranges, true);
2df5a7b5
MA		 774}
775
dcdca296
MA		 776static gint crs_range_compare(gconstpointer a, gconstpointer b)
777{
778 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
779 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
780
781 return (int64_t)entry_a->base - (int64_t)entry_b->base;
782}
783
784/*
785 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
786 * interval, computes the 'free' ranges from the same interval.
787 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
788 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
789 */
790static void crs_replace_with_free_ranges(GPtrArray *ranges,
791 uint64_t start, uint64_t end)
792{
354fb471 793 GPtrArray *free_ranges = g_ptr_array_new();
dcdca296
MA		 794 uint64_t free_base = start;
795 int i;
796
797 g_ptr_array_sort(ranges, crs_range_compare);
798 for (i = 0; i < ranges->len; i++) {
799 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
800
801 if (free_base < used->base) {
802 crs_range_insert(free_ranges, free_base, used->base - 1);
803 }
804
805 free_base = used->limit + 1;
806 }
807
808 if (free_base < end) {
809 crs_range_insert(free_ranges, free_base, end);
810 }
811
812 g_ptr_array_set_size(ranges, 0);
813 for (i = 0; i < free_ranges->len; i++) {
814 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
815 }
816
354fb471 817 g_ptr_array_free(free_ranges, true);
dcdca296
MA		 818}
819
d7fd0e69
MA		 820/*
821 * crs_range_merge - merges adjacent ranges in the given array.
822 * Array elements are deleted and replaced with the merged ranges.
823 */
824static void crs_range_merge(GPtrArray *range)
825{
826 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
827 CrsRangeEntry *entry;
828 uint64_t range_base, range_limit;
829 int i;
830
831 if (!range->len) {
832 return;
833 }
834
835 g_ptr_array_sort(range, crs_range_compare);
836
837 entry = g_ptr_array_index(range, 0);
838 range_base = entry->base;
839 range_limit = entry->limit;
840 for (i = 1; i < range->len; i++) {
841 entry = g_ptr_array_index(range, i);
842 if (entry->base - 1 == range_limit) {
843 range_limit = entry->limit;
844 } else {
845 crs_range_insert(tmp, range_base, range_limit);
846 range_base = entry->base;
847 range_limit = entry->limit;
848 }
849 }
850 crs_range_insert(tmp, range_base, range_limit);
851
852 g_ptr_array_set_size(range, 0);
853 for (i = 0; i < tmp->len; i++) {
854 entry = g_ptr_array_index(tmp, i);
855 crs_range_insert(range, entry->base, entry->limit);
856 }
857 g_ptr_array_free(tmp, true);
858}
859
2df5a7b5 860static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
a43c6e27
MA		 861{
862 Aml *crs = aml_resource_template();
2df5a7b5 863 CrsRangeSet temp_range_set;
d7fd0e69 864 CrsRangeEntry *entry;
a43c6e27
MA		 865 uint8_t max_bus = pci_bus_num(host->bus);
866 uint8_t type;
867 int devfn;
d7fd0e69 868 int i;
a43c6e27 869
2df5a7b5 870 crs_range_set_init(&temp_range_set);
a43c6e27 871 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
a43c6e27
MA		 872 uint64_t range_base, range_limit;
873 PCIDevice *dev = host->bus->devices[devfn];
874
875 if (!dev) {
876 continue;
877 }
878
879 for (i = 0; i < PCI_NUM_REGIONS; i++) {
880 PCIIORegion *r = &dev->io_regions[i];
881
882 range_base = r->addr;
883 range_limit = r->addr + r->size - 1;
884
0f6dd8e1
MA		 885 /*
886 * Work-around for old bioses
887 * that do not support multiple root buses
888 */
889 if (!range_base || range_base > range_limit) {
890 continue;
891 }
892
a43c6e27 893 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
2df5a7b5
MA		 894 crs_range_insert(temp_range_set.io_ranges,
895 range_base, range_limit);
a43c6e27 896 } else { /* "memory" */
2df5a7b5
MA		 897 crs_range_insert(temp_range_set.mem_ranges,
898 range_base, range_limit);
a43c6e27
MA		 899 }
900 }
901
902 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
903 if (type == PCI_HEADER_TYPE_BRIDGE) {
904 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
905 if (subordinate > max_bus) {
906 max_bus = subordinate;
907 }
908
909 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
910 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
0f6dd8e1
MA		 911
912 /*
913 * Work-around for old bioses
914 * that do not support multiple root buses
915 */
4ebc736e 916 if (range_base && range_base <= range_limit) {
2df5a7b5
MA		 917 crs_range_insert(temp_range_set.io_ranges,
918 range_base, range_limit);
0f6dd8e1 919 }
a43c6e27
MA		 920
921 range_base =
922 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
923 range_limit =
924 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
0f6dd8e1
MA		 925
926 /*
927 * Work-around for old bioses
928 * that do not support multiple root buses
929 */
4ebc736e 930 if (range_base && range_base <= range_limit) {
16de88a4
MA		 931 uint64_t length = range_limit - range_base + 1;
932 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
933 crs_range_insert(temp_range_set.mem_ranges,
934 range_base, range_limit);
935 } else {
936 crs_range_insert(temp_range_set.mem_64bit_ranges,
937 range_base, range_limit);
938 }
4ebc736e 939 }
a43c6e27
MA		 940
941 range_base =
942 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
943 range_limit =
944 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
0f6dd8e1
MA		 945
946 /*
947 * Work-around for old bioses
948 * that do not support multiple root buses
949 */
4ebc736e 950 if (range_base && range_base <= range_limit) {
16de88a4
MA		 951 uint64_t length = range_limit - range_base + 1;
952 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
953 crs_range_insert(temp_range_set.mem_ranges,
954 range_base, range_limit);
955 } else {
956 crs_range_insert(temp_range_set.mem_64bit_ranges,
957 range_base, range_limit);
958 }
0f6dd8e1 959 }
a43c6e27
MA		 960 }
961 }
962
2df5a7b5
MA		 963 crs_range_merge(temp_range_set.io_ranges);
964 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
965 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
d7fd0e69
MA		 966 aml_append(crs,
967 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
968 AML_POS_DECODE, AML_ENTIRE_RANGE,
969 0, entry->base, entry->limit, 0,
970 entry->limit - entry->base + 1));
2df5a7b5 971 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
d7fd0e69 972 }
d7fd0e69 973
2df5a7b5
MA		 974 crs_range_merge(temp_range_set.mem_ranges);
975 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
976 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
d7fd0e69
MA		 977 aml_append(crs,
978 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
979 AML_MAX_FIXED, AML_NON_CACHEABLE,
980 AML_READ_WRITE,
981 0, entry->base, entry->limit, 0,
982 entry->limit - entry->base + 1));
2df5a7b5 983 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
d7fd0e69 984 }
2df5a7b5 985
16de88a4
MA		 986 crs_range_merge(temp_range_set.mem_64bit_ranges);
987 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
988 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
989 aml_append(crs,
990 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
991 AML_MAX_FIXED, AML_NON_CACHEABLE,
992 AML_READ_WRITE,
993 0, entry->base, entry->limit, 0,
994 entry->limit - entry->base + 1));
995 crs_range_insert(range_set->mem_64bit_ranges,
996 entry->base, entry->limit);
997 }
998
2df5a7b5 999 crs_range_set_free(&temp_range_set);
d7fd0e69 1000
a43c6e27 1001 aml_append(crs,
dcdca296 1002 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
a43c6e27
MA		 1003 0,
1004 pci_bus_num(host->bus),
1005 max_bus,
1006 0,
1007 max_bus - pci_bus_num(host->bus) + 1));
1008
1009 return crs;
1010}
1011
f177d40a
IM		 1012static void build_memory_devices(Aml *sb_scope, int nr_mem,
1013 uint16_t io_base, uint16_t io_len)
1014{
1015 int i;
1016 Aml *scope;
1017 Aml *crs;
1018 Aml *field;
1019 Aml *dev;
1020 Aml *method;
1021 Aml *ifctx;
1022
1023 /* build memory devices */
1024 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
f84548dd 1025 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
f177d40a 1026 aml_append(scope,
f84548dd 1027 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
f177d40a
IM		 1028 );
1029
1030 crs = aml_resource_template();
1031 aml_append(crs,
1032 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
1033 );
1034 aml_append(scope, aml_name_decl("_CRS", crs));
1035
1036 aml_append(scope, aml_operation_region(
f84548dd 1037 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
3f3009c0 1038 aml_int(io_base), io_len)
f177d40a
IM		 1039 );
1040
f84548dd 1041 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
f177d40a
IM		 1042 AML_NOLOCK, AML_PRESERVE);
1043 aml_append(field, /* read only */
f84548dd 1044 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
f177d40a 1045 aml_append(field, /* read only */
f84548dd 1046 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
f177d40a 1047 aml_append(field, /* read only */
f84548dd 1048 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
f177d40a 1049 aml_append(field, /* read only */
f84548dd 1050 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
f177d40a 1051 aml_append(field, /* read only */
f84548dd 1052 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
f177d40a
IM		 1053 aml_append(scope, field);
1054
f84548dd 1055 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
f177d40a
IM		 1056 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1057 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1058 aml_append(field, /* 1 if enabled, read only */
f84548dd 1059 aml_named_field(MEMORY_SLOT_ENABLED, 1));
f177d40a
IM		 1060 aml_append(field,
1061 /*(read) 1 if has a insert event. (write) 1 to clear event */
f84548dd 1062 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
f177d40a
IM		 1063 aml_append(field,
1064 /* (read) 1 if has a remove event. (write) 1 to clear event */
f84548dd 1065 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
f177d40a
IM		 1066 aml_append(field,
1067 /* initiates device eject, write only */
f84548dd 1068 aml_named_field(MEMORY_SLOT_EJECT, 1));
f177d40a
IM		 1069 aml_append(scope, field);
1070
f84548dd 1071 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
f177d40a
IM		 1072 AML_NOLOCK, AML_PRESERVE);
1073 aml_append(field, /* DIMM selector, write only */
f84548dd 1074 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
f177d40a 1075 aml_append(field, /* _OST event code, write only */
f84548dd 1076 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
f177d40a 1077 aml_append(field, /* _OST status code, write only */
f84548dd 1078 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
f177d40a
IM		 1079 aml_append(scope, field);
1080 aml_append(sb_scope, scope);
1081
1082 for (i = 0; i < nr_mem; i++) {
f84548dd 1083 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
f177d40a
IM		 1084 const char *s;
1085
1086 dev = aml_device("MP%02X", i);
1087 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1088 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1089
1090 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
f84548dd 1091 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
f177d40a
IM		 1092 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1093 aml_append(dev, method);
1094
1095 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
f84548dd 1096 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
f177d40a
IM		 1097 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1098 aml_append(dev, method);
1099
1100 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
f84548dd 1101 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
f177d40a
IM		 1102 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1103 aml_append(dev, method);
1104
1105 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
f84548dd
IM		 1106 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1107
f177d40a
IM		 1108 aml_append(method, aml_return(aml_call4(
1109 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1110 )));
1111 aml_append(dev, method);
1112
1113 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
f84548dd 1114 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
f177d40a
IM		 1115 aml_append(method, aml_return(aml_call2(
1116 s, aml_name("_UID"), aml_arg(0))));
1117 aml_append(dev, method);
1118
1119 aml_append(sb_scope, dev);
1120 }
1121
1122 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1123 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1124 */
f84548dd 1125 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
f177d40a
IM		 1126 for (i = 0; i < nr_mem; i++) {
1127 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1128 aml_append(ifctx,
1129 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1130 );
1131 aml_append(method, ifctx);
1132 }
1133 aml_append(sb_scope, method);
1134}
1135
a57d708d
IM		 1136static void build_hpet_aml(Aml *table)
1137{
1138 Aml *crs;
1139 Aml *field;
1140 Aml *method;
1141 Aml *if_ctx;
1142 Aml *scope = aml_scope("_SB");
1143 Aml *dev = aml_device("HPET");
1144 Aml *zero = aml_int(0);
1145 Aml *id = aml_local(0);
1146 Aml *period = aml_local(1);
1147
1148 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1149 aml_append(dev, aml_name_decl("_UID", zero));
1150
1151 aml_append(dev,
3f3009c0
XG		 1152 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1153 HPET_LEN));
a57d708d
IM		 1154 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1155 aml_append(field, aml_named_field("VEND", 32));
1156 aml_append(field, aml_named_field("PRD", 32));
1157 aml_append(dev, field);
1158
1159 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1160 aml_append(method, aml_store(aml_name("VEND"), id));
1161 aml_append(method, aml_store(aml_name("PRD"), period));
1162 aml_append(method, aml_shiftright(id, aml_int(16), id));
1163 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1164 aml_equal(id, aml_int(0xffff))));
1165 {
1166 aml_append(if_ctx, aml_return(zero));
1167 }
1168 aml_append(method, if_ctx);
1169
1170 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1171 aml_lgreater(period, aml_int(100000000))));
1172 {
1173 aml_append(if_ctx, aml_return(zero));
1174 }
1175 aml_append(method, if_ctx);
1176
1177 aml_append(method, aml_return(aml_int(0x0F)));
1178 aml_append(dev, method);
1179
1180 crs = aml_resource_template();
1181 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1182 aml_append(dev, aml_name_decl("_CRS", crs));
1183
1184 aml_append(scope, dev);
1185 aml_append(table, scope);
1186}
1187
27b9fc54 1188static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
95ed7e97 1189{
27b9fc54
RK		 1190 Aml *dev, *fdi;
1191 uint8_t maxc, maxh, maxs;
1192
1193 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1194
1195 dev = aml_device("FLP%c", 'A' + idx);
1196
1197 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1198
1199 fdi = aml_package(16);
1200 aml_append(fdi, aml_int(idx)); /* Drive Number */
1201 aml_append(fdi,
1202 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1203 /*
1204 * the values below are the limits of the drive, and are thus independent
1205 * of the inserted media
1206 */
1207 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1208 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1209 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1210 /*
1211 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1212 * the drive type, so shall we
1213 */
1214 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1215 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1216 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1217 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1218 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1219 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1220 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1221 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1222 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1223 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1224 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1225
1226 aml_append(dev, aml_name_decl("_FDI", fdi));
1227 return dev;
1228}
1229
1230static Aml *build_fdc_device_aml(ISADevice *fdc)
1231{
1232 int i;
95ed7e97
IM		 1233 Aml *dev;
1234 Aml *crs;
95ed7e97 1235
27b9fc54
RK		 1236#define ACPI_FDE_MAX_FD 4
1237 uint32_t fde_buf[5] = {
1238 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1239 cpu_to_le32(2) /* tape presence (2 == never present) */
1240 };
1241
95ed7e97
IM		 1242 dev = aml_device("FDC0");
1243 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1244
95ed7e97
IM		 1245 crs = aml_resource_template();
1246 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1247 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1248 aml_append(crs, aml_irq_no_flags(6));
1249 aml_append(crs,
1250 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1251 aml_append(dev, aml_name_decl("_CRS", crs));
1252
27b9fc54
RK		 1253 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1254 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1255
1256 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1257 fde_buf[i] = cpu_to_le32(1); /* drive present */
1258 aml_append(dev, build_fdinfo_aml(i, type));
1259 }
1260 }
1261 aml_append(dev, aml_name_decl("_FDE",
1262 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1263
95ed7e97
IM		 1264 return dev;
1265}
1266
ee135849
IM		 1267static Aml *build_rtc_device_aml(void)
1268{
1269 Aml *dev;
1270 Aml *crs;
1271
1272 dev = aml_device("RTC");
1273 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1274 crs = aml_resource_template();
1275 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1276 aml_append(crs, aml_irq_no_flags(8));
1277 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
95ed7e97 1278 aml_append(dev, aml_name_decl("_CRS", crs));
f58190e2
IM		 1279
1280 return dev;
1281}
1282
1283static Aml *build_kbd_device_aml(void)
1284{
1285 Aml *dev;
1286 Aml *crs;
1287 Aml *method;
1288
1289 dev = aml_device("KBD");
1290 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1291
1292 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1293 aml_append(method, aml_return(aml_int(0x0f)));
1294 aml_append(dev, method);
1295
1296 crs = aml_resource_template();
1297 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1298 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1299 aml_append(crs, aml_irq_no_flags(1));
ee135849
IM		 1300 aml_append(dev, aml_name_decl("_CRS", crs));
1301
1302 return dev;
1303}
1304
c355cb2c
IM		 1305static Aml *build_mouse_device_aml(void)
1306{
1307 Aml *dev;
1308 Aml *crs;
1309 Aml *method;
1310
1311 dev = aml_device("MOU");
1312 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1313
1314 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1315 aml_append(method, aml_return(aml_int(0x0f)));
1316 aml_append(dev, method);
1317
1318 crs = aml_resource_template();
1319 aml_append(crs, aml_irq_no_flags(12));
1320 aml_append(dev, aml_name_decl("_CRS", crs));
1321
1322 return dev;
1323}
1324
8b1da5f8
IM		 1325static Aml *build_lpt_device_aml(void)
1326{
1327 Aml *dev;
1328 Aml *crs;
1329 Aml *method;
1330 Aml *if_ctx;
1331 Aml *else_ctx;
1332 Aml *zero = aml_int(0);
1333 Aml *is_present = aml_local(0);
1334
1335 dev = aml_device("LPT");
1336 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1337
1338 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1339 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1340 if_ctx = aml_if(aml_equal(is_present, zero));
1341 {
1342 aml_append(if_ctx, aml_return(aml_int(0x00)));
1343 }
1344 aml_append(method, if_ctx);
1345 else_ctx = aml_else();
1346 {
1347 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1348 }
1349 aml_append(method, else_ctx);
1350 aml_append(dev, method);
1351
1352 crs = aml_resource_template();
1353 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1354 aml_append(crs, aml_irq_no_flags(7));
1355 aml_append(dev, aml_name_decl("_CRS", crs));
1356
1357 return dev;
1358}
1359
28f1f0e9
IM		 1360static Aml *build_com_device_aml(uint8_t uid)
1361{
1362 Aml *dev;
1363 Aml *crs;
1364 Aml *method;
1365 Aml *if_ctx;
1366 Aml *else_ctx;
1367 Aml *zero = aml_int(0);
1368 Aml *is_present = aml_local(0);
1369 const char *enabled_field = "CAEN";
1370 uint8_t irq = 4;
1371 uint16_t io_port = 0x03F8;
1372
1373 assert(uid == 1 || uid == 2);
1374 if (uid == 2) {
1375 enabled_field = "CBEN";
1376 irq = 3;
1377 io_port = 0x02F8;
1378 }
1379
1380 dev = aml_device("COM%d", uid);
1381 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1382 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1383
1384 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1385 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1386 if_ctx = aml_if(aml_equal(is_present, zero));
1387 {
1388 aml_append(if_ctx, aml_return(aml_int(0x00)));
1389 }
1390 aml_append(method, if_ctx);
1391 else_ctx = aml_else();
1392 {
1393 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1394 }
1395 aml_append(method, else_ctx);
1396 aml_append(dev, method);
1397
1398 crs = aml_resource_template();
1399 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1400 aml_append(crs, aml_irq_no_flags(irq));
1401 aml_append(dev, aml_name_decl("_CRS", crs));
1402
1403 return dev;
1404}
1405
ee135849
IM		 1406static void build_isa_devices_aml(Aml *table)
1407{
27b9fc54 1408 ISADevice *fdc = pc_find_fdc0();
86e91dd7 1409 bool ambiguous;
27b9fc54 1410
ee135849 1411 Aml *scope = aml_scope("_SB.PCI0.ISA");
86e91dd7 1412 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
ee135849
IM		 1413
1414 aml_append(scope, build_rtc_device_aml());
f58190e2 1415 aml_append(scope, build_kbd_device_aml());
c355cb2c 1416 aml_append(scope, build_mouse_device_aml());
27b9fc54
RK		 1417 if (fdc) {
1418 aml_append(scope, build_fdc_device_aml(fdc));
9b613f4e 1419 }
8b1da5f8 1420 aml_append(scope, build_lpt_device_aml());
28f1f0e9
IM		 1421 aml_append(scope, build_com_device_aml(1));
1422 aml_append(scope, build_com_device_aml(2));
ee135849 1423
86e91dd7
CM		 1424 if (ambiguous) {
1425 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1426 } else if (!obj) {
1427 error_report("No ISA bus, unable to define IPMI ACPI data");
1428 } else {
1429 build_acpi_ipmi_devices(scope, BUS(obj));
1430 }
1431
ee135849
IM		 1432 aml_append(table, scope);
1433}
1434
3892a2b7
IM		 1435static void build_dbg_aml(Aml *table)
1436{
1437 Aml *field;
1438 Aml *method;
1439 Aml *while_ctx;
1440 Aml *scope = aml_scope("\\");
1441 Aml *buf = aml_local(0);
1442 Aml *len = aml_local(1);
1443 Aml *idx = aml_local(2);
1444
1445 aml_append(scope,
3f3009c0 1446 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
3892a2b7
IM		 1447 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1448 aml_append(field, aml_named_field("DBGB", 8));
1449 aml_append(scope, field);
1450
1451 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1452
1453 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1454 aml_append(method, aml_to_buffer(buf, buf));
1455 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1456 aml_append(method, aml_store(aml_int(0), idx));
1457
1458 while_ctx = aml_while(aml_lless(idx, len));
1459 aml_append(while_ctx,
1460 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1461 aml_append(while_ctx, aml_increment(idx));
1462 aml_append(method, while_ctx);
1463
1464 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1465 aml_append(scope, method);
1466
1467 aml_append(table, scope);
1468}
1469
c35b6e80
IM		 1470static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1471{
1472 Aml *dev;
1473 Aml *crs;
1474 Aml *method;
1475 uint32_t irqs[] = {5, 10, 11};
1476
1477 dev = aml_device("%s", name);
1478 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1479 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1480
1481 crs = aml_resource_template();
1482 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1483 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1484 aml_append(dev, aml_name_decl("_PRS", crs));
1485
1486 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1487 aml_append(method, aml_return(aml_call1("IQST", reg)));
1488 aml_append(dev, method);
1489
1490 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1491 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1492 aml_append(dev, method);
1493
1494 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1495 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1496 aml_append(dev, method);
1497
1498 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1499 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1500 aml_append(method, aml_store(aml_name("PRRI"), reg));
1501 aml_append(dev, method);
1502
1503 return dev;
1504 }
1505
80b32df5
IM		 1506static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1507{
1508 Aml *dev;
1509 Aml *crs;
1510 Aml *method;
1511 uint32_t irqs;
1512
1513 dev = aml_device("%s", name);
1514 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1515 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1516
1517 crs = aml_resource_template();
1518 irqs = gsi;
1519 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1520 AML_SHARED, &irqs, 1));
1521 aml_append(dev, aml_name_decl("_PRS", crs));
1522
1523 aml_append(dev, aml_name_decl("_CRS", crs));
1524
c82f503d
MA		 1525 /*
1526 * _DIS can be no-op because the interrupt cannot be disabled.
1527 */
1528 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1529 aml_append(dev, method);
1530
80b32df5
IM		 1531 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1532 aml_append(dev, method);
1533
1534 return dev;
1535}
1536
16682a9d
IM		 1537/* _CRS method - get current settings */
1538static Aml *build_iqcr_method(bool is_piix4)
1539{
1540 Aml *if_ctx;
1541 uint32_t irqs;
1542 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1543 Aml *crs = aml_resource_template();
1544
1545 irqs = 0;
1546 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1547 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1548 aml_append(method, aml_name_decl("PRR0", crs));
1549
1550 aml_append(method,
1551 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1552
1553 if (is_piix4) {
1554 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1555 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1556 aml_append(method, if_ctx);
1557 } else {
1558 aml_append(method,
1559 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1560 aml_name("PRRI")));
1561 }
1562
1563 aml_append(method, aml_return(aml_name("PRR0")));
1564 return method;
1565}
1566
78e1ad05
IM		 1567/* _STA method - get status */
1568static Aml *build_irq_status_method(void)
1569{
1570 Aml *if_ctx;
1571 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1572
1573 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1574 aml_append(if_ctx, aml_return(aml_int(0x09)));
1575 aml_append(method, if_ctx);
1576 aml_append(method, aml_return(aml_int(0x0B)));
1577 return method;
1578}
1579
e4db2798
IM		 1580static void build_piix4_pci0_int(Aml *table)
1581{
c35b6e80
IM		 1582 Aml *dev;
1583 Aml *crs;
e4db2798 1584 Aml *field;
c35b6e80
IM		 1585 Aml *method;
1586 uint32_t irqs;
e4db2798 1587 Aml *sb_scope = aml_scope("_SB");
196e2137
IM		 1588 Aml *pci0_scope = aml_scope("PCI0");
1589
1590 aml_append(pci0_scope, build_prt(true));
1591 aml_append(sb_scope, pci0_scope);
e4db2798
IM		 1592
1593 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1594 aml_append(field, aml_named_field("PRQ0", 8));
1595 aml_append(field, aml_named_field("PRQ1", 8));
1596 aml_append(field, aml_named_field("PRQ2", 8));
1597 aml_append(field, aml_named_field("PRQ3", 8));
1598 aml_append(sb_scope, field);
1599
78e1ad05 1600 aml_append(sb_scope, build_irq_status_method());
16682a9d 1601 aml_append(sb_scope, build_iqcr_method(true));
100681cc 1602
c35b6e80
IM		 1603 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1604 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1605 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1606 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1607
1608 dev = aml_device("LNKS");
1609 {
1610 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1611 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1612
1613 crs = aml_resource_template();
1614 irqs = 9;
1615 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1616 AML_ACTIVE_HIGH, AML_SHARED,
1617 &irqs, 1));
1618 aml_append(dev, aml_name_decl("_PRS", crs));
1619
1620 /* The SCI cannot be disabled and is always attached to GSI 9,
1621 * so these are no-ops. We only need this link to override the
1622 * polarity to active high and match the content of the MADT.
1623 */
1624 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1625 aml_append(method, aml_return(aml_int(0x0b)));
1626 aml_append(dev, method);
1627
1628 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1629 aml_append(dev, method);
1630
1631 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1632 aml_append(method, aml_return(aml_name("_PRS")));
1633 aml_append(dev, method);
1634
1635 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1636 aml_append(dev, method);
1637 }
1638 aml_append(sb_scope, dev);
1639
e4db2798
IM		 1640 aml_append(table, sb_scope);
1641}
1642
22b5b8bf
IM		 1643static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1644{
1645 int i;
1646 int head;
1647 Aml *pkg;
1648 char base = name[3] < 'E' ? 'A' : 'E';
1649 char *s = g_strdup(name);
1650 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1651
1652 assert(strlen(s) == 4);
1653
1654 head = name[3] - base;
1655 for (i = 0; i < 4; i++) {
1656 if (head + i > 3) {
1657 head = i * -1;
1658 }
1659 s[3] = base + head + i;
1660 pkg = aml_package(4);
1661 aml_append(pkg, a_nr);
1662 aml_append(pkg, aml_int(i));
1663 aml_append(pkg, aml_name("%s", s));
1664 aml_append(pkg, aml_int(0));
1665 aml_append(ctx, pkg);
1666 }
1667 g_free(s);
1668}
1669
1670static Aml *build_q35_routing_table(const char *str)
1671{
1672 int i;
1673 Aml *pkg;
1674 char *name = g_strdup_printf("%s ", str);
1675
1676 pkg = aml_package(128);
1677 for (i = 0; i < 0x18; i++) {
1678 name[3] = 'E' + (i & 0x3);
1679 append_q35_prt_entry(pkg, i, name);
1680 }
1681
1682 name[3] = 'E';
1683 append_q35_prt_entry(pkg, 0x18, name);
1684
1685 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1686 for (i = 0x0019; i < 0x1e; i++) {
1687 name[3] = 'A';
1688 append_q35_prt_entry(pkg, i, name);
1689 }
1690
1691 /* PCIe->PCI bridge. use PIRQ[E-H] */
1692 name[3] = 'E';
1693 append_q35_prt_entry(pkg, 0x1e, name);
1694 name[3] = 'A';
1695 append_q35_prt_entry(pkg, 0x1f, name);
1696
1697 g_free(name);
1698 return pkg;
1699}
1700
80b32df5
IM		 1701static void build_q35_pci0_int(Aml *table)
1702{
41f95a52 1703 Aml *field;
0dafe3b3 1704 Aml *method;
80b32df5 1705 Aml *sb_scope = aml_scope("_SB");
0dafe3b3
IM		 1706 Aml *pci0_scope = aml_scope("PCI0");
1707
e9fce798
IM		 1708 /* Zero => PIC mode, One => APIC Mode */
1709 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1710 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1711 {
1712 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1713 }
1714 aml_append(table, method);
1715
65aef4de
IM		 1716 aml_append(pci0_scope,
1717 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
22b5b8bf
IM		 1718 aml_append(pci0_scope,
1719 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1720
0dafe3b3
IM		 1721 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1722 {
1723 Aml *if_ctx;
1724 Aml *else_ctx;
1725
1726 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1727 section 6.2.8.1 */
1728 /* Note: we provide the same info as the PCI routing
1729 table of the Bochs BIOS */
1730 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1731 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1732 aml_append(method, if_ctx);
1733 else_ctx = aml_else();
1734 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1735 aml_append(method, else_ctx);
1736 }
1737 aml_append(pci0_scope, method);
1738 aml_append(sb_scope, pci0_scope);
80b32df5 1739
41f95a52
IM		 1740 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1741 aml_append(field, aml_named_field("PRQA", 8));
1742 aml_append(field, aml_named_field("PRQB", 8));
1743 aml_append(field, aml_named_field("PRQC", 8));
1744 aml_append(field, aml_named_field("PRQD", 8));
1745 aml_append(field, aml_reserved_field(0x20));
1746 aml_append(field, aml_named_field("PRQE", 8));
1747 aml_append(field, aml_named_field("PRQF", 8));
1748 aml_append(field, aml_named_field("PRQG", 8));
1749 aml_append(field, aml_named_field("PRQH", 8));
1750 aml_append(sb_scope, field);
1751
78e1ad05 1752 aml_append(sb_scope, build_irq_status_method());
16682a9d
IM		 1753 aml_append(sb_scope, build_iqcr_method(false));
1754
12e3b1f7
IM		 1755 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1756 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1757 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1758 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1759 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1760 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1761 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1762 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1763
6a991e07
MA		 1764 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1765 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1766 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1767 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1768 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1769 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1770 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1771 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
80b32df5
IM		 1772
1773 aml_append(table, sb_scope);
1774}
1775
41f95a52
IM		 1776static void build_q35_isa_bridge(Aml *table)
1777{
1778 Aml *dev;
1779 Aml *scope;
1780 Aml *field;
1781
1782 scope = aml_scope("_SB.PCI0");
1783 dev = aml_device("ISA");
1784 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1785
1786 /* ICH9 PCI to ISA irq remapping */
1787 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
3f3009c0 1788 aml_int(0x60), 0x0C));
41f95a52
IM		 1789
1790 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
3f3009c0 1791 aml_int(0x80), 0x02));
41f95a52
IM		 1792 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1793 aml_append(field, aml_named_field("COMA", 3));
1794 aml_append(field, aml_reserved_field(1));
1795 aml_append(field, aml_named_field("COMB", 3));
1796 aml_append(field, aml_reserved_field(1));
1797 aml_append(field, aml_named_field("LPTD", 2));
41f95a52
IM		 1798 aml_append(dev, field);
1799
1800 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
3f3009c0 1801 aml_int(0x82), 0x02));
41f95a52
IM		 1802 /* enable bits */
1803 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1804 aml_append(field, aml_named_field("CAEN", 1));
1805 aml_append(field, aml_named_field("CBEN", 1));
1806 aml_append(field, aml_named_field("LPEN", 1));
41f95a52
IM		 1807 aml_append(dev, field);
1808
1809 aml_append(scope, dev);
1810 aml_append(table, scope);
1811}
1812
e4db2798
IM		 1813static void build_piix4_pm(Aml *table)
1814{
1815 Aml *dev;
1816 Aml *scope;
1817
1818 scope = aml_scope("_SB.PCI0");
1819 dev = aml_device("PX13");
1820 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1821
1822 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
3f3009c0 1823 aml_int(0x00), 0xff));
e4db2798
IM		 1824 aml_append(scope, dev);
1825 aml_append(table, scope);
1826}
1827
1828static void build_piix4_isa_bridge(Aml *table)
1829{
1830 Aml *dev;
1831 Aml *scope;
1832 Aml *field;
1833
1834 scope = aml_scope("_SB.PCI0");
1835 dev = aml_device("ISA");
1836 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1837
1838 /* PIIX PCI to ISA irq remapping */
1839 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
3f3009c0 1840 aml_int(0x60), 0x04));
e4db2798
IM		 1841 /* enable bits */
1842 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1843 /* Offset(0x5f),, 7, */
1844 aml_append(field, aml_reserved_field(0x2f8));
1845 aml_append(field, aml_reserved_field(7));
1846 aml_append(field, aml_named_field("LPEN", 1));
1847 /* Offset(0x67),, 3, */
1848 aml_append(field, aml_reserved_field(0x38));
1849 aml_append(field, aml_reserved_field(3));
1850 aml_append(field, aml_named_field("CAEN", 1));
1851 aml_append(field, aml_reserved_field(3));
1852 aml_append(field, aml_named_field("CBEN", 1));
1853 aml_append(dev, field);
e4db2798
IM		 1854
1855 aml_append(scope, dev);
1856 aml_append(table, scope);
1857}
1858
b616ec4d
IM		 1859static void build_piix4_pci_hotplug(Aml *table)
1860{
1861 Aml *scope;
1862 Aml *field;
1863 Aml *method;
1864
1865 scope = aml_scope("_SB.PCI0");
1866
1867 aml_append(scope,
3f3009c0 1868 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
b616ec4d
IM		 1869 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1870 aml_append(field, aml_named_field("PCIU", 32));
1871 aml_append(field, aml_named_field("PCID", 32));
1872 aml_append(scope, field);
1873
1874 aml_append(scope,
3f3009c0 1875 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
b616ec4d
IM		 1876 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1877 aml_append(field, aml_named_field("B0EJ", 32));
1878 aml_append(scope, field);
1879
1880 aml_append(scope,
3f3009c0 1881 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
b616ec4d
IM		 1882 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1883 aml_append(field, aml_named_field("BNUM", 32));
1884 aml_append(scope, field);
1885
1886 aml_append(scope, aml_mutex("BLCK", 0));
1887
1888 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1889 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1890 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1891 aml_append(method,
1892 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1893 aml_append(method, aml_release(aml_name("BLCK")));
1894 aml_append(method, aml_return(aml_int(0)));
1895 aml_append(scope, method);
1896
1897 aml_append(table, scope);
1898}
1899
f97a88a8
IM		 1900static Aml *build_q35_osc_method(void)
1901{
1902 Aml *if_ctx;
1903 Aml *if_ctx2;
1904 Aml *else_ctx;
1905 Aml *method;
1906 Aml *a_cwd1 = aml_name("CDW1");
1907 Aml *a_ctrl = aml_name("CTRL");
1908
1909 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1910 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1911
1912 if_ctx = aml_if(aml_equal(
1913 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1914 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1915 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1916
1917 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1918 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1919
1920 /*
1921 * Always allow native PME, AER (no dependencies)
1922 * Never allow SHPC (no SHPC controller in this system)
1923 */
1924 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1925
1926 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1927 /* Unknown revision */
1928 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1929 aml_append(if_ctx, if_ctx2);
1930
1931 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1932 /* Capabilities bits were masked */
1933 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1934 aml_append(if_ctx, if_ctx2);
1935
1936 /* Update DWORD3 in the buffer */
1937 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1938 aml_append(method, if_ctx);
1939
1940 else_ctx = aml_else();
1941 /* Unrecognized UUID */
1942 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1943 aml_append(method, else_ctx);
1944
1945 aml_append(method, aml_return(aml_arg(3)));
1946 return method;
1947}
b616ec4d 1948
72c194f7 1949static void
0e9b9eda 1950build_dsdt(GArray *table_data, BIOSLinker *linker,
adcb89d5 1951 AcpiPmInfo *pm, AcpiMiscInfo *misc,
01c9742d 1952 Range *pci_hole, Range *pci_hole64, MachineState *machine)
72c194f7 1953{
41fa5c04
IM		 1954 CrsRangeEntry *entry;
1955 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
2df5a7b5 1956 CrsRangeSet crs_range_set;
fb306ffe 1957 PCMachineState *pcms = PC_MACHINE(machine);
679dd1a9 1958 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
bef3492d 1959 uint32_t nr_mem = machine->ram_slots;
dcdca296 1960 int root_bus_limit = 0xFF;
41fa5c04 1961 PCIBus *bus = NULL;
72c194f7
MT		 1962 int i;
1963
41fa5c04 1964 dsdt = init_aml_allocator();
2fd71f1b 1965
4ec8d2b3 1966 /* Reserve space for header */
41fa5c04
IM		 1967 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1968
1969 build_dbg_aml(dsdt);
1970 if (misc->is_piix4) {
1971 sb_scope = aml_scope("_SB");
1972 dev = aml_device("PCI0");
1973 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1974 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1975 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1976 aml_append(sb_scope, dev);
1977 aml_append(dsdt, sb_scope);
1978
1979 build_hpet_aml(dsdt);
1980 build_piix4_pm(dsdt);
1981 build_piix4_isa_bridge(dsdt);
1982 build_isa_devices_aml(dsdt);
1983 build_piix4_pci_hotplug(dsdt);
1984 build_piix4_pci0_int(dsdt);
1985 } else {
1986 sb_scope = aml_scope("_SB");
1987 aml_append(sb_scope,
3f3009c0 1988 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
41fa5c04 1989 aml_append(sb_scope,
3f3009c0 1990 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
41fa5c04
IM		 1991 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1992 aml_append(field, aml_named_field("PCIB", 8));
1993 aml_append(sb_scope, field);
1994 aml_append(dsdt, sb_scope);
1995
1996 sb_scope = aml_scope("_SB");
1997 dev = aml_device("PCI0");
1998 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1999 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
2000 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2001 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2002 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
2003 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
2004 aml_append(dev, build_q35_osc_method());
2005 aml_append(sb_scope, dev);
2006 aml_append(dsdt, sb_scope);
2007
2008 build_hpet_aml(dsdt);
2009 build_q35_isa_bridge(dsdt);
2010 build_isa_devices_aml(dsdt);
2011 build_q35_pci0_int(dsdt);
2012 }
2013
679dd1a9
IM		 2014 if (pcmc->legacy_cpu_hotplug) {
2015 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
2016 } else {
2017 CPUHotplugFeatures opts = {
2018 .apci_1_compatible = true, .has_legacy_cphp = true
2019 };
2020 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
2021 "\\_SB.PCI0", "\\_GPE._E02");
2022 }
41fa5c04
IM		 2023 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
2024 pm->mem_hp_io_len);
2025
2026 scope = aml_scope("_GPE");
2027 {
2028 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
2029
41fa5c04
IM		 2030 if (misc->is_piix4) {
2031 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
2032 aml_append(method,
2033 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
2034 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
2035 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
2036 aml_append(scope, method);
41fa5c04
IM		 2037 }
2038
41fa5c04
IM		 2039 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
2040 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
2041 aml_append(scope, method);
41fa5c04
IM		 2042 }
2043 aml_append(dsdt, scope);
72c194f7 2044
2df5a7b5 2045 crs_range_set_init(&crs_range_set);
81ed6482 2046 bus = PC_MACHINE(machine)->bus;
a4894206
MA		 2047 if (bus) {
2048 QLIST_FOREACH(bus, &bus->child, sibling) {
2049 uint8_t bus_num = pci_bus_num(bus);
0e79e51a 2050 uint8_t numa_node = pci_bus_numa_node(bus);
a4894206
MA		 2051
2052 /* look only for expander root buses */
2053 if (!pci_bus_is_root(bus)) {
2054 continue;
2055 }
2056
dcdca296
MA		 2057 if (bus_num < root_bus_limit) {
2058 root_bus_limit = bus_num - 1;
2059 }
2060
a4894206
MA		 2061 scope = aml_scope("\\_SB");
2062 dev = aml_device("PC%.02X", bus_num);
c96d9286
LE		 2063 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
2064 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
a4894206 2065 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
0e79e51a
MA		 2066
2067 if (numa_node != NUMA_NODE_UNASSIGNED) {
2068 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2069 }
2070
196e2137 2071 aml_append(dev, build_prt(false));
2df5a7b5 2072 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
a43c6e27 2073 aml_append(dev, aml_name_decl("_CRS", crs));
a4894206 2074 aml_append(scope, dev);
41fa5c04 2075 aml_append(dsdt, scope);
a4894206
MA		 2076 }
2077 }
2078
500b11ea 2079 scope = aml_scope("\\_SB.PCI0");
60efd429
IM		 2080 /* build PCI0._CRS */
2081 crs = aml_resource_template();
2082 aml_append(crs,
ff80dc7f 2083 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
dcdca296
MA		 2084 0x0000, 0x0, root_bus_limit,
2085 0x0000, root_bus_limit + 1));
ff80dc7f 2086 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
60efd429
IM		 2087
2088 aml_append(crs,
ff80dc7f
SZ		 2089 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2090 AML_POS_DECODE, AML_ENTIRE_RANGE,
60efd429 2091 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
dcdca296 2092
2df5a7b5
MA		 2093 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
2094 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
2095 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
dcdca296
MA		 2096 aml_append(crs,
2097 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2098 AML_POS_DECODE, AML_ENTIRE_RANGE,
2099 0x0000, entry->base, entry->limit,
2100 0x0000, entry->limit - entry->base + 1));
2101 }
2102
60efd429 2103 aml_append(crs,
ff80dc7f
SZ		 2104 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2105 AML_CACHEABLE, AML_READ_WRITE,
60efd429 2106 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
dcdca296 2107
2df5a7b5 2108 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
a0efbf16
MA		 2109 range_lob(pci_hole),
2110 range_upb(pci_hole));
2df5a7b5
MA		 2111 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
2112 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
dcdca296
MA		 2113 aml_append(crs,
2114 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2115 AML_NON_CACHEABLE, AML_READ_WRITE,
2116 0, entry->base, entry->limit,
2117 0, entry->limit - entry->base + 1));
2118 }
2119
a0efbf16 2120 if (!range_is_empty(pci_hole64)) {
16de88a4
MA		 2121 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
2122 range_lob(pci_hole64),
2123 range_upb(pci_hole64));
2124 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
2125 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
2126 aml_append(crs,
2127 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
2128 AML_MAX_FIXED,
2129 AML_CACHEABLE, AML_READ_WRITE,
2130 0, entry->base, entry->limit,
2131 0, entry->limit - entry->base + 1));
2132 }
60efd429 2133 }
2b1c2e8e
IM		 2134
2135 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2136 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2137 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2138 }
60efd429
IM		 2139 aml_append(scope, aml_name_decl("_CRS", crs));
2140
d31c909e
IM		 2141 /* reserve GPE0 block resources */
2142 dev = aml_device("GPE0");
2143 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2144 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2145 /* device present, functioning, decoding, not shown in UI */
2146 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2147 crs = aml_resource_template();
2148 aml_append(crs,
ff80dc7f 2149 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
d31c909e
IM		 2150 );
2151 aml_append(dev, aml_name_decl("_CRS", crs));
2152 aml_append(scope, dev);
2153
2df5a7b5 2154 crs_range_set_free(&crs_range_set);
dcdca296 2155
500b11ea
IM		 2156 /* reserve PCIHP resources */
2157 if (pm->pcihp_io_len) {
2158 dev = aml_device("PHPR");
2159 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2160 aml_append(dev,
2161 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2162 /* device present, functioning, decoding, not shown in UI */
2163 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2164 crs = aml_resource_template();
2165 aml_append(crs,
ff80dc7f 2166 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
500b11ea
IM		 2167 pm->pcihp_io_len)
2168 );
2169 aml_append(dev, aml_name_decl("_CRS", crs));
2170 aml_append(scope, dev);
2171 }
41fa5c04 2172 aml_append(dsdt, scope);
500b11ea 2173
ebc3028f
IM		 2174 /* create S3_ / S4_ / S5_ packages if necessary */
2175 scope = aml_scope("\\");
2176 if (!pm->s3_disabled) {
2177 pkg = aml_package(4);
2178 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2179 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2180 aml_append(pkg, aml_int(0)); /* reserved */
2181 aml_append(pkg, aml_int(0)); /* reserved */
2182 aml_append(scope, aml_name_decl("_S3", pkg));
2183 }
2184
2185 if (!pm->s4_disabled) {
2186 pkg = aml_package(4);
2187 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2188 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2189 aml_append(pkg, aml_int(pm->s4_val));
2190 aml_append(pkg, aml_int(0)); /* reserved */
2191 aml_append(pkg, aml_int(0)); /* reserved */
2192 aml_append(scope, aml_name_decl("_S4", pkg));
2193 }
2194
2195 pkg = aml_package(4);
2196 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2197 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2198 aml_append(pkg, aml_int(0)); /* reserved */
2199 aml_append(pkg, aml_int(0)); /* reserved */
2200 aml_append(scope, aml_name_decl("_S5", pkg));
41fa5c04 2201 aml_append(dsdt, scope);
ebc3028f 2202
e2ec7568
GS		 2203 /* create fw_cfg node, unconditionally */
2204 {
2205 /* when using port i/o, the 8-bit data register *always* overlaps
2206 * with half of the 16-bit control register. Hence, the total size
2207 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2208 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2209 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2210 "dma_enabled", NULL) ?
2211 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2212 FW_CFG_CTL_SIZE;
2213
2214 scope = aml_scope("\\_SB.PCI0");
2215 dev = aml_device("FWCF");
2216
2217 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2218
2219 /* device present, functioning, decoding, not shown in UI */
2220 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2221
2222 crs = aml_resource_template();
2223 aml_append(crs,
2224 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2225 );
2226 aml_append(dev, aml_name_decl("_CRS", crs));
2227
2228 aml_append(scope, dev);
2229 aml_append(dsdt, scope);
2230 }
2231
8ac6f7a6
IM		 2232 if (misc->applesmc_io_base) {
2233 scope = aml_scope("\\_SB.PCI0.ISA");
2234 dev = aml_device("SMC");
2235
2236 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2237 /* device present, functioning, decoding, not shown in UI */
2238 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2239
2240 crs = aml_resource_template();
2241 aml_append(crs,
ff80dc7f 2242 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
8ac6f7a6
IM		 2243 0x01, APPLESMC_MAX_DATA_LENGTH)
2244 );
2245 aml_append(crs, aml_irq_no_flags(6));
2246 aml_append(dev, aml_name_decl("_CRS", crs));
2247
2248 aml_append(scope, dev);
41fa5c04 2249 aml_append(dsdt, scope);
8ac6f7a6
IM		 2250 }
2251
cd61cb2e
IM		 2252 if (misc->pvpanic_port) {
2253 scope = aml_scope("\\_SB.PCI0.ISA");
2254
2332333c 2255 dev = aml_device("PEVT");
e65bef69 2256 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
cd61cb2e
IM		 2257
2258 crs = aml_resource_template();
2259 aml_append(crs,
ff80dc7f 2260 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
cd61cb2e
IM		 2261 );
2262 aml_append(dev, aml_name_decl("_CRS", crs));
2263
ff80dc7f 2264 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
3f3009c0 2265 aml_int(misc->pvpanic_port), 1));
36de884a 2266 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
cd61cb2e
IM		 2267 aml_append(field, aml_named_field("PEPT", 8));
2268 aml_append(dev, field);
2269
8ef3ea25
GH		 2270 /* device present, functioning, decoding, shown in UI */
2271 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2332333c 2272
4dbfc881 2273 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
cd61cb2e
IM		 2274 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2275 aml_append(method, aml_return(aml_local(0)));
2276 aml_append(dev, method);
2277
4dbfc881 2278 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
cd61cb2e
IM		 2279 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2280 aml_append(dev, method);
2281
2282 aml_append(scope, dev);
41fa5c04 2283 aml_append(dsdt, scope);
cd61cb2e
IM		 2284 }
2285
7824df38 2286 sb_scope = aml_scope("\\_SB");
72c194f7 2287 {
f177d40a
IM		 2288 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2289 pm->mem_hp_io_len);
8698c0c0 2290
72c194f7 2291 {
8dcf525a
MT		 2292 Object *pci_host;
2293 PCIBus *bus = NULL;
8dcf525a 2294
ca6c1855
MA		 2295 pci_host = acpi_get_i386_pci_host();
2296 if (pci_host) {
8dcf525a
MT		 2297 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2298 }
72c194f7 2299
99fd437d 2300 if (bus) {
62b52c26 2301 Aml *scope = aml_scope("PCI0");
99fd437d 2302 /* Scan all PCI buses. Generate tables to support hotplug. */
62b52c26 2303 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
72d97b3a
IM		 2304
2305 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2306 dev = aml_device("ISA.TPM");
2307 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2308 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2309 crs = aml_resource_template();
2310 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2311 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
52e38eb0
IM		 2312 /*
2313 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2314 Rewrite to take IRQ from TPM device model and
2315 fix default IRQ value there to use some unused IRQ
2316 */
2317 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
72d97b3a
IM		 2318 aml_append(dev, aml_name_decl("_CRS", crs));
2319 aml_append(scope, dev);
2320 }
2321
62b52c26 2322 aml_append(sb_scope, scope);
72c194f7 2323 }
72c194f7 2324 }
41fa5c04 2325 aml_append(dsdt, sb_scope);
72c194f7
MT		 2326 }
2327
011bb749 2328 /* copy AML table into ACPI tables blob and patch header there */
41fa5c04 2329 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
72c194f7 2330 build_header(linker, table_data,
41fa5c04 2331 (void *)(table_data->data + table_data->len - dsdt->buf->len),
37ad223c 2332 "DSDT", dsdt->buf->len, 1, NULL, NULL);
011bb749 2333 free_aml_allocator();
72c194f7
MT		 2334}
2335
2336static void
0e9b9eda 2337build_hpet(GArray *table_data, BIOSLinker *linker)
72c194f7
MT		 2338{
2339 Acpi20Hpet *hpet;
2340
2341 hpet = acpi_data_push(table_data, sizeof(*hpet));
2342 /* Note timer_block_id value must be kept in sync with value advertised by
2343 * emulated hpet
2344 */
2345 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2346 hpet->addr.address = cpu_to_le64(HPET_BASE);
2347 build_header(linker, table_data,
37ad223c 2348 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
72c194f7
MT		 2349}
2350
711b20b4 2351static void
0e9b9eda 2352build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
711b20b4
SB		 2353{
2354 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
4678124b
IM		 2355 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2356 unsigned log_addr_offset =
2357 (char *)&tcpa->log_area_start_address - table_data->data;
711b20b4
SB		 2358
2359 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2360 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
9774ccf7 2361 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
711b20b4 2362
ad9671b8 2363 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
42a5b308
SB		 2364 false /* high memory */);
2365
711b20b4 2366 /* log area start address to be filled by Guest linker */
4678124b
IM		 2367 bios_linker_loader_add_pointer(linker,
2368 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2369 ACPI_BUILD_TPMLOG_FILE, 0);
711b20b4
SB		 2370
2371 build_header(linker, table_data,
37ad223c 2372 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
711b20b4
SB		 2373}
2374
5cb18b3d 2375static void
0e9b9eda 2376build_tpm2(GArray *table_data, BIOSLinker *linker)
5cb18b3d
SB		 2377{
2378 Acpi20TPM2 *tpm2_ptr;
5cb18b3d
SB		 2379
2380 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2381
2382 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2383 tpm2_ptr->control_area_address = cpu_to_le64(0);
2384 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2385
2386 build_header(linker, table_data,
37ad223c 2387 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
5cb18b3d
SB		 2388}
2389
72c194f7 2390static void
0e9b9eda 2391build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
72c194f7
MT		 2392{
2393 AcpiSystemResourceAffinityTable *srat;
2394 AcpiSratProcessorAffinity *core;
2395 AcpiSratMemoryAffinity *numamem;
2396
2397 int i;
72c194f7
MT		 2398 int srat_start, numa_start, slots;
2399 uint64_t mem_len, mem_base, next_base;
5803fce3
IM		 2400 MachineClass *mc = MACHINE_GET_CLASS(machine);
2401 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
3d3ebcad 2402 PCMachineState *pcms = PC_MACHINE(machine);
cec65193
IM		 2403 ram_addr_t hotplugabble_address_space_size =
2404 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2405 NULL);
72c194f7
MT		 2406
2407 srat_start = table_data->len;
2408
2409 srat = acpi_data_push(table_data, sizeof *srat);
2410 srat->reserved1 = cpu_to_le32(1);
72c194f7 2411
5803fce3 2412 for (i = 0; i < apic_ids->len; i++) {
6bea1ddf 2413 int j = numa_get_node_for_cpu(i);
5803fce3
IM		 2414 int apic_id = apic_ids->cpus[i].arch_id;
2415
72c194f7 2416 core = acpi_data_push(table_data, sizeof *core);
e6e400d5 2417 core->type = ACPI_SRAT_PROCESSOR_APIC;
72c194f7 2418 core->length = sizeof(*core);
5803fce3 2419 core->local_apic_id = apic_id;
6bea1ddf 2420 if (j < nb_numa_nodes) {
1f3aba37 2421 core->proximity_lo = j;
1f3aba37 2422 }
72c194f7
MT		 2423 memset(core->proximity_hi, 0, 3);
2424 core->local_sapic_eid = 0;
dd0247e0 2425 core->flags = cpu_to_le32(1);
72c194f7
MT		 2426 }
2427
2428
2429 /* the memory map is a bit tricky, it contains at least one hole
2430 * from 640k-1M and possibly another one from 3.5G-4G.
2431 */
2432 next_base = 0;
2433 numa_start = table_data->len;
2434
2435 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136 2436 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED);
72c194f7 2437 next_base = 1024 * 1024;
dd4c2f01 2438 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
72c194f7 2439 mem_base = next_base;
dd4c2f01 2440 mem_len = pcms->node_mem[i - 1];
72c194f7
MT		 2441 if (i == 1) {
2442 mem_len -= 1024 * 1024;
2443 }
2444 next_base = mem_base + mem_len;
2445
2446 /* Cut out the ACPI_PCI hole */
5299f1c7
EH		 2447 if (mem_base <= pcms->below_4g_mem_size &&
2448 next_base > pcms->below_4g_mem_size) {
2449 mem_len -= next_base - pcms->below_4g_mem_size;
72c194f7
MT		 2450 if (mem_len > 0) {
2451 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136
SZ		 2452 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2453 MEM_AFFINITY_ENABLED);
72c194f7
MT		 2454 }
2455 mem_base = 1ULL << 32;
5299f1c7
EH		 2456 mem_len = next_base - pcms->below_4g_mem_size;
2457 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
72c194f7
MT		 2458 }
2459 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136
SZ		 2460 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2461 MEM_AFFINITY_ENABLED);
72c194f7
MT		 2462 }
2463 slots = (table_data->len - numa_start) / sizeof *numamem;
dd4c2f01 2464 for (; slots < pcms->numa_nodes + 2; slots++) {
72c194f7 2465 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136 2466 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
72c194f7
MT		 2467 }
2468
cec65193
IM		 2469 /*
2470 * Entry is required for Windows to enable memory hotplug in OS.
2471 * Memory devices may override proximity set by this entry,
2472 * providing _PXM method if necessary.
2473 */
2474 if (hotplugabble_address_space_size) {
2475 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136
SZ		 2476 build_srat_memory(numamem, pcms->hotplug_memory.base,
2477 hotplugabble_address_space_size, 0,
2478 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
cec65193
IM		 2479 }
2480
72c194f7
MT		 2481 build_header(linker, table_data,
2482 (void *)(table_data->data + srat_start),
821e3227 2483 "SRAT",
37ad223c 2484 table_data->len - srat_start, 1, NULL, NULL);
5803fce3 2485 g_free(apic_ids);
72c194f7
MT		 2486}
2487
2488static void
0e9b9eda 2489build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
72c194f7
MT		 2490{
2491 AcpiTableMcfg *mcfg;
821e3227 2492 const char *sig;
72c194f7
MT		 2493 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2494
2495 mcfg = acpi_data_push(table_data, len);
2496 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2497 /* Only a single allocation so no need to play with segments */
2498 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2499 mcfg->allocation[0].start_bus_number = 0;
2500 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2501
2502 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2503 * To avoid table size changes (which create migration issues),
2504 * always create the table even if there are no allocations,
2505 * but set the signature to a reserved value in this case.
2506 * ACPI spec requires OSPMs to ignore such tables.
2507 */
2508 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
821e3227
MT		 2509 /* Reserved signature: ignored by OSPM */
2510 sig = "QEMU";
72c194f7 2511 } else {
821e3227 2512 sig = "MCFG";
72c194f7 2513 }
37ad223c 2514 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
72c194f7
MT		 2515}
2516
d46114f9
PX		 2517/*
2518 * VT-d spec 8.1 DMA Remapping Reporting Structure
2519 * (version Oct. 2014 or later)
2520 */
d4eb9119 2521static void
0e9b9eda 2522build_dmar_q35(GArray *table_data, BIOSLinker *linker)
d4eb9119
LT		 2523{
2524 int dmar_start = table_data->len;
2525
2526 AcpiTableDmar *dmar;
2527 AcpiDmarHardwareUnit *drhd;
d46114f9
PX		 2528 uint8_t dmar_flags = 0;
2529 X86IOMMUState *iommu = x86_iommu_get_default();
cfc13df4
PX		 2530 AcpiDmarDeviceScope *scope = NULL;
2531 /* Root complex IOAPIC use one path[0] only */
2532 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
d46114f9
PX		 2533
2534 assert(iommu);
2535 if (iommu->intr_supported) {
2536 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2537 }
d4eb9119
LT		 2538
2539 dmar = acpi_data_push(table_data, sizeof(*dmar));
2540 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
d46114f9 2541 dmar->flags = dmar_flags;
d4eb9119
LT		 2542
2543 /* DMAR Remapping Hardware Unit Definition structure */
cfc13df4 2544 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
d4eb9119 2545 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
cfc13df4 2546 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
d4eb9119
LT		 2547 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2548 drhd->pci_segment = cpu_to_le16(0);
2549 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2550
cfc13df4
PX		 2551 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2552 * 8.3.1 (version Oct. 2014 or later). */
2553 scope = &drhd->scope[0];
2554 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2555 scope->length = ioapic_scope_size;
2556 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2557 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2558 scope->path[0] = cpu_to_le16(Q35_PSEUDO_DEVFN_IOAPIC);
2559
d4eb9119 2560 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
37ad223c 2561 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
d4eb9119 2562}
fb9f5926
DK		 2563/*
2564 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2565 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2566 */
2567static void
2568build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2569{
2570 int iommu_start = table_data->len;
2571 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2572
2573 /* IVRS header */
2574 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2575 /* IVinfo - IO virtualization information common to all
2576 * IOMMU units in a system
2577 */
2578 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2579 /* reserved */
2580 build_append_int_noprefix(table_data, 0, 8);
2581
2582 /* IVHD definition - type 10h */
2583 build_append_int_noprefix(table_data, 0x10, 1);
2584 /* virtualization flags */
2585 build_append_int_noprefix(table_data,
2586 (1UL << 0) | /* HtTunEn */
2587 (1UL << 4) | /* iotblSup */
2588 (1UL << 6) | /* PrefSup */
2589 (1UL << 7), /* PPRSup */
2590 1);
2591 /* IVHD length */
2592 build_append_int_noprefix(table_data, 0x24, 2);
2593 /* DeviceID */
2594 build_append_int_noprefix(table_data, s->devid, 2);
2595 /* Capability offset */
2596 build_append_int_noprefix(table_data, s->capab_offset, 2);
2597 /* IOMMU base address */
2598 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2599 /* PCI Segment Group */
2600 build_append_int_noprefix(table_data, 0, 2);
2601 /* IOMMU info */
2602 build_append_int_noprefix(table_data, 0, 2);
2603 /* IOMMU Feature Reporting */
2604 build_append_int_noprefix(table_data,
2605 (48UL << 30) | /* HATS */
2606 (48UL << 28) | /* GATS */
2607 (1UL << 2), /* GTSup */
2608 4);
2609 /*
2610 * Type 1 device entry reporting all devices
2611 * These are 4-byte device entries currently reporting the range of
2612 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2613 */
2614 build_append_int_noprefix(table_data, 0x0000001, 4);
2615
2616 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2617 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2618}
d4eb9119 2619
72c194f7 2620static GArray *
4678124b 2621build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
72c194f7
MT		 2622{
2623 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
4678124b
IM		 2624 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2625 unsigned rsdt_pa_offset =
2626 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
72c194f7 2627
ad9671b8 2628 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
72c194f7
MT		 2629 true /* fseg memory */);
2630
821e3227 2631 memcpy(&rsdp->signature, "RSD PTR ", 8);
72c194f7 2632 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
72c194f7 2633 /* Address to be filled by Guest linker */
4678124b
IM		 2634 bios_linker_loader_add_pointer(linker,
2635 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2636 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2637
72c194f7
MT		 2638 /* Checksum to be filled by Guest linker */
2639 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
28213cb6
IM		 2640 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2641 (char *)&rsdp->checksum - rsdp_table->data);
72c194f7
MT		 2642
2643 return rsdp_table;
2644}
2645
72c194f7
MT		 2646typedef
2647struct AcpiBuildState {
2648 /* Copy of table in RAM (for patching). */
339240b5 2649 MemoryRegion *table_mr;
72c194f7
MT		 2650 /* Is table patched? */
2651 uint8_t patched;
d70414a5 2652 void *rsdp;
339240b5
PB		 2653 MemoryRegion *rsdp_mr;
2654 MemoryRegion *linker_mr;
72c194f7
MT		 2655} AcpiBuildState;
2656
2657static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2658{
2659 Object *pci_host;
2660 QObject *o;
72c194f7 2661
ca6c1855 2662 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 2663 g_assert(pci_host);
2664
2665 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2666 if (!o) {
2667 return false;
2668 }
2669 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
097a97a6 2670 qobject_decref(o);
72c194f7
MT		 2671
2672 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2673 assert(o);
2674 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
097a97a6 2675 qobject_decref(o);
72c194f7
MT		 2676 return true;
2677}
2678
2679static
3d3ebcad 2680void acpi_build(AcpiBuildTables *tables, MachineState *machine)
72c194f7 2681{
3d3ebcad 2682 PCMachineState *pcms = PC_MACHINE(machine);
bb292f5a 2683 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72c194f7 2684 GArray *table_offsets;
41fa5c04 2685 unsigned facs, dsdt, rsdt, fadt;
72c194f7
MT		 2686 AcpiPmInfo pm;
2687 AcpiMiscInfo misc;
2688 AcpiMcfgInfo mcfg;
01c9742d 2689 Range pci_hole, pci_hole64;
72c194f7 2690 uint8_t *u;
07fb6176 2691 size_t aml_len = 0;
7c2c1fa5 2692 GArray *tables_blob = tables->table_data;
ae123749 2693 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
72c194f7 2694
72c194f7 2695 acpi_get_pm_info(&pm);
72c194f7 2696 acpi_get_misc_info(&misc);
01c9742d 2697 acpi_get_pci_holes(&pci_hole, &pci_hole64);
ae123749 2698 acpi_get_slic_oem(&slic_oem);
72c194f7
MT		 2699
2700 table_offsets = g_array_new(false, true /* clear */,
2701 sizeof(uint32_t));
8b310fc4 2702 ACPI_BUILD_DPRINTF("init ACPI tables\n");
72c194f7 2703
ad9671b8
IM		 2704 bios_linker_loader_alloc(tables->linker,
2705 ACPI_BUILD_TABLE_FILE, tables_blob,
72c194f7
MT		 2706 64 /* Ensure FACS is aligned */,
2707 false /* high memory */);
2708
2709 /*
2710 * FACS is pointed to by FADT.
2711 * We place it first since it's the only table that has alignment
2712 * requirements.
2713 */
7c2c1fa5 2714 facs = tables_blob->len;
fb306ffe 2715 build_facs(tables_blob, tables->linker);
72c194f7
MT		 2716
2717 /* DSDT is pointed to by FADT */
7c2c1fa5 2718 dsdt = tables_blob->len;
01c9742d
MA		 2719 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2720 &pci_hole, &pci_hole64, machine);
72c194f7 2721
07fb6176
PB		 2722 /* Count the size of the DSDT and SSDT, we will need it for legacy
2723 * sizing of ACPI tables.
2724 */
7c2c1fa5 2725 aml_len += tables_blob->len - dsdt;
07fb6176 2726
72c194f7 2727 /* ACPI tables pointed to by RSDT */
41fa5c04 2728 fadt = tables_blob->len;
7c2c1fa5 2729 acpi_add_table(table_offsets, tables_blob);
ae123749
LE		 2730 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2731 slic_oem.id, slic_oem.table_id);
41fa5c04 2732 aml_len += tables_blob->len - fadt;
72c194f7 2733
7c2c1fa5 2734 acpi_add_table(table_offsets, tables_blob);
907e7c94 2735 build_madt(tables_blob, tables->linker, pcms);
9ac1c4c0 2736
72c194f7 2737 if (misc.has_hpet) {
7c2c1fa5
IM		 2738 acpi_add_table(table_offsets, tables_blob);
2739 build_hpet(tables_blob, tables->linker);
711b20b4 2740 }
5cb18b3d 2741 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
7c2c1fa5
IM		 2742 acpi_add_table(table_offsets, tables_blob);
2743 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
711b20b4 2744
72d97b3a
IM		 2745 if (misc.tpm_version == TPM_VERSION_2_0) {
2746 acpi_add_table(table_offsets, tables_blob);
5cb18b3d 2747 build_tpm2(tables_blob, tables->linker);
5cb18b3d 2748 }
72c194f7 2749 }
dd4c2f01 2750 if (pcms->numa_nodes) {
7c2c1fa5 2751 acpi_add_table(table_offsets, tables_blob);
3d3ebcad 2752 build_srat(tables_blob, tables->linker, machine);
72c194f7
MT		 2753 }
2754 if (acpi_get_mcfg(&mcfg)) {
7c2c1fa5
IM		 2755 acpi_add_table(table_offsets, tables_blob);
2756 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
72c194f7 2757 }
fb9f5926
DK		 2758 if (x86_iommu_get_default()) {
2759 IommuType IOMMUType = x86_iommu_get_type();
2760 if (IOMMUType == TYPE_AMD) {
2761 acpi_add_table(table_offsets, tables_blob);
2762 build_amd_iommu(tables_blob, tables->linker);
2763 } else if (IOMMUType == TYPE_INTEL) {
2764 acpi_add_table(table_offsets, tables_blob);
2765 build_dmar_q35(tables_blob, tables->linker);
2766 }
d4eb9119 2767 }
5fe79386 2768 if (pcms->acpi_nvdimm_state.is_enabled) {
ad9671b8
IM		 2769 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2770 pcms->acpi_nvdimm_state.dsm_mem);
87252e1b
XG		 2771 }
2772
72c194f7
MT		 2773 /* Add tables supplied by user (if any) */
2774 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2775 unsigned len = acpi_table_len(u);
2776
7c2c1fa5
IM		 2777 acpi_add_table(table_offsets, tables_blob);
2778 g_array_append_vals(tables_blob, u, len);
72c194f7
MT		 2779 }
2780
2781 /* RSDT is pointed to by RSDP */
7c2c1fa5 2782 rsdt = tables_blob->len;
ae123749
LE		 2783 build_rsdt(tables_blob, tables->linker, table_offsets,
2784 slic_oem.id, slic_oem.table_id);
72c194f7
MT		 2785
2786 /* RSDP is in FSEG memory, so allocate it separately */
2787 build_rsdp(tables->rsdp, tables->linker, rsdt);
2788
07fb6176 2789 /* We'll expose it all to Guest so we want to reduce
72c194f7 2790 * chance of size changes.
07fb6176
PB		 2791 *
2792 * We used to align the tables to 4k, but of course this would
2793 * too simple to be enough. 4k turned out to be too small an
2794 * alignment very soon, and in fact it is almost impossible to
2795 * keep the table size stable for all (max_cpus, max_memory_slots)
2796 * combinations. So the table size is always 64k for pc-i440fx-2.1
2797 * and we give an error if the table grows beyond that limit.
2798 *
2799 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2800 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2801 * than 2.0 and we can always pad the smaller tables with zeros. We can
2802 * then use the exact size of the 2.0 tables.
2803 *
2804 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
72c194f7 2805 */
bb292f5a 2806 if (pcmc->legacy_acpi_table_size) {
07fb6176
PB		 2807 /* Subtracting aml_len gives the size of fixed tables. Then add the
2808 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2809 */
2810 int legacy_aml_len =
bb292f5a 2811 pcmc->legacy_acpi_table_size +
07fb6176
PB		 2812 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2813 int legacy_table_size =
7c2c1fa5 2814 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
07fb6176 2815 ACPI_BUILD_ALIGN_SIZE);
7c2c1fa5 2816 if (tables_blob->len > legacy_table_size) {
07fb6176 2817 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
868270f2 2818 error_report("Warning: migration may not work.");
07fb6176 2819 }
7c2c1fa5 2820 g_array_set_size(tables_blob, legacy_table_size);
07fb6176 2821 } else {
868270f2 2822 /* Make sure we have a buffer in case we need to resize the tables. */
7c2c1fa5 2823 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
18045fb9 2824 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
868270f2
MT		 2825 error_report("Warning: ACPI tables are larger than 64k.");
2826 error_report("Warning: migration may not work.");
2827 error_report("Warning: please remove CPUs, NUMA nodes, "
2828 "memory slots or PCI bridges.");
18045fb9 2829 }
7c2c1fa5 2830 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
07fb6176 2831 }
72c194f7 2832
0e9b9eda 2833 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
72c194f7
MT		 2834
2835 /* Cleanup memory that's no longer used. */
2836 g_array_free(table_offsets, true);
2837}
2838
339240b5 2839static void acpi_ram_update(MemoryRegion *mr, GArray *data)
42d85900
MT		 2840{
2841 uint32_t size = acpi_data_len(data);
2842
2843 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
339240b5 2844 memory_region_ram_resize(mr, size, &error_abort);
42d85900 2845
339240b5
PB		 2846 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2847 memory_region_set_dirty(mr, 0, size);
42d85900
MT		 2848}
2849
3f8752b4 2850static void acpi_build_update(void *build_opaque)
72c194f7
MT		 2851{
2852 AcpiBuildState *build_state = build_opaque;
2853 AcpiBuildTables tables;
2854
2855 /* No state to update or already patched? Nothing to do. */
2856 if (!build_state || build_state->patched) {
2857 return;
2858 }
2859 build_state->patched = 1;
2860
2861 acpi_build_tables_init(&tables);
2862
3d3ebcad 2863 acpi_build(&tables, MACHINE(qdev_get_machine()));
72c194f7 2864
339240b5 2865 acpi_ram_update(build_state->table_mr, tables.table_data);
a1666142 2866
42d85900
MT		 2867 if (build_state->rsdp) {
2868 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2869 } else {
339240b5 2870 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
42d85900 2871 }
ad5b88b1 2872
0e9b9eda 2873 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
72c194f7
MT		 2874 acpi_build_tables_cleanup(&tables, true);
2875}
2876
2877static void acpi_build_reset(void *build_opaque)
2878{
2879 AcpiBuildState *build_state = build_opaque;
2880 build_state->patched = 0;
2881}
2882
339240b5
PB		 2883static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2884 GArray *blob, const char *name,
2885 uint64_t max_size)
72c194f7 2886{
a1666142
MT		 2887 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2888 name, acpi_build_update, build_state);
72c194f7
MT		 2889}
2890
2891static const VMStateDescription vmstate_acpi_build = {
2892 .name = "acpi_build",
2893 .version_id = 1,
2894 .minimum_version_id = 1,
d49805ae 2895 .fields = (VMStateField[]) {
72c194f7
MT		 2896 VMSTATE_UINT8(patched, AcpiBuildState),
2897 VMSTATE_END_OF_LIST()
2898 },
2899};
2900
fb306ffe 2901void acpi_setup(void)
72c194f7 2902{
fb306ffe 2903 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
bb292f5a 2904 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72c194f7
MT		 2905 AcpiBuildTables tables;
2906 AcpiBuildState *build_state;
2907
f264d360 2908 if (!pcms->fw_cfg) {
8b310fc4 2909 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
72c194f7
MT		 2910 return;
2911 }
2912
bb292f5a 2913 if (!pcmc->has_acpi_build) {
8b310fc4 2914 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
72c194f7
MT		 2915 return;
2916 }
2917
81adc513 2918 if (!acpi_enabled) {
8b310fc4 2919 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
81adc513
MT		 2920 return;
2921 }
2922
72c194f7
MT		 2923 build_state = g_malloc0(sizeof *build_state);
2924
99fd437d
MT		 2925 acpi_set_pci_info();
2926
72c194f7 2927 acpi_build_tables_init(&tables);
3d3ebcad 2928 acpi_build(&tables, MACHINE(pcms));
72c194f7
MT		 2929
2930 /* Now expose it all to Guest */
339240b5 2931 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
a1666142
MT		 2932 ACPI_BUILD_TABLE_FILE,
2933 ACPI_BUILD_TABLE_MAX_SIZE);
339240b5 2934 assert(build_state->table_mr != NULL);
72c194f7 2935
339240b5 2936 build_state->linker_mr =
0e9b9eda
IM		 2937 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2938 "etc/table-loader", 0);
72c194f7 2939
f264d360 2940 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
42a5b308
SB		 2941 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2942
bb292f5a 2943 if (!pcmc->rsdp_in_ram) {
358774d7
IM		 2944 /*
2945 * Keep for compatibility with old machine types.
2946 * Though RSDP is small, its contents isn't immutable, so
afaa2e4b 2947 * we'll update it along with the rest of tables on guest access.
358774d7 2948 */
afaa2e4b
MT		 2949 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2950
2951 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
f264d360 2952 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
358774d7 2953 acpi_build_update, build_state,
afaa2e4b 2954 build_state->rsdp, rsdp_size);
339240b5 2955 build_state->rsdp_mr = NULL;
358774d7 2956 } else {
42d85900 2957 build_state->rsdp = NULL;
339240b5 2958 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
42d85900 2959 ACPI_BUILD_RSDP_FILE, 0);
358774d7 2960 }
72c194f7
MT		 2961
2962 qemu_register_reset(acpi_build_reset, build_state);
2963 acpi_build_reset(build_state);
2964 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2965
2966 /* Cleanup tables but don't free the memory: we track it
2967 * in build_state.
2968 */
2969 acpi_build_tables_cleanup(&tables, false);
2970}
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