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acpi: tpm: Do not build TCPA table for TPM 2
[mirror_qemu.git] / hw / i386 / acpi-build.c
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72c194f7
MT		 1/* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
b6a0aa05 23#include "qemu/osdep.h"
da34e65c 24#include "qapi/error.h"
15280c36 25#include "qapi/qmp/qnum.h"
72c194f7 26#include "acpi-build.h"
72c194f7 27#include "qemu/bitmap.h"
07fb6176 28#include "qemu/error-report.h"
72c194f7 29#include "hw/pci/pci.h"
2e5b09fd 30#include "hw/core/cpu.h"
fcf5ef2a 31#include "target/i386/cpu.h"
0d5d8a3a 32#include "hw/misc/pvpanic.h"
72c194f7 33#include "hw/timer/hpet.h"
395e5fb4 34#include "hw/acpi/acpi-defs.h"
72c194f7 35#include "hw/acpi/acpi.h"
679dd1a9 36#include "hw/acpi/cpu.h"
72c194f7 37#include "hw/nvram/fw_cfg.h"
0058ae1d 38#include "hw/acpi/bios-linker-loader.h"
15bce1b7 39#include "hw/isa/isa.h"
27b9fc54 40#include "hw/block/fdc.h"
bef3492d 41#include "hw/acpi/memory_hotplug.h"
711b20b4
SB		 42#include "sysemu/tpm.h"
43#include "hw/acpi/tpm.h"
d03637bc 44#include "hw/acpi/vmgenid.h"
0e11fc69 45#include "hw/boards.h"
5cb18b3d 46#include "sysemu/tpm_backend.h"
bcdb9064 47#include "hw/rtc/mc146818rtc_regs.h"
d6454270 48#include "migration/vmstate.h"
2cc0e2e8 49#include "hw/mem/memory-device.h"
4b997690 50#include "hw/mem/nvdimm.h"
1f3aba37 51#include "sysemu/numa.h"
71e8a915 52#include "sysemu/reset.h"
72c194f7
MT		 53
54/* Supported chipsets: */
fff123b8 55#include "hw/southbridge/piix.h"
99fd437d 56#include "hw/acpi/pcihp.h"
89a289c7 57#include "hw/i386/fw_cfg.h"
72c194f7
MT		 58#include "hw/i386/ich9.h"
59#include "hw/pci/pci_bus.h"
60#include "hw/pci-host/q35.h"
1cf5fd57 61#include "hw/i386/x86-iommu.h"
72c194f7 62
19934e0e 63#include "hw/acpi/aml-build.h"
82f76c67 64#include "hw/acpi/utils.h"
48cefd94 65#include "hw/acpi/pci.h"
19934e0e 66
72c194f7 67#include "qom/qom-qobject.h"
fb9f5926
DK		 68#include "hw/i386/amd_iommu.h"
69#include "hw/i386/intel_iommu.h"
72c194f7 70
86e91dd7 71#include "hw/acpi/ipmi.h"
e6f123c3 72#include "hw/acpi/hmat.h"
86e91dd7 73
07fb6176
PB		 74/* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
75 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
76 * a little bit, there should be plenty of free space since the DSDT
77 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
78 */
79#define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
80#define ACPI_BUILD_ALIGN_SIZE 0x1000
81
868270f2 82#define ACPI_BUILD_TABLE_SIZE 0x20000
18045fb9 83
8b310fc4
GA		 84/* #define DEBUG_ACPI_BUILD */
85#ifdef DEBUG_ACPI_BUILD
86#define ACPI_BUILD_DPRINTF(fmt, ...) \
87 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
88#else
89#define ACPI_BUILD_DPRINTF(fmt, ...)
90#endif
91
cfc13df4
PX		 92/* Default IOAPIC ID */
93#define ACPI_BUILD_IOAPIC_ID 0x0
94
72c194f7
MT		 95typedef struct AcpiPmInfo {
96 bool s3_disabled;
97 bool s4_disabled;
133a2da4 98 bool pcihp_bridge_en;
72c194f7 99 uint8_t s4_val;
937d1b58 100 AcpiFadtData fadt;
ddf1ec2f 101 uint16_t cpu_hp_io_base;
500b11ea
IM		 102 uint16_t pcihp_io_base;
103 uint16_t pcihp_io_len;
72c194f7
MT		 104} AcpiPmInfo;
105
106typedef struct AcpiMiscInfo {
e4db2798 107 bool is_piix4;
72c194f7 108 bool has_hpet;
5cb18b3d 109 TPMVersion tpm_version;
72c194f7
MT		 110 const unsigned char *dsdt_code;
111 unsigned dsdt_size;
112 uint16_t pvpanic_port;
8ac6f7a6 113 uint16_t applesmc_io_base;
72c194f7
MT		 114} AcpiMiscInfo;
115
99fd437d
MT		 116typedef struct AcpiBuildPciBusHotplugState {
117 GArray *device_table;
118 GArray *notify_table;
119 struct AcpiBuildPciBusHotplugState *parent;
133a2da4 120 bool pcihp_bridge_en;
99fd437d
MT		 121} AcpiBuildPciBusHotplugState;
122
0fe24669
SB		 123typedef struct FwCfgTPMConfig {
124 uint32_t tpmppi_address;
125 uint8_t tpm_version;
126 uint8_t tpmppi_version;
127} QEMU_PACKED FwCfgTPMConfig;
128
4a441836
GH		 129static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
130
5c94b826
KL		 131const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
132 .space_id = AML_AS_SYSTEM_IO,
133 .address = NVDIMM_ACPI_IO_BASE,
134 .bit_width = NVDIMM_ACPI_IO_LEN << 3
135};
136
0e11fc69
LX		 137static void init_common_fadt_data(MachineState *ms, Object *o,
138 AcpiFadtData *data)
937d1b58
IM		 139{
140 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
141 AmlAddressSpace as = AML_AS_SYSTEM_IO;
142 AcpiFadtData fadt = {
143 .rev = 3,
144 .flags =
145 (1 << ACPI_FADT_F_WBINVD) |
146 (1 << ACPI_FADT_F_PROC_C1) |
147 (1 << ACPI_FADT_F_SLP_BUTTON) |
148 (1 << ACPI_FADT_F_RTC_S4) |
149 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
150 /* APIC destination mode ("Flat Logical") has an upper limit of 8
151 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
152 * used
153 */
0e11fc69
LX		 154 ((ms->smp.max_cpus > 8) ?
155 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
937d1b58
IM		 156 .int_model = 1 /* Multiple APIC */,
157 .rtc_century = RTC_CENTURY,
158 .plvl2_lat = 0xfff /* C2 state not supported */,
159 .plvl3_lat = 0xfff /* C3 state not supported */,
160 .smi_cmd = ACPI_PORT_SMI_CMD,
161 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
162 .acpi_enable_cmd =
163 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
164 .acpi_disable_cmd =
165 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
166 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
167 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
168 .address = io + 0x04 },
169 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
170 .gpe0_blk = { .space_id = as, .bit_width =
171 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
172 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
173 },
174 };
175 *data = fadt;
176}
177
81c48dd7
PMD		 178static Object *object_resolve_type_unambiguous(const char *typename)
179{
180 bool ambig;
181 Object *o = object_resolve_path_type("", typename, &ambig);
182
183 if (ambig || !o) {
184 return NULL;
185 }
186 return o;
187}
188
0e11fc69 189static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
72c194f7 190{
81c48dd7
PMD		 191 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
192 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
697155cd 193 Object *obj = piix ? piix : lpc;
72c194f7 194 QObject *o;
94aaca64 195 pm->cpu_hp_io_base = 0;
500b11ea
IM		 196 pm->pcihp_io_base = 0;
197 pm->pcihp_io_len = 0;
937d1b58 198
6fa5171f 199 assert(obj);
a0628599 200 init_common_fadt_data(machine, obj, &pm->fadt);
72c194f7 201 if (piix) {
3a3fcc75 202 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
937d1b58 203 pm->fadt.rev = 1;
ddf1ec2f 204 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
500b11ea 205 pm->pcihp_io_base =
35f91e50 206 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
500b11ea 207 pm->pcihp_io_len =
35f91e50 208 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
72c194f7
MT		 209 }
210 if (lpc) {
937d1b58
IM		 211 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
212 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
213 pm->fadt.reset_reg = r;
214 pm->fadt.reset_val = 0xf;
215 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
ddf1ec2f 216 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
72c194f7 217 }
72c194f7 218
937d1b58
IM		 219 /* The above need not be conditional on machine type because the reset port
220 * happens to be the same on PIIX (pc) and ICH9 (q35). */
0063454a 221 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
937d1b58 222
72c194f7
MT		 223 /* Fill in optional s3/s4 related properties */
224 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
225 if (o) {
7dc847eb 226 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
72c194f7
MT		 227 } else {
228 pm->s3_disabled = false;
229 }
cb3e7f08 230 qobject_unref(o);
72c194f7
MT		 231 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
232 if (o) {
7dc847eb 233 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
72c194f7
MT		 234 } else {
235 pm->s4_disabled = false;
236 }
cb3e7f08 237 qobject_unref(o);
72c194f7
MT		 238 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
239 if (o) {
7dc847eb 240 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
72c194f7
MT		 241 } else {
242 pm->s4_val = false;
243 }
cb3e7f08 244 qobject_unref(o);
72c194f7 245
133a2da4
IM		 246 pm->pcihp_bridge_en =
247 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
248 NULL);
72c194f7
MT		 249}
250
72c194f7
MT		 251static void acpi_get_misc_info(AcpiMiscInfo *info)
252{
81c48dd7
PMD		 253 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
254 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
3db119da
IM		 255 assert(!!piix != !!lpc);
256
257 if (piix) {
258 info->is_piix4 = true;
259 }
260 if (lpc) {
261 info->is_piix4 = false;
262 }
263
72c194f7 264 info->has_hpet = hpet_find();
3dfd5a2a 265 info->tpm_version = tpm_get_version(tpm_find());
72c194f7 266 info->pvpanic_port = pvpanic_port();
8ac6f7a6 267 info->applesmc_io_base = applesmc_port();
72c194f7
MT		 268}
269
ca6c1855
MA		 270/*
271 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
272 * On i386 arch we only have two pci hosts, so we can look only for them.
273 */
274static Object *acpi_get_i386_pci_host(void)
275{
276 PCIHostState *host;
277
278 host = OBJECT_CHECK(PCIHostState,
279 object_resolve_path("/machine/i440fx", NULL),
280 TYPE_PCI_HOST_BRIDGE);
281 if (!host) {
282 host = OBJECT_CHECK(PCIHostState,
283 object_resolve_path("/machine/q35", NULL),
284 TYPE_PCI_HOST_BRIDGE);
285 }
286
287 return OBJECT(host);
288}
289
01c9742d 290static void acpi_get_pci_holes(Range *hole, Range *hole64)
72c194f7
MT		 291{
292 Object *pci_host;
72c194f7 293
ca6c1855 294 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 295 g_assert(pci_host);
296
a0efbf16 297 range_set_bounds1(hole,
60555365
MAL		 298 object_property_get_uint(pci_host,
299 PCI_HOST_PROP_PCI_HOLE_START,
300 NULL),
301 object_property_get_uint(pci_host,
302 PCI_HOST_PROP_PCI_HOLE_END,
303 NULL));
a0efbf16 304 range_set_bounds1(hole64,
60555365
MAL		 305 object_property_get_uint(pci_host,
306 PCI_HOST_PROP_PCI_HOLE64_START,
307 NULL),
308 object_property_get_uint(pci_host,
309 PCI_HOST_PROP_PCI_HOLE64_END,
310 NULL));
72c194f7
MT		 311}
312
72c194f7
MT		 313static void acpi_align_size(GArray *blob, unsigned align)
314{
315 /* Align size to multiple of given size. This reduces the chance
316 * we need to change size in the future (breaking cross version migration).
317 */
134d42d6 318 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
72c194f7
MT		 319}
320
72c194f7
MT		 321/* FACS */
322static void
009180bd 323build_facs(GArray *table_data)
72c194f7
MT		 324{
325 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
821e3227 326 memcpy(&facs->signature, "FACS", 4);
72c194f7
MT		 327 facs->length = cpu_to_le32(sizeof(*facs));
328}
329
ac35f13b 330void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
80e5db30 331 const CPUArchIdList *apic_ids, GArray *entry)
ac35f13b 332{
e2c95939
IM		 333 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
334
335 /* ACPI spec says that LAPIC entry for non present
336 * CPU may be omitted from MADT or it must be marked
337 * as disabled. However omitting non present CPU from
338 * MADT breaks hotplug on linux. So possible CPUs
339 * should be put in MADT but kept disabled.
340 */
341 if (apic_id < 255) {
342 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
343
344 apic->type = ACPI_APIC_PROCESSOR;
345 apic->length = sizeof(*apic);
346 apic->processor_id = uid;
347 apic->local_apic_id = apic_id;
348 if (apic_ids->cpus[uid].cpu != NULL) {
349 apic->flags = cpu_to_le32(1);
350 } else {
351 apic->flags = cpu_to_le32(0);
352 }
ac35f13b 353 } else {
e2c95939
IM		 354 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
355
356 apic->type = ACPI_APIC_LOCAL_X2APIC;
357 apic->length = sizeof(*apic);
358 apic->uid = cpu_to_le32(uid);
359 apic->x2apic_id = cpu_to_le32(apic_id);
360 if (apic_ids->cpus[uid].cpu != NULL) {
361 apic->flags = cpu_to_le32(1);
362 } else {
363 apic->flags = cpu_to_le32(0);
364 }
ac35f13b
IM		 365 }
366}
367
72c194f7 368static void
0e9b9eda 369build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
72c194f7 370{
907e7c94 371 MachineClass *mc = MACHINE_GET_CLASS(pcms);
f0bb276b 372 X86MachineState *x86ms = X86_MACHINE(pcms);
80e5db30 373 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
72c194f7 374 int madt_start = table_data->len;
ac35f13b
IM		 375 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
376 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
e2c95939 377 bool x2apic_mode = false;
72c194f7
MT		 378
379 AcpiMultipleApicTable *madt;
380 AcpiMadtIoApic *io_apic;
381 AcpiMadtIntsrcovr *intsrcovr;
72c194f7
MT		 382 int i;
383
384 madt = acpi_data_push(table_data, sizeof *madt);
385 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
386 madt->flags = cpu_to_le32(1);
387
907e7c94 388 for (i = 0; i < apic_ids->len; i++) {
ac35f13b 389 adevc->madt_cpu(adev, i, apic_ids, table_data);
e2c95939
IM		 390 if (apic_ids->cpus[i].arch_id > 254) {
391 x2apic_mode = true;
392 }
72c194f7 393 }
907e7c94 394
72c194f7
MT		 395 io_apic = acpi_data_push(table_data, sizeof *io_apic);
396 io_apic->type = ACPI_APIC_IO;
397 io_apic->length = sizeof(*io_apic);
72c194f7
MT		 398 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
399 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
400 io_apic->interrupt = cpu_to_le32(0);
401
f0bb276b 402 if (x86ms->apic_xrupt_override) {
72c194f7
MT		 403 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
404 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
405 intsrcovr->length = sizeof(*intsrcovr);
406 intsrcovr->source = 0;
407 intsrcovr->gsi = cpu_to_le32(2);
408 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
409 }
410 for (i = 1; i < 16; i++) {
411#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
412 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
413 /* No need for a INT source override structure. */
414 continue;
415 }
416 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
417 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
418 intsrcovr->length = sizeof(*intsrcovr);
419 intsrcovr->source = i;
420 intsrcovr->gsi = cpu_to_le32(i);
421 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
422 }
423
e2c95939
IM		 424 if (x2apic_mode) {
425 AcpiMadtLocalX2ApicNmi *local_nmi;
426
427 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
428 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
429 local_nmi->length = sizeof(*local_nmi);
430 local_nmi->uid = 0xFFFFFFFF; /* all processors */
431 local_nmi->flags = cpu_to_le16(0);
432 local_nmi->lint = 1; /* ACPI_LINT1 */
433 } else {
434 AcpiMadtLocalNmi *local_nmi;
435
436 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
437 local_nmi->type = ACPI_APIC_LOCAL_NMI;
438 local_nmi->length = sizeof(*local_nmi);
439 local_nmi->processor_id = 0xff; /* all processors */
440 local_nmi->flags = cpu_to_le16(0);
441 local_nmi->lint = 1; /* ACPI_LINT1 */
442 }
72c194f7
MT		 443
444 build_header(linker, table_data,
821e3227 445 (void *)(table_data->data + madt_start), "APIC",
37ad223c 446 table_data->len - madt_start, 1, NULL, NULL);
72c194f7
MT		 447}
448
62b52c26 449static void build_append_pcihp_notify_entry(Aml *method, int slot)
99fd437d 450{
62b52c26
IM		 451 Aml *if_ctx;
452 int32_t devfn = PCI_DEVFN(slot, 0);
453
5530427f 454 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
62b52c26
IM		 455 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
456 aml_append(method, if_ctx);
99fd437d
MT		 457}
458
62b52c26 459static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
b23046ab 460 bool pcihp_bridge_en)
99fd437d 461{
7dc847eb 462 Aml *dev, *notify_method = NULL, *method;
99fd437d 463 QObject *bsel;
b23046ab
IM		 464 PCIBus *sec;
465 int i;
133a2da4 466
99fd437d
MT		 467 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
468 if (bsel) {
7dc847eb 469 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
62b52c26
IM		 470
471 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
4dbfc881 472 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
8dcf525a 473 }
99fd437d 474
8dcf525a
MT		 475 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
476 DeviceClass *dc;
477 PCIDeviceClass *pc;
478 PCIDevice *pdev = bus->devices[i];
479 int slot = PCI_SLOT(i);
b23046ab 480 bool hotplug_enabled_dev;
093a35e5 481 bool bridge_in_acpi;
99fd437d 482
8dcf525a 483 if (!pdev) {
b23046ab 484 if (bsel) { /* add hotplug slots for non present devices */
62b52c26
IM		 485 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
486 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
487 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
4dbfc881 488 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 489 aml_append(method,
490 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
491 );
492 aml_append(dev, method);
493 aml_append(parent_scope, dev);
494
495 build_append_pcihp_notify_entry(notify_method, slot);
b23046ab 496 }
8dcf525a
MT		 497 continue;
498 }
99fd437d 499
8dcf525a
MT		 500 pc = PCI_DEVICE_GET_CLASS(pdev);
501 dc = DEVICE_GET_CLASS(pdev);
99fd437d 502
093a35e5
MT		 503 /* When hotplug for bridges is enabled, bridges are
504 * described in ACPI separately (see build_pci_bus_end).
505 * In this case they aren't themselves hot-pluggable.
a20275fa 506 * Hotplugged bridges *are* hot-pluggable.
093a35e5 507 */
b23046ab
IM		 508 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
509 !DEVICE(pdev)->hotplugged;
510
511 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
093a35e5 512
b23046ab
IM		 513 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
514 continue;
99fd437d
MT		 515 }
516
62b52c26
IM		 517 /* start to compose PCI slot descriptor */
518 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
519 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
520
8dcf525a 521 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
62b52c26
IM		 522 /* add VGA specific AML methods */
523 int s3d;
524
8dcf525a 525 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
62b52c26 526 s3d = 3;
b23046ab 527 } else {
62b52c26 528 s3d = 0;
99fd437d 529 }
62b52c26 530
4dbfc881 531 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 532 aml_append(method, aml_return(aml_int(0)));
533 aml_append(dev, method);
534
4dbfc881 535 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 536 aml_append(method, aml_return(aml_int(0)));
537 aml_append(dev, method);
538
4dbfc881 539 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 540 aml_append(method, aml_return(aml_int(s3d)));
541 aml_append(dev, method);
b23046ab 542 } else if (hotplug_enabled_dev) {
62b52c26
IM		 543 /* add _SUN/_EJ0 to make slot hotpluggable */
544 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
99fd437d 545
4dbfc881 546 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 547 aml_append(method,
548 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
549 );
550 aml_append(dev, method);
551
552 if (bsel) {
553 build_append_pcihp_notify_entry(notify_method, slot);
554 }
b23046ab 555 } else if (bridge_in_acpi) {
62b52c26
IM		 556 /*
557 * device is coldplugged bridge,
558 * add child device descriptions into its scope
559 */
b23046ab 560 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
b23046ab 561
62b52c26 562 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
8dcf525a 563 }
62b52c26
IM		 564 /* slot descriptor has been composed, add it into parent context */
565 aml_append(parent_scope, dev);
8dcf525a
MT		 566 }
567
568 if (bsel) {
62b52c26 569 aml_append(parent_scope, notify_method);
99fd437d
MT		 570 }
571
572 /* Append PCNT method to notify about events on local and child buses.
573 * Add unconditionally for root since DSDT expects it.
72c194f7 574 */
4dbfc881 575 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
99fd437d 576
b23046ab
IM		 577 /* If bus supports hotplug select it and notify about local events */
578 if (bsel) {
7dc847eb 579 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
01b2ffce 580
62b52c26
IM		 581 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
582 aml_append(method,
583 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
584 );
585 aml_append(method,
586 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
587 );
b23046ab 588 }
99fd437d 589
b23046ab
IM		 590 /* Notify about child bus events in any case */
591 if (pcihp_bridge_en) {
592 QLIST_FOREACH(sec, &bus->child, sibling) {
62b52c26
IM		 593 int32_t devfn = sec->parent_dev->devfn;
594
c99cb18e
MA		 595 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
596 continue;
597 }
598
62b52c26 599 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
99fd437d 600 }
72c194f7 601 }
62b52c26 602 aml_append(parent_scope, method);
cb3e7f08 603 qobject_unref(bsel);
72c194f7
MT		 604}
605
196e2137
IM		 606/**
607 * build_prt_entry:
608 * @link_name: link name for PCI route entry
609 *
610 * build AML package containing a PCI route entry for @link_name
611 */
612static Aml *build_prt_entry(const char *link_name)
613{
614 Aml *a_zero = aml_int(0);
615 Aml *pkg = aml_package(4);
616 aml_append(pkg, a_zero);
617 aml_append(pkg, a_zero);
618 aml_append(pkg, aml_name("%s", link_name));
619 aml_append(pkg, a_zero);
620 return pkg;
621}
622
0d8935e3
MA		 623/*
624 * initialize_route - Initialize the interrupt routing rule
625 * through a specific LINK:
626 * if (lnk_idx == idx)
627 * route using link 'link_name'
628 */
629static Aml *initialize_route(Aml *route, const char *link_name,
630 Aml *lnk_idx, int idx)
631{
632 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
196e2137 633 Aml *pkg = build_prt_entry(link_name);
0d8935e3 634
0d8935e3
MA		 635 aml_append(if_ctx, aml_store(pkg, route));
636
637 return if_ctx;
638}
639
640/*
641 * build_prt - Define interrupt rounting rules
642 *
643 * Returns an array of 128 routes, one for each device,
644 * based on device location.
645 * The main goal is to equaly distribute the interrupts
646 * over the 4 existing ACPI links (works only for i440fx).
647 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
648 *
649 */
196e2137 650static Aml *build_prt(bool is_pci0_prt)
0d8935e3
MA		 651{
652 Aml *method, *while_ctx, *pin, *res;
653
4dbfc881 654 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
0d8935e3
MA		 655 res = aml_local(0);
656 pin = aml_local(1);
657 aml_append(method, aml_store(aml_package(128), res));
658 aml_append(method, aml_store(aml_int(0), pin));
659
660 /* while (pin < 128) */
661 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
662 {
663 Aml *slot = aml_local(2);
664 Aml *lnk_idx = aml_local(3);
665 Aml *route = aml_local(4);
666
667 /* slot = pin >> 2 */
668 aml_append(while_ctx,
c360639a 669 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
0d8935e3
MA		 670 /* lnk_idx = (slot + pin) & 3 */
671 aml_append(while_ctx,
5530427f
IM		 672 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
673 lnk_idx));
0d8935e3
MA		 674
675 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
676 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
196e2137
IM		 677 if (is_pci0_prt) {
678 Aml *if_device_1, *if_pin_4, *else_pin_4;
679
680 /* device 1 is the power-management device, needs SCI */
681 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
682 {
683 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
684 {
685 aml_append(if_pin_4,
686 aml_store(build_prt_entry("LNKS"), route));
687 }
688 aml_append(if_device_1, if_pin_4);
689 else_pin_4 = aml_else();
690 {
691 aml_append(else_pin_4,
692 aml_store(build_prt_entry("LNKA"), route));
693 }
694 aml_append(if_device_1, else_pin_4);
695 }
696 aml_append(while_ctx, if_device_1);
697 } else {
698 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
699 }
0d8935e3
MA		 700 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
701 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
702
703 /* route[0] = 0x[slot]FFFF */
704 aml_append(while_ctx,
ca3df95d
IM		 705 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
706 NULL),
0d8935e3
MA		 707 aml_index(route, aml_int(0))));
708 /* route[1] = pin & 3 */
709 aml_append(while_ctx,
5530427f
IM		 710 aml_store(aml_and(pin, aml_int(3), NULL),
711 aml_index(route, aml_int(1))));
0d8935e3
MA		 712 /* res[pin] = route */
713 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
714 /* pin++ */
715 aml_append(while_ctx, aml_increment(pin));
716 }
717 aml_append(method, while_ctx);
718 /* return res*/
719 aml_append(method, aml_return(res));
720
721 return method;
722}
723
a43c6e27
MA		 724typedef struct CrsRangeEntry {
725 uint64_t base;
726 uint64_t limit;
727} CrsRangeEntry;
728
729static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
730{
731 CrsRangeEntry *entry;
732
733 entry = g_malloc(sizeof(*entry));
734 entry->base = base;
735 entry->limit = limit;
736
737 g_ptr_array_add(ranges, entry);
738}
739
740static void crs_range_free(gpointer data)
741{
742 CrsRangeEntry *entry = (CrsRangeEntry *)data;
743 g_free(entry);
744}
745
2df5a7b5
MA		 746typedef struct CrsRangeSet {
747 GPtrArray *io_ranges;
748 GPtrArray *mem_ranges;
16de88a4 749 GPtrArray *mem_64bit_ranges;
2df5a7b5
MA		 750 } CrsRangeSet;
751
752static void crs_range_set_init(CrsRangeSet *range_set)
753{
754 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
755 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
16de88a4
MA		 756 range_set->mem_64bit_ranges =
757 g_ptr_array_new_with_free_func(crs_range_free);
2df5a7b5
MA		 758}
759
760static void crs_range_set_free(CrsRangeSet *range_set)
761{
762 g_ptr_array_free(range_set->io_ranges, true);
763 g_ptr_array_free(range_set->mem_ranges, true);
16de88a4 764 g_ptr_array_free(range_set->mem_64bit_ranges, true);
2df5a7b5
MA		 765}
766
dcdca296
MA		 767static gint crs_range_compare(gconstpointer a, gconstpointer b)
768{
21e2acd5
EY		 769 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
770 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
dcdca296 771
21e2acd5
EY		 772 if (entry_a->base < entry_b->base) {
773 return -1;
774 } else if (entry_a->base > entry_b->base) {
775 return 1;
776 } else {
777 return 0;
778 }
dcdca296
MA		 779}
780
781/*
782 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
783 * interval, computes the 'free' ranges from the same interval.
784 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
785 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
786 */
787static void crs_replace_with_free_ranges(GPtrArray *ranges,
788 uint64_t start, uint64_t end)
789{
354fb471 790 GPtrArray *free_ranges = g_ptr_array_new();
dcdca296
MA		 791 uint64_t free_base = start;
792 int i;
793
794 g_ptr_array_sort(ranges, crs_range_compare);
795 for (i = 0; i < ranges->len; i++) {
796 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
797
798 if (free_base < used->base) {
799 crs_range_insert(free_ranges, free_base, used->base - 1);
800 }
801
802 free_base = used->limit + 1;
803 }
804
805 if (free_base < end) {
806 crs_range_insert(free_ranges, free_base, end);
807 }
808
809 g_ptr_array_set_size(ranges, 0);
810 for (i = 0; i < free_ranges->len; i++) {
811 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
812 }
813
354fb471 814 g_ptr_array_free(free_ranges, true);
dcdca296
MA		 815}
816
d7fd0e69
MA		 817/*
818 * crs_range_merge - merges adjacent ranges in the given array.
819 * Array elements are deleted and replaced with the merged ranges.
820 */
821static void crs_range_merge(GPtrArray *range)
822{
823 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
824 CrsRangeEntry *entry;
825 uint64_t range_base, range_limit;
826 int i;
827
828 if (!range->len) {
829 return;
830 }
831
832 g_ptr_array_sort(range, crs_range_compare);
833
834 entry = g_ptr_array_index(range, 0);
835 range_base = entry->base;
836 range_limit = entry->limit;
837 for (i = 1; i < range->len; i++) {
838 entry = g_ptr_array_index(range, i);
839 if (entry->base - 1 == range_limit) {
840 range_limit = entry->limit;
841 } else {
842 crs_range_insert(tmp, range_base, range_limit);
843 range_base = entry->base;
844 range_limit = entry->limit;
845 }
846 }
847 crs_range_insert(tmp, range_base, range_limit);
848
849 g_ptr_array_set_size(range, 0);
850 for (i = 0; i < tmp->len; i++) {
851 entry = g_ptr_array_index(tmp, i);
852 crs_range_insert(range, entry->base, entry->limit);
853 }
854 g_ptr_array_free(tmp, true);
855}
856
2df5a7b5 857static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
a43c6e27
MA		 858{
859 Aml *crs = aml_resource_template();
2df5a7b5 860 CrsRangeSet temp_range_set;
d7fd0e69 861 CrsRangeEntry *entry;
a43c6e27
MA		 862 uint8_t max_bus = pci_bus_num(host->bus);
863 uint8_t type;
864 int devfn;
d7fd0e69 865 int i;
a43c6e27 866
2df5a7b5 867 crs_range_set_init(&temp_range_set);
a43c6e27 868 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
a43c6e27
MA		 869 uint64_t range_base, range_limit;
870 PCIDevice *dev = host->bus->devices[devfn];
871
872 if (!dev) {
873 continue;
874 }
875
876 for (i = 0; i < PCI_NUM_REGIONS; i++) {
877 PCIIORegion *r = &dev->io_regions[i];
878
879 range_base = r->addr;
880 range_limit = r->addr + r->size - 1;
881
0f6dd8e1
MA		 882 /*
883 * Work-around for old bioses
884 * that do not support multiple root buses
885 */
886 if (!range_base || range_base > range_limit) {
887 continue;
888 }
889
a43c6e27 890 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
2df5a7b5
MA		 891 crs_range_insert(temp_range_set.io_ranges,
892 range_base, range_limit);
a43c6e27 893 } else { /* "memory" */
2df5a7b5
MA		 894 crs_range_insert(temp_range_set.mem_ranges,
895 range_base, range_limit);
a43c6e27
MA		 896 }
897 }
898
899 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
900 if (type == PCI_HEADER_TYPE_BRIDGE) {
901 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
902 if (subordinate > max_bus) {
903 max_bus = subordinate;
904 }
905
906 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
907 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
0f6dd8e1
MA		 908
909 /*
910 * Work-around for old bioses
911 * that do not support multiple root buses
912 */
4ebc736e 913 if (range_base && range_base <= range_limit) {
2df5a7b5
MA		 914 crs_range_insert(temp_range_set.io_ranges,
915 range_base, range_limit);
0f6dd8e1 916 }
a43c6e27
MA		 917
918 range_base =
919 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
920 range_limit =
921 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
0f6dd8e1
MA		 922
923 /*
924 * Work-around for old bioses
925 * that do not support multiple root buses
926 */
4ebc736e 927 if (range_base && range_base <= range_limit) {
16de88a4
MA		 928 uint64_t length = range_limit - range_base + 1;
929 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
930 crs_range_insert(temp_range_set.mem_ranges,
931 range_base, range_limit);
932 } else {
933 crs_range_insert(temp_range_set.mem_64bit_ranges,
934 range_base, range_limit);
935 }
4ebc736e 936 }
a43c6e27
MA		 937
938 range_base =
939 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
940 range_limit =
941 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
0f6dd8e1
MA		 942
943 /*
944 * Work-around for old bioses
945 * that do not support multiple root buses
946 */
4ebc736e 947 if (range_base && range_base <= range_limit) {
16de88a4
MA		 948 uint64_t length = range_limit - range_base + 1;
949 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
950 crs_range_insert(temp_range_set.mem_ranges,
951 range_base, range_limit);
952 } else {
953 crs_range_insert(temp_range_set.mem_64bit_ranges,
954 range_base, range_limit);
955 }
0f6dd8e1 956 }
a43c6e27
MA		 957 }
958 }
959
2df5a7b5
MA		 960 crs_range_merge(temp_range_set.io_ranges);
961 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
962 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
d7fd0e69
MA		 963 aml_append(crs,
964 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
965 AML_POS_DECODE, AML_ENTIRE_RANGE,
966 0, entry->base, entry->limit, 0,
967 entry->limit - entry->base + 1));
2df5a7b5 968 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
d7fd0e69 969 }
d7fd0e69 970
2df5a7b5
MA		 971 crs_range_merge(temp_range_set.mem_ranges);
972 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
973 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
d7fd0e69
MA		 974 aml_append(crs,
975 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
976 AML_MAX_FIXED, AML_NON_CACHEABLE,
977 AML_READ_WRITE,
978 0, entry->base, entry->limit, 0,
979 entry->limit - entry->base + 1));
2df5a7b5 980 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
d7fd0e69 981 }
2df5a7b5 982
16de88a4
MA		 983 crs_range_merge(temp_range_set.mem_64bit_ranges);
984 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
985 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
986 aml_append(crs,
987 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
988 AML_MAX_FIXED, AML_NON_CACHEABLE,
989 AML_READ_WRITE,
990 0, entry->base, entry->limit, 0,
991 entry->limit - entry->base + 1));
992 crs_range_insert(range_set->mem_64bit_ranges,
993 entry->base, entry->limit);
994 }
995
2df5a7b5 996 crs_range_set_free(&temp_range_set);
d7fd0e69 997
a43c6e27 998 aml_append(crs,
dcdca296 999 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
a43c6e27
MA		 1000 0,
1001 pci_bus_num(host->bus),
1002 max_bus,
1003 0,
1004 max_bus - pci_bus_num(host->bus) + 1));
1005
1006 return crs;
1007}
1008
a57d708d
IM		 1009static void build_hpet_aml(Aml *table)
1010{
1011 Aml *crs;
1012 Aml *field;
1013 Aml *method;
1014 Aml *if_ctx;
1015 Aml *scope = aml_scope("_SB");
1016 Aml *dev = aml_device("HPET");
1017 Aml *zero = aml_int(0);
1018 Aml *id = aml_local(0);
1019 Aml *period = aml_local(1);
1020
1021 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1022 aml_append(dev, aml_name_decl("_UID", zero));
1023
1024 aml_append(dev,
3f3009c0
XG		 1025 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1026 HPET_LEN));
a57d708d
IM		 1027 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1028 aml_append(field, aml_named_field("VEND", 32));
1029 aml_append(field, aml_named_field("PRD", 32));
1030 aml_append(dev, field);
1031
1032 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1033 aml_append(method, aml_store(aml_name("VEND"), id));
1034 aml_append(method, aml_store(aml_name("PRD"), period));
1035 aml_append(method, aml_shiftright(id, aml_int(16), id));
1036 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1037 aml_equal(id, aml_int(0xffff))));
1038 {
1039 aml_append(if_ctx, aml_return(zero));
1040 }
1041 aml_append(method, if_ctx);
1042
1043 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1044 aml_lgreater(period, aml_int(100000000))));
1045 {
1046 aml_append(if_ctx, aml_return(zero));
1047 }
1048 aml_append(method, if_ctx);
1049
1050 aml_append(method, aml_return(aml_int(0x0F)));
1051 aml_append(dev, method);
1052
1053 crs = aml_resource_template();
1054 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1055 aml_append(dev, aml_name_decl("_CRS", crs));
1056
1057 aml_append(scope, dev);
1058 aml_append(table, scope);
1059}
1060
27b9fc54 1061static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
95ed7e97 1062{
27b9fc54
RK		 1063 Aml *dev, *fdi;
1064 uint8_t maxc, maxh, maxs;
1065
1066 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1067
1068 dev = aml_device("FLP%c", 'A' + idx);
1069
1070 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1071
1072 fdi = aml_package(16);
1073 aml_append(fdi, aml_int(idx)); /* Drive Number */
1074 aml_append(fdi,
1075 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1076 /*
1077 * the values below are the limits of the drive, and are thus independent
1078 * of the inserted media
1079 */
1080 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1081 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1082 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1083 /*
1084 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1085 * the drive type, so shall we
1086 */
1087 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1088 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1089 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1090 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1091 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1092 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1093 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1094 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1095 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1096 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1097 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1098
1099 aml_append(dev, aml_name_decl("_FDI", fdi));
1100 return dev;
1101}
1102
1103static Aml *build_fdc_device_aml(ISADevice *fdc)
1104{
1105 int i;
95ed7e97
IM		 1106 Aml *dev;
1107 Aml *crs;
95ed7e97 1108
27b9fc54
RK		 1109#define ACPI_FDE_MAX_FD 4
1110 uint32_t fde_buf[5] = {
1111 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1112 cpu_to_le32(2) /* tape presence (2 == never present) */
1113 };
1114
95ed7e97
IM		 1115 dev = aml_device("FDC0");
1116 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1117
95ed7e97
IM		 1118 crs = aml_resource_template();
1119 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1120 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1121 aml_append(crs, aml_irq_no_flags(6));
1122 aml_append(crs,
1123 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1124 aml_append(dev, aml_name_decl("_CRS", crs));
1125
27b9fc54
RK		 1126 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1127 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1128
1129 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1130 fde_buf[i] = cpu_to_le32(1); /* drive present */
1131 aml_append(dev, build_fdinfo_aml(i, type));
1132 }
1133 }
1134 aml_append(dev, aml_name_decl("_FDE",
1135 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1136
95ed7e97
IM		 1137 return dev;
1138}
1139
f58190e2
IM		 1140static Aml *build_kbd_device_aml(void)
1141{
1142 Aml *dev;
1143 Aml *crs;
f58190e2
IM		 1144
1145 dev = aml_device("KBD");
1146 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1147
88b3648f 1148 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
f58190e2
IM		 1149
1150 crs = aml_resource_template();
1151 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1152 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1153 aml_append(crs, aml_irq_no_flags(1));
ee135849
IM		 1154 aml_append(dev, aml_name_decl("_CRS", crs));
1155
1156 return dev;
1157}
1158
c355cb2c
IM		 1159static Aml *build_mouse_device_aml(void)
1160{
1161 Aml *dev;
1162 Aml *crs;
c355cb2c
IM		 1163
1164 dev = aml_device("MOU");
1165 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1166
88b3648f 1167 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
c355cb2c
IM		 1168
1169 crs = aml_resource_template();
1170 aml_append(crs, aml_irq_no_flags(12));
1171 aml_append(dev, aml_name_decl("_CRS", crs));
1172
1173 return dev;
1174}
1175
ee135849
IM		 1176static void build_isa_devices_aml(Aml *table)
1177{
27b9fc54 1178 ISADevice *fdc = pc_find_fdc0();
86e91dd7 1179 bool ambiguous;
27b9fc54 1180
ee135849 1181 Aml *scope = aml_scope("_SB.PCI0.ISA");
86e91dd7 1182 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
ee135849 1183
f58190e2 1184 aml_append(scope, build_kbd_device_aml());
c355cb2c 1185 aml_append(scope, build_mouse_device_aml());
27b9fc54
RK		 1186 if (fdc) {
1187 aml_append(scope, build_fdc_device_aml(fdc));
9b613f4e 1188 }
ee135849 1189
86e91dd7
CM		 1190 if (ambiguous) {
1191 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1192 } else if (!obj) {
1193 error_report("No ISA bus, unable to define IPMI ACPI data");
1194 } else {
576d05b6 1195 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
a53e581e 1196 isa_build_aml(ISA_BUS(obj), scope);
86e91dd7
CM		 1197 }
1198
ee135849
IM		 1199 aml_append(table, scope);
1200}
1201
3892a2b7
IM		 1202static void build_dbg_aml(Aml *table)
1203{
1204 Aml *field;
1205 Aml *method;
1206 Aml *while_ctx;
1207 Aml *scope = aml_scope("\\");
1208 Aml *buf = aml_local(0);
1209 Aml *len = aml_local(1);
1210 Aml *idx = aml_local(2);
1211
1212 aml_append(scope,
3f3009c0 1213 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
3892a2b7
IM		 1214 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1215 aml_append(field, aml_named_field("DBGB", 8));
1216 aml_append(scope, field);
1217
1218 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1219
1220 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1221 aml_append(method, aml_to_buffer(buf, buf));
1222 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1223 aml_append(method, aml_store(aml_int(0), idx));
1224
1225 while_ctx = aml_while(aml_lless(idx, len));
1226 aml_append(while_ctx,
1227 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1228 aml_append(while_ctx, aml_increment(idx));
1229 aml_append(method, while_ctx);
1230
1231 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1232 aml_append(scope, method);
1233
1234 aml_append(table, scope);
1235}
1236
c35b6e80
IM		 1237static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1238{
1239 Aml *dev;
1240 Aml *crs;
1241 Aml *method;
1242 uint32_t irqs[] = {5, 10, 11};
1243
1244 dev = aml_device("%s", name);
1245 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1246 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1247
1248 crs = aml_resource_template();
1249 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1250 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1251 aml_append(dev, aml_name_decl("_PRS", crs));
1252
1253 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1254 aml_append(method, aml_return(aml_call1("IQST", reg)));
1255 aml_append(dev, method);
1256
1257 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1258 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1259 aml_append(dev, method);
1260
1261 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1262 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1263 aml_append(dev, method);
1264
1265 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1266 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1267 aml_append(method, aml_store(aml_name("PRRI"), reg));
1268 aml_append(dev, method);
1269
1270 return dev;
1271 }
1272
80b32df5
IM		 1273static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1274{
1275 Aml *dev;
1276 Aml *crs;
1277 Aml *method;
1278 uint32_t irqs;
1279
1280 dev = aml_device("%s", name);
1281 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1282 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1283
1284 crs = aml_resource_template();
1285 irqs = gsi;
1286 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1287 AML_SHARED, &irqs, 1));
1288 aml_append(dev, aml_name_decl("_PRS", crs));
1289
1290 aml_append(dev, aml_name_decl("_CRS", crs));
1291
c82f503d
MA		 1292 /*
1293 * _DIS can be no-op because the interrupt cannot be disabled.
1294 */
1295 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1296 aml_append(dev, method);
1297
80b32df5
IM		 1298 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1299 aml_append(dev, method);
1300
1301 return dev;
1302}
1303
16682a9d
IM		 1304/* _CRS method - get current settings */
1305static Aml *build_iqcr_method(bool is_piix4)
1306{
1307 Aml *if_ctx;
1308 uint32_t irqs;
1309 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1310 Aml *crs = aml_resource_template();
1311
1312 irqs = 0;
1313 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1314 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1315 aml_append(method, aml_name_decl("PRR0", crs));
1316
1317 aml_append(method,
1318 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1319
1320 if (is_piix4) {
1321 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1322 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1323 aml_append(method, if_ctx);
1324 } else {
1325 aml_append(method,
1326 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1327 aml_name("PRRI")));
1328 }
1329
1330 aml_append(method, aml_return(aml_name("PRR0")));
1331 return method;
1332}
1333
78e1ad05
IM		 1334/* _STA method - get status */
1335static Aml *build_irq_status_method(void)
1336{
1337 Aml *if_ctx;
1338 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1339
1340 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1341 aml_append(if_ctx, aml_return(aml_int(0x09)));
1342 aml_append(method, if_ctx);
1343 aml_append(method, aml_return(aml_int(0x0B)));
1344 return method;
1345}
1346
e4db2798
IM		 1347static void build_piix4_pci0_int(Aml *table)
1348{
c35b6e80
IM		 1349 Aml *dev;
1350 Aml *crs;
e4db2798 1351 Aml *field;
c35b6e80
IM		 1352 Aml *method;
1353 uint32_t irqs;
e4db2798 1354 Aml *sb_scope = aml_scope("_SB");
196e2137
IM		 1355 Aml *pci0_scope = aml_scope("PCI0");
1356
1357 aml_append(pci0_scope, build_prt(true));
1358 aml_append(sb_scope, pci0_scope);
e4db2798
IM		 1359
1360 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1361 aml_append(field, aml_named_field("PRQ0", 8));
1362 aml_append(field, aml_named_field("PRQ1", 8));
1363 aml_append(field, aml_named_field("PRQ2", 8));
1364 aml_append(field, aml_named_field("PRQ3", 8));
1365 aml_append(sb_scope, field);
1366
78e1ad05 1367 aml_append(sb_scope, build_irq_status_method());
16682a9d 1368 aml_append(sb_scope, build_iqcr_method(true));
100681cc 1369
c35b6e80
IM		 1370 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1371 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1372 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1373 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1374
1375 dev = aml_device("LNKS");
1376 {
1377 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1378 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1379
1380 crs = aml_resource_template();
1381 irqs = 9;
1382 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1383 AML_ACTIVE_HIGH, AML_SHARED,
1384 &irqs, 1));
1385 aml_append(dev, aml_name_decl("_PRS", crs));
1386
1387 /* The SCI cannot be disabled and is always attached to GSI 9,
1388 * so these are no-ops. We only need this link to override the
1389 * polarity to active high and match the content of the MADT.
1390 */
1391 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1392 aml_append(method, aml_return(aml_int(0x0b)));
1393 aml_append(dev, method);
1394
1395 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1396 aml_append(dev, method);
1397
1398 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1399 aml_append(method, aml_return(aml_name("_PRS")));
1400 aml_append(dev, method);
1401
1402 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1403 aml_append(dev, method);
1404 }
1405 aml_append(sb_scope, dev);
1406
e4db2798
IM		 1407 aml_append(table, sb_scope);
1408}
1409
22b5b8bf
IM		 1410static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1411{
1412 int i;
1413 int head;
1414 Aml *pkg;
1415 char base = name[3] < 'E' ? 'A' : 'E';
1416 char *s = g_strdup(name);
1417 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1418
1419 assert(strlen(s) == 4);
1420
1421 head = name[3] - base;
1422 for (i = 0; i < 4; i++) {
1423 if (head + i > 3) {
1424 head = i * -1;
1425 }
1426 s[3] = base + head + i;
1427 pkg = aml_package(4);
1428 aml_append(pkg, a_nr);
1429 aml_append(pkg, aml_int(i));
1430 aml_append(pkg, aml_name("%s", s));
1431 aml_append(pkg, aml_int(0));
1432 aml_append(ctx, pkg);
1433 }
1434 g_free(s);
1435}
1436
1437static Aml *build_q35_routing_table(const char *str)
1438{
1439 int i;
1440 Aml *pkg;
1441 char *name = g_strdup_printf("%s ", str);
1442
1443 pkg = aml_package(128);
1444 for (i = 0; i < 0x18; i++) {
1445 name[3] = 'E' + (i & 0x3);
1446 append_q35_prt_entry(pkg, i, name);
1447 }
1448
1449 name[3] = 'E';
1450 append_q35_prt_entry(pkg, 0x18, name);
1451
1452 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1453 for (i = 0x0019; i < 0x1e; i++) {
1454 name[3] = 'A';
1455 append_q35_prt_entry(pkg, i, name);
1456 }
1457
1458 /* PCIe->PCI bridge. use PIRQ[E-H] */
1459 name[3] = 'E';
1460 append_q35_prt_entry(pkg, 0x1e, name);
1461 name[3] = 'A';
1462 append_q35_prt_entry(pkg, 0x1f, name);
1463
1464 g_free(name);
1465 return pkg;
1466}
1467
80b32df5
IM		 1468static void build_q35_pci0_int(Aml *table)
1469{
41f95a52 1470 Aml *field;
0dafe3b3 1471 Aml *method;
80b32df5 1472 Aml *sb_scope = aml_scope("_SB");
0dafe3b3
IM		 1473 Aml *pci0_scope = aml_scope("PCI0");
1474
e9fce798
IM		 1475 /* Zero => PIC mode, One => APIC Mode */
1476 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1477 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1478 {
1479 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1480 }
1481 aml_append(table, method);
1482
65aef4de
IM		 1483 aml_append(pci0_scope,
1484 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
22b5b8bf
IM		 1485 aml_append(pci0_scope,
1486 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1487
0dafe3b3
IM		 1488 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1489 {
1490 Aml *if_ctx;
1491 Aml *else_ctx;
1492
1493 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1494 section 6.2.8.1 */
1495 /* Note: we provide the same info as the PCI routing
1496 table of the Bochs BIOS */
1497 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1498 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1499 aml_append(method, if_ctx);
1500 else_ctx = aml_else();
1501 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1502 aml_append(method, else_ctx);
1503 }
1504 aml_append(pci0_scope, method);
1505 aml_append(sb_scope, pci0_scope);
80b32df5 1506
41f95a52
IM		 1507 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1508 aml_append(field, aml_named_field("PRQA", 8));
1509 aml_append(field, aml_named_field("PRQB", 8));
1510 aml_append(field, aml_named_field("PRQC", 8));
1511 aml_append(field, aml_named_field("PRQD", 8));
1512 aml_append(field, aml_reserved_field(0x20));
1513 aml_append(field, aml_named_field("PRQE", 8));
1514 aml_append(field, aml_named_field("PRQF", 8));
1515 aml_append(field, aml_named_field("PRQG", 8));
1516 aml_append(field, aml_named_field("PRQH", 8));
1517 aml_append(sb_scope, field);
1518
78e1ad05 1519 aml_append(sb_scope, build_irq_status_method());
16682a9d
IM		 1520 aml_append(sb_scope, build_iqcr_method(false));
1521
12e3b1f7
IM		 1522 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1523 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1524 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1525 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1526 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1527 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1528 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1529 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1530
6a991e07
MA		 1531 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1532 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1533 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1534 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1535 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1536 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1537 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1538 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
80b32df5
IM		 1539
1540 aml_append(table, sb_scope);
1541}
1542
41f95a52
IM		 1543static void build_q35_isa_bridge(Aml *table)
1544{
1545 Aml *dev;
1546 Aml *scope;
1547 Aml *field;
1548
1549 scope = aml_scope("_SB.PCI0");
1550 dev = aml_device("ISA");
1551 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1552
1553 /* ICH9 PCI to ISA irq remapping */
1554 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
3f3009c0 1555 aml_int(0x60), 0x0C));
41f95a52
IM		 1556
1557 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
3f3009c0 1558 aml_int(0x80), 0x02));
41f95a52
IM		 1559 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1560 aml_append(field, aml_named_field("COMA", 3));
1561 aml_append(field, aml_reserved_field(1));
1562 aml_append(field, aml_named_field("COMB", 3));
1563 aml_append(field, aml_reserved_field(1));
1564 aml_append(field, aml_named_field("LPTD", 2));
41f95a52
IM		 1565 aml_append(dev, field);
1566
1567 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
3f3009c0 1568 aml_int(0x82), 0x02));
41f95a52
IM		 1569 /* enable bits */
1570 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1571 aml_append(field, aml_named_field("CAEN", 1));
1572 aml_append(field, aml_named_field("CBEN", 1));
1573 aml_append(field, aml_named_field("LPEN", 1));
41f95a52
IM		 1574 aml_append(dev, field);
1575
1576 aml_append(scope, dev);
1577 aml_append(table, scope);
1578}
1579
e4db2798
IM		 1580static void build_piix4_pm(Aml *table)
1581{
1582 Aml *dev;
1583 Aml *scope;
1584
1585 scope = aml_scope("_SB.PCI0");
1586 dev = aml_device("PX13");
1587 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1588
1589 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
3f3009c0 1590 aml_int(0x00), 0xff));
e4db2798
IM		 1591 aml_append(scope, dev);
1592 aml_append(table, scope);
1593}
1594
1595static void build_piix4_isa_bridge(Aml *table)
1596{
1597 Aml *dev;
1598 Aml *scope;
1599 Aml *field;
1600
1601 scope = aml_scope("_SB.PCI0");
1602 dev = aml_device("ISA");
1603 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1604
1605 /* PIIX PCI to ISA irq remapping */
1606 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
3f3009c0 1607 aml_int(0x60), 0x04));
e4db2798
IM		 1608 /* enable bits */
1609 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1610 /* Offset(0x5f),, 7, */
1611 aml_append(field, aml_reserved_field(0x2f8));
1612 aml_append(field, aml_reserved_field(7));
1613 aml_append(field, aml_named_field("LPEN", 1));
1614 /* Offset(0x67),, 3, */
1615 aml_append(field, aml_reserved_field(0x38));
1616 aml_append(field, aml_reserved_field(3));
1617 aml_append(field, aml_named_field("CAEN", 1));
1618 aml_append(field, aml_reserved_field(3));
1619 aml_append(field, aml_named_field("CBEN", 1));
1620 aml_append(dev, field);
e4db2798
IM		 1621
1622 aml_append(scope, dev);
1623 aml_append(table, scope);
1624}
1625
b616ec4d
IM		 1626static void build_piix4_pci_hotplug(Aml *table)
1627{
1628 Aml *scope;
1629 Aml *field;
1630 Aml *method;
1631
1632 scope = aml_scope("_SB.PCI0");
1633
1634 aml_append(scope,
3f3009c0 1635 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
b616ec4d
IM		 1636 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1637 aml_append(field, aml_named_field("PCIU", 32));
1638 aml_append(field, aml_named_field("PCID", 32));
1639 aml_append(scope, field);
1640
1641 aml_append(scope,
3f3009c0 1642 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
b616ec4d
IM		 1643 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1644 aml_append(field, aml_named_field("B0EJ", 32));
1645 aml_append(scope, field);
1646
1647 aml_append(scope,
3f3009c0 1648 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
b616ec4d
IM		 1649 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1650 aml_append(field, aml_named_field("BNUM", 32));
1651 aml_append(scope, field);
1652
1653 aml_append(scope, aml_mutex("BLCK", 0));
1654
1655 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1656 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1657 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1658 aml_append(method,
1659 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1660 aml_append(method, aml_release(aml_name("BLCK")));
1661 aml_append(method, aml_return(aml_int(0)));
1662 aml_append(scope, method);
1663
1664 aml_append(table, scope);
1665}
1666
f97a88a8
IM		 1667static Aml *build_q35_osc_method(void)
1668{
1669 Aml *if_ctx;
1670 Aml *if_ctx2;
1671 Aml *else_ctx;
1672 Aml *method;
1673 Aml *a_cwd1 = aml_name("CDW1");
b3c782db 1674 Aml *a_ctrl = aml_local(0);
f97a88a8
IM		 1675
1676 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1677 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1678
1679 if_ctx = aml_if(aml_equal(
1680 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1681 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1682 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1683
f97a88a8
IM		 1684 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1685
1686 /*
1687 * Always allow native PME, AER (no dependencies)
a41c78c1 1688 * Allow SHPC (PCI bridges can have SHPC controller)
f97a88a8 1689 */
a41c78c1 1690 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
f97a88a8
IM		 1691
1692 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1693 /* Unknown revision */
1694 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1695 aml_append(if_ctx, if_ctx2);
1696
1697 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1698 /* Capabilities bits were masked */
1699 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1700 aml_append(if_ctx, if_ctx2);
1701
1702 /* Update DWORD3 in the buffer */
1703 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1704 aml_append(method, if_ctx);
1705
1706 else_ctx = aml_else();
1707 /* Unrecognized UUID */
1708 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1709 aml_append(method, else_ctx);
1710
1711 aml_append(method, aml_return(aml_arg(3)));
1712 return method;
1713}
b616ec4d 1714
ebe15582
CM		 1715static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func)
1716{
1717 Aml *scope = aml_scope("_SB.PCI0");
1718 Aml *dev = aml_device("SMB0");
1719
ebe15582
CM		 1720 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1721 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
1722 aml_append(scope, dev);
1723 aml_append(table, scope);
1724}
1725
72c194f7 1726static void
0e9b9eda 1727build_dsdt(GArray *table_data, BIOSLinker *linker,
adcb89d5 1728 AcpiPmInfo *pm, AcpiMiscInfo *misc,
01c9742d 1729 Range *pci_hole, Range *pci_hole64, MachineState *machine)
72c194f7 1730{
41fa5c04
IM		 1731 CrsRangeEntry *entry;
1732 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
2df5a7b5 1733 CrsRangeSet crs_range_set;
fb306ffe 1734 PCMachineState *pcms = PC_MACHINE(machine);
679dd1a9 1735 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
f0bb276b 1736 X86MachineState *x86ms = X86_MACHINE(machine);
4a441836 1737 AcpiMcfgInfo mcfg;
bef3492d 1738 uint32_t nr_mem = machine->ram_slots;
dcdca296 1739 int root_bus_limit = 0xFF;
41fa5c04 1740 PCIBus *bus = NULL;
ac6dd31e 1741 TPMIf *tpm = tpm_find();
72c194f7
MT		 1742 int i;
1743
41fa5c04 1744 dsdt = init_aml_allocator();
2fd71f1b 1745
4ec8d2b3 1746 /* Reserve space for header */
41fa5c04
IM		 1747 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1748
1749 build_dbg_aml(dsdt);
1750 if (misc->is_piix4) {
1751 sb_scope = aml_scope("_SB");
1752 dev = aml_device("PCI0");
1753 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1754 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1755 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1756 aml_append(sb_scope, dev);
1757 aml_append(dsdt, sb_scope);
1758
1759 build_hpet_aml(dsdt);
1760 build_piix4_pm(dsdt);
1761 build_piix4_isa_bridge(dsdt);
1762 build_isa_devices_aml(dsdt);
1763 build_piix4_pci_hotplug(dsdt);
1764 build_piix4_pci0_int(dsdt);
1765 } else {
41fa5c04
IM		 1766 sb_scope = aml_scope("_SB");
1767 dev = aml_device("PCI0");
1768 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1769 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1770 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1771 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
41fa5c04
IM		 1772 aml_append(dev, build_q35_osc_method());
1773 aml_append(sb_scope, dev);
1774 aml_append(dsdt, sb_scope);
1775
1776 build_hpet_aml(dsdt);
1777 build_q35_isa_bridge(dsdt);
1778 build_isa_devices_aml(dsdt);
1779 build_q35_pci0_int(dsdt);
ebe15582
CM		 1780 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
1781 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1782 }
41fa5c04
IM		 1783 }
1784
679dd1a9
IM		 1785 if (pcmc->legacy_cpu_hotplug) {
1786 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1787 } else {
1788 CPUHotplugFeatures opts = {
89cb0c04 1789 .acpi_1_compatible = true, .has_legacy_cphp = true
679dd1a9
IM		 1790 };
1791 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1792 "\\_SB.PCI0", "\\_GPE._E02");
1793 }
091c466e
SK		 1794
1795 if (pcms->memhp_io_base && nr_mem) {
1796 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1797 "\\_GPE._E03", AML_SYSTEM_IO,
1798 pcms->memhp_io_base);
1799 }
41fa5c04
IM		 1800
1801 scope = aml_scope("_GPE");
1802 {
1803 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1804
41fa5c04
IM		 1805 if (misc->is_piix4) {
1806 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1807 aml_append(method,
1808 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1809 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1810 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1811 aml_append(scope, method);
41fa5c04
IM		 1812 }
1813
f6a0d06b 1814 if (machine->nvdimms_state->is_enabled) {
b097cc52
XG		 1815 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1816 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1817 aml_int(0x80)));
1818 aml_append(scope, method);
1819 }
41fa5c04
IM		 1820 }
1821 aml_append(dsdt, scope);
72c194f7 1822
2df5a7b5 1823 crs_range_set_init(&crs_range_set);
81ed6482 1824 bus = PC_MACHINE(machine)->bus;
a4894206
MA		 1825 if (bus) {
1826 QLIST_FOREACH(bus, &bus->child, sibling) {
1827 uint8_t bus_num = pci_bus_num(bus);
0e79e51a 1828 uint8_t numa_node = pci_bus_numa_node(bus);
a4894206
MA		 1829
1830 /* look only for expander root buses */
1831 if (!pci_bus_is_root(bus)) {
1832 continue;
1833 }
1834
dcdca296
MA		 1835 if (bus_num < root_bus_limit) {
1836 root_bus_limit = bus_num - 1;
1837 }
1838
a4894206
MA		 1839 scope = aml_scope("\\_SB");
1840 dev = aml_device("PC%.02X", bus_num);
c96d9286 1841 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
a4894206 1842 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
077dd742 1843 if (pci_bus_is_express(bus)) {
ee4b0c86
EY		 1844 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1845 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
077dd742 1846 aml_append(dev, build_q35_osc_method());
ee4b0c86
EY		 1847 } else {
1848 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
077dd742 1849 }
0e79e51a
MA		 1850
1851 if (numa_node != NUMA_NODE_UNASSIGNED) {
1852 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1853 }
1854
196e2137 1855 aml_append(dev, build_prt(false));
2df5a7b5 1856 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
a43c6e27 1857 aml_append(dev, aml_name_decl("_CRS", crs));
a4894206 1858 aml_append(scope, dev);
41fa5c04 1859 aml_append(dsdt, scope);
a4894206
MA		 1860 }
1861 }
1862
4a441836
GH		 1863 /*
1864 * At this point crs_range_set has all the ranges used by pci
1865 * busses *other* than PCI0. These ranges will be excluded from
1866 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1867 * too.
1868 */
1869 if (acpi_get_mcfg(&mcfg)) {
1870 crs_range_insert(crs_range_set.mem_ranges,
1871 mcfg.base, mcfg.base + mcfg.size - 1);
1872 }
1873
500b11ea 1874 scope = aml_scope("\\_SB.PCI0");
60efd429
IM		 1875 /* build PCI0._CRS */
1876 crs = aml_resource_template();
1877 aml_append(crs,
ff80dc7f 1878 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
dcdca296
MA		 1879 0x0000, 0x0, root_bus_limit,
1880 0x0000, root_bus_limit + 1));
ff80dc7f 1881 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
60efd429
IM		 1882
1883 aml_append(crs,
ff80dc7f
SZ		 1884 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1885 AML_POS_DECODE, AML_ENTIRE_RANGE,
60efd429 1886 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
dcdca296 1887
2df5a7b5
MA		 1888 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1889 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1890 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
dcdca296
MA		 1891 aml_append(crs,
1892 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1893 AML_POS_DECODE, AML_ENTIRE_RANGE,
1894 0x0000, entry->base, entry->limit,
1895 0x0000, entry->limit - entry->base + 1));
1896 }
1897
60efd429 1898 aml_append(crs,
ff80dc7f
SZ		 1899 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1900 AML_CACHEABLE, AML_READ_WRITE,
60efd429 1901 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
dcdca296 1902
2df5a7b5 1903 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
a0efbf16
MA		 1904 range_lob(pci_hole),
1905 range_upb(pci_hole));
2df5a7b5
MA		 1906 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1907 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
dcdca296
MA		 1908 aml_append(crs,
1909 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1910 AML_NON_CACHEABLE, AML_READ_WRITE,
1911 0, entry->base, entry->limit,
1912 0, entry->limit - entry->base + 1));
1913 }
1914
a0efbf16 1915 if (!range_is_empty(pci_hole64)) {
16de88a4
MA		 1916 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1917 range_lob(pci_hole64),
1918 range_upb(pci_hole64));
1919 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1920 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1921 aml_append(crs,
1922 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1923 AML_MAX_FIXED,
1924 AML_CACHEABLE, AML_READ_WRITE,
1925 0, entry->base, entry->limit,
1926 0, entry->limit - entry->base + 1));
1927 }
60efd429 1928 }
2b1c2e8e 1929
43bc7f84 1930 if (TPM_IS_TIS_ISA(tpm_find())) {
2b1c2e8e
IM		 1931 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1932 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1933 }
60efd429
IM		 1934 aml_append(scope, aml_name_decl("_CRS", crs));
1935
d31c909e
IM		 1936 /* reserve GPE0 block resources */
1937 dev = aml_device("GPE0");
1938 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1939 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1940 /* device present, functioning, decoding, not shown in UI */
1941 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1942 crs = aml_resource_template();
1943 aml_append(crs,
937d1b58
IM		 1944 aml_io(
1945 AML_DECODE16,
1946 pm->fadt.gpe0_blk.address,
1947 pm->fadt.gpe0_blk.address,
1948 1,
1949 pm->fadt.gpe0_blk.bit_width / 8)
d31c909e
IM		 1950 );
1951 aml_append(dev, aml_name_decl("_CRS", crs));
1952 aml_append(scope, dev);
1953
2df5a7b5 1954 crs_range_set_free(&crs_range_set);
dcdca296 1955
500b11ea
IM		 1956 /* reserve PCIHP resources */
1957 if (pm->pcihp_io_len) {
1958 dev = aml_device("PHPR");
1959 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1960 aml_append(dev,
1961 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1962 /* device present, functioning, decoding, not shown in UI */
1963 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1964 crs = aml_resource_template();
1965 aml_append(crs,
ff80dc7f 1966 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
500b11ea
IM		 1967 pm->pcihp_io_len)
1968 );
1969 aml_append(dev, aml_name_decl("_CRS", crs));
1970 aml_append(scope, dev);
1971 }
41fa5c04 1972 aml_append(dsdt, scope);
500b11ea 1973
ebc3028f
IM		 1974 /* create S3_ / S4_ / S5_ packages if necessary */
1975 scope = aml_scope("\\");
1976 if (!pm->s3_disabled) {
1977 pkg = aml_package(4);
1978 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1979 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1980 aml_append(pkg, aml_int(0)); /* reserved */
1981 aml_append(pkg, aml_int(0)); /* reserved */
1982 aml_append(scope, aml_name_decl("_S3", pkg));
1983 }
1984
1985 if (!pm->s4_disabled) {
1986 pkg = aml_package(4);
1987 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1988 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1989 aml_append(pkg, aml_int(pm->s4_val));
1990 aml_append(pkg, aml_int(0)); /* reserved */
1991 aml_append(pkg, aml_int(0)); /* reserved */
1992 aml_append(scope, aml_name_decl("_S4", pkg));
1993 }
1994
1995 pkg = aml_package(4);
1996 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1997 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1998 aml_append(pkg, aml_int(0)); /* reserved */
1999 aml_append(pkg, aml_int(0)); /* reserved */
2000 aml_append(scope, aml_name_decl("_S5", pkg));
41fa5c04 2001 aml_append(dsdt, scope);
ebc3028f 2002
e2ec7568
GS		 2003 /* create fw_cfg node, unconditionally */
2004 {
2005 /* when using port i/o, the 8-bit data register *always* overlaps
2006 * with half of the 16-bit control register. Hence, the total size
2007 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2008 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
f0bb276b 2009 uint8_t io_size = object_property_get_bool(OBJECT(x86ms->fw_cfg),
e2ec7568
GS		 2010 "dma_enabled", NULL) ?
2011 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2012 FW_CFG_CTL_SIZE;
2013
2014 scope = aml_scope("\\_SB.PCI0");
2015 dev = aml_device("FWCF");
2016
2017 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2018
2019 /* device present, functioning, decoding, not shown in UI */
2020 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2021
2022 crs = aml_resource_template();
2023 aml_append(crs,
2024 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2025 );
2026 aml_append(dev, aml_name_decl("_CRS", crs));
2027
2028 aml_append(scope, dev);
2029 aml_append(dsdt, scope);
2030 }
2031
8ac6f7a6
IM		 2032 if (misc->applesmc_io_base) {
2033 scope = aml_scope("\\_SB.PCI0.ISA");
2034 dev = aml_device("SMC");
2035
2036 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2037 /* device present, functioning, decoding, not shown in UI */
2038 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2039
2040 crs = aml_resource_template();
2041 aml_append(crs,
ff80dc7f 2042 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
8ac6f7a6
IM		 2043 0x01, APPLESMC_MAX_DATA_LENGTH)
2044 );
2045 aml_append(crs, aml_irq_no_flags(6));
2046 aml_append(dev, aml_name_decl("_CRS", crs));
2047
2048 aml_append(scope, dev);
41fa5c04 2049 aml_append(dsdt, scope);
8ac6f7a6
IM		 2050 }
2051
cd61cb2e
IM		 2052 if (misc->pvpanic_port) {
2053 scope = aml_scope("\\_SB.PCI0.ISA");
2054
2332333c 2055 dev = aml_device("PEVT");
e65bef69 2056 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
cd61cb2e
IM		 2057
2058 crs = aml_resource_template();
2059 aml_append(crs,
ff80dc7f 2060 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
cd61cb2e
IM		 2061 );
2062 aml_append(dev, aml_name_decl("_CRS", crs));
2063
ff80dc7f 2064 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
3f3009c0 2065 aml_int(misc->pvpanic_port), 1));
36de884a 2066 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
cd61cb2e
IM		 2067 aml_append(field, aml_named_field("PEPT", 8));
2068 aml_append(dev, field);
2069
8ef3ea25
GH		 2070 /* device present, functioning, decoding, shown in UI */
2071 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2332333c 2072
4dbfc881 2073 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
cd61cb2e
IM		 2074 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2075 aml_append(method, aml_return(aml_local(0)));
2076 aml_append(dev, method);
2077
4dbfc881 2078 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
cd61cb2e
IM		 2079 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2080 aml_append(dev, method);
2081
2082 aml_append(scope, dev);
41fa5c04 2083 aml_append(dsdt, scope);
cd61cb2e
IM		 2084 }
2085
7824df38 2086 sb_scope = aml_scope("\\_SB");
72c194f7 2087 {
8b35ab27
IM		 2088 Object *pci_host;
2089 PCIBus *bus = NULL;
8698c0c0 2090
8b35ab27
IM		 2091 pci_host = acpi_get_i386_pci_host();
2092 if (pci_host) {
2093 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2094 }
8dcf525a 2095
8b35ab27
IM		 2096 if (bus) {
2097 Aml *scope = aml_scope("PCI0");
2098 /* Scan all PCI buses. Generate tables to support hotplug. */
2099 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2100
43bc7f84 2101 if (TPM_IS_TIS_ISA(tpm)) {
24cf5413
SB		 2102 if (misc->tpm_version == TPM_VERSION_2_0) {
2103 dev = aml_device("TPM");
2104 aml_append(dev, aml_name_decl("_HID",
2105 aml_string("MSFT0101")));
2106 } else {
2107 dev = aml_device("ISA.TPM");
2108 aml_append(dev, aml_name_decl("_HID",
2109 aml_eisaid("PNP0C31")));
2110 }
2111
8b35ab27
IM		 2112 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2113 crs = aml_resource_template();
2114 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2115 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2116 /*
2117 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2118 Rewrite to take IRQ from TPM device model and
2119 fix default IRQ value there to use some unused IRQ
2120 */
2121 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2122 aml_append(dev, aml_name_decl("_CRS", crs));
ac6dd31e
SB		 2123
2124 tpm_build_ppi_acpi(tpm, dev);
2125
8b35ab27 2126 aml_append(scope, dev);
8dcf525a 2127 }
72c194f7 2128
8b35ab27 2129 aml_append(sb_scope, scope);
72c194f7 2130 }
72c194f7 2131 }
4ab6cb4c 2132
ac6dd31e 2133 if (TPM_IS_CRB(tpm)) {
4ab6cb4c
MAL		 2134 dev = aml_device("TPM");
2135 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
2136 crs = aml_resource_template();
2137 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
2138 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
2139 aml_append(dev, aml_name_decl("_CRS", crs));
2140
88b3648f 2141 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
4ab6cb4c 2142
ac6dd31e
SB		 2143 tpm_build_ppi_acpi(tpm, dev);
2144
4ab6cb4c
MAL		 2145 aml_append(sb_scope, dev);
2146 }
2147
8b35ab27 2148 aml_append(dsdt, sb_scope);
72c194f7 2149
011bb749 2150 /* copy AML table into ACPI tables blob and patch header there */
41fa5c04 2151 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
72c194f7 2152 build_header(linker, table_data,
41fa5c04 2153 (void *)(table_data->data + table_data->len - dsdt->buf->len),
37ad223c 2154 "DSDT", dsdt->buf->len, 1, NULL, NULL);
011bb749 2155 free_aml_allocator();
72c194f7
MT		 2156}
2157
2158static void
0e9b9eda 2159build_hpet(GArray *table_data, BIOSLinker *linker)
72c194f7
MT		 2160{
2161 Acpi20Hpet *hpet;
2162
2163 hpet = acpi_data_push(table_data, sizeof(*hpet));
2164 /* Note timer_block_id value must be kept in sync with value advertised by
2165 * emulated hpet
2166 */
2167 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2168 hpet->addr.address = cpu_to_le64(HPET_BASE);
2169 build_header(linker, table_data,
37ad223c 2170 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
72c194f7
MT		 2171}
2172
711b20b4 2173static void
0e9b9eda 2174build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
711b20b4
SB		 2175{
2176 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
4678124b
IM		 2177 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2178 unsigned log_addr_offset =
2179 (char *)&tcpa->log_area_start_address - table_data->data;
711b20b4
SB		 2180
2181 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2182 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
9774ccf7 2183 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
711b20b4 2184
ad9671b8 2185 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
42a5b308
SB		 2186 false /* high memory */);
2187
711b20b4 2188 /* log area start address to be filled by Guest linker */
4678124b
IM		 2189 bios_linker_loader_add_pointer(linker,
2190 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2191 ACPI_BUILD_TPMLOG_FILE, 0);
711b20b4
SB		 2192
2193 build_header(linker, table_data,
37ad223c 2194 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
711b20b4
SB		 2195}
2196
5cb18b3d 2197static void
4a42fa0e 2198build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
5cb18b3d 2199{
4a42fa0e
SB		 2200 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2201 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
2202 unsigned log_addr_offset =
2203 (char *)&tpm2_ptr->log_area_start_address - table_data->data;
5cb18b3d
SB		 2204
2205 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
43bc7f84 2206 if (TPM_IS_TIS_ISA(tpm_find())) {
ff5ce21e
MAL		 2207 tpm2_ptr->control_area_address = cpu_to_le64(0);
2208 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
4ab6cb4c
MAL		 2209 } else if (TPM_IS_CRB(tpm_find())) {
2210 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL);
2211 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB);
ff5ce21e
MAL		 2212 } else {
2213 g_warn_if_reached();
2214 }
5cb18b3d 2215
4ab6cb4c
MAL		 2216 tpm2_ptr->log_area_minimum_length =
2217 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2218
7e7c1b84
SB		 2219 acpi_data_push(tcpalog, le32_to_cpu(tpm2_ptr->log_area_minimum_length));
2220 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2221 false);
2222
4ab6cb4c
MAL		 2223 /* log area start address to be filled by Guest linker */
2224 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2225 log_addr_offset, log_addr_size,
2226 ACPI_BUILD_TPMLOG_FILE, 0);
5cb18b3d 2227 build_header(linker, table_data,
37ad223c 2228 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
5cb18b3d
SB		 2229}
2230
d471bf3e
PB		 2231#define HOLE_640K_START (640 * KiB)
2232#define HOLE_640K_END (1 * MiB)
4926403c 2233
72c194f7 2234static void
0e9b9eda 2235build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
72c194f7
MT		 2236{
2237 AcpiSystemResourceAffinityTable *srat;
72c194f7
MT		 2238 AcpiSratMemoryAffinity *numamem;
2239
2240 int i;
72c194f7
MT		 2241 int srat_start, numa_start, slots;
2242 uint64_t mem_len, mem_base, next_base;
5803fce3 2243 MachineClass *mc = MACHINE_GET_CLASS(machine);
f0bb276b 2244 X86MachineState *x86ms = X86_MACHINE(machine);
80e5db30 2245 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
3d3ebcad 2246 PCMachineState *pcms = PC_MACHINE(machine);
cec65193 2247 ram_addr_t hotplugabble_address_space_size =
f2ffbe2b 2248 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
cec65193 2249 NULL);
72c194f7
MT		 2250
2251 srat_start = table_data->len;
2252
2253 srat = acpi_data_push(table_data, sizeof *srat);
2254 srat->reserved1 = cpu_to_le32(1);
72c194f7 2255
5803fce3 2256 for (i = 0; i < apic_ids->len; i++) {
d41f3e75 2257 int node_id = apic_ids->cpus[i].props.node_id;
5eff33a2 2258 uint32_t apic_id = apic_ids->cpus[i].arch_id;
5803fce3 2259
5eff33a2
IM		 2260 if (apic_id < 255) {
2261 AcpiSratProcessorAffinity *core;
2262
2263 core = acpi_data_push(table_data, sizeof *core);
2264 core->type = ACPI_SRAT_PROCESSOR_APIC;
2265 core->length = sizeof(*core);
2266 core->local_apic_id = apic_id;
ea265072 2267 core->proximity_lo = node_id;
5eff33a2
IM		 2268 memset(core->proximity_hi, 0, 3);
2269 core->local_sapic_eid = 0;
2270 core->flags = cpu_to_le32(1);
2271 } else {
2272 AcpiSratProcessorX2ApicAffinity *core;
2273
2274 core = acpi_data_push(table_data, sizeof *core);
2275 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2276 core->length = sizeof(*core);
2277 core->x2apic_id = cpu_to_le32(apic_id);
ea265072 2278 core->proximity_domain = cpu_to_le32(node_id);
5eff33a2 2279 core->flags = cpu_to_le32(1);
1f3aba37 2280 }
72c194f7
MT		 2281 }
2282
2283
2284 /* the memory map is a bit tricky, it contains at least one hole
2285 * from 640k-1M and possibly another one from 3.5G-4G.
2286 */
2287 next_base = 0;
2288 numa_start = table_data->len;
2289
dd4c2f01 2290 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
72c194f7 2291 mem_base = next_base;
dd4c2f01 2292 mem_len = pcms->node_mem[i - 1];
72c194f7
MT		 2293 next_base = mem_base + mem_len;
2294
4926403c
EH		 2295 /* Cut out the 640K hole */
2296 if (mem_base <= HOLE_640K_START &&
2297 next_base > HOLE_640K_START) {
2298 mem_len -= next_base - HOLE_640K_START;
2299 if (mem_len > 0) {
2300 numamem = acpi_data_push(table_data, sizeof *numamem);
2301 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2302 MEM_AFFINITY_ENABLED);
2303 }
2304
2305 /* Check for the rare case: 640K < RAM < 1M */
2306 if (next_base <= HOLE_640K_END) {
2307 next_base = HOLE_640K_END;
2308 continue;
2309 }
2310 mem_base = HOLE_640K_END;
2311 mem_len = next_base - HOLE_640K_END;
2312 }
2313
72c194f7 2314 /* Cut out the ACPI_PCI hole */
f0bb276b
PB		 2315 if (mem_base <= x86ms->below_4g_mem_size &&
2316 next_base > x86ms->below_4g_mem_size) {
2317 mem_len -= next_base - x86ms->below_4g_mem_size;
72c194f7
MT		 2318 if (mem_len > 0) {
2319 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136
SZ		 2320 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2321 MEM_AFFINITY_ENABLED);
72c194f7
MT		 2322 }
2323 mem_base = 1ULL << 32;
f0bb276b 2324 mem_len = next_base - x86ms->below_4g_mem_size;
6cf6fe39 2325 next_base = mem_base + mem_len;
72c194f7 2326 }
16b42263
DL		 2327
2328 if (mem_len > 0) {
2329 numamem = acpi_data_push(table_data, sizeof *numamem);
2330 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2331 MEM_AFFINITY_ENABLED);
2332 }
72c194f7 2333 }
c3b0cf6e
VV		 2334
2335 if (machine->nvdimms_state->is_enabled) {
2336 nvdimm_build_srat(table_data);
2337 }
2338
72c194f7 2339 slots = (table_data->len - numa_start) / sizeof *numamem;
dd4c2f01 2340 for (; slots < pcms->numa_nodes + 2; slots++) {
72c194f7 2341 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136 2342 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
72c194f7
MT		 2343 }
2344
dbb6da8b
IM		 2345 /*
2346 * Entry is required for Windows to enable memory hotplug in OS
2347 * and for Linux to enable SWIOTLB when booted with less than
2348 * 4G of RAM. Windows works better if the entry sets proximity
2349 * to the highest NUMA node in the machine.
2350 * Memory devices may override proximity set by this entry,
2351 * providing _PXM method if necessary.
2352 */
cec65193 2353 if (hotplugabble_address_space_size) {
dbb6da8b
IM		 2354 numamem = acpi_data_push(table_data, sizeof *numamem);
2355 build_srat_memory(numamem, machine->device_memory->base,
2356 hotplugabble_address_space_size, pcms->numa_nodes - 1,
2357 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
cec65193
IM		 2358 }
2359
72c194f7
MT		 2360 build_header(linker, table_data,
2361 (void *)(table_data->data + srat_start),
821e3227 2362 "SRAT",
37ad223c 2363 table_data->len - srat_start, 1, NULL, NULL);
72c194f7
MT		 2364}
2365
d46114f9
PX		 2366/*
2367 * VT-d spec 8.1 DMA Remapping Reporting Structure
2368 * (version Oct. 2014 or later)
2369 */
d4eb9119 2370static void
0e9b9eda 2371build_dmar_q35(GArray *table_data, BIOSLinker *linker)
d4eb9119
LT		 2372{
2373 int dmar_start = table_data->len;
2374
2375 AcpiTableDmar *dmar;
2376 AcpiDmarHardwareUnit *drhd;
bd2baacc 2377 AcpiDmarRootPortATS *atsr;
d46114f9
PX		 2378 uint8_t dmar_flags = 0;
2379 X86IOMMUState *iommu = x86_iommu_get_default();
cfc13df4
PX		 2380 AcpiDmarDeviceScope *scope = NULL;
2381 /* Root complex IOAPIC use one path[0] only */
2382 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
37f51384 2383 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
d46114f9
PX		 2384
2385 assert(iommu);
a924b3d8 2386 if (x86_iommu_ir_supported(iommu)) {
d46114f9
PX		 2387 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2388 }
d4eb9119
LT		 2389
2390 dmar = acpi_data_push(table_data, sizeof(*dmar));
37f51384 2391 dmar->host_address_width = intel_iommu->aw_bits - 1;
d46114f9 2392 dmar->flags = dmar_flags;
d4eb9119
LT		 2393
2394 /* DMAR Remapping Hardware Unit Definition structure */
cfc13df4 2395 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
d4eb9119 2396 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
cfc13df4 2397 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
d4eb9119
LT		 2398 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2399 drhd->pci_segment = cpu_to_le16(0);
2400 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2401
cfc13df4
PX		 2402 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2403 * 8.3.1 (version Oct. 2014 or later). */
2404 scope = &drhd->scope[0];
2405 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2406 scope->length = ioapic_scope_size;
2407 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2408 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
1b39bc1c
PX		 2409 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2410 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
cfc13df4 2411
bd2baacc
JW		 2412 if (iommu->dt_supported) {
2413 atsr = acpi_data_push(table_data, sizeof(*atsr));
2414 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2415 atsr->length = cpu_to_le16(sizeof(*atsr));
2416 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2417 atsr->pci_segment = cpu_to_le16(0);
2418 }
2419
d4eb9119 2420 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
37ad223c 2421 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
d4eb9119 2422}
14cda350
LA		 2423
2424/*
2425 * Windows ACPI Emulated Devices Table
2426 * (Version 1.0 - April 6, 2009)
2427 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2428 *
2429 * Helpful to speedup Windows guests and ignored by others.
2430 */
2431static void
2432build_waet(GArray *table_data, BIOSLinker *linker)
2433{
2434 int waet_start = table_data->len;
2435
2436 /* WAET header */
2437 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2438 /*
2439 * Set "ACPI PM timer good" flag.
2440 *
2441 * Tells Windows guests that our ACPI PM timer is reliable in the
2442 * sense that guest can read it only once to obtain a reliable value.
2443 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2444 */
2445 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
2446
2447 build_header(linker, table_data, (void *)(table_data->data + waet_start),
2448 "WAET", table_data->len - waet_start, 1, NULL, NULL);
2449}
2450
fb9f5926
DK		 2451/*
2452 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2453 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2454 */
c028818d
BS		 2455#define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2456
977aff10
AW		 2457/*
2458 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2459 * necessary for the PCI topology.
2460 */
2461static void
2462insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2463{
2464 GArray *table_data = opaque;
2465 uint32_t entry;
2466
2467 /* "Select" IVHD entry, type 0x2 */
2468 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2469 build_append_int_noprefix(table_data, entry, 4);
2470
2471 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2472 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2473 uint8_t sec = pci_bus_num(sec_bus);
2474 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2475
2476 if (pci_bus_is_express(sec_bus)) {
2477 /*
2478 * Walk the bus if there are subordinates, otherwise use a range
2479 * to cover an entire leaf bus. We could potentially also use a
2480 * range for traversed buses, but we'd need to take care not to
2481 * create both Select and Range entries covering the same device.
2482 * This is easier and potentially more compact.
2483 *
2484 * An example bare metal system seems to use Select entries for
2485 * root ports without a slot (ie. built-ins) and Range entries
2486 * when there is a slot. The same system also only hard-codes
2487 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2488 * making no effort to support nested bridges. We attempt to
2489 * be more thorough here.
2490 */
2491 if (sec == sub) { /* leaf bus */
2492 /* "Start of Range" IVHD entry, type 0x3 */
2493 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2494 build_append_int_noprefix(table_data, entry, 4);
2495 /* "End of Range" IVHD entry, type 0x4 */
2496 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2497 build_append_int_noprefix(table_data, entry, 4);
2498 } else {
2499 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2500 }
2501 } else {
2502 /*
2503 * If the secondary bus is conventional, then we need to create an
2504 * Alias range for everything downstream. The range covers the
2505 * first devfn on the secondary bus to the last devfn on the
2506 * subordinate bus. The alias target depends on legacy versus
2507 * express bridges, just as in pci_device_iommu_address_space().
2508 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2509 */
2510 uint16_t dev_id_a, dev_id_b;
2511
2512 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2513
2514 if (pci_is_express(dev) &&
2515 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2516 dev_id_b = dev_id_a;
2517 } else {
2518 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2519 }
2520
2521 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2522 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2523 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2524
2525 /* "End of Range" IVHD entry, type 0x4 */
2526 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2527 build_append_int_noprefix(table_data, entry, 4);
2528 }
2529 }
2530}
2531
2532/* For all PCI host bridges, walk and insert IVHD entries */
2533static int
2534ivrs_host_bridges(Object *obj, void *opaque)
2535{
2536 GArray *ivhd_blob = opaque;
2537
2538 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2539 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2540
2541 if (bus) {
2542 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob);
2543 }
2544 }
2545
2546 return 0;
2547}
2548
fb9f5926
DK		 2549static void
2550build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2551{
977aff10 2552 int ivhd_table_len = 24;
fb9f5926
DK		 2553 int iommu_start = table_data->len;
2554 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
977aff10 2555 GArray *ivhd_blob = g_array_new(false, true, 1);
fb9f5926
DK		 2556
2557 /* IVRS header */
2558 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2559 /* IVinfo - IO virtualization information common to all
2560 * IOMMU units in a system
2561 */
2562 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2563 /* reserved */
2564 build_append_int_noprefix(table_data, 0, 8);
2565
2566 /* IVHD definition - type 10h */
2567 build_append_int_noprefix(table_data, 0x10, 1);
2568 /* virtualization flags */
2569 build_append_int_noprefix(table_data,
2570 (1UL << 0) | /* HtTunEn */
2571 (1UL << 4) | /* iotblSup */
2572 (1UL << 6) | /* PrefSup */
2573 (1UL << 7), /* PPRSup */
2574 1);
c028818d 2575
977aff10
AW		 2576 /*
2577 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2578 * complete set of IVHD entries. Do this into a separate blob so that we
2579 * can calculate the total IVRS table length here and then append the new
2580 * blob further below. Fall back to an entry covering all devices, which
2581 * is sufficient when no aliases are present.
2582 */
2583 object_child_foreach_recursive(object_get_root(),
2584 ivrs_host_bridges, ivhd_blob);
2585
2586 if (!ivhd_blob->len) {
2587 /*
2588 * Type 1 device entry reporting all devices
2589 * These are 4-byte device entries currently reporting the range of
2590 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2591 */
2592 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2593 }
2594
2595 ivhd_table_len += ivhd_blob->len;
2596
c028818d
BS		 2597 /*
2598 * When interrupt remapping is supported, we add a special IVHD device
2599 * for type IO-APIC.
2600 */
a924b3d8 2601 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
c028818d
BS		 2602 ivhd_table_len += 8;
2603 }
977aff10 2604
fb9f5926 2605 /* IVHD length */
c028818d 2606 build_append_int_noprefix(table_data, ivhd_table_len, 2);
fb9f5926
DK		 2607 /* DeviceID */
2608 build_append_int_noprefix(table_data, s->devid, 2);
2609 /* Capability offset */
2610 build_append_int_noprefix(table_data, s->capab_offset, 2);
2611 /* IOMMU base address */
2612 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2613 /* PCI Segment Group */
2614 build_append_int_noprefix(table_data, 0, 2);
2615 /* IOMMU info */
2616 build_append_int_noprefix(table_data, 0, 2);
2617 /* IOMMU Feature Reporting */
2618 build_append_int_noprefix(table_data,
2619 (48UL << 30) | /* HATS */
2620 (48UL << 28) | /* GATS */
12499b23
BS		 2621 (1UL << 2) | /* GTSup */
2622 (1UL << 6), /* GASup */
fb9f5926 2623 4);
977aff10
AW		 2624
2625 /* IVHD entries as found above */
2626 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2627 g_array_free(ivhd_blob, TRUE);
fb9f5926 2628
c028818d
BS		 2629 /*
2630 * Add a special IVHD device type.
2631 * Refer to spec - Table 95: IVHD device entry type codes
2632 *
2633 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2634 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2635 */
a924b3d8 2636 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
c028818d
BS		 2637 build_append_int_noprefix(table_data,
2638 (0x1ull << 56) | /* type IOAPIC */
2639 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2640 0x48, /* special device */
2641 8);
2642 }
2643
fb9f5926
DK		 2644 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2645 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2646}
d4eb9119 2647
72c194f7
MT		 2648typedef
2649struct AcpiBuildState {
2650 /* Copy of table in RAM (for patching). */
339240b5 2651 MemoryRegion *table_mr;
72c194f7
MT		 2652 /* Is table patched? */
2653 uint8_t patched;
d70414a5 2654 void *rsdp;
339240b5
PB		 2655 MemoryRegion *rsdp_mr;
2656 MemoryRegion *linker_mr;
72c194f7
MT		 2657} AcpiBuildState;
2658
2659static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2660{
2661 Object *pci_host;
2662 QObject *o;
72c194f7 2663
ca6c1855 2664 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 2665 g_assert(pci_host);
2666
2667 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2668 if (!o) {
2669 return false;
2670 }
c309434e 2671 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
cb3e7f08 2672 qobject_unref(o);
c309434e 2673 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
fe4970ad
IM		 2674 return false;
2675 }
72c194f7
MT		 2676
2677 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2678 assert(o);
c309434e 2679 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
cb3e7f08 2680 qobject_unref(o);
72c194f7
MT		 2681 return true;
2682}
2683
2684static
3d3ebcad 2685void acpi_build(AcpiBuildTables *tables, MachineState *machine)
72c194f7 2686{
3d3ebcad 2687 PCMachineState *pcms = PC_MACHINE(machine);
bb292f5a 2688 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f0bb276b 2689 X86MachineState *x86ms = X86_MACHINE(machine);
72c194f7 2690 GArray *table_offsets;
41fa5c04 2691 unsigned facs, dsdt, rsdt, fadt;
72c194f7
MT		 2692 AcpiPmInfo pm;
2693 AcpiMiscInfo misc;
2694 AcpiMcfgInfo mcfg;
01c9742d 2695 Range pci_hole, pci_hole64;
72c194f7 2696 uint8_t *u;
07fb6176 2697 size_t aml_len = 0;
7c2c1fa5 2698 GArray *tables_blob = tables->table_data;
ae123749 2699 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
d03637bc 2700 Object *vmgenid_dev;
72c194f7 2701
0e11fc69 2702 acpi_get_pm_info(machine, &pm);
72c194f7 2703 acpi_get_misc_info(&misc);
01c9742d 2704 acpi_get_pci_holes(&pci_hole, &pci_hole64);
ae123749 2705 acpi_get_slic_oem(&slic_oem);
72c194f7
MT		 2706
2707 table_offsets = g_array_new(false, true /* clear */,
2708 sizeof(uint32_t));
8b310fc4 2709 ACPI_BUILD_DPRINTF("init ACPI tables\n");
72c194f7 2710
ad9671b8
IM		 2711 bios_linker_loader_alloc(tables->linker,
2712 ACPI_BUILD_TABLE_FILE, tables_blob,
72c194f7
MT		 2713 64 /* Ensure FACS is aligned */,
2714 false /* high memory */);
2715
2716 /*
2717 * FACS is pointed to by FADT.
2718 * We place it first since it's the only table that has alignment
2719 * requirements.
2720 */
7c2c1fa5 2721 facs = tables_blob->len;
009180bd 2722 build_facs(tables_blob);
72c194f7
MT		 2723
2724 /* DSDT is pointed to by FADT */
7c2c1fa5 2725 dsdt = tables_blob->len;
01c9742d
MA		 2726 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2727 &pci_hole, &pci_hole64, machine);
72c194f7 2728
07fb6176
PB		 2729 /* Count the size of the DSDT and SSDT, we will need it for legacy
2730 * sizing of ACPI tables.
2731 */
7c2c1fa5 2732 aml_len += tables_blob->len - dsdt;
07fb6176 2733
72c194f7 2734 /* ACPI tables pointed to by RSDT */
41fa5c04 2735 fadt = tables_blob->len;
7c2c1fa5 2736 acpi_add_table(table_offsets, tables_blob);
937d1b58
IM		 2737 pm.fadt.facs_tbl_offset = &facs;
2738 pm.fadt.dsdt_tbl_offset = &dsdt;
2739 pm.fadt.xdsdt_tbl_offset = &dsdt;
2740 build_fadt(tables_blob, tables->linker, &pm.fadt,
ae123749 2741 slic_oem.id, slic_oem.table_id);
41fa5c04 2742 aml_len += tables_blob->len - fadt;
72c194f7 2743
7c2c1fa5 2744 acpi_add_table(table_offsets, tables_blob);
907e7c94 2745 build_madt(tables_blob, tables->linker, pcms);
9ac1c4c0 2746
d03637bc
BW		 2747 vmgenid_dev = find_vmgenid_dev();
2748 if (vmgenid_dev) {
2749 acpi_add_table(table_offsets, tables_blob);
2750 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2751 tables->vmgenid, tables->linker);
2752 }
2753
72c194f7 2754 if (misc.has_hpet) {
7c2c1fa5
IM		 2755 acpi_add_table(table_offsets, tables_blob);
2756 build_hpet(tables_blob, tables->linker);
711b20b4 2757 }
5cb18b3d 2758 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
7e7c1b84
SB		 2759 if (misc.tpm_version == TPM_VERSION_1_2) {
2760 acpi_add_table(table_offsets, tables_blob);
2761 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2762 } else { /* TPM_VERSION_2_0 */
72d97b3a 2763 acpi_add_table(table_offsets, tables_blob);
4a42fa0e 2764 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
5cb18b3d 2765 }
72c194f7 2766 }
dd4c2f01 2767 if (pcms->numa_nodes) {
7c2c1fa5 2768 acpi_add_table(table_offsets, tables_blob);
3d3ebcad 2769 build_srat(tables_blob, tables->linker, machine);
118154b7 2770 if (machine->numa_state->have_numa_distance) {
0f203430 2771 acpi_add_table(table_offsets, tables_blob);
aa570207 2772 build_slit(tables_blob, tables->linker, machine);
0f203430 2773 }
e6f123c3
LJ		 2774 if (machine->numa_state->hmat_enabled) {
2775 acpi_add_table(table_offsets, tables_blob);
2776 build_hmat(tables_blob, tables->linker, machine->numa_state);
2777 }
72c194f7
MT		 2778 }
2779 if (acpi_get_mcfg(&mcfg)) {
7c2c1fa5 2780 acpi_add_table(table_offsets, tables_blob);
f13a944c 2781 build_mcfg(tables_blob, tables->linker, &mcfg);
72c194f7 2782 }
fb9f5926
DK		 2783 if (x86_iommu_get_default()) {
2784 IommuType IOMMUType = x86_iommu_get_type();
2785 if (IOMMUType == TYPE_AMD) {
2786 acpi_add_table(table_offsets, tables_blob);
2787 build_amd_iommu(tables_blob, tables->linker);
2788 } else if (IOMMUType == TYPE_INTEL) {
2789 acpi_add_table(table_offsets, tables_blob);
2790 build_dmar_q35(tables_blob, tables->linker);
2791 }
d4eb9119 2792 }
f6a0d06b 2793 if (machine->nvdimms_state->is_enabled) {
ad9671b8 2794 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
f6a0d06b 2795 machine->nvdimms_state, machine->ram_slots);
87252e1b
XG		 2796 }
2797
14cda350
LA		 2798 acpi_add_table(table_offsets, tables_blob);
2799 build_waet(tables_blob, tables->linker);
2800
72c194f7
MT		 2801 /* Add tables supplied by user (if any) */
2802 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2803 unsigned len = acpi_table_len(u);
2804
7c2c1fa5
IM		 2805 acpi_add_table(table_offsets, tables_blob);
2806 g_array_append_vals(tables_blob, u, len);
72c194f7
MT		 2807 }
2808
2809 /* RSDT is pointed to by RSDP */
7c2c1fa5 2810 rsdt = tables_blob->len;
ae123749
LE		 2811 build_rsdt(tables_blob, tables->linker, table_offsets,
2812 slic_oem.id, slic_oem.table_id);
72c194f7
MT		 2813
2814 /* RSDP is in FSEG memory, so allocate it separately */
a46ce1c2
SO		 2815 {
2816 AcpiRsdpData rsdp_data = {
2817 .revision = 0,
2818 .oem_id = ACPI_BUILD_APPNAME6,
2819 .xsdt_tbl_offset = NULL,
2820 .rsdt_tbl_offset = &rsdt,
2821 };
2822 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2823 if (!pcmc->rsdp_in_ram) {
2824 /* We used to allocate some extra space for RSDP revision 2 but
2825 * only used the RSDP revision 0 space. The extra bytes were
2826 * zeroed out and not used.
2827 * Here we continue wasting those extra 16 bytes to make sure we
2828 * don't break migration for machine types 2.2 and older due to
2829 * RSDP blob size mismatch.
2830 */
2831 build_append_int_noprefix(tables->rsdp, 0, 16);
2832 }
2833 }
72c194f7 2834
07fb6176 2835 /* We'll expose it all to Guest so we want to reduce
72c194f7 2836 * chance of size changes.
07fb6176
PB		 2837 *
2838 * We used to align the tables to 4k, but of course this would
2839 * too simple to be enough. 4k turned out to be too small an
2840 * alignment very soon, and in fact it is almost impossible to
2841 * keep the table size stable for all (max_cpus, max_memory_slots)
2842 * combinations. So the table size is always 64k for pc-i440fx-2.1
2843 * and we give an error if the table grows beyond that limit.
2844 *
2845 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2846 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2847 * than 2.0 and we can always pad the smaller tables with zeros. We can
2848 * then use the exact size of the 2.0 tables.
2849 *
2850 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
72c194f7 2851 */
bb292f5a 2852 if (pcmc->legacy_acpi_table_size) {
07fb6176
PB		 2853 /* Subtracting aml_len gives the size of fixed tables. Then add the
2854 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2855 */
2856 int legacy_aml_len =
bb292f5a 2857 pcmc->legacy_acpi_table_size +
f0bb276b 2858 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
07fb6176 2859 int legacy_table_size =
7c2c1fa5 2860 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
07fb6176 2861 ACPI_BUILD_ALIGN_SIZE);
7c2c1fa5 2862 if (tables_blob->len > legacy_table_size) {
07fb6176 2863 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
9e5d2c52
AF		 2864 warn_report("ACPI table size %u exceeds %d bytes,"
2865 " migration may not work",
2866 tables_blob->len, legacy_table_size);
2867 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2868 " or PCI bridges.");
07fb6176 2869 }
7c2c1fa5 2870 g_array_set_size(tables_blob, legacy_table_size);
07fb6176 2871 } else {
868270f2 2872 /* Make sure we have a buffer in case we need to resize the tables. */
7c2c1fa5 2873 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
18045fb9 2874 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
9e5d2c52
AF		 2875 warn_report("ACPI table size %u exceeds %d bytes,"
2876 " migration may not work",
2877 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2878 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2879 " or PCI bridges.");
18045fb9 2880 }
7c2c1fa5 2881 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
07fb6176 2882 }
72c194f7 2883
0e9b9eda 2884 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
72c194f7
MT		 2885
2886 /* Cleanup memory that's no longer used. */
2887 g_array_free(table_offsets, true);
2888}
2889
339240b5 2890static void acpi_ram_update(MemoryRegion *mr, GArray *data)
42d85900
MT		 2891{
2892 uint32_t size = acpi_data_len(data);
2893
2894 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
339240b5 2895 memory_region_ram_resize(mr, size, &error_abort);
42d85900 2896
339240b5
PB		 2897 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2898 memory_region_set_dirty(mr, 0, size);
42d85900
MT		 2899}
2900
3f8752b4 2901static void acpi_build_update(void *build_opaque)
72c194f7
MT		 2902{
2903 AcpiBuildState *build_state = build_opaque;
2904 AcpiBuildTables tables;
2905
2906 /* No state to update or already patched? Nothing to do. */
2907 if (!build_state || build_state->patched) {
2908 return;
2909 }
2910 build_state->patched = 1;
2911
2912 acpi_build_tables_init(&tables);
2913
3d3ebcad 2914 acpi_build(&tables, MACHINE(qdev_get_machine()));
72c194f7 2915
339240b5 2916 acpi_ram_update(build_state->table_mr, tables.table_data);
a1666142 2917
42d85900
MT		 2918 if (build_state->rsdp) {
2919 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2920 } else {
339240b5 2921 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
42d85900 2922 }
ad5b88b1 2923
0e9b9eda 2924 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
72c194f7
MT		 2925 acpi_build_tables_cleanup(&tables, true);
2926}
2927
2928static void acpi_build_reset(void *build_opaque)
2929{
2930 AcpiBuildState *build_state = build_opaque;
2931 build_state->patched = 0;
2932}
2933
72c194f7
MT		 2934static const VMStateDescription vmstate_acpi_build = {
2935 .name = "acpi_build",
2936 .version_id = 1,
2937 .minimum_version_id = 1,
d49805ae 2938 .fields = (VMStateField[]) {
72c194f7
MT		 2939 VMSTATE_UINT8(patched, AcpiBuildState),
2940 VMSTATE_END_OF_LIST()
2941 },
2942};
2943
fb306ffe 2944void acpi_setup(void)
72c194f7 2945{
fb306ffe 2946 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
bb292f5a 2947 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f0bb276b 2948 X86MachineState *x86ms = X86_MACHINE(pcms);
72c194f7
MT		 2949 AcpiBuildTables tables;
2950 AcpiBuildState *build_state;
d03637bc 2951 Object *vmgenid_dev;
0fe24669
SB		 2952 TPMIf *tpm;
2953 static FwCfgTPMConfig tpm_config;
72c194f7 2954
f0bb276b 2955 if (!x86ms->fw_cfg) {
8b310fc4 2956 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
72c194f7
MT		 2957 return;
2958 }
2959
021746c1 2960 if (!pcms->acpi_build_enabled) {
8b310fc4 2961 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
72c194f7
MT		 2962 return;
2963 }
2964
17e89077 2965 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
8b310fc4 2966 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
81adc513
MT		 2967 return;
2968 }
2969
72c194f7
MT		 2970 build_state = g_malloc0(sizeof *build_state);
2971
72c194f7 2972 acpi_build_tables_init(&tables);
3d3ebcad 2973 acpi_build(&tables, MACHINE(pcms));
72c194f7
MT		 2974
2975 /* Now expose it all to Guest */
82f76c67
WY		 2976 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2977 build_state, tables.table_data,
2978 ACPI_BUILD_TABLE_FILE,
2979 ACPI_BUILD_TABLE_MAX_SIZE);
339240b5 2980 assert(build_state->table_mr != NULL);
72c194f7 2981
339240b5 2982 build_state->linker_mr =
82f76c67 2983 acpi_add_rom_blob(acpi_build_update, build_state,
bac78f9c 2984 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0);
72c194f7 2985
f0bb276b 2986 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
42a5b308
SB		 2987 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2988
0fe24669
SB		 2989 tpm = tpm_find();
2990 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2991 tpm_config = (FwCfgTPMConfig) {
2992 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2993 .tpm_version = tpm_get_version(tpm),
ac6dd31e 2994 .tpmppi_version = TPM_PPI_VERSION_1_30
0fe24669 2995 };
f0bb276b 2996 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
0fe24669
SB		 2997 &tpm_config, sizeof tpm_config);
2998 }
2999
d03637bc
BW		 3000 vmgenid_dev = find_vmgenid_dev();
3001 if (vmgenid_dev) {
f0bb276b 3002 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
d03637bc
BW		 3003 tables.vmgenid);
3004 }
3005
bb292f5a 3006 if (!pcmc->rsdp_in_ram) {
358774d7
IM		 3007 /*
3008 * Keep for compatibility with old machine types.
3009 * Though RSDP is small, its contents isn't immutable, so
afaa2e4b 3010 * we'll update it along with the rest of tables on guest access.
358774d7 3011 */
afaa2e4b
MT		 3012 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
3013
3014 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
f0bb276b 3015 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
5f9252f7 3016 acpi_build_update, NULL, build_state,
baf2d5bf 3017 build_state->rsdp, rsdp_size, true);
339240b5 3018 build_state->rsdp_mr = NULL;
358774d7 3019 } else {
42d85900 3020 build_state->rsdp = NULL;
82f76c67
WY		 3021 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
3022 build_state, tables.rsdp,
3023 ACPI_BUILD_RSDP_FILE, 0);
358774d7 3024 }
72c194f7
MT		 3025
3026 qemu_register_reset(acpi_build_reset, build_state);
3027 acpi_build_reset(build_state);
3028 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
3029
3030 /* Cleanup tables but don't free the memory: we track it
3031 * in build_state.
3032 */
3033 acpi_build_tables_cleanup(&tables, false);
3034}
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