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72c194f7 MT |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
4 | * Copyright (C) 2006 Fabrice Bellard | |
5 | * Copyright (C) 2013 Red Hat Inc | |
6 | * | |
7 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | ||
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | ||
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
b6a0aa05 | 23 | #include "qemu/osdep.h" |
da34e65c | 24 | #include "qapi/error.h" |
15280c36 | 25 | #include "qapi/qmp/qnum.h" |
72c194f7 | 26 | #include "acpi-build.h" |
eb66ffab | 27 | #include "acpi-common.h" |
72c194f7 | 28 | #include "qemu/bitmap.h" |
07fb6176 | 29 | #include "qemu/error-report.h" |
72c194f7 | 30 | #include "hw/pci/pci.h" |
2e5b09fd | 31 | #include "hw/core/cpu.h" |
fcf5ef2a | 32 | #include "target/i386/cpu.h" |
0d5d8a3a | 33 | #include "hw/misc/pvpanic.h" |
72c194f7 | 34 | #include "hw/timer/hpet.h" |
395e5fb4 | 35 | #include "hw/acpi/acpi-defs.h" |
72c194f7 | 36 | #include "hw/acpi/acpi.h" |
679dd1a9 | 37 | #include "hw/acpi/cpu.h" |
72c194f7 | 38 | #include "hw/nvram/fw_cfg.h" |
0058ae1d | 39 | #include "hw/acpi/bios-linker-loader.h" |
15bce1b7 | 40 | #include "hw/isa/isa.h" |
27b9fc54 | 41 | #include "hw/block/fdc.h" |
bef3492d | 42 | #include "hw/acpi/memory_hotplug.h" |
711b20b4 SB |
43 | #include "sysemu/tpm.h" |
44 | #include "hw/acpi/tpm.h" | |
d03637bc | 45 | #include "hw/acpi/vmgenid.h" |
0e11fc69 | 46 | #include "hw/boards.h" |
5cb18b3d | 47 | #include "sysemu/tpm_backend.h" |
bcdb9064 | 48 | #include "hw/rtc/mc146818rtc_regs.h" |
d6454270 | 49 | #include "migration/vmstate.h" |
2cc0e2e8 | 50 | #include "hw/mem/memory-device.h" |
4b997690 | 51 | #include "hw/mem/nvdimm.h" |
1f3aba37 | 52 | #include "sysemu/numa.h" |
71e8a915 | 53 | #include "sysemu/reset.h" |
6775d15d | 54 | #include "hw/hyperv/vmbus-bridge.h" |
72c194f7 MT |
55 | |
56 | /* Supported chipsets: */ | |
fff123b8 | 57 | #include "hw/southbridge/piix.h" |
99fd437d | 58 | #include "hw/acpi/pcihp.h" |
89a289c7 | 59 | #include "hw/i386/fw_cfg.h" |
72c194f7 MT |
60 | #include "hw/i386/ich9.h" |
61 | #include "hw/pci/pci_bus.h" | |
62 | #include "hw/pci-host/q35.h" | |
1cf5fd57 | 63 | #include "hw/i386/x86-iommu.h" |
72c194f7 | 64 | |
19934e0e | 65 | #include "hw/acpi/aml-build.h" |
82f76c67 | 66 | #include "hw/acpi/utils.h" |
48cefd94 | 67 | #include "hw/acpi/pci.h" |
19934e0e | 68 | |
72c194f7 | 69 | #include "qom/qom-qobject.h" |
fb9f5926 DK |
70 | #include "hw/i386/amd_iommu.h" |
71 | #include "hw/i386/intel_iommu.h" | |
72c194f7 | 72 | |
86e91dd7 | 73 | #include "hw/acpi/ipmi.h" |
e6f123c3 | 74 | #include "hw/acpi/hmat.h" |
86e91dd7 | 75 | |
07fb6176 PB |
76 | /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and |
77 | * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows | |
78 | * a little bit, there should be plenty of free space since the DSDT | |
79 | * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. | |
80 | */ | |
81 | #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 | |
82 | #define ACPI_BUILD_ALIGN_SIZE 0x1000 | |
83 | ||
868270f2 | 84 | #define ACPI_BUILD_TABLE_SIZE 0x20000 |
18045fb9 | 85 | |
8b310fc4 GA |
86 | /* #define DEBUG_ACPI_BUILD */ |
87 | #ifdef DEBUG_ACPI_BUILD | |
88 | #define ACPI_BUILD_DPRINTF(fmt, ...) \ | |
89 | do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) | |
90 | #else | |
91 | #define ACPI_BUILD_DPRINTF(fmt, ...) | |
92 | #endif | |
93 | ||
72c194f7 MT |
94 | typedef struct AcpiPmInfo { |
95 | bool s3_disabled; | |
96 | bool s4_disabled; | |
133a2da4 | 97 | bool pcihp_bridge_en; |
6d837f1f | 98 | bool smi_on_cpuhp; |
892aae74 | 99 | bool smi_on_cpu_unplug; |
df4008c9 | 100 | bool pcihp_root_en; |
72c194f7 | 101 | uint8_t s4_val; |
937d1b58 | 102 | AcpiFadtData fadt; |
ddf1ec2f | 103 | uint16_t cpu_hp_io_base; |
500b11ea IM |
104 | uint16_t pcihp_io_base; |
105 | uint16_t pcihp_io_len; | |
72c194f7 MT |
106 | } AcpiPmInfo; |
107 | ||
108 | typedef struct AcpiMiscInfo { | |
e4db2798 | 109 | bool is_piix4; |
72c194f7 | 110 | bool has_hpet; |
5cb18b3d | 111 | TPMVersion tpm_version; |
72c194f7 MT |
112 | const unsigned char *dsdt_code; |
113 | unsigned dsdt_size; | |
114 | uint16_t pvpanic_port; | |
8ac6f7a6 | 115 | uint16_t applesmc_io_base; |
72c194f7 MT |
116 | } AcpiMiscInfo; |
117 | ||
99fd437d MT |
118 | typedef struct AcpiBuildPciBusHotplugState { |
119 | GArray *device_table; | |
120 | GArray *notify_table; | |
121 | struct AcpiBuildPciBusHotplugState *parent; | |
133a2da4 | 122 | bool pcihp_bridge_en; |
99fd437d MT |
123 | } AcpiBuildPciBusHotplugState; |
124 | ||
0fe24669 SB |
125 | typedef struct FwCfgTPMConfig { |
126 | uint32_t tpmppi_address; | |
127 | uint8_t tpm_version; | |
128 | uint8_t tpmppi_version; | |
129 | } QEMU_PACKED FwCfgTPMConfig; | |
130 | ||
4a441836 GH |
131 | static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); |
132 | ||
5c94b826 KL |
133 | const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { |
134 | .space_id = AML_AS_SYSTEM_IO, | |
135 | .address = NVDIMM_ACPI_IO_BASE, | |
136 | .bit_width = NVDIMM_ACPI_IO_LEN << 3 | |
137 | }; | |
138 | ||
0e11fc69 LX |
139 | static void init_common_fadt_data(MachineState *ms, Object *o, |
140 | AcpiFadtData *data) | |
937d1b58 IM |
141 | { |
142 | uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); | |
143 | AmlAddressSpace as = AML_AS_SYSTEM_IO; | |
144 | AcpiFadtData fadt = { | |
145 | .rev = 3, | |
146 | .flags = | |
147 | (1 << ACPI_FADT_F_WBINVD) | | |
148 | (1 << ACPI_FADT_F_PROC_C1) | | |
149 | (1 << ACPI_FADT_F_SLP_BUTTON) | | |
150 | (1 << ACPI_FADT_F_RTC_S4) | | |
151 | (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | | |
152 | /* APIC destination mode ("Flat Logical") has an upper limit of 8 | |
153 | * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be | |
154 | * used | |
155 | */ | |
0e11fc69 LX |
156 | ((ms->smp.max_cpus > 8) ? |
157 | (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), | |
937d1b58 IM |
158 | .int_model = 1 /* Multiple APIC */, |
159 | .rtc_century = RTC_CENTURY, | |
160 | .plvl2_lat = 0xfff /* C2 state not supported */, | |
161 | .plvl3_lat = 0xfff /* C3 state not supported */, | |
162 | .smi_cmd = ACPI_PORT_SMI_CMD, | |
163 | .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), | |
164 | .acpi_enable_cmd = | |
165 | object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL), | |
166 | .acpi_disable_cmd = | |
167 | object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL), | |
168 | .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, | |
169 | .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, | |
170 | .address = io + 0x04 }, | |
171 | .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, | |
172 | .gpe0_blk = { .space_id = as, .bit_width = | |
173 | object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, | |
174 | .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) | |
175 | }, | |
176 | }; | |
177 | *data = fadt; | |
178 | } | |
179 | ||
81c48dd7 PMD |
180 | static Object *object_resolve_type_unambiguous(const char *typename) |
181 | { | |
182 | bool ambig; | |
183 | Object *o = object_resolve_path_type("", typename, &ambig); | |
184 | ||
185 | if (ambig || !o) { | |
186 | return NULL; | |
187 | } | |
188 | return o; | |
189 | } | |
190 | ||
0e11fc69 | 191 | static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) |
72c194f7 | 192 | { |
81c48dd7 PMD |
193 | Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); |
194 | Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); | |
697155cd | 195 | Object *obj = piix ? piix : lpc; |
72c194f7 | 196 | QObject *o; |
94aaca64 | 197 | pm->cpu_hp_io_base = 0; |
500b11ea IM |
198 | pm->pcihp_io_base = 0; |
199 | pm->pcihp_io_len = 0; | |
6d837f1f | 200 | pm->smi_on_cpuhp = false; |
892aae74 | 201 | pm->smi_on_cpu_unplug = false; |
937d1b58 | 202 | |
6fa5171f | 203 | assert(obj); |
a0628599 | 204 | init_common_fadt_data(machine, obj, &pm->fadt); |
72c194f7 | 205 | if (piix) { |
3a3fcc75 | 206 | /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ |
937d1b58 | 207 | pm->fadt.rev = 1; |
ddf1ec2f | 208 | pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; |
500b11ea | 209 | pm->pcihp_io_base = |
35f91e50 | 210 | object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); |
500b11ea | 211 | pm->pcihp_io_len = |
35f91e50 | 212 | object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); |
72c194f7 MT |
213 | } |
214 | if (lpc) { | |
6d837f1f IM |
215 | uint64_t smi_features = object_property_get_uint(lpc, |
216 | ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); | |
937d1b58 IM |
217 | struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, |
218 | .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; | |
219 | pm->fadt.reset_reg = r; | |
220 | pm->fadt.reset_val = 0xf; | |
221 | pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; | |
ddf1ec2f | 222 | pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; |
6d837f1f IM |
223 | pm->smi_on_cpuhp = |
224 | !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); | |
892aae74 IM |
225 | pm->smi_on_cpu_unplug = |
226 | !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); | |
72c194f7 | 227 | } |
72c194f7 | 228 | |
937d1b58 IM |
229 | /* The above need not be conditional on machine type because the reset port |
230 | * happens to be the same on PIIX (pc) and ICH9 (q35). */ | |
0063454a | 231 | QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); |
937d1b58 | 232 | |
72c194f7 MT |
233 | /* Fill in optional s3/s4 related properties */ |
234 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); | |
235 | if (o) { | |
7dc847eb | 236 | pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); |
72c194f7 MT |
237 | } else { |
238 | pm->s3_disabled = false; | |
239 | } | |
cb3e7f08 | 240 | qobject_unref(o); |
72c194f7 MT |
241 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); |
242 | if (o) { | |
7dc847eb | 243 | pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); |
72c194f7 MT |
244 | } else { |
245 | pm->s4_disabled = false; | |
246 | } | |
cb3e7f08 | 247 | qobject_unref(o); |
72c194f7 MT |
248 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); |
249 | if (o) { | |
7dc847eb | 250 | pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); |
72c194f7 MT |
251 | } else { |
252 | pm->s4_val = false; | |
253 | } | |
cb3e7f08 | 254 | qobject_unref(o); |
72c194f7 | 255 | |
133a2da4 IM |
256 | pm->pcihp_bridge_en = |
257 | object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", | |
258 | NULL); | |
df4008c9 AS |
259 | pm->pcihp_root_en = |
260 | object_property_get_bool(obj, "acpi-root-pci-hotplug", | |
261 | NULL); | |
72c194f7 MT |
262 | } |
263 | ||
72c194f7 MT |
264 | static void acpi_get_misc_info(AcpiMiscInfo *info) |
265 | { | |
81c48dd7 PMD |
266 | Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); |
267 | Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); | |
3db119da IM |
268 | assert(!!piix != !!lpc); |
269 | ||
270 | if (piix) { | |
271 | info->is_piix4 = true; | |
272 | } | |
273 | if (lpc) { | |
274 | info->is_piix4 = false; | |
275 | } | |
276 | ||
72c194f7 | 277 | info->has_hpet = hpet_find(); |
3dfd5a2a | 278 | info->tpm_version = tpm_get_version(tpm_find()); |
72c194f7 | 279 | info->pvpanic_port = pvpanic_port(); |
8ac6f7a6 | 280 | info->applesmc_io_base = applesmc_port(); |
72c194f7 MT |
281 | } |
282 | ||
ca6c1855 MA |
283 | /* |
284 | * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. | |
285 | * On i386 arch we only have two pci hosts, so we can look only for them. | |
286 | */ | |
287 | static Object *acpi_get_i386_pci_host(void) | |
288 | { | |
289 | PCIHostState *host; | |
290 | ||
291 | host = OBJECT_CHECK(PCIHostState, | |
292 | object_resolve_path("/machine/i440fx", NULL), | |
293 | TYPE_PCI_HOST_BRIDGE); | |
294 | if (!host) { | |
295 | host = OBJECT_CHECK(PCIHostState, | |
296 | object_resolve_path("/machine/q35", NULL), | |
297 | TYPE_PCI_HOST_BRIDGE); | |
298 | } | |
299 | ||
300 | return OBJECT(host); | |
301 | } | |
302 | ||
01c9742d | 303 | static void acpi_get_pci_holes(Range *hole, Range *hole64) |
72c194f7 MT |
304 | { |
305 | Object *pci_host; | |
72c194f7 | 306 | |
ca6c1855 | 307 | pci_host = acpi_get_i386_pci_host(); |
72c194f7 MT |
308 | g_assert(pci_host); |
309 | ||
a0efbf16 | 310 | range_set_bounds1(hole, |
60555365 MAL |
311 | object_property_get_uint(pci_host, |
312 | PCI_HOST_PROP_PCI_HOLE_START, | |
313 | NULL), | |
314 | object_property_get_uint(pci_host, | |
315 | PCI_HOST_PROP_PCI_HOLE_END, | |
316 | NULL)); | |
a0efbf16 | 317 | range_set_bounds1(hole64, |
60555365 MAL |
318 | object_property_get_uint(pci_host, |
319 | PCI_HOST_PROP_PCI_HOLE64_START, | |
320 | NULL), | |
321 | object_property_get_uint(pci_host, | |
322 | PCI_HOST_PROP_PCI_HOLE64_END, | |
323 | NULL)); | |
72c194f7 MT |
324 | } |
325 | ||
72c194f7 MT |
326 | static void acpi_align_size(GArray *blob, unsigned align) |
327 | { | |
328 | /* Align size to multiple of given size. This reduces the chance | |
329 | * we need to change size in the future (breaking cross version migration). | |
330 | */ | |
134d42d6 | 331 | g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); |
72c194f7 MT |
332 | } |
333 | ||
72c194f7 MT |
334 | /* FACS */ |
335 | static void | |
009180bd | 336 | build_facs(GArray *table_data) |
72c194f7 MT |
337 | { |
338 | AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); | |
821e3227 | 339 | memcpy(&facs->signature, "FACS", 4); |
72c194f7 MT |
340 | facs->length = cpu_to_le32(sizeof(*facs)); |
341 | } | |
342 | ||
62b52c26 | 343 | static void build_append_pcihp_notify_entry(Aml *method, int slot) |
99fd437d | 344 | { |
62b52c26 IM |
345 | Aml *if_ctx; |
346 | int32_t devfn = PCI_DEVFN(slot, 0); | |
347 | ||
5530427f | 348 | if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); |
62b52c26 IM |
349 | aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); |
350 | aml_append(method, if_ctx); | |
99fd437d MT |
351 | } |
352 | ||
62b52c26 | 353 | static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, |
b23046ab | 354 | bool pcihp_bridge_en) |
99fd437d | 355 | { |
7dc847eb | 356 | Aml *dev, *notify_method = NULL, *method; |
99fd437d | 357 | QObject *bsel; |
b23046ab IM |
358 | PCIBus *sec; |
359 | int i; | |
133a2da4 | 360 | |
99fd437d MT |
361 | bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); |
362 | if (bsel) { | |
7dc847eb | 363 | uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); |
62b52c26 IM |
364 | |
365 | aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); | |
4dbfc881 | 366 | notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); |
8dcf525a | 367 | } |
99fd437d | 368 | |
8dcf525a MT |
369 | for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { |
370 | DeviceClass *dc; | |
371 | PCIDeviceClass *pc; | |
372 | PCIDevice *pdev = bus->devices[i]; | |
373 | int slot = PCI_SLOT(i); | |
b23046ab | 374 | bool hotplug_enabled_dev; |
093a35e5 | 375 | bool bridge_in_acpi; |
15a5b254 | 376 | bool cold_plugged_bridge; |
99fd437d | 377 | |
8dcf525a | 378 | if (!pdev) { |
b23046ab | 379 | if (bsel) { /* add hotplug slots for non present devices */ |
62b52c26 IM |
380 | dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); |
381 | aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); | |
382 | aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); | |
4dbfc881 | 383 | method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); |
62b52c26 IM |
384 | aml_append(method, |
385 | aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) | |
386 | ); | |
387 | aml_append(dev, method); | |
388 | aml_append(parent_scope, dev); | |
389 | ||
390 | build_append_pcihp_notify_entry(notify_method, slot); | |
b23046ab | 391 | } |
8dcf525a MT |
392 | continue; |
393 | } | |
99fd437d | 394 | |
8dcf525a MT |
395 | pc = PCI_DEVICE_GET_CLASS(pdev); |
396 | dc = DEVICE_GET_CLASS(pdev); | |
99fd437d | 397 | |
15a5b254 AS |
398 | /* |
399 | * Cold plugged bridges aren't themselves hot-pluggable. | |
a20275fa | 400 | * Hotplugged bridges *are* hot-pluggable. |
093a35e5 | 401 | */ |
15a5b254 AS |
402 | cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; |
403 | bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; | |
b23046ab | 404 | |
15a5b254 | 405 | hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; |
093a35e5 | 406 | |
b23046ab IM |
407 | if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { |
408 | continue; | |
99fd437d MT |
409 | } |
410 | ||
62b52c26 IM |
411 | /* start to compose PCI slot descriptor */ |
412 | dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); | |
413 | aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); | |
414 | ||
8dcf525a | 415 | if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { |
62b52c26 IM |
416 | /* add VGA specific AML methods */ |
417 | int s3d; | |
418 | ||
8dcf525a | 419 | if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { |
62b52c26 | 420 | s3d = 3; |
b23046ab | 421 | } else { |
62b52c26 | 422 | s3d = 0; |
99fd437d | 423 | } |
62b52c26 | 424 | |
4dbfc881 | 425 | method = aml_method("_S1D", 0, AML_NOTSERIALIZED); |
62b52c26 IM |
426 | aml_append(method, aml_return(aml_int(0))); |
427 | aml_append(dev, method); | |
428 | ||
4dbfc881 | 429 | method = aml_method("_S2D", 0, AML_NOTSERIALIZED); |
62b52c26 IM |
430 | aml_append(method, aml_return(aml_int(0))); |
431 | aml_append(dev, method); | |
432 | ||
4dbfc881 | 433 | method = aml_method("_S3D", 0, AML_NOTSERIALIZED); |
62b52c26 IM |
434 | aml_append(method, aml_return(aml_int(s3d))); |
435 | aml_append(dev, method); | |
b23046ab | 436 | } else if (hotplug_enabled_dev) { |
62b52c26 IM |
437 | /* add _SUN/_EJ0 to make slot hotpluggable */ |
438 | aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); | |
99fd437d | 439 | |
4dbfc881 | 440 | method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); |
62b52c26 IM |
441 | aml_append(method, |
442 | aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) | |
443 | ); | |
444 | aml_append(dev, method); | |
445 | ||
446 | if (bsel) { | |
447 | build_append_pcihp_notify_entry(notify_method, slot); | |
448 | } | |
b23046ab | 449 | } else if (bridge_in_acpi) { |
62b52c26 IM |
450 | /* |
451 | * device is coldplugged bridge, | |
452 | * add child device descriptions into its scope | |
453 | */ | |
b23046ab | 454 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); |
b23046ab | 455 | |
62b52c26 | 456 | build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); |
8dcf525a | 457 | } |
62b52c26 IM |
458 | /* slot descriptor has been composed, add it into parent context */ |
459 | aml_append(parent_scope, dev); | |
8dcf525a MT |
460 | } |
461 | ||
462 | if (bsel) { | |
62b52c26 | 463 | aml_append(parent_scope, notify_method); |
99fd437d MT |
464 | } |
465 | ||
466 | /* Append PCNT method to notify about events on local and child buses. | |
df4008c9 AS |
467 | * Add this method for root bus only when hotplug is enabled since DSDT |
468 | * expects it. | |
72c194f7 | 469 | */ |
df4008c9 AS |
470 | if (bsel || pcihp_bridge_en) { |
471 | method = aml_method("PCNT", 0, AML_NOTSERIALIZED); | |
01b2ffce | 472 | |
811c74fb PMD |
473 | /* If bus supports hotplug select it and notify about local events */ |
474 | if (bsel) { | |
475 | uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); | |
476 | ||
477 | aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); | |
478 | aml_append(method, aml_call2("DVNT", aml_name("PCIU"), | |
479 | aml_int(1))); /* Device Check */ | |
480 | aml_append(method, aml_call2("DVNT", aml_name("PCID"), | |
481 | aml_int(3))); /* Eject Request */ | |
482 | } | |
99fd437d | 483 | |
811c74fb PMD |
484 | /* Notify about child bus events in any case */ |
485 | if (pcihp_bridge_en) { | |
486 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
487 | int32_t devfn = sec->parent_dev->devfn; | |
62b52c26 | 488 | |
811c74fb PMD |
489 | if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { |
490 | continue; | |
491 | } | |
c99cb18e | 492 | |
811c74fb PMD |
493 | aml_append(method, aml_name("^S%.02X.PCNT", devfn)); |
494 | } | |
99fd437d | 495 | } |
df4008c9 | 496 | |
df4008c9 AS |
497 | aml_append(parent_scope, method); |
498 | } | |
cb3e7f08 | 499 | qobject_unref(bsel); |
72c194f7 MT |
500 | } |
501 | ||
196e2137 IM |
502 | /** |
503 | * build_prt_entry: | |
504 | * @link_name: link name for PCI route entry | |
505 | * | |
506 | * build AML package containing a PCI route entry for @link_name | |
507 | */ | |
508 | static Aml *build_prt_entry(const char *link_name) | |
509 | { | |
510 | Aml *a_zero = aml_int(0); | |
511 | Aml *pkg = aml_package(4); | |
512 | aml_append(pkg, a_zero); | |
513 | aml_append(pkg, a_zero); | |
514 | aml_append(pkg, aml_name("%s", link_name)); | |
515 | aml_append(pkg, a_zero); | |
516 | return pkg; | |
517 | } | |
518 | ||
0d8935e3 MA |
519 | /* |
520 | * initialize_route - Initialize the interrupt routing rule | |
521 | * through a specific LINK: | |
522 | * if (lnk_idx == idx) | |
523 | * route using link 'link_name' | |
524 | */ | |
525 | static Aml *initialize_route(Aml *route, const char *link_name, | |
526 | Aml *lnk_idx, int idx) | |
527 | { | |
528 | Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); | |
196e2137 | 529 | Aml *pkg = build_prt_entry(link_name); |
0d8935e3 | 530 | |
0d8935e3 MA |
531 | aml_append(if_ctx, aml_store(pkg, route)); |
532 | ||
533 | return if_ctx; | |
534 | } | |
535 | ||
536 | /* | |
537 | * build_prt - Define interrupt rounting rules | |
538 | * | |
539 | * Returns an array of 128 routes, one for each device, | |
540 | * based on device location. | |
541 | * The main goal is to equaly distribute the interrupts | |
542 | * over the 4 existing ACPI links (works only for i440fx). | |
543 | * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". | |
544 | * | |
545 | */ | |
196e2137 | 546 | static Aml *build_prt(bool is_pci0_prt) |
0d8935e3 MA |
547 | { |
548 | Aml *method, *while_ctx, *pin, *res; | |
549 | ||
4dbfc881 | 550 | method = aml_method("_PRT", 0, AML_NOTSERIALIZED); |
0d8935e3 MA |
551 | res = aml_local(0); |
552 | pin = aml_local(1); | |
553 | aml_append(method, aml_store(aml_package(128), res)); | |
554 | aml_append(method, aml_store(aml_int(0), pin)); | |
555 | ||
556 | /* while (pin < 128) */ | |
557 | while_ctx = aml_while(aml_lless(pin, aml_int(128))); | |
558 | { | |
559 | Aml *slot = aml_local(2); | |
560 | Aml *lnk_idx = aml_local(3); | |
561 | Aml *route = aml_local(4); | |
562 | ||
563 | /* slot = pin >> 2 */ | |
564 | aml_append(while_ctx, | |
c360639a | 565 | aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); |
0d8935e3 MA |
566 | /* lnk_idx = (slot + pin) & 3 */ |
567 | aml_append(while_ctx, | |
5530427f IM |
568 | aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), |
569 | lnk_idx)); | |
0d8935e3 MA |
570 | |
571 | /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ | |
572 | aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); | |
196e2137 IM |
573 | if (is_pci0_prt) { |
574 | Aml *if_device_1, *if_pin_4, *else_pin_4; | |
575 | ||
576 | /* device 1 is the power-management device, needs SCI */ | |
577 | if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); | |
578 | { | |
579 | if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); | |
580 | { | |
581 | aml_append(if_pin_4, | |
582 | aml_store(build_prt_entry("LNKS"), route)); | |
583 | } | |
584 | aml_append(if_device_1, if_pin_4); | |
585 | else_pin_4 = aml_else(); | |
586 | { | |
587 | aml_append(else_pin_4, | |
588 | aml_store(build_prt_entry("LNKA"), route)); | |
589 | } | |
590 | aml_append(if_device_1, else_pin_4); | |
591 | } | |
592 | aml_append(while_ctx, if_device_1); | |
593 | } else { | |
594 | aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); | |
595 | } | |
0d8935e3 MA |
596 | aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); |
597 | aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); | |
598 | ||
599 | /* route[0] = 0x[slot]FFFF */ | |
600 | aml_append(while_ctx, | |
ca3df95d IM |
601 | aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), |
602 | NULL), | |
0d8935e3 MA |
603 | aml_index(route, aml_int(0)))); |
604 | /* route[1] = pin & 3 */ | |
605 | aml_append(while_ctx, | |
5530427f IM |
606 | aml_store(aml_and(pin, aml_int(3), NULL), |
607 | aml_index(route, aml_int(1)))); | |
0d8935e3 MA |
608 | /* res[pin] = route */ |
609 | aml_append(while_ctx, aml_store(route, aml_index(res, pin))); | |
610 | /* pin++ */ | |
611 | aml_append(while_ctx, aml_increment(pin)); | |
612 | } | |
613 | aml_append(method, while_ctx); | |
614 | /* return res*/ | |
615 | aml_append(method, aml_return(res)); | |
616 | ||
617 | return method; | |
618 | } | |
619 | ||
a57d708d IM |
620 | static void build_hpet_aml(Aml *table) |
621 | { | |
622 | Aml *crs; | |
623 | Aml *field; | |
624 | Aml *method; | |
625 | Aml *if_ctx; | |
626 | Aml *scope = aml_scope("_SB"); | |
627 | Aml *dev = aml_device("HPET"); | |
628 | Aml *zero = aml_int(0); | |
629 | Aml *id = aml_local(0); | |
630 | Aml *period = aml_local(1); | |
631 | ||
632 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); | |
633 | aml_append(dev, aml_name_decl("_UID", zero)); | |
634 | ||
635 | aml_append(dev, | |
3f3009c0 XG |
636 | aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), |
637 | HPET_LEN)); | |
a57d708d IM |
638 | field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); |
639 | aml_append(field, aml_named_field("VEND", 32)); | |
640 | aml_append(field, aml_named_field("PRD", 32)); | |
641 | aml_append(dev, field); | |
642 | ||
643 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
644 | aml_append(method, aml_store(aml_name("VEND"), id)); | |
645 | aml_append(method, aml_store(aml_name("PRD"), period)); | |
646 | aml_append(method, aml_shiftright(id, aml_int(16), id)); | |
647 | if_ctx = aml_if(aml_lor(aml_equal(id, zero), | |
648 | aml_equal(id, aml_int(0xffff)))); | |
649 | { | |
650 | aml_append(if_ctx, aml_return(zero)); | |
651 | } | |
652 | aml_append(method, if_ctx); | |
653 | ||
654 | if_ctx = aml_if(aml_lor(aml_equal(period, zero), | |
655 | aml_lgreater(period, aml_int(100000000)))); | |
656 | { | |
657 | aml_append(if_ctx, aml_return(zero)); | |
658 | } | |
659 | aml_append(method, if_ctx); | |
660 | ||
661 | aml_append(method, aml_return(aml_int(0x0F))); | |
662 | aml_append(dev, method); | |
663 | ||
664 | crs = aml_resource_template(); | |
665 | aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); | |
666 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
667 | ||
668 | aml_append(scope, dev); | |
669 | aml_append(table, scope); | |
670 | } | |
671 | ||
6775d15d JD |
672 | static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) |
673 | { | |
674 | Aml *dev; | |
675 | Aml *method; | |
676 | Aml *crs; | |
677 | ||
678 | dev = aml_device("VMBS"); | |
679 | aml_append(dev, aml_name_decl("STA", aml_int(0xF))); | |
680 | aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); | |
681 | aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); | |
682 | aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); | |
683 | ||
684 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
685 | aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), | |
686 | aml_name("STA"))); | |
687 | aml_append(dev, method); | |
688 | ||
689 | method = aml_method("_PS0", 0, AML_NOTSERIALIZED); | |
690 | aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), | |
691 | aml_name("STA"))); | |
692 | aml_append(dev, method); | |
693 | ||
694 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
695 | aml_append(method, aml_return(aml_name("STA"))); | |
696 | aml_append(dev, method); | |
697 | ||
698 | aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); | |
699 | ||
700 | crs = aml_resource_template(); | |
8f06f22f | 701 | aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); |
6775d15d JD |
702 | aml_append(dev, aml_name_decl("_CRS", crs)); |
703 | ||
704 | return dev; | |
705 | } | |
706 | ||
ee135849 IM |
707 | static void build_isa_devices_aml(Aml *table) |
708 | { | |
86e91dd7 | 709 | bool ambiguous; |
86e91dd7 | 710 | Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); |
13371f9b | 711 | Aml *scope; |
ee135849 | 712 | |
13371f9b GH |
713 | assert(obj && !ambiguous); |
714 | ||
715 | scope = aml_scope("_SB.PCI0.ISA"); | |
716 | build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); | |
717 | isa_build_aml(ISA_BUS(obj), scope); | |
86e91dd7 | 718 | |
ee135849 IM |
719 | aml_append(table, scope); |
720 | } | |
721 | ||
3892a2b7 IM |
722 | static void build_dbg_aml(Aml *table) |
723 | { | |
724 | Aml *field; | |
725 | Aml *method; | |
726 | Aml *while_ctx; | |
727 | Aml *scope = aml_scope("\\"); | |
728 | Aml *buf = aml_local(0); | |
729 | Aml *len = aml_local(1); | |
730 | Aml *idx = aml_local(2); | |
731 | ||
732 | aml_append(scope, | |
3f3009c0 | 733 | aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); |
3892a2b7 IM |
734 | field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); |
735 | aml_append(field, aml_named_field("DBGB", 8)); | |
736 | aml_append(scope, field); | |
737 | ||
738 | method = aml_method("DBUG", 1, AML_NOTSERIALIZED); | |
739 | ||
740 | aml_append(method, aml_to_hexstring(aml_arg(0), buf)); | |
741 | aml_append(method, aml_to_buffer(buf, buf)); | |
742 | aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); | |
743 | aml_append(method, aml_store(aml_int(0), idx)); | |
744 | ||
745 | while_ctx = aml_while(aml_lless(idx, len)); | |
746 | aml_append(while_ctx, | |
747 | aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); | |
748 | aml_append(while_ctx, aml_increment(idx)); | |
749 | aml_append(method, while_ctx); | |
750 | ||
751 | aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); | |
752 | aml_append(scope, method); | |
753 | ||
754 | aml_append(table, scope); | |
755 | } | |
756 | ||
c35b6e80 IM |
757 | static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) |
758 | { | |
759 | Aml *dev; | |
760 | Aml *crs; | |
761 | Aml *method; | |
762 | uint32_t irqs[] = {5, 10, 11}; | |
763 | ||
764 | dev = aml_device("%s", name); | |
765 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); | |
766 | aml_append(dev, aml_name_decl("_UID", aml_int(uid))); | |
767 | ||
768 | crs = aml_resource_template(); | |
769 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
770 | AML_SHARED, irqs, ARRAY_SIZE(irqs))); | |
771 | aml_append(dev, aml_name_decl("_PRS", crs)); | |
772 | ||
773 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
774 | aml_append(method, aml_return(aml_call1("IQST", reg))); | |
775 | aml_append(dev, method); | |
776 | ||
777 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
778 | aml_append(method, aml_or(reg, aml_int(0x80), reg)); | |
779 | aml_append(dev, method); | |
780 | ||
781 | method = aml_method("_CRS", 0, AML_NOTSERIALIZED); | |
782 | aml_append(method, aml_return(aml_call1("IQCR", reg))); | |
783 | aml_append(dev, method); | |
784 | ||
785 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); | |
786 | aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); | |
787 | aml_append(method, aml_store(aml_name("PRRI"), reg)); | |
788 | aml_append(dev, method); | |
789 | ||
790 | return dev; | |
791 | } | |
792 | ||
80b32df5 IM |
793 | static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) |
794 | { | |
795 | Aml *dev; | |
796 | Aml *crs; | |
797 | Aml *method; | |
798 | uint32_t irqs; | |
799 | ||
800 | dev = aml_device("%s", name); | |
801 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); | |
802 | aml_append(dev, aml_name_decl("_UID", aml_int(uid))); | |
803 | ||
804 | crs = aml_resource_template(); | |
805 | irqs = gsi; | |
806 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
807 | AML_SHARED, &irqs, 1)); | |
808 | aml_append(dev, aml_name_decl("_PRS", crs)); | |
809 | ||
810 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
811 | ||
c82f503d MA |
812 | /* |
813 | * _DIS can be no-op because the interrupt cannot be disabled. | |
814 | */ | |
815 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
816 | aml_append(dev, method); | |
817 | ||
80b32df5 IM |
818 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); |
819 | aml_append(dev, method); | |
820 | ||
821 | return dev; | |
822 | } | |
823 | ||
16682a9d IM |
824 | /* _CRS method - get current settings */ |
825 | static Aml *build_iqcr_method(bool is_piix4) | |
826 | { | |
827 | Aml *if_ctx; | |
828 | uint32_t irqs; | |
829 | Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); | |
830 | Aml *crs = aml_resource_template(); | |
831 | ||
832 | irqs = 0; | |
833 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, | |
834 | AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); | |
835 | aml_append(method, aml_name_decl("PRR0", crs)); | |
836 | ||
837 | aml_append(method, | |
838 | aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); | |
839 | ||
840 | if (is_piix4) { | |
841 | if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); | |
842 | aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); | |
843 | aml_append(method, if_ctx); | |
844 | } else { | |
845 | aml_append(method, | |
846 | aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), | |
847 | aml_name("PRRI"))); | |
848 | } | |
849 | ||
850 | aml_append(method, aml_return(aml_name("PRR0"))); | |
851 | return method; | |
852 | } | |
853 | ||
78e1ad05 IM |
854 | /* _STA method - get status */ |
855 | static Aml *build_irq_status_method(void) | |
856 | { | |
857 | Aml *if_ctx; | |
858 | Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); | |
859 | ||
860 | if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); | |
861 | aml_append(if_ctx, aml_return(aml_int(0x09))); | |
862 | aml_append(method, if_ctx); | |
863 | aml_append(method, aml_return(aml_int(0x0B))); | |
864 | return method; | |
865 | } | |
866 | ||
e4db2798 IM |
867 | static void build_piix4_pci0_int(Aml *table) |
868 | { | |
c35b6e80 IM |
869 | Aml *dev; |
870 | Aml *crs; | |
e4db2798 | 871 | Aml *field; |
c35b6e80 IM |
872 | Aml *method; |
873 | uint32_t irqs; | |
e4db2798 | 874 | Aml *sb_scope = aml_scope("_SB"); |
196e2137 IM |
875 | Aml *pci0_scope = aml_scope("PCI0"); |
876 | ||
877 | aml_append(pci0_scope, build_prt(true)); | |
878 | aml_append(sb_scope, pci0_scope); | |
e4db2798 IM |
879 | |
880 | field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); | |
881 | aml_append(field, aml_named_field("PRQ0", 8)); | |
882 | aml_append(field, aml_named_field("PRQ1", 8)); | |
883 | aml_append(field, aml_named_field("PRQ2", 8)); | |
884 | aml_append(field, aml_named_field("PRQ3", 8)); | |
885 | aml_append(sb_scope, field); | |
886 | ||
78e1ad05 | 887 | aml_append(sb_scope, build_irq_status_method()); |
16682a9d | 888 | aml_append(sb_scope, build_iqcr_method(true)); |
100681cc | 889 | |
c35b6e80 IM |
890 | aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); |
891 | aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); | |
892 | aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); | |
893 | aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); | |
894 | ||
895 | dev = aml_device("LNKS"); | |
896 | { | |
897 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); | |
898 | aml_append(dev, aml_name_decl("_UID", aml_int(4))); | |
899 | ||
900 | crs = aml_resource_template(); | |
901 | irqs = 9; | |
902 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, | |
903 | AML_ACTIVE_HIGH, AML_SHARED, | |
904 | &irqs, 1)); | |
905 | aml_append(dev, aml_name_decl("_PRS", crs)); | |
906 | ||
907 | /* The SCI cannot be disabled and is always attached to GSI 9, | |
908 | * so these are no-ops. We only need this link to override the | |
909 | * polarity to active high and match the content of the MADT. | |
910 | */ | |
911 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
912 | aml_append(method, aml_return(aml_int(0x0b))); | |
913 | aml_append(dev, method); | |
914 | ||
915 | method = aml_method("_DIS", 0, AML_NOTSERIALIZED); | |
916 | aml_append(dev, method); | |
917 | ||
918 | method = aml_method("_CRS", 0, AML_NOTSERIALIZED); | |
919 | aml_append(method, aml_return(aml_name("_PRS"))); | |
920 | aml_append(dev, method); | |
921 | ||
922 | method = aml_method("_SRS", 1, AML_NOTSERIALIZED); | |
923 | aml_append(dev, method); | |
924 | } | |
925 | aml_append(sb_scope, dev); | |
926 | ||
e4db2798 IM |
927 | aml_append(table, sb_scope); |
928 | } | |
929 | ||
22b5b8bf IM |
930 | static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) |
931 | { | |
932 | int i; | |
933 | int head; | |
934 | Aml *pkg; | |
935 | char base = name[3] < 'E' ? 'A' : 'E'; | |
936 | char *s = g_strdup(name); | |
937 | Aml *a_nr = aml_int((nr << 16) | 0xffff); | |
938 | ||
939 | assert(strlen(s) == 4); | |
940 | ||
941 | head = name[3] - base; | |
942 | for (i = 0; i < 4; i++) { | |
943 | if (head + i > 3) { | |
944 | head = i * -1; | |
945 | } | |
946 | s[3] = base + head + i; | |
947 | pkg = aml_package(4); | |
948 | aml_append(pkg, a_nr); | |
949 | aml_append(pkg, aml_int(i)); | |
950 | aml_append(pkg, aml_name("%s", s)); | |
951 | aml_append(pkg, aml_int(0)); | |
952 | aml_append(ctx, pkg); | |
953 | } | |
954 | g_free(s); | |
955 | } | |
956 | ||
957 | static Aml *build_q35_routing_table(const char *str) | |
958 | { | |
959 | int i; | |
960 | Aml *pkg; | |
961 | char *name = g_strdup_printf("%s ", str); | |
962 | ||
963 | pkg = aml_package(128); | |
964 | for (i = 0; i < 0x18; i++) { | |
965 | name[3] = 'E' + (i & 0x3); | |
966 | append_q35_prt_entry(pkg, i, name); | |
967 | } | |
968 | ||
969 | name[3] = 'E'; | |
970 | append_q35_prt_entry(pkg, 0x18, name); | |
971 | ||
972 | /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ | |
973 | for (i = 0x0019; i < 0x1e; i++) { | |
974 | name[3] = 'A'; | |
975 | append_q35_prt_entry(pkg, i, name); | |
976 | } | |
977 | ||
978 | /* PCIe->PCI bridge. use PIRQ[E-H] */ | |
979 | name[3] = 'E'; | |
980 | append_q35_prt_entry(pkg, 0x1e, name); | |
981 | name[3] = 'A'; | |
982 | append_q35_prt_entry(pkg, 0x1f, name); | |
983 | ||
984 | g_free(name); | |
985 | return pkg; | |
986 | } | |
987 | ||
80b32df5 IM |
988 | static void build_q35_pci0_int(Aml *table) |
989 | { | |
41f95a52 | 990 | Aml *field; |
0dafe3b3 | 991 | Aml *method; |
80b32df5 | 992 | Aml *sb_scope = aml_scope("_SB"); |
0dafe3b3 IM |
993 | Aml *pci0_scope = aml_scope("PCI0"); |
994 | ||
e9fce798 IM |
995 | /* Zero => PIC mode, One => APIC Mode */ |
996 | aml_append(table, aml_name_decl("PICF", aml_int(0))); | |
997 | method = aml_method("_PIC", 1, AML_NOTSERIALIZED); | |
998 | { | |
999 | aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); | |
1000 | } | |
1001 | aml_append(table, method); | |
1002 | ||
65aef4de IM |
1003 | aml_append(pci0_scope, |
1004 | aml_name_decl("PRTP", build_q35_routing_table("LNK"))); | |
22b5b8bf IM |
1005 | aml_append(pci0_scope, |
1006 | aml_name_decl("PRTA", build_q35_routing_table("GSI"))); | |
1007 | ||
0dafe3b3 IM |
1008 | method = aml_method("_PRT", 0, AML_NOTSERIALIZED); |
1009 | { | |
1010 | Aml *if_ctx; | |
1011 | Aml *else_ctx; | |
1012 | ||
1013 | /* PCI IRQ routing table, example from ACPI 2.0a specification, | |
1014 | section 6.2.8.1 */ | |
1015 | /* Note: we provide the same info as the PCI routing | |
1016 | table of the Bochs BIOS */ | |
1017 | if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); | |
1018 | aml_append(if_ctx, aml_return(aml_name("PRTP"))); | |
1019 | aml_append(method, if_ctx); | |
1020 | else_ctx = aml_else(); | |
1021 | aml_append(else_ctx, aml_return(aml_name("PRTA"))); | |
1022 | aml_append(method, else_ctx); | |
1023 | } | |
1024 | aml_append(pci0_scope, method); | |
1025 | aml_append(sb_scope, pci0_scope); | |
80b32df5 | 1026 | |
41f95a52 IM |
1027 | field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); |
1028 | aml_append(field, aml_named_field("PRQA", 8)); | |
1029 | aml_append(field, aml_named_field("PRQB", 8)); | |
1030 | aml_append(field, aml_named_field("PRQC", 8)); | |
1031 | aml_append(field, aml_named_field("PRQD", 8)); | |
1032 | aml_append(field, aml_reserved_field(0x20)); | |
1033 | aml_append(field, aml_named_field("PRQE", 8)); | |
1034 | aml_append(field, aml_named_field("PRQF", 8)); | |
1035 | aml_append(field, aml_named_field("PRQG", 8)); | |
1036 | aml_append(field, aml_named_field("PRQH", 8)); | |
1037 | aml_append(sb_scope, field); | |
1038 | ||
78e1ad05 | 1039 | aml_append(sb_scope, build_irq_status_method()); |
16682a9d IM |
1040 | aml_append(sb_scope, build_iqcr_method(false)); |
1041 | ||
12e3b1f7 IM |
1042 | aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); |
1043 | aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); | |
1044 | aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); | |
1045 | aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); | |
1046 | aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); | |
1047 | aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); | |
1048 | aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); | |
1049 | aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); | |
1050 | ||
6a991e07 MA |
1051 | aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); |
1052 | aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); | |
1053 | aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); | |
1054 | aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); | |
1055 | aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); | |
1056 | aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); | |
1057 | aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); | |
1058 | aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); | |
80b32df5 IM |
1059 | |
1060 | aml_append(table, sb_scope); | |
1061 | } | |
1062 | ||
41f95a52 IM |
1063 | static void build_q35_isa_bridge(Aml *table) |
1064 | { | |
1065 | Aml *dev; | |
1066 | Aml *scope; | |
41f95a52 IM |
1067 | |
1068 | scope = aml_scope("_SB.PCI0"); | |
1069 | dev = aml_device("ISA"); | |
1070 | aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); | |
1071 | ||
1072 | /* ICH9 PCI to ISA irq remapping */ | |
1073 | aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, | |
3f3009c0 | 1074 | aml_int(0x60), 0x0C)); |
41f95a52 | 1075 | |
41f95a52 IM |
1076 | aml_append(scope, dev); |
1077 | aml_append(table, scope); | |
1078 | } | |
1079 | ||
e4db2798 IM |
1080 | static void build_piix4_isa_bridge(Aml *table) |
1081 | { | |
1082 | Aml *dev; | |
1083 | Aml *scope; | |
e4db2798 IM |
1084 | |
1085 | scope = aml_scope("_SB.PCI0"); | |
1086 | dev = aml_device("ISA"); | |
1087 | aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); | |
1088 | ||
1089 | /* PIIX PCI to ISA irq remapping */ | |
1090 | aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, | |
3f3009c0 | 1091 | aml_int(0x60), 0x04)); |
e4db2798 IM |
1092 | |
1093 | aml_append(scope, dev); | |
1094 | aml_append(table, scope); | |
1095 | } | |
1096 | ||
b616ec4d IM |
1097 | static void build_piix4_pci_hotplug(Aml *table) |
1098 | { | |
1099 | Aml *scope; | |
1100 | Aml *field; | |
1101 | Aml *method; | |
1102 | ||
1103 | scope = aml_scope("_SB.PCI0"); | |
1104 | ||
1105 | aml_append(scope, | |
3f3009c0 | 1106 | aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); |
b616ec4d IM |
1107 | field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); |
1108 | aml_append(field, aml_named_field("PCIU", 32)); | |
1109 | aml_append(field, aml_named_field("PCID", 32)); | |
1110 | aml_append(scope, field); | |
1111 | ||
1112 | aml_append(scope, | |
3f3009c0 | 1113 | aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); |
b616ec4d IM |
1114 | field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); |
1115 | aml_append(field, aml_named_field("B0EJ", 32)); | |
1116 | aml_append(scope, field); | |
1117 | ||
1118 | aml_append(scope, | |
3f3009c0 | 1119 | aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); |
b616ec4d IM |
1120 | field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); |
1121 | aml_append(field, aml_named_field("BNUM", 32)); | |
1122 | aml_append(scope, field); | |
1123 | ||
1124 | aml_append(scope, aml_mutex("BLCK", 0)); | |
1125 | ||
1126 | method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); | |
1127 | aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); | |
1128 | aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); | |
1129 | aml_append(method, | |
1130 | aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); | |
1131 | aml_append(method, aml_release(aml_name("BLCK"))); | |
1132 | aml_append(method, aml_return(aml_int(0))); | |
1133 | aml_append(scope, method); | |
1134 | ||
1135 | aml_append(table, scope); | |
1136 | } | |
1137 | ||
f97a88a8 IM |
1138 | static Aml *build_q35_osc_method(void) |
1139 | { | |
1140 | Aml *if_ctx; | |
1141 | Aml *if_ctx2; | |
1142 | Aml *else_ctx; | |
1143 | Aml *method; | |
1144 | Aml *a_cwd1 = aml_name("CDW1"); | |
b3c782db | 1145 | Aml *a_ctrl = aml_local(0); |
f97a88a8 IM |
1146 | |
1147 | method = aml_method("_OSC", 4, AML_NOTSERIALIZED); | |
1148 | aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); | |
1149 | ||
1150 | if_ctx = aml_if(aml_equal( | |
1151 | aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); | |
1152 | aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); | |
1153 | aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); | |
1154 | ||
f97a88a8 IM |
1155 | aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); |
1156 | ||
1157 | /* | |
1158 | * Always allow native PME, AER (no dependencies) | |
a41c78c1 | 1159 | * Allow SHPC (PCI bridges can have SHPC controller) |
f97a88a8 | 1160 | */ |
a41c78c1 | 1161 | aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); |
f97a88a8 IM |
1162 | |
1163 | if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); | |
1164 | /* Unknown revision */ | |
1165 | aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); | |
1166 | aml_append(if_ctx, if_ctx2); | |
1167 | ||
1168 | if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); | |
1169 | /* Capabilities bits were masked */ | |
1170 | aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); | |
1171 | aml_append(if_ctx, if_ctx2); | |
1172 | ||
1173 | /* Update DWORD3 in the buffer */ | |
1174 | aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); | |
1175 | aml_append(method, if_ctx); | |
1176 | ||
1177 | else_ctx = aml_else(); | |
1178 | /* Unrecognized UUID */ | |
1179 | aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); | |
1180 | aml_append(method, else_ctx); | |
1181 | ||
1182 | aml_append(method, aml_return(aml_arg(3))); | |
1183 | return method; | |
1184 | } | |
b616ec4d | 1185 | |
ebe15582 CM |
1186 | static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) |
1187 | { | |
1188 | Aml *scope = aml_scope("_SB.PCI0"); | |
1189 | Aml *dev = aml_device("SMB0"); | |
1190 | ||
ebe15582 CM |
1191 | aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); |
1192 | build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); | |
1193 | aml_append(scope, dev); | |
1194 | aml_append(table, scope); | |
1195 | } | |
1196 | ||
72c194f7 | 1197 | static void |
0e9b9eda | 1198 | build_dsdt(GArray *table_data, BIOSLinker *linker, |
adcb89d5 | 1199 | AcpiPmInfo *pm, AcpiMiscInfo *misc, |
01c9742d | 1200 | Range *pci_hole, Range *pci_hole64, MachineState *machine) |
72c194f7 | 1201 | { |
41fa5c04 IM |
1202 | CrsRangeEntry *entry; |
1203 | Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; | |
2df5a7b5 | 1204 | CrsRangeSet crs_range_set; |
fb306ffe | 1205 | PCMachineState *pcms = PC_MACHINE(machine); |
679dd1a9 | 1206 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); |
f0bb276b | 1207 | X86MachineState *x86ms = X86_MACHINE(machine); |
4a441836 | 1208 | AcpiMcfgInfo mcfg; |
bef3492d | 1209 | uint32_t nr_mem = machine->ram_slots; |
dcdca296 | 1210 | int root_bus_limit = 0xFF; |
41fa5c04 | 1211 | PCIBus *bus = NULL; |
ac6dd31e | 1212 | TPMIf *tpm = tpm_find(); |
72c194f7 | 1213 | int i; |
8f814ea1 | 1214 | VMBusBridge *vmbus_bridge = vmbus_bridge_find(); |
72c194f7 | 1215 | |
41fa5c04 | 1216 | dsdt = init_aml_allocator(); |
2fd71f1b | 1217 | |
4ec8d2b3 | 1218 | /* Reserve space for header */ |
41fa5c04 IM |
1219 | acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); |
1220 | ||
1221 | build_dbg_aml(dsdt); | |
1222 | if (misc->is_piix4) { | |
1223 | sb_scope = aml_scope("_SB"); | |
1224 | dev = aml_device("PCI0"); | |
1225 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); | |
1226 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
af1b80ae | 1227 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); |
41fa5c04 IM |
1228 | aml_append(sb_scope, dev); |
1229 | aml_append(dsdt, sb_scope); | |
1230 | ||
1231 | build_hpet_aml(dsdt); | |
41fa5c04 IM |
1232 | build_piix4_isa_bridge(dsdt); |
1233 | build_isa_devices_aml(dsdt); | |
df4008c9 AS |
1234 | if (pm->pcihp_bridge_en || pm->pcihp_root_en) { |
1235 | build_piix4_pci_hotplug(dsdt); | |
1236 | } | |
41fa5c04 IM |
1237 | build_piix4_pci0_int(dsdt); |
1238 | } else { | |
41fa5c04 IM |
1239 | sb_scope = aml_scope("_SB"); |
1240 | dev = aml_device("PCI0"); | |
1241 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); | |
1242 | aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); | |
1243 | aml_append(dev, aml_name_decl("_ADR", aml_int(0))); | |
af1b80ae | 1244 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); |
41fa5c04 IM |
1245 | aml_append(dev, build_q35_osc_method()); |
1246 | aml_append(sb_scope, dev); | |
998ba950 IM |
1247 | |
1248 | if (pm->smi_on_cpuhp) { | |
1249 | /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ | |
1250 | dev = aml_device("PCI0.SMI0"); | |
1251 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); | |
1252 | aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); | |
1253 | crs = aml_resource_template(); | |
1254 | aml_append(crs, | |
1255 | aml_io( | |
1256 | AML_DECODE16, | |
1257 | ACPI_PORT_SMI_CMD, | |
1258 | ACPI_PORT_SMI_CMD, | |
1259 | 1, | |
1260 | 2) | |
1261 | ); | |
1262 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1263 | aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, | |
1264 | aml_int(ACPI_PORT_SMI_CMD), 2)); | |
1265 | field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, | |
1266 | AML_WRITE_AS_ZEROS); | |
1267 | aml_append(field, aml_named_field("SMIC", 8)); | |
1268 | aml_append(field, aml_reserved_field(8)); | |
1269 | aml_append(dev, field); | |
1270 | aml_append(sb_scope, dev); | |
1271 | } | |
1272 | ||
41fa5c04 IM |
1273 | aml_append(dsdt, sb_scope); |
1274 | ||
1275 | build_hpet_aml(dsdt); | |
1276 | build_q35_isa_bridge(dsdt); | |
1277 | build_isa_devices_aml(dsdt); | |
1278 | build_q35_pci0_int(dsdt); | |
ebe15582 CM |
1279 | if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { |
1280 | build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); | |
1281 | } | |
41fa5c04 IM |
1282 | } |
1283 | ||
8f814ea1 JD |
1284 | if (vmbus_bridge) { |
1285 | sb_scope = aml_scope("_SB"); | |
1286 | aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); | |
1287 | aml_append(dsdt, sb_scope); | |
1288 | } | |
1289 | ||
679dd1a9 IM |
1290 | if (pcmc->legacy_cpu_hotplug) { |
1291 | build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); | |
1292 | } else { | |
1293 | CPUHotplugFeatures opts = { | |
998ba950 IM |
1294 | .acpi_1_compatible = true, .has_legacy_cphp = true, |
1295 | .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, | |
69dea9d6 | 1296 | .fw_unplugs_cpu = pm->smi_on_cpu_unplug, |
679dd1a9 IM |
1297 | }; |
1298 | build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, | |
1299 | "\\_SB.PCI0", "\\_GPE._E02"); | |
1300 | } | |
091c466e SK |
1301 | |
1302 | if (pcms->memhp_io_base && nr_mem) { | |
1303 | build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", | |
1304 | "\\_GPE._E03", AML_SYSTEM_IO, | |
1305 | pcms->memhp_io_base); | |
1306 | } | |
41fa5c04 IM |
1307 | |
1308 | scope = aml_scope("_GPE"); | |
1309 | { | |
1310 | aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); | |
1311 | ||
df4008c9 | 1312 | if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { |
41fa5c04 IM |
1313 | method = aml_method("_E01", 0, AML_NOTSERIALIZED); |
1314 | aml_append(method, | |
1315 | aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); | |
1316 | aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); | |
1317 | aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); | |
1318 | aml_append(scope, method); | |
41fa5c04 IM |
1319 | } |
1320 | ||
f6a0d06b | 1321 | if (machine->nvdimms_state->is_enabled) { |
b097cc52 XG |
1322 | method = aml_method("_E04", 0, AML_NOTSERIALIZED); |
1323 | aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), | |
1324 | aml_int(0x80))); | |
1325 | aml_append(scope, method); | |
1326 | } | |
41fa5c04 IM |
1327 | } |
1328 | aml_append(dsdt, scope); | |
72c194f7 | 1329 | |
2df5a7b5 | 1330 | crs_range_set_init(&crs_range_set); |
81ed6482 | 1331 | bus = PC_MACHINE(machine)->bus; |
a4894206 MA |
1332 | if (bus) { |
1333 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1334 | uint8_t bus_num = pci_bus_num(bus); | |
0e79e51a | 1335 | uint8_t numa_node = pci_bus_numa_node(bus); |
a4894206 MA |
1336 | |
1337 | /* look only for expander root buses */ | |
1338 | if (!pci_bus_is_root(bus)) { | |
1339 | continue; | |
1340 | } | |
1341 | ||
dcdca296 MA |
1342 | if (bus_num < root_bus_limit) { |
1343 | root_bus_limit = bus_num - 1; | |
1344 | } | |
1345 | ||
a4894206 MA |
1346 | scope = aml_scope("\\_SB"); |
1347 | dev = aml_device("PC%.02X", bus_num); | |
c96d9286 | 1348 | aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); |
a4894206 | 1349 | aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); |
077dd742 | 1350 | if (pci_bus_is_express(bus)) { |
ee4b0c86 EY |
1351 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); |
1352 | aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); | |
077dd742 | 1353 | aml_append(dev, build_q35_osc_method()); |
ee4b0c86 EY |
1354 | } else { |
1355 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); | |
077dd742 | 1356 | } |
0e79e51a MA |
1357 | |
1358 | if (numa_node != NUMA_NODE_UNASSIGNED) { | |
1359 | aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); | |
1360 | } | |
1361 | ||
196e2137 | 1362 | aml_append(dev, build_prt(false)); |
e41ee855 JC |
1363 | crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, |
1364 | 0, 0, 0, 0); | |
a43c6e27 | 1365 | aml_append(dev, aml_name_decl("_CRS", crs)); |
a4894206 | 1366 | aml_append(scope, dev); |
41fa5c04 | 1367 | aml_append(dsdt, scope); |
a4894206 MA |
1368 | } |
1369 | } | |
1370 | ||
4a441836 GH |
1371 | /* |
1372 | * At this point crs_range_set has all the ranges used by pci | |
1373 | * busses *other* than PCI0. These ranges will be excluded from | |
1374 | * the PCI0._CRS. Add mmconfig to the set so it will be excluded | |
1375 | * too. | |
1376 | */ | |
1377 | if (acpi_get_mcfg(&mcfg)) { | |
1378 | crs_range_insert(crs_range_set.mem_ranges, | |
1379 | mcfg.base, mcfg.base + mcfg.size - 1); | |
1380 | } | |
1381 | ||
500b11ea | 1382 | scope = aml_scope("\\_SB.PCI0"); |
60efd429 IM |
1383 | /* build PCI0._CRS */ |
1384 | crs = aml_resource_template(); | |
1385 | aml_append(crs, | |
ff80dc7f | 1386 | aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, |
dcdca296 MA |
1387 | 0x0000, 0x0, root_bus_limit, |
1388 | 0x0000, root_bus_limit + 1)); | |
ff80dc7f | 1389 | aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); |
60efd429 IM |
1390 | |
1391 | aml_append(crs, | |
ff80dc7f SZ |
1392 | aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, |
1393 | AML_POS_DECODE, AML_ENTIRE_RANGE, | |
60efd429 | 1394 | 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); |
dcdca296 | 1395 | |
2df5a7b5 MA |
1396 | crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); |
1397 | for (i = 0; i < crs_range_set.io_ranges->len; i++) { | |
1398 | entry = g_ptr_array_index(crs_range_set.io_ranges, i); | |
dcdca296 MA |
1399 | aml_append(crs, |
1400 | aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, | |
1401 | AML_POS_DECODE, AML_ENTIRE_RANGE, | |
1402 | 0x0000, entry->base, entry->limit, | |
1403 | 0x0000, entry->limit - entry->base + 1)); | |
1404 | } | |
1405 | ||
60efd429 | 1406 | aml_append(crs, |
ff80dc7f SZ |
1407 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, |
1408 | AML_CACHEABLE, AML_READ_WRITE, | |
60efd429 | 1409 | 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); |
dcdca296 | 1410 | |
2df5a7b5 | 1411 | crs_replace_with_free_ranges(crs_range_set.mem_ranges, |
a0efbf16 MA |
1412 | range_lob(pci_hole), |
1413 | range_upb(pci_hole)); | |
2df5a7b5 MA |
1414 | for (i = 0; i < crs_range_set.mem_ranges->len; i++) { |
1415 | entry = g_ptr_array_index(crs_range_set.mem_ranges, i); | |
dcdca296 MA |
1416 | aml_append(crs, |
1417 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, | |
1418 | AML_NON_CACHEABLE, AML_READ_WRITE, | |
1419 | 0, entry->base, entry->limit, | |
1420 | 0, entry->limit - entry->base + 1)); | |
1421 | } | |
1422 | ||
a0efbf16 | 1423 | if (!range_is_empty(pci_hole64)) { |
16de88a4 MA |
1424 | crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, |
1425 | range_lob(pci_hole64), | |
1426 | range_upb(pci_hole64)); | |
1427 | for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { | |
1428 | entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); | |
1429 | aml_append(crs, | |
1430 | aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, | |
1431 | AML_MAX_FIXED, | |
1432 | AML_CACHEABLE, AML_READ_WRITE, | |
1433 | 0, entry->base, entry->limit, | |
1434 | 0, entry->limit - entry->base + 1)); | |
1435 | } | |
60efd429 | 1436 | } |
2b1c2e8e | 1437 | |
43bc7f84 | 1438 | if (TPM_IS_TIS_ISA(tpm_find())) { |
2b1c2e8e IM |
1439 | aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, |
1440 | TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); | |
1441 | } | |
60efd429 IM |
1442 | aml_append(scope, aml_name_decl("_CRS", crs)); |
1443 | ||
d31c909e IM |
1444 | /* reserve GPE0 block resources */ |
1445 | dev = aml_device("GPE0"); | |
1446 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
1447 | aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); | |
1448 | /* device present, functioning, decoding, not shown in UI */ | |
1449 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1450 | crs = aml_resource_template(); | |
1451 | aml_append(crs, | |
937d1b58 IM |
1452 | aml_io( |
1453 | AML_DECODE16, | |
1454 | pm->fadt.gpe0_blk.address, | |
1455 | pm->fadt.gpe0_blk.address, | |
1456 | 1, | |
1457 | pm->fadt.gpe0_blk.bit_width / 8) | |
d31c909e IM |
1458 | ); |
1459 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1460 | aml_append(scope, dev); | |
1461 | ||
2df5a7b5 | 1462 | crs_range_set_free(&crs_range_set); |
dcdca296 | 1463 | |
500b11ea | 1464 | /* reserve PCIHP resources */ |
df4008c9 | 1465 | if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { |
500b11ea IM |
1466 | dev = aml_device("PHPR"); |
1467 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
1468 | aml_append(dev, | |
1469 | aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); | |
1470 | /* device present, functioning, decoding, not shown in UI */ | |
1471 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1472 | crs = aml_resource_template(); | |
1473 | aml_append(crs, | |
ff80dc7f | 1474 | aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, |
500b11ea IM |
1475 | pm->pcihp_io_len) |
1476 | ); | |
1477 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1478 | aml_append(scope, dev); | |
1479 | } | |
41fa5c04 | 1480 | aml_append(dsdt, scope); |
500b11ea | 1481 | |
ebc3028f IM |
1482 | /* create S3_ / S4_ / S5_ packages if necessary */ |
1483 | scope = aml_scope("\\"); | |
1484 | if (!pm->s3_disabled) { | |
1485 | pkg = aml_package(4); | |
1486 | aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ | |
1487 | aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
1488 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1489 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1490 | aml_append(scope, aml_name_decl("_S3", pkg)); | |
1491 | } | |
1492 | ||
1493 | if (!pm->s4_disabled) { | |
1494 | pkg = aml_package(4); | |
1495 | aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ | |
1496 | /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
1497 | aml_append(pkg, aml_int(pm->s4_val)); | |
1498 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1499 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1500 | aml_append(scope, aml_name_decl("_S4", pkg)); | |
1501 | } | |
1502 | ||
1503 | pkg = aml_package(4); | |
1504 | aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ | |
1505 | aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ | |
1506 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1507 | aml_append(pkg, aml_int(0)); /* reserved */ | |
1508 | aml_append(scope, aml_name_decl("_S5", pkg)); | |
41fa5c04 | 1509 | aml_append(dsdt, scope); |
ebc3028f | 1510 | |
e2ec7568 GS |
1511 | /* create fw_cfg node, unconditionally */ |
1512 | { | |
e2ec7568 | 1513 | scope = aml_scope("\\_SB.PCI0"); |
0575c2fd | 1514 | fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); |
e2ec7568 GS |
1515 | aml_append(dsdt, scope); |
1516 | } | |
1517 | ||
8ac6f7a6 IM |
1518 | if (misc->applesmc_io_base) { |
1519 | scope = aml_scope("\\_SB.PCI0.ISA"); | |
1520 | dev = aml_device("SMC"); | |
1521 | ||
1522 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); | |
1523 | /* device present, functioning, decoding, not shown in UI */ | |
1524 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1525 | ||
1526 | crs = aml_resource_template(); | |
1527 | aml_append(crs, | |
ff80dc7f | 1528 | aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, |
8ac6f7a6 IM |
1529 | 0x01, APPLESMC_MAX_DATA_LENGTH) |
1530 | ); | |
1531 | aml_append(crs, aml_irq_no_flags(6)); | |
1532 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1533 | ||
1534 | aml_append(scope, dev); | |
41fa5c04 | 1535 | aml_append(dsdt, scope); |
8ac6f7a6 IM |
1536 | } |
1537 | ||
cd61cb2e IM |
1538 | if (misc->pvpanic_port) { |
1539 | scope = aml_scope("\\_SB.PCI0.ISA"); | |
1540 | ||
2332333c | 1541 | dev = aml_device("PEVT"); |
e65bef69 | 1542 | aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); |
cd61cb2e IM |
1543 | |
1544 | crs = aml_resource_template(); | |
1545 | aml_append(crs, | |
ff80dc7f | 1546 | aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) |
cd61cb2e IM |
1547 | ); |
1548 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1549 | ||
ff80dc7f | 1550 | aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, |
3f3009c0 | 1551 | aml_int(misc->pvpanic_port), 1)); |
36de884a | 1552 | field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); |
cd61cb2e IM |
1553 | aml_append(field, aml_named_field("PEPT", 8)); |
1554 | aml_append(dev, field); | |
1555 | ||
8ef3ea25 GH |
1556 | /* device present, functioning, decoding, shown in UI */ |
1557 | aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); | |
2332333c | 1558 | |
4dbfc881 | 1559 | method = aml_method("RDPT", 0, AML_NOTSERIALIZED); |
cd61cb2e IM |
1560 | aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); |
1561 | aml_append(method, aml_return(aml_local(0))); | |
1562 | aml_append(dev, method); | |
1563 | ||
4dbfc881 | 1564 | method = aml_method("WRPT", 1, AML_NOTSERIALIZED); |
cd61cb2e IM |
1565 | aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); |
1566 | aml_append(dev, method); | |
1567 | ||
1568 | aml_append(scope, dev); | |
41fa5c04 | 1569 | aml_append(dsdt, scope); |
cd61cb2e IM |
1570 | } |
1571 | ||
7824df38 | 1572 | sb_scope = aml_scope("\\_SB"); |
72c194f7 | 1573 | { |
8b35ab27 IM |
1574 | Object *pci_host; |
1575 | PCIBus *bus = NULL; | |
8698c0c0 | 1576 | |
8b35ab27 IM |
1577 | pci_host = acpi_get_i386_pci_host(); |
1578 | if (pci_host) { | |
1579 | bus = PCI_HOST_BRIDGE(pci_host)->bus; | |
1580 | } | |
8dcf525a | 1581 | |
8b35ab27 IM |
1582 | if (bus) { |
1583 | Aml *scope = aml_scope("PCI0"); | |
1584 | /* Scan all PCI buses. Generate tables to support hotplug. */ | |
1585 | build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); | |
1586 | ||
43bc7f84 | 1587 | if (TPM_IS_TIS_ISA(tpm)) { |
24cf5413 SB |
1588 | if (misc->tpm_version == TPM_VERSION_2_0) { |
1589 | dev = aml_device("TPM"); | |
1590 | aml_append(dev, aml_name_decl("_HID", | |
1591 | aml_string("MSFT0101"))); | |
1592 | } else { | |
1593 | dev = aml_device("ISA.TPM"); | |
1594 | aml_append(dev, aml_name_decl("_HID", | |
1595 | aml_eisaid("PNP0C31"))); | |
1596 | } | |
1597 | ||
8b35ab27 IM |
1598 | aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); |
1599 | crs = aml_resource_template(); | |
1600 | aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, | |
1601 | TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); | |
1602 | /* | |
1603 | FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, | |
1604 | Rewrite to take IRQ from TPM device model and | |
1605 | fix default IRQ value there to use some unused IRQ | |
1606 | */ | |
1607 | /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ | |
1608 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
ac6dd31e SB |
1609 | |
1610 | tpm_build_ppi_acpi(tpm, dev); | |
1611 | ||
8b35ab27 | 1612 | aml_append(scope, dev); |
8dcf525a | 1613 | } |
72c194f7 | 1614 | |
8b35ab27 | 1615 | aml_append(sb_scope, scope); |
72c194f7 | 1616 | } |
72c194f7 | 1617 | } |
4ab6cb4c | 1618 | |
ac6dd31e | 1619 | if (TPM_IS_CRB(tpm)) { |
4ab6cb4c MAL |
1620 | dev = aml_device("TPM"); |
1621 | aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); | |
1622 | crs = aml_resource_template(); | |
1623 | aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, | |
1624 | TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); | |
1625 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1626 | ||
88b3648f | 1627 | aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); |
4ab6cb4c | 1628 | |
ac6dd31e SB |
1629 | tpm_build_ppi_acpi(tpm, dev); |
1630 | ||
4ab6cb4c MAL |
1631 | aml_append(sb_scope, dev); |
1632 | } | |
1633 | ||
8b35ab27 | 1634 | aml_append(dsdt, sb_scope); |
72c194f7 | 1635 | |
011bb749 | 1636 | /* copy AML table into ACPI tables blob and patch header there */ |
41fa5c04 | 1637 | g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); |
72c194f7 | 1638 | build_header(linker, table_data, |
41fa5c04 | 1639 | (void *)(table_data->data + table_data->len - dsdt->buf->len), |
37ad223c | 1640 | "DSDT", dsdt->buf->len, 1, NULL, NULL); |
011bb749 | 1641 | free_aml_allocator(); |
72c194f7 MT |
1642 | } |
1643 | ||
1644 | static void | |
0e9b9eda | 1645 | build_hpet(GArray *table_data, BIOSLinker *linker) |
72c194f7 MT |
1646 | { |
1647 | Acpi20Hpet *hpet; | |
1648 | ||
1649 | hpet = acpi_data_push(table_data, sizeof(*hpet)); | |
1650 | /* Note timer_block_id value must be kept in sync with value advertised by | |
1651 | * emulated hpet | |
1652 | */ | |
1653 | hpet->timer_block_id = cpu_to_le32(0x8086a201); | |
1654 | hpet->addr.address = cpu_to_le64(HPET_BASE); | |
1655 | build_header(linker, table_data, | |
37ad223c | 1656 | (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); |
72c194f7 MT |
1657 | } |
1658 | ||
711b20b4 | 1659 | static void |
0e9b9eda | 1660 | build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) |
711b20b4 SB |
1661 | { |
1662 | Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); | |
4678124b IM |
1663 | unsigned log_addr_size = sizeof(tcpa->log_area_start_address); |
1664 | unsigned log_addr_offset = | |
1665 | (char *)&tcpa->log_area_start_address - table_data->data; | |
711b20b4 SB |
1666 | |
1667 | tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); | |
1668 | tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); | |
9774ccf7 | 1669 | acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); |
711b20b4 | 1670 | |
ad9671b8 | 1671 | bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, |
42a5b308 SB |
1672 | false /* high memory */); |
1673 | ||
711b20b4 | 1674 | /* log area start address to be filled by Guest linker */ |
4678124b IM |
1675 | bios_linker_loader_add_pointer(linker, |
1676 | ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, | |
1677 | ACPI_BUILD_TPMLOG_FILE, 0); | |
711b20b4 SB |
1678 | |
1679 | build_header(linker, table_data, | |
37ad223c | 1680 | (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); |
711b20b4 SB |
1681 | } |
1682 | ||
d471bf3e PB |
1683 | #define HOLE_640K_START (640 * KiB) |
1684 | #define HOLE_640K_END (1 * MiB) | |
4926403c | 1685 | |
72c194f7 | 1686 | static void |
0e9b9eda | 1687 | build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) |
72c194f7 MT |
1688 | { |
1689 | AcpiSystemResourceAffinityTable *srat; | |
72c194f7 MT |
1690 | AcpiSratMemoryAffinity *numamem; |
1691 | ||
1692 | int i; | |
72c194f7 MT |
1693 | int srat_start, numa_start, slots; |
1694 | uint64_t mem_len, mem_base, next_base; | |
5803fce3 | 1695 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
f0bb276b | 1696 | X86MachineState *x86ms = X86_MACHINE(machine); |
80e5db30 | 1697 | const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); |
3d3ebcad | 1698 | PCMachineState *pcms = PC_MACHINE(machine); |
cec65193 | 1699 | ram_addr_t hotplugabble_address_space_size = |
f2ffbe2b | 1700 | object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, |
cec65193 | 1701 | NULL); |
72c194f7 MT |
1702 | |
1703 | srat_start = table_data->len; | |
1704 | ||
1705 | srat = acpi_data_push(table_data, sizeof *srat); | |
1706 | srat->reserved1 = cpu_to_le32(1); | |
72c194f7 | 1707 | |
5803fce3 | 1708 | for (i = 0; i < apic_ids->len; i++) { |
d41f3e75 | 1709 | int node_id = apic_ids->cpus[i].props.node_id; |
5eff33a2 | 1710 | uint32_t apic_id = apic_ids->cpus[i].arch_id; |
5803fce3 | 1711 | |
5eff33a2 IM |
1712 | if (apic_id < 255) { |
1713 | AcpiSratProcessorAffinity *core; | |
1714 | ||
1715 | core = acpi_data_push(table_data, sizeof *core); | |
1716 | core->type = ACPI_SRAT_PROCESSOR_APIC; | |
1717 | core->length = sizeof(*core); | |
1718 | core->local_apic_id = apic_id; | |
ea265072 | 1719 | core->proximity_lo = node_id; |
5eff33a2 IM |
1720 | memset(core->proximity_hi, 0, 3); |
1721 | core->local_sapic_eid = 0; | |
1722 | core->flags = cpu_to_le32(1); | |
1723 | } else { | |
1724 | AcpiSratProcessorX2ApicAffinity *core; | |
1725 | ||
1726 | core = acpi_data_push(table_data, sizeof *core); | |
1727 | core->type = ACPI_SRAT_PROCESSOR_x2APIC; | |
1728 | core->length = sizeof(*core); | |
1729 | core->x2apic_id = cpu_to_le32(apic_id); | |
ea265072 | 1730 | core->proximity_domain = cpu_to_le32(node_id); |
5eff33a2 | 1731 | core->flags = cpu_to_le32(1); |
1f3aba37 | 1732 | } |
72c194f7 MT |
1733 | } |
1734 | ||
1735 | ||
1736 | /* the memory map is a bit tricky, it contains at least one hole | |
1737 | * from 640k-1M and possibly another one from 3.5G-4G. | |
1738 | */ | |
1739 | next_base = 0; | |
1740 | numa_start = table_data->len; | |
1741 | ||
dd4c2f01 | 1742 | for (i = 1; i < pcms->numa_nodes + 1; ++i) { |
72c194f7 | 1743 | mem_base = next_base; |
dd4c2f01 | 1744 | mem_len = pcms->node_mem[i - 1]; |
72c194f7 MT |
1745 | next_base = mem_base + mem_len; |
1746 | ||
4926403c EH |
1747 | /* Cut out the 640K hole */ |
1748 | if (mem_base <= HOLE_640K_START && | |
1749 | next_base > HOLE_640K_START) { | |
1750 | mem_len -= next_base - HOLE_640K_START; | |
1751 | if (mem_len > 0) { | |
1752 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
1753 | build_srat_memory(numamem, mem_base, mem_len, i - 1, | |
1754 | MEM_AFFINITY_ENABLED); | |
1755 | } | |
1756 | ||
1757 | /* Check for the rare case: 640K < RAM < 1M */ | |
1758 | if (next_base <= HOLE_640K_END) { | |
1759 | next_base = HOLE_640K_END; | |
1760 | continue; | |
1761 | } | |
1762 | mem_base = HOLE_640K_END; | |
1763 | mem_len = next_base - HOLE_640K_END; | |
1764 | } | |
1765 | ||
72c194f7 | 1766 | /* Cut out the ACPI_PCI hole */ |
f0bb276b PB |
1767 | if (mem_base <= x86ms->below_4g_mem_size && |
1768 | next_base > x86ms->below_4g_mem_size) { | |
1769 | mem_len -= next_base - x86ms->below_4g_mem_size; | |
72c194f7 MT |
1770 | if (mem_len > 0) { |
1771 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
64b83136 SZ |
1772 | build_srat_memory(numamem, mem_base, mem_len, i - 1, |
1773 | MEM_AFFINITY_ENABLED); | |
72c194f7 MT |
1774 | } |
1775 | mem_base = 1ULL << 32; | |
f0bb276b | 1776 | mem_len = next_base - x86ms->below_4g_mem_size; |
6cf6fe39 | 1777 | next_base = mem_base + mem_len; |
72c194f7 | 1778 | } |
16b42263 DL |
1779 | |
1780 | if (mem_len > 0) { | |
1781 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
1782 | build_srat_memory(numamem, mem_base, mem_len, i - 1, | |
1783 | MEM_AFFINITY_ENABLED); | |
1784 | } | |
72c194f7 | 1785 | } |
c3b0cf6e VV |
1786 | |
1787 | if (machine->nvdimms_state->is_enabled) { | |
1788 | nvdimm_build_srat(table_data); | |
1789 | } | |
1790 | ||
72c194f7 | 1791 | slots = (table_data->len - numa_start) / sizeof *numamem; |
dd4c2f01 | 1792 | for (; slots < pcms->numa_nodes + 2; slots++) { |
72c194f7 | 1793 | numamem = acpi_data_push(table_data, sizeof *numamem); |
64b83136 | 1794 | build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); |
72c194f7 MT |
1795 | } |
1796 | ||
dbb6da8b IM |
1797 | /* |
1798 | * Entry is required for Windows to enable memory hotplug in OS | |
1799 | * and for Linux to enable SWIOTLB when booted with less than | |
1800 | * 4G of RAM. Windows works better if the entry sets proximity | |
1801 | * to the highest NUMA node in the machine. | |
1802 | * Memory devices may override proximity set by this entry, | |
1803 | * providing _PXM method if necessary. | |
1804 | */ | |
cec65193 | 1805 | if (hotplugabble_address_space_size) { |
dbb6da8b IM |
1806 | numamem = acpi_data_push(table_data, sizeof *numamem); |
1807 | build_srat_memory(numamem, machine->device_memory->base, | |
1808 | hotplugabble_address_space_size, pcms->numa_nodes - 1, | |
1809 | MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); | |
cec65193 IM |
1810 | } |
1811 | ||
72c194f7 MT |
1812 | build_header(linker, table_data, |
1813 | (void *)(table_data->data + srat_start), | |
821e3227 | 1814 | "SRAT", |
37ad223c | 1815 | table_data->len - srat_start, 1, NULL, NULL); |
72c194f7 MT |
1816 | } |
1817 | ||
d46114f9 PX |
1818 | /* |
1819 | * VT-d spec 8.1 DMA Remapping Reporting Structure | |
1820 | * (version Oct. 2014 or later) | |
1821 | */ | |
d4eb9119 | 1822 | static void |
0e9b9eda | 1823 | build_dmar_q35(GArray *table_data, BIOSLinker *linker) |
d4eb9119 LT |
1824 | { |
1825 | int dmar_start = table_data->len; | |
1826 | ||
1827 | AcpiTableDmar *dmar; | |
1828 | AcpiDmarHardwareUnit *drhd; | |
bd2baacc | 1829 | AcpiDmarRootPortATS *atsr; |
d46114f9 PX |
1830 | uint8_t dmar_flags = 0; |
1831 | X86IOMMUState *iommu = x86_iommu_get_default(); | |
cfc13df4 PX |
1832 | AcpiDmarDeviceScope *scope = NULL; |
1833 | /* Root complex IOAPIC use one path[0] only */ | |
1834 | size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); | |
37f51384 | 1835 | IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); |
d46114f9 PX |
1836 | |
1837 | assert(iommu); | |
a924b3d8 | 1838 | if (x86_iommu_ir_supported(iommu)) { |
d46114f9 PX |
1839 | dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ |
1840 | } | |
d4eb9119 LT |
1841 | |
1842 | dmar = acpi_data_push(table_data, sizeof(*dmar)); | |
37f51384 | 1843 | dmar->host_address_width = intel_iommu->aw_bits - 1; |
d46114f9 | 1844 | dmar->flags = dmar_flags; |
d4eb9119 LT |
1845 | |
1846 | /* DMAR Remapping Hardware Unit Definition structure */ | |
cfc13df4 | 1847 | drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); |
d4eb9119 | 1848 | drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); |
cfc13df4 | 1849 | drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); |
d4eb9119 LT |
1850 | drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; |
1851 | drhd->pci_segment = cpu_to_le16(0); | |
1852 | drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); | |
1853 | ||
cfc13df4 PX |
1854 | /* Scope definition for the root-complex IOAPIC. See VT-d spec |
1855 | * 8.3.1 (version Oct. 2014 or later). */ | |
1856 | scope = &drhd->scope[0]; | |
1857 | scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ | |
1858 | scope->length = ioapic_scope_size; | |
1859 | scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; | |
1860 | scope->bus = Q35_PSEUDO_BUS_PLATFORM; | |
1b39bc1c PX |
1861 | scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); |
1862 | scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); | |
cfc13df4 | 1863 | |
bd2baacc JW |
1864 | if (iommu->dt_supported) { |
1865 | atsr = acpi_data_push(table_data, sizeof(*atsr)); | |
1866 | atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); | |
1867 | atsr->length = cpu_to_le16(sizeof(*atsr)); | |
1868 | atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; | |
1869 | atsr->pci_segment = cpu_to_le16(0); | |
1870 | } | |
1871 | ||
d4eb9119 | 1872 | build_header(linker, table_data, (void *)(table_data->data + dmar_start), |
37ad223c | 1873 | "DMAR", table_data->len - dmar_start, 1, NULL, NULL); |
d4eb9119 | 1874 | } |
14cda350 LA |
1875 | |
1876 | /* | |
1877 | * Windows ACPI Emulated Devices Table | |
1878 | * (Version 1.0 - April 6, 2009) | |
1879 | * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx | |
1880 | * | |
1881 | * Helpful to speedup Windows guests and ignored by others. | |
1882 | */ | |
1883 | static void | |
1884 | build_waet(GArray *table_data, BIOSLinker *linker) | |
1885 | { | |
1886 | int waet_start = table_data->len; | |
1887 | ||
1888 | /* WAET header */ | |
1889 | acpi_data_push(table_data, sizeof(AcpiTableHeader)); | |
1890 | /* | |
1891 | * Set "ACPI PM timer good" flag. | |
1892 | * | |
1893 | * Tells Windows guests that our ACPI PM timer is reliable in the | |
1894 | * sense that guest can read it only once to obtain a reliable value. | |
1895 | * Which avoids costly VMExits caused by guest re-reading it unnecessarily. | |
1896 | */ | |
1897 | build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); | |
1898 | ||
1899 | build_header(linker, table_data, (void *)(table_data->data + waet_start), | |
1900 | "WAET", table_data->len - waet_start, 1, NULL, NULL); | |
1901 | } | |
1902 | ||
fb9f5926 DK |
1903 | /* |
1904 | * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 | |
1905 | * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf | |
1906 | */ | |
c028818d BS |
1907 | #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) |
1908 | ||
977aff10 AW |
1909 | /* |
1910 | * Insert IVHD entry for device and recurse, insert alias, or insert range as | |
1911 | * necessary for the PCI topology. | |
1912 | */ | |
1913 | static void | |
1914 | insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) | |
1915 | { | |
1916 | GArray *table_data = opaque; | |
1917 | uint32_t entry; | |
1918 | ||
1919 | /* "Select" IVHD entry, type 0x2 */ | |
1920 | entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; | |
1921 | build_append_int_noprefix(table_data, entry, 4); | |
1922 | ||
1923 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { | |
1924 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); | |
1925 | uint8_t sec = pci_bus_num(sec_bus); | |
1926 | uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; | |
1927 | ||
1928 | if (pci_bus_is_express(sec_bus)) { | |
1929 | /* | |
1930 | * Walk the bus if there are subordinates, otherwise use a range | |
1931 | * to cover an entire leaf bus. We could potentially also use a | |
1932 | * range for traversed buses, but we'd need to take care not to | |
1933 | * create both Select and Range entries covering the same device. | |
1934 | * This is easier and potentially more compact. | |
1935 | * | |
1936 | * An example bare metal system seems to use Select entries for | |
1937 | * root ports without a slot (ie. built-ins) and Range entries | |
1938 | * when there is a slot. The same system also only hard-codes | |
1939 | * the alias range for an onboard PCIe-to-PCI bridge, apparently | |
1940 | * making no effort to support nested bridges. We attempt to | |
1941 | * be more thorough here. | |
1942 | */ | |
1943 | if (sec == sub) { /* leaf bus */ | |
1944 | /* "Start of Range" IVHD entry, type 0x3 */ | |
1945 | entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; | |
1946 | build_append_int_noprefix(table_data, entry, 4); | |
1947 | /* "End of Range" IVHD entry, type 0x4 */ | |
1948 | entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; | |
1949 | build_append_int_noprefix(table_data, entry, 4); | |
1950 | } else { | |
1951 | pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); | |
1952 | } | |
1953 | } else { | |
1954 | /* | |
1955 | * If the secondary bus is conventional, then we need to create an | |
1956 | * Alias range for everything downstream. The range covers the | |
1957 | * first devfn on the secondary bus to the last devfn on the | |
1958 | * subordinate bus. The alias target depends on legacy versus | |
1959 | * express bridges, just as in pci_device_iommu_address_space(). | |
1960 | * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. | |
1961 | */ | |
1962 | uint16_t dev_id_a, dev_id_b; | |
1963 | ||
1964 | dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); | |
1965 | ||
1966 | if (pci_is_express(dev) && | |
1967 | pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
1968 | dev_id_b = dev_id_a; | |
1969 | } else { | |
1970 | dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); | |
1971 | } | |
1972 | ||
1973 | /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ | |
1974 | build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); | |
1975 | build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); | |
1976 | ||
1977 | /* "End of Range" IVHD entry, type 0x4 */ | |
1978 | entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; | |
1979 | build_append_int_noprefix(table_data, entry, 4); | |
1980 | } | |
1981 | } | |
1982 | } | |
1983 | ||
1984 | /* For all PCI host bridges, walk and insert IVHD entries */ | |
1985 | static int | |
1986 | ivrs_host_bridges(Object *obj, void *opaque) | |
1987 | { | |
1988 | GArray *ivhd_blob = opaque; | |
1989 | ||
1990 | if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { | |
1991 | PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; | |
1992 | ||
1993 | if (bus) { | |
1994 | pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob); | |
1995 | } | |
1996 | } | |
1997 | ||
1998 | return 0; | |
1999 | } | |
2000 | ||
fb9f5926 DK |
2001 | static void |
2002 | build_amd_iommu(GArray *table_data, BIOSLinker *linker) | |
2003 | { | |
977aff10 | 2004 | int ivhd_table_len = 24; |
fb9f5926 DK |
2005 | int iommu_start = table_data->len; |
2006 | AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); | |
977aff10 | 2007 | GArray *ivhd_blob = g_array_new(false, true, 1); |
fb9f5926 DK |
2008 | |
2009 | /* IVRS header */ | |
2010 | acpi_data_push(table_data, sizeof(AcpiTableHeader)); | |
2011 | /* IVinfo - IO virtualization information common to all | |
2012 | * IOMMU units in a system | |
2013 | */ | |
2014 | build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); | |
2015 | /* reserved */ | |
2016 | build_append_int_noprefix(table_data, 0, 8); | |
2017 | ||
2018 | /* IVHD definition - type 10h */ | |
2019 | build_append_int_noprefix(table_data, 0x10, 1); | |
2020 | /* virtualization flags */ | |
2021 | build_append_int_noprefix(table_data, | |
2022 | (1UL << 0) | /* HtTunEn */ | |
2023 | (1UL << 4) | /* iotblSup */ | |
2024 | (1UL << 6) | /* PrefSup */ | |
2025 | (1UL << 7), /* PPRSup */ | |
2026 | 1); | |
c028818d | 2027 | |
977aff10 AW |
2028 | /* |
2029 | * A PCI bus walk, for each PCI host bridge, is necessary to create a | |
2030 | * complete set of IVHD entries. Do this into a separate blob so that we | |
2031 | * can calculate the total IVRS table length here and then append the new | |
2032 | * blob further below. Fall back to an entry covering all devices, which | |
2033 | * is sufficient when no aliases are present. | |
2034 | */ | |
2035 | object_child_foreach_recursive(object_get_root(), | |
2036 | ivrs_host_bridges, ivhd_blob); | |
2037 | ||
2038 | if (!ivhd_blob->len) { | |
2039 | /* | |
2040 | * Type 1 device entry reporting all devices | |
2041 | * These are 4-byte device entries currently reporting the range of | |
2042 | * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) | |
2043 | */ | |
2044 | build_append_int_noprefix(ivhd_blob, 0x0000001, 4); | |
2045 | } | |
2046 | ||
2047 | ivhd_table_len += ivhd_blob->len; | |
2048 | ||
c028818d BS |
2049 | /* |
2050 | * When interrupt remapping is supported, we add a special IVHD device | |
2051 | * for type IO-APIC. | |
2052 | */ | |
a924b3d8 | 2053 | if (x86_iommu_ir_supported(x86_iommu_get_default())) { |
c028818d BS |
2054 | ivhd_table_len += 8; |
2055 | } | |
977aff10 | 2056 | |
fb9f5926 | 2057 | /* IVHD length */ |
c028818d | 2058 | build_append_int_noprefix(table_data, ivhd_table_len, 2); |
fb9f5926 DK |
2059 | /* DeviceID */ |
2060 | build_append_int_noprefix(table_data, s->devid, 2); | |
2061 | /* Capability offset */ | |
2062 | build_append_int_noprefix(table_data, s->capab_offset, 2); | |
2063 | /* IOMMU base address */ | |
2064 | build_append_int_noprefix(table_data, s->mmio.addr, 8); | |
2065 | /* PCI Segment Group */ | |
2066 | build_append_int_noprefix(table_data, 0, 2); | |
2067 | /* IOMMU info */ | |
2068 | build_append_int_noprefix(table_data, 0, 2); | |
2069 | /* IOMMU Feature Reporting */ | |
2070 | build_append_int_noprefix(table_data, | |
2071 | (48UL << 30) | /* HATS */ | |
2072 | (48UL << 28) | /* GATS */ | |
12499b23 BS |
2073 | (1UL << 2) | /* GTSup */ |
2074 | (1UL << 6), /* GASup */ | |
fb9f5926 | 2075 | 4); |
977aff10 AW |
2076 | |
2077 | /* IVHD entries as found above */ | |
2078 | g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); | |
2079 | g_array_free(ivhd_blob, TRUE); | |
fb9f5926 | 2080 | |
c028818d BS |
2081 | /* |
2082 | * Add a special IVHD device type. | |
2083 | * Refer to spec - Table 95: IVHD device entry type codes | |
2084 | * | |
2085 | * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). | |
2086 | * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' | |
2087 | */ | |
a924b3d8 | 2088 | if (x86_iommu_ir_supported(x86_iommu_get_default())) { |
c028818d BS |
2089 | build_append_int_noprefix(table_data, |
2090 | (0x1ull << 56) | /* type IOAPIC */ | |
2091 | (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ | |
2092 | 0x48, /* special device */ | |
2093 | 8); | |
2094 | } | |
2095 | ||
fb9f5926 DK |
2096 | build_header(linker, table_data, (void *)(table_data->data + iommu_start), |
2097 | "IVRS", table_data->len - iommu_start, 1, NULL, NULL); | |
2098 | } | |
d4eb9119 | 2099 | |
72c194f7 MT |
2100 | typedef |
2101 | struct AcpiBuildState { | |
2102 | /* Copy of table in RAM (for patching). */ | |
339240b5 | 2103 | MemoryRegion *table_mr; |
72c194f7 MT |
2104 | /* Is table patched? */ |
2105 | uint8_t patched; | |
d70414a5 | 2106 | void *rsdp; |
339240b5 PB |
2107 | MemoryRegion *rsdp_mr; |
2108 | MemoryRegion *linker_mr; | |
72c194f7 MT |
2109 | } AcpiBuildState; |
2110 | ||
2111 | static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) | |
2112 | { | |
2113 | Object *pci_host; | |
2114 | QObject *o; | |
72c194f7 | 2115 | |
ca6c1855 | 2116 | pci_host = acpi_get_i386_pci_host(); |
72c194f7 MT |
2117 | g_assert(pci_host); |
2118 | ||
2119 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); | |
2120 | if (!o) { | |
2121 | return false; | |
2122 | } | |
c309434e | 2123 | mcfg->base = qnum_get_uint(qobject_to(QNum, o)); |
cb3e7f08 | 2124 | qobject_unref(o); |
c309434e | 2125 | if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { |
fe4970ad IM |
2126 | return false; |
2127 | } | |
72c194f7 MT |
2128 | |
2129 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); | |
2130 | assert(o); | |
c309434e | 2131 | mcfg->size = qnum_get_uint(qobject_to(QNum, o)); |
cb3e7f08 | 2132 | qobject_unref(o); |
72c194f7 MT |
2133 | return true; |
2134 | } | |
2135 | ||
2136 | static | |
3d3ebcad | 2137 | void acpi_build(AcpiBuildTables *tables, MachineState *machine) |
72c194f7 | 2138 | { |
3d3ebcad | 2139 | PCMachineState *pcms = PC_MACHINE(machine); |
bb292f5a | 2140 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 2141 | X86MachineState *x86ms = X86_MACHINE(machine); |
72c194f7 | 2142 | GArray *table_offsets; |
41fa5c04 | 2143 | unsigned facs, dsdt, rsdt, fadt; |
72c194f7 MT |
2144 | AcpiPmInfo pm; |
2145 | AcpiMiscInfo misc; | |
2146 | AcpiMcfgInfo mcfg; | |
01c9742d | 2147 | Range pci_hole, pci_hole64; |
72c194f7 | 2148 | uint8_t *u; |
07fb6176 | 2149 | size_t aml_len = 0; |
7c2c1fa5 | 2150 | GArray *tables_blob = tables->table_data; |
ae123749 | 2151 | AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; |
d03637bc | 2152 | Object *vmgenid_dev; |
72c194f7 | 2153 | |
0e11fc69 | 2154 | acpi_get_pm_info(machine, &pm); |
72c194f7 | 2155 | acpi_get_misc_info(&misc); |
01c9742d | 2156 | acpi_get_pci_holes(&pci_hole, &pci_hole64); |
ae123749 | 2157 | acpi_get_slic_oem(&slic_oem); |
72c194f7 MT |
2158 | |
2159 | table_offsets = g_array_new(false, true /* clear */, | |
2160 | sizeof(uint32_t)); | |
8b310fc4 | 2161 | ACPI_BUILD_DPRINTF("init ACPI tables\n"); |
72c194f7 | 2162 | |
ad9671b8 IM |
2163 | bios_linker_loader_alloc(tables->linker, |
2164 | ACPI_BUILD_TABLE_FILE, tables_blob, | |
72c194f7 MT |
2165 | 64 /* Ensure FACS is aligned */, |
2166 | false /* high memory */); | |
2167 | ||
2168 | /* | |
2169 | * FACS is pointed to by FADT. | |
2170 | * We place it first since it's the only table that has alignment | |
2171 | * requirements. | |
2172 | */ | |
7c2c1fa5 | 2173 | facs = tables_blob->len; |
009180bd | 2174 | build_facs(tables_blob); |
72c194f7 MT |
2175 | |
2176 | /* DSDT is pointed to by FADT */ | |
7c2c1fa5 | 2177 | dsdt = tables_blob->len; |
01c9742d MA |
2178 | build_dsdt(tables_blob, tables->linker, &pm, &misc, |
2179 | &pci_hole, &pci_hole64, machine); | |
72c194f7 | 2180 | |
07fb6176 PB |
2181 | /* Count the size of the DSDT and SSDT, we will need it for legacy |
2182 | * sizing of ACPI tables. | |
2183 | */ | |
7c2c1fa5 | 2184 | aml_len += tables_blob->len - dsdt; |
07fb6176 | 2185 | |
72c194f7 | 2186 | /* ACPI tables pointed to by RSDT */ |
41fa5c04 | 2187 | fadt = tables_blob->len; |
7c2c1fa5 | 2188 | acpi_add_table(table_offsets, tables_blob); |
937d1b58 IM |
2189 | pm.fadt.facs_tbl_offset = &facs; |
2190 | pm.fadt.dsdt_tbl_offset = &dsdt; | |
2191 | pm.fadt.xdsdt_tbl_offset = &dsdt; | |
2192 | build_fadt(tables_blob, tables->linker, &pm.fadt, | |
ae123749 | 2193 | slic_oem.id, slic_oem.table_id); |
41fa5c04 | 2194 | aml_len += tables_blob->len - fadt; |
72c194f7 | 2195 | |
7c2c1fa5 | 2196 | acpi_add_table(table_offsets, tables_blob); |
eb66ffab | 2197 | acpi_build_madt(tables_blob, tables->linker, x86ms, |
a6518755 | 2198 | ACPI_DEVICE_IF(x86ms->acpi_dev)); |
9ac1c4c0 | 2199 | |
d03637bc BW |
2200 | vmgenid_dev = find_vmgenid_dev(); |
2201 | if (vmgenid_dev) { | |
2202 | acpi_add_table(table_offsets, tables_blob); | |
2203 | vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, | |
2204 | tables->vmgenid, tables->linker); | |
2205 | } | |
2206 | ||
72c194f7 | 2207 | if (misc.has_hpet) { |
7c2c1fa5 IM |
2208 | acpi_add_table(table_offsets, tables_blob); |
2209 | build_hpet(tables_blob, tables->linker); | |
711b20b4 | 2210 | } |
5cb18b3d | 2211 | if (misc.tpm_version != TPM_VERSION_UNSPEC) { |
7e7c1b84 SB |
2212 | if (misc.tpm_version == TPM_VERSION_1_2) { |
2213 | acpi_add_table(table_offsets, tables_blob); | |
2214 | build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); | |
2215 | } else { /* TPM_VERSION_2_0 */ | |
72d97b3a | 2216 | acpi_add_table(table_offsets, tables_blob); |
4a42fa0e | 2217 | build_tpm2(tables_blob, tables->linker, tables->tcpalog); |
5cb18b3d | 2218 | } |
72c194f7 | 2219 | } |
dd4c2f01 | 2220 | if (pcms->numa_nodes) { |
7c2c1fa5 | 2221 | acpi_add_table(table_offsets, tables_blob); |
3d3ebcad | 2222 | build_srat(tables_blob, tables->linker, machine); |
118154b7 | 2223 | if (machine->numa_state->have_numa_distance) { |
0f203430 | 2224 | acpi_add_table(table_offsets, tables_blob); |
aa570207 | 2225 | build_slit(tables_blob, tables->linker, machine); |
0f203430 | 2226 | } |
e6f123c3 LJ |
2227 | if (machine->numa_state->hmat_enabled) { |
2228 | acpi_add_table(table_offsets, tables_blob); | |
2229 | build_hmat(tables_blob, tables->linker, machine->numa_state); | |
2230 | } | |
72c194f7 MT |
2231 | } |
2232 | if (acpi_get_mcfg(&mcfg)) { | |
7c2c1fa5 | 2233 | acpi_add_table(table_offsets, tables_blob); |
f13a944c | 2234 | build_mcfg(tables_blob, tables->linker, &mcfg); |
72c194f7 | 2235 | } |
fb9f5926 DK |
2236 | if (x86_iommu_get_default()) { |
2237 | IommuType IOMMUType = x86_iommu_get_type(); | |
2238 | if (IOMMUType == TYPE_AMD) { | |
2239 | acpi_add_table(table_offsets, tables_blob); | |
2240 | build_amd_iommu(tables_blob, tables->linker); | |
2241 | } else if (IOMMUType == TYPE_INTEL) { | |
2242 | acpi_add_table(table_offsets, tables_blob); | |
2243 | build_dmar_q35(tables_blob, tables->linker); | |
2244 | } | |
d4eb9119 | 2245 | } |
f6a0d06b | 2246 | if (machine->nvdimms_state->is_enabled) { |
ad9671b8 | 2247 | nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, |
f6a0d06b | 2248 | machine->nvdimms_state, machine->ram_slots); |
87252e1b XG |
2249 | } |
2250 | ||
14cda350 LA |
2251 | acpi_add_table(table_offsets, tables_blob); |
2252 | build_waet(tables_blob, tables->linker); | |
2253 | ||
72c194f7 MT |
2254 | /* Add tables supplied by user (if any) */ |
2255 | for (u = acpi_table_first(); u; u = acpi_table_next(u)) { | |
2256 | unsigned len = acpi_table_len(u); | |
2257 | ||
7c2c1fa5 IM |
2258 | acpi_add_table(table_offsets, tables_blob); |
2259 | g_array_append_vals(tables_blob, u, len); | |
72c194f7 MT |
2260 | } |
2261 | ||
2262 | /* RSDT is pointed to by RSDP */ | |
7c2c1fa5 | 2263 | rsdt = tables_blob->len; |
ae123749 LE |
2264 | build_rsdt(tables_blob, tables->linker, table_offsets, |
2265 | slic_oem.id, slic_oem.table_id); | |
72c194f7 MT |
2266 | |
2267 | /* RSDP is in FSEG memory, so allocate it separately */ | |
a46ce1c2 SO |
2268 | { |
2269 | AcpiRsdpData rsdp_data = { | |
2270 | .revision = 0, | |
2271 | .oem_id = ACPI_BUILD_APPNAME6, | |
2272 | .xsdt_tbl_offset = NULL, | |
2273 | .rsdt_tbl_offset = &rsdt, | |
2274 | }; | |
2275 | build_rsdp(tables->rsdp, tables->linker, &rsdp_data); | |
2276 | if (!pcmc->rsdp_in_ram) { | |
2277 | /* We used to allocate some extra space for RSDP revision 2 but | |
2278 | * only used the RSDP revision 0 space. The extra bytes were | |
2279 | * zeroed out and not used. | |
2280 | * Here we continue wasting those extra 16 bytes to make sure we | |
2281 | * don't break migration for machine types 2.2 and older due to | |
2282 | * RSDP blob size mismatch. | |
2283 | */ | |
2284 | build_append_int_noprefix(tables->rsdp, 0, 16); | |
2285 | } | |
2286 | } | |
72c194f7 | 2287 | |
07fb6176 | 2288 | /* We'll expose it all to Guest so we want to reduce |
72c194f7 | 2289 | * chance of size changes. |
07fb6176 PB |
2290 | * |
2291 | * We used to align the tables to 4k, but of course this would | |
2292 | * too simple to be enough. 4k turned out to be too small an | |
2293 | * alignment very soon, and in fact it is almost impossible to | |
2294 | * keep the table size stable for all (max_cpus, max_memory_slots) | |
2295 | * combinations. So the table size is always 64k for pc-i440fx-2.1 | |
2296 | * and we give an error if the table grows beyond that limit. | |
2297 | * | |
2298 | * We still have the problem of migrating from "-M pc-i440fx-2.0". For | |
2299 | * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables | |
2300 | * than 2.0 and we can always pad the smaller tables with zeros. We can | |
2301 | * then use the exact size of the 2.0 tables. | |
2302 | * | |
2303 | * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. | |
72c194f7 | 2304 | */ |
bb292f5a | 2305 | if (pcmc->legacy_acpi_table_size) { |
07fb6176 PB |
2306 | /* Subtracting aml_len gives the size of fixed tables. Then add the |
2307 | * size of the PIIX4 DSDT/SSDT in QEMU 2.0. | |
2308 | */ | |
2309 | int legacy_aml_len = | |
bb292f5a | 2310 | pcmc->legacy_acpi_table_size + |
f0bb276b | 2311 | ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; |
07fb6176 | 2312 | int legacy_table_size = |
7c2c1fa5 | 2313 | ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, |
07fb6176 | 2314 | ACPI_BUILD_ALIGN_SIZE); |
7c2c1fa5 | 2315 | if (tables_blob->len > legacy_table_size) { |
07fb6176 | 2316 | /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ |
9e5d2c52 AF |
2317 | warn_report("ACPI table size %u exceeds %d bytes," |
2318 | " migration may not work", | |
2319 | tables_blob->len, legacy_table_size); | |
2320 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
2321 | " or PCI bridges."); | |
07fb6176 | 2322 | } |
7c2c1fa5 | 2323 | g_array_set_size(tables_blob, legacy_table_size); |
07fb6176 | 2324 | } else { |
868270f2 | 2325 | /* Make sure we have a buffer in case we need to resize the tables. */ |
7c2c1fa5 | 2326 | if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { |
18045fb9 | 2327 | /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ |
9e5d2c52 AF |
2328 | warn_report("ACPI table size %u exceeds %d bytes," |
2329 | " migration may not work", | |
2330 | tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); | |
2331 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
2332 | " or PCI bridges."); | |
18045fb9 | 2333 | } |
7c2c1fa5 | 2334 | acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); |
07fb6176 | 2335 | } |
72c194f7 | 2336 | |
0e9b9eda | 2337 | acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); |
72c194f7 MT |
2338 | |
2339 | /* Cleanup memory that's no longer used. */ | |
2340 | g_array_free(table_offsets, true); | |
2341 | } | |
2342 | ||
339240b5 | 2343 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) |
42d85900 MT |
2344 | { |
2345 | uint32_t size = acpi_data_len(data); | |
2346 | ||
2347 | /* Make sure RAM size is correct - in case it got changed e.g. by migration */ | |
339240b5 | 2348 | memory_region_ram_resize(mr, size, &error_abort); |
42d85900 | 2349 | |
339240b5 PB |
2350 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); |
2351 | memory_region_set_dirty(mr, 0, size); | |
42d85900 MT |
2352 | } |
2353 | ||
3f8752b4 | 2354 | static void acpi_build_update(void *build_opaque) |
72c194f7 MT |
2355 | { |
2356 | AcpiBuildState *build_state = build_opaque; | |
2357 | AcpiBuildTables tables; | |
2358 | ||
2359 | /* No state to update or already patched? Nothing to do. */ | |
2360 | if (!build_state || build_state->patched) { | |
2361 | return; | |
2362 | } | |
2363 | build_state->patched = 1; | |
2364 | ||
2365 | acpi_build_tables_init(&tables); | |
2366 | ||
3d3ebcad | 2367 | acpi_build(&tables, MACHINE(qdev_get_machine())); |
72c194f7 | 2368 | |
339240b5 | 2369 | acpi_ram_update(build_state->table_mr, tables.table_data); |
a1666142 | 2370 | |
42d85900 MT |
2371 | if (build_state->rsdp) { |
2372 | memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); | |
2373 | } else { | |
339240b5 | 2374 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); |
42d85900 | 2375 | } |
ad5b88b1 | 2376 | |
0e9b9eda | 2377 | acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); |
72c194f7 MT |
2378 | acpi_build_tables_cleanup(&tables, true); |
2379 | } | |
2380 | ||
2381 | static void acpi_build_reset(void *build_opaque) | |
2382 | { | |
2383 | AcpiBuildState *build_state = build_opaque; | |
2384 | build_state->patched = 0; | |
2385 | } | |
2386 | ||
72c194f7 MT |
2387 | static const VMStateDescription vmstate_acpi_build = { |
2388 | .name = "acpi_build", | |
2389 | .version_id = 1, | |
2390 | .minimum_version_id = 1, | |
d49805ae | 2391 | .fields = (VMStateField[]) { |
72c194f7 MT |
2392 | VMSTATE_UINT8(patched, AcpiBuildState), |
2393 | VMSTATE_END_OF_LIST() | |
2394 | }, | |
2395 | }; | |
2396 | ||
fb306ffe | 2397 | void acpi_setup(void) |
72c194f7 | 2398 | { |
fb306ffe | 2399 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); |
bb292f5a | 2400 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 2401 | X86MachineState *x86ms = X86_MACHINE(pcms); |
72c194f7 MT |
2402 | AcpiBuildTables tables; |
2403 | AcpiBuildState *build_state; | |
d03637bc | 2404 | Object *vmgenid_dev; |
0fe24669 SB |
2405 | TPMIf *tpm; |
2406 | static FwCfgTPMConfig tpm_config; | |
72c194f7 | 2407 | |
f0bb276b | 2408 | if (!x86ms->fw_cfg) { |
8b310fc4 | 2409 | ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); |
72c194f7 MT |
2410 | return; |
2411 | } | |
2412 | ||
021746c1 | 2413 | if (!pcms->acpi_build_enabled) { |
8b310fc4 | 2414 | ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); |
72c194f7 MT |
2415 | return; |
2416 | } | |
2417 | ||
17e89077 | 2418 | if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { |
8b310fc4 | 2419 | ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); |
81adc513 MT |
2420 | return; |
2421 | } | |
2422 | ||
72c194f7 MT |
2423 | build_state = g_malloc0(sizeof *build_state); |
2424 | ||
72c194f7 | 2425 | acpi_build_tables_init(&tables); |
3d3ebcad | 2426 | acpi_build(&tables, MACHINE(pcms)); |
72c194f7 MT |
2427 | |
2428 | /* Now expose it all to Guest */ | |
82f76c67 WY |
2429 | build_state->table_mr = acpi_add_rom_blob(acpi_build_update, |
2430 | build_state, tables.table_data, | |
2431 | ACPI_BUILD_TABLE_FILE, | |
2432 | ACPI_BUILD_TABLE_MAX_SIZE); | |
339240b5 | 2433 | assert(build_state->table_mr != NULL); |
72c194f7 | 2434 | |
339240b5 | 2435 | build_state->linker_mr = |
82f76c67 | 2436 | acpi_add_rom_blob(acpi_build_update, build_state, |
bac78f9c | 2437 | tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); |
72c194f7 | 2438 | |
f0bb276b | 2439 | fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, |
42a5b308 SB |
2440 | tables.tcpalog->data, acpi_data_len(tables.tcpalog)); |
2441 | ||
0fe24669 SB |
2442 | tpm = tpm_find(); |
2443 | if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { | |
2444 | tpm_config = (FwCfgTPMConfig) { | |
2445 | .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), | |
2446 | .tpm_version = tpm_get_version(tpm), | |
ac6dd31e | 2447 | .tpmppi_version = TPM_PPI_VERSION_1_30 |
0fe24669 | 2448 | }; |
f0bb276b | 2449 | fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", |
0fe24669 SB |
2450 | &tpm_config, sizeof tpm_config); |
2451 | } | |
2452 | ||
d03637bc BW |
2453 | vmgenid_dev = find_vmgenid_dev(); |
2454 | if (vmgenid_dev) { | |
f0bb276b | 2455 | vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, |
d03637bc BW |
2456 | tables.vmgenid); |
2457 | } | |
2458 | ||
bb292f5a | 2459 | if (!pcmc->rsdp_in_ram) { |
358774d7 IM |
2460 | /* |
2461 | * Keep for compatibility with old machine types. | |
2462 | * Though RSDP is small, its contents isn't immutable, so | |
afaa2e4b | 2463 | * we'll update it along with the rest of tables on guest access. |
358774d7 | 2464 | */ |
afaa2e4b MT |
2465 | uint32_t rsdp_size = acpi_data_len(tables.rsdp); |
2466 | ||
2467 | build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); | |
f0bb276b | 2468 | fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, |
5f9252f7 | 2469 | acpi_build_update, NULL, build_state, |
baf2d5bf | 2470 | build_state->rsdp, rsdp_size, true); |
339240b5 | 2471 | build_state->rsdp_mr = NULL; |
358774d7 | 2472 | } else { |
42d85900 | 2473 | build_state->rsdp = NULL; |
82f76c67 WY |
2474 | build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, |
2475 | build_state, tables.rsdp, | |
2476 | ACPI_BUILD_RSDP_FILE, 0); | |
358774d7 | 2477 | } |
72c194f7 MT |
2478 | |
2479 | qemu_register_reset(acpi_build_reset, build_state); | |
2480 | acpi_build_reset(build_state); | |
2481 | vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); | |
2482 | ||
2483 | /* Cleanup tables but don't free the memory: we track it | |
2484 | * in build_state. | |
2485 | */ | |
2486 | acpi_build_tables_cleanup(&tables, false); | |
2487 | } |