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72c194f7 MT |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
4 | * Copyright (C) 2006 Fabrice Bellard | |
5 | * Copyright (C) 2013 Red Hat Inc | |
6 | * | |
7 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | ||
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | ||
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include "acpi-build.h" | |
24 | #include <stddef.h> | |
25 | #include <glib.h> | |
26 | #include "qemu-common.h" | |
27 | #include "qemu/bitmap.h" | |
07fb6176 | 28 | #include "qemu/osdep.h" |
07fb6176 | 29 | #include "qemu/error-report.h" |
72c194f7 MT |
30 | #include "hw/pci/pci.h" |
31 | #include "qom/cpu.h" | |
32 | #include "hw/i386/pc.h" | |
33 | #include "target-i386/cpu.h" | |
34 | #include "hw/timer/hpet.h" | |
395e5fb4 | 35 | #include "hw/acpi/acpi-defs.h" |
72c194f7 MT |
36 | #include "hw/acpi/acpi.h" |
37 | #include "hw/nvram/fw_cfg.h" | |
0058ae1d | 38 | #include "hw/acpi/bios-linker-loader.h" |
72c194f7 | 39 | #include "hw/loader.h" |
15bce1b7 | 40 | #include "hw/isa/isa.h" |
bef3492d | 41 | #include "hw/acpi/memory_hotplug.h" |
711b20b4 SB |
42 | #include "sysemu/tpm.h" |
43 | #include "hw/acpi/tpm.h" | |
5cb18b3d | 44 | #include "sysemu/tpm_backend.h" |
72c194f7 MT |
45 | |
46 | /* Supported chipsets: */ | |
47 | #include "hw/acpi/piix4.h" | |
99fd437d | 48 | #include "hw/acpi/pcihp.h" |
72c194f7 MT |
49 | #include "hw/i386/ich9.h" |
50 | #include "hw/pci/pci_bus.h" | |
51 | #include "hw/pci-host/q35.h" | |
d4eb9119 | 52 | #include "hw/i386/intel_iommu.h" |
72c194f7 MT |
53 | |
54 | #include "hw/i386/q35-acpi-dsdt.hex" | |
55 | #include "hw/i386/acpi-dsdt.hex" | |
56 | ||
19934e0e IM |
57 | #include "hw/acpi/aml-build.h" |
58 | ||
72c194f7 MT |
59 | #include "qapi/qmp/qint.h" |
60 | #include "qom/qom-qobject.h" | |
61 | ||
07fb6176 PB |
62 | /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and |
63 | * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows | |
64 | * a little bit, there should be plenty of free space since the DSDT | |
65 | * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. | |
66 | */ | |
67 | #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 | |
68 | #define ACPI_BUILD_ALIGN_SIZE 0x1000 | |
69 | ||
868270f2 | 70 | #define ACPI_BUILD_TABLE_SIZE 0x20000 |
18045fb9 | 71 | |
8b310fc4 GA |
72 | /* #define DEBUG_ACPI_BUILD */ |
73 | #ifdef DEBUG_ACPI_BUILD | |
74 | #define ACPI_BUILD_DPRINTF(fmt, ...) \ | |
75 | do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) | |
76 | #else | |
77 | #define ACPI_BUILD_DPRINTF(fmt, ...) | |
78 | #endif | |
79 | ||
72c194f7 | 80 | typedef struct AcpiCpuInfo { |
798325ed | 81 | DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); |
72c194f7 MT |
82 | } AcpiCpuInfo; |
83 | ||
84 | typedef struct AcpiMcfgInfo { | |
85 | uint64_t mcfg_base; | |
86 | uint32_t mcfg_size; | |
87 | } AcpiMcfgInfo; | |
88 | ||
89 | typedef struct AcpiPmInfo { | |
90 | bool s3_disabled; | |
91 | bool s4_disabled; | |
133a2da4 | 92 | bool pcihp_bridge_en; |
72c194f7 MT |
93 | uint8_t s4_val; |
94 | uint16_t sci_int; | |
95 | uint8_t acpi_enable_cmd; | |
96 | uint8_t acpi_disable_cmd; | |
97 | uint32_t gpe0_blk; | |
98 | uint32_t gpe0_blk_len; | |
99 | uint32_t io_base; | |
ddf1ec2f IM |
100 | uint16_t cpu_hp_io_base; |
101 | uint16_t cpu_hp_io_len; | |
2c6b94d8 IM |
102 | uint16_t mem_hp_io_base; |
103 | uint16_t mem_hp_io_len; | |
500b11ea IM |
104 | uint16_t pcihp_io_base; |
105 | uint16_t pcihp_io_len; | |
72c194f7 MT |
106 | } AcpiPmInfo; |
107 | ||
108 | typedef struct AcpiMiscInfo { | |
109 | bool has_hpet; | |
5cb18b3d | 110 | TPMVersion tpm_version; |
72c194f7 MT |
111 | const unsigned char *dsdt_code; |
112 | unsigned dsdt_size; | |
113 | uint16_t pvpanic_port; | |
8ac6f7a6 | 114 | uint16_t applesmc_io_base; |
72c194f7 MT |
115 | } AcpiMiscInfo; |
116 | ||
99fd437d MT |
117 | typedef struct AcpiBuildPciBusHotplugState { |
118 | GArray *device_table; | |
119 | GArray *notify_table; | |
120 | struct AcpiBuildPciBusHotplugState *parent; | |
133a2da4 | 121 | bool pcihp_bridge_en; |
99fd437d MT |
122 | } AcpiBuildPciBusHotplugState; |
123 | ||
72c194f7 MT |
124 | static void acpi_get_dsdt(AcpiMiscInfo *info) |
125 | { | |
126 | Object *piix = piix4_pm_find(); | |
127 | Object *lpc = ich9_lpc_find(); | |
128 | assert(!!piix != !!lpc); | |
129 | ||
130 | if (piix) { | |
131 | info->dsdt_code = AcpiDsdtAmlCode; | |
132 | info->dsdt_size = sizeof AcpiDsdtAmlCode; | |
133 | } | |
134 | if (lpc) { | |
135 | info->dsdt_code = Q35AcpiDsdtAmlCode; | |
136 | info->dsdt_size = sizeof Q35AcpiDsdtAmlCode; | |
137 | } | |
138 | } | |
139 | ||
140 | static | |
141 | int acpi_add_cpu_info(Object *o, void *opaque) | |
142 | { | |
143 | AcpiCpuInfo *cpu = opaque; | |
144 | uint64_t apic_id; | |
145 | ||
146 | if (object_dynamic_cast(o, TYPE_CPU)) { | |
147 | apic_id = object_property_get_int(o, "apic-id", NULL); | |
798325ed | 148 | assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); |
72c194f7 MT |
149 | |
150 | set_bit(apic_id, cpu->found_cpus); | |
151 | } | |
152 | ||
153 | object_child_foreach(o, acpi_add_cpu_info, opaque); | |
154 | return 0; | |
155 | } | |
156 | ||
157 | static void acpi_get_cpu_info(AcpiCpuInfo *cpu) | |
158 | { | |
159 | Object *root = object_get_root(); | |
160 | ||
161 | memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); | |
162 | object_child_foreach(root, acpi_add_cpu_info, cpu); | |
163 | } | |
164 | ||
165 | static void acpi_get_pm_info(AcpiPmInfo *pm) | |
166 | { | |
167 | Object *piix = piix4_pm_find(); | |
168 | Object *lpc = ich9_lpc_find(); | |
169 | Object *obj = NULL; | |
170 | QObject *o; | |
171 | ||
500b11ea IM |
172 | pm->pcihp_io_base = 0; |
173 | pm->pcihp_io_len = 0; | |
72c194f7 MT |
174 | if (piix) { |
175 | obj = piix; | |
ddf1ec2f | 176 | pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; |
500b11ea IM |
177 | pm->pcihp_io_base = |
178 | object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); | |
179 | pm->pcihp_io_len = | |
180 | object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); | |
72c194f7 MT |
181 | } |
182 | if (lpc) { | |
183 | obj = lpc; | |
ddf1ec2f | 184 | pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; |
72c194f7 MT |
185 | } |
186 | assert(obj); | |
187 | ||
ddf1ec2f | 188 | pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; |
2c6b94d8 IM |
189 | pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; |
190 | pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; | |
191 | ||
72c194f7 MT |
192 | /* Fill in optional s3/s4 related properties */ |
193 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); | |
194 | if (o) { | |
195 | pm->s3_disabled = qint_get_int(qobject_to_qint(o)); | |
196 | } else { | |
197 | pm->s3_disabled = false; | |
198 | } | |
097a97a6 | 199 | qobject_decref(o); |
72c194f7 MT |
200 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); |
201 | if (o) { | |
202 | pm->s4_disabled = qint_get_int(qobject_to_qint(o)); | |
203 | } else { | |
204 | pm->s4_disabled = false; | |
205 | } | |
097a97a6 | 206 | qobject_decref(o); |
72c194f7 MT |
207 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); |
208 | if (o) { | |
209 | pm->s4_val = qint_get_int(qobject_to_qint(o)); | |
210 | } else { | |
211 | pm->s4_val = false; | |
212 | } | |
097a97a6 | 213 | qobject_decref(o); |
72c194f7 MT |
214 | |
215 | /* Fill in mandatory properties */ | |
216 | pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); | |
217 | ||
218 | pm->acpi_enable_cmd = object_property_get_int(obj, | |
219 | ACPI_PM_PROP_ACPI_ENABLE_CMD, | |
220 | NULL); | |
221 | pm->acpi_disable_cmd = object_property_get_int(obj, | |
222 | ACPI_PM_PROP_ACPI_DISABLE_CMD, | |
223 | NULL); | |
224 | pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, | |
225 | NULL); | |
226 | pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, | |
227 | NULL); | |
228 | pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, | |
229 | NULL); | |
133a2da4 IM |
230 | pm->pcihp_bridge_en = |
231 | object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", | |
232 | NULL); | |
72c194f7 MT |
233 | } |
234 | ||
72c194f7 MT |
235 | static void acpi_get_misc_info(AcpiMiscInfo *info) |
236 | { | |
237 | info->has_hpet = hpet_find(); | |
5cb18b3d | 238 | info->tpm_version = tpm_get_version(); |
72c194f7 | 239 | info->pvpanic_port = pvpanic_port(); |
8ac6f7a6 | 240 | info->applesmc_io_base = applesmc_port(); |
72c194f7 MT |
241 | } |
242 | ||
ca6c1855 MA |
243 | /* |
244 | * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. | |
245 | * On i386 arch we only have two pci hosts, so we can look only for them. | |
246 | */ | |
247 | static Object *acpi_get_i386_pci_host(void) | |
248 | { | |
249 | PCIHostState *host; | |
250 | ||
251 | host = OBJECT_CHECK(PCIHostState, | |
252 | object_resolve_path("/machine/i440fx", NULL), | |
253 | TYPE_PCI_HOST_BRIDGE); | |
254 | if (!host) { | |
255 | host = OBJECT_CHECK(PCIHostState, | |
256 | object_resolve_path("/machine/q35", NULL), | |
257 | TYPE_PCI_HOST_BRIDGE); | |
258 | } | |
259 | ||
260 | return OBJECT(host); | |
261 | } | |
262 | ||
72c194f7 MT |
263 | static void acpi_get_pci_info(PcPciInfo *info) |
264 | { | |
265 | Object *pci_host; | |
72c194f7 | 266 | |
ca6c1855 MA |
267 | |
268 | pci_host = acpi_get_i386_pci_host(); | |
72c194f7 MT |
269 | g_assert(pci_host); |
270 | ||
271 | info->w32.begin = object_property_get_int(pci_host, | |
272 | PCI_HOST_PROP_PCI_HOLE_START, | |
273 | NULL); | |
274 | info->w32.end = object_property_get_int(pci_host, | |
275 | PCI_HOST_PROP_PCI_HOLE_END, | |
276 | NULL); | |
277 | info->w64.begin = object_property_get_int(pci_host, | |
278 | PCI_HOST_PROP_PCI_HOLE64_START, | |
279 | NULL); | |
280 | info->w64.end = object_property_get_int(pci_host, | |
281 | PCI_HOST_PROP_PCI_HOLE64_END, | |
282 | NULL); | |
283 | } | |
284 | ||
72c194f7 MT |
285 | #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ |
286 | ||
72c194f7 MT |
287 | static void acpi_align_size(GArray *blob, unsigned align) |
288 | { | |
289 | /* Align size to multiple of given size. This reduces the chance | |
290 | * we need to change size in the future (breaking cross version migration). | |
291 | */ | |
134d42d6 | 292 | g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); |
72c194f7 MT |
293 | } |
294 | ||
72c194f7 MT |
295 | /* FACS */ |
296 | static void | |
297 | build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) | |
298 | { | |
299 | AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); | |
821e3227 | 300 | memcpy(&facs->signature, "FACS", 4); |
72c194f7 MT |
301 | facs->length = cpu_to_le32(sizeof(*facs)); |
302 | } | |
303 | ||
304 | /* Load chipset information in FADT */ | |
305 | static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) | |
306 | { | |
307 | fadt->model = 1; | |
308 | fadt->reserved1 = 0; | |
309 | fadt->sci_int = cpu_to_le16(pm->sci_int); | |
310 | fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); | |
311 | fadt->acpi_enable = pm->acpi_enable_cmd; | |
312 | fadt->acpi_disable = pm->acpi_disable_cmd; | |
313 | /* EVT, CNT, TMR offset matches hw/acpi/core.c */ | |
314 | fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); | |
315 | fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); | |
316 | fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); | |
317 | fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); | |
318 | /* EVT, CNT, TMR length matches hw/acpi/core.c */ | |
319 | fadt->pm1_evt_len = 4; | |
320 | fadt->pm1_cnt_len = 2; | |
321 | fadt->pm_tmr_len = 4; | |
322 | fadt->gpe0_blk_len = pm->gpe0_blk_len; | |
323 | fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ | |
324 | fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ | |
325 | fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | | |
326 | (1 << ACPI_FADT_F_PROC_C1) | | |
327 | (1 << ACPI_FADT_F_SLP_BUTTON) | | |
328 | (1 << ACPI_FADT_F_RTC_S4)); | |
329 | fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); | |
07b81ed9 HZ |
330 | /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs |
331 | * For more than 8 CPUs, "Clustered Logical" mode has to be used | |
332 | */ | |
333 | if (max_cpus > 8) { | |
334 | fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); | |
335 | } | |
72c194f7 MT |
336 | } |
337 | ||
338 | ||
339 | /* FADT */ | |
340 | static void | |
341 | build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, | |
342 | unsigned facs, unsigned dsdt) | |
343 | { | |
344 | AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); | |
345 | ||
346 | fadt->firmware_ctrl = cpu_to_le32(facs); | |
347 | /* FACS address to be filled by Guest linker */ | |
348 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, | |
349 | ACPI_BUILD_TABLE_FILE, | |
350 | table_data, &fadt->firmware_ctrl, | |
351 | sizeof fadt->firmware_ctrl); | |
352 | ||
353 | fadt->dsdt = cpu_to_le32(dsdt); | |
354 | /* DSDT address to be filled by Guest linker */ | |
355 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, | |
356 | ACPI_BUILD_TABLE_FILE, | |
357 | table_data, &fadt->dsdt, | |
358 | sizeof fadt->dsdt); | |
359 | ||
360 | fadt_setup(fadt, pm); | |
361 | ||
362 | build_header(linker, table_data, | |
821e3227 | 363 | (void *)fadt, "FACP", sizeof(*fadt), 1); |
72c194f7 MT |
364 | } |
365 | ||
366 | static void | |
367 | build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, | |
368 | PcGuestInfo *guest_info) | |
369 | { | |
370 | int madt_start = table_data->len; | |
371 | ||
372 | AcpiMultipleApicTable *madt; | |
373 | AcpiMadtIoApic *io_apic; | |
374 | AcpiMadtIntsrcovr *intsrcovr; | |
375 | AcpiMadtLocalNmi *local_nmi; | |
376 | int i; | |
377 | ||
378 | madt = acpi_data_push(table_data, sizeof *madt); | |
379 | madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); | |
380 | madt->flags = cpu_to_le32(1); | |
381 | ||
382 | for (i = 0; i < guest_info->apic_id_limit; i++) { | |
383 | AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); | |
384 | apic->type = ACPI_APIC_PROCESSOR; | |
385 | apic->length = sizeof(*apic); | |
386 | apic->processor_id = i; | |
387 | apic->local_apic_id = i; | |
388 | if (test_bit(i, cpu->found_cpus)) { | |
389 | apic->flags = cpu_to_le32(1); | |
390 | } else { | |
391 | apic->flags = cpu_to_le32(0); | |
392 | } | |
393 | } | |
394 | io_apic = acpi_data_push(table_data, sizeof *io_apic); | |
395 | io_apic->type = ACPI_APIC_IO; | |
396 | io_apic->length = sizeof(*io_apic); | |
397 | #define ACPI_BUILD_IOAPIC_ID 0x0 | |
398 | io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; | |
399 | io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); | |
400 | io_apic->interrupt = cpu_to_le32(0); | |
401 | ||
402 | if (guest_info->apic_xrupt_override) { | |
403 | intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); | |
404 | intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; | |
405 | intsrcovr->length = sizeof(*intsrcovr); | |
406 | intsrcovr->source = 0; | |
407 | intsrcovr->gsi = cpu_to_le32(2); | |
408 | intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ | |
409 | } | |
410 | for (i = 1; i < 16; i++) { | |
411 | #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) | |
412 | if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { | |
413 | /* No need for a INT source override structure. */ | |
414 | continue; | |
415 | } | |
416 | intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); | |
417 | intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; | |
418 | intsrcovr->length = sizeof(*intsrcovr); | |
419 | intsrcovr->source = i; | |
420 | intsrcovr->gsi = cpu_to_le32(i); | |
421 | intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ | |
422 | } | |
423 | ||
424 | local_nmi = acpi_data_push(table_data, sizeof *local_nmi); | |
425 | local_nmi->type = ACPI_APIC_LOCAL_NMI; | |
426 | local_nmi->length = sizeof(*local_nmi); | |
427 | local_nmi->processor_id = 0xff; /* all processors */ | |
428 | local_nmi->flags = cpu_to_le16(0); | |
429 | local_nmi->lint = 1; /* ACPI_LINT1 */ | |
430 | ||
431 | build_header(linker, table_data, | |
821e3227 | 432 | (void *)(table_data->data + madt_start), "APIC", |
72c194f7 MT |
433 | table_data->len - madt_start, 1); |
434 | } | |
435 | ||
711b20b4 | 436 | #include "hw/i386/ssdt-tpm.hex" |
5cb18b3d | 437 | #include "hw/i386/ssdt-tpm2.hex" |
72c194f7 | 438 | |
99fd437d MT |
439 | /* Assign BSEL property to all buses. In the future, this can be changed |
440 | * to only assign to buses that support hotplug. | |
441 | */ | |
442 | static void *acpi_set_bsel(PCIBus *bus, void *opaque) | |
443 | { | |
444 | unsigned *bsel_alloc = opaque; | |
445 | unsigned *bus_bsel; | |
446 | ||
39b888bd | 447 | if (qbus_is_hotpluggable(BUS(bus))) { |
99fd437d MT |
448 | bus_bsel = g_malloc(sizeof *bus_bsel); |
449 | ||
450 | *bus_bsel = (*bsel_alloc)++; | |
451 | object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, | |
452 | bus_bsel, NULL); | |
453 | } | |
454 | ||
455 | return bsel_alloc; | |
456 | } | |
457 | ||
458 | static void acpi_set_pci_info(void) | |
459 | { | |
460 | PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ | |
461 | unsigned bsel_alloc = 0; | |
462 | ||
463 | if (bus) { | |
464 | /* Scan all PCI buses. Set property to enable acpi based hotplug. */ | |
465 | pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); | |
466 | } | |
467 | } | |
468 | ||
62b52c26 | 469 | static void build_append_pcihp_notify_entry(Aml *method, int slot) |
99fd437d | 470 | { |
62b52c26 IM |
471 | Aml *if_ctx; |
472 | int32_t devfn = PCI_DEVFN(slot, 0); | |
473 | ||
474 | if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot))); | |
475 | aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); | |
476 | aml_append(method, if_ctx); | |
99fd437d MT |
477 | } |
478 | ||
62b52c26 | 479 | static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, |
b23046ab | 480 | bool pcihp_bridge_en) |
99fd437d | 481 | { |
62b52c26 | 482 | Aml *dev, *notify_method, *method; |
99fd437d | 483 | QObject *bsel; |
b23046ab IM |
484 | PCIBus *sec; |
485 | int i; | |
133a2da4 | 486 | |
99fd437d MT |
487 | bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); |
488 | if (bsel) { | |
62b52c26 IM |
489 | int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); |
490 | ||
491 | aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); | |
492 | notify_method = aml_method("DVNT", 2); | |
8dcf525a | 493 | } |
99fd437d | 494 | |
8dcf525a MT |
495 | for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { |
496 | DeviceClass *dc; | |
497 | PCIDeviceClass *pc; | |
498 | PCIDevice *pdev = bus->devices[i]; | |
499 | int slot = PCI_SLOT(i); | |
b23046ab | 500 | bool hotplug_enabled_dev; |
093a35e5 | 501 | bool bridge_in_acpi; |
99fd437d | 502 | |
8dcf525a | 503 | if (!pdev) { |
b23046ab | 504 | if (bsel) { /* add hotplug slots for non present devices */ |
62b52c26 IM |
505 | dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); |
506 | aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); | |
507 | aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); | |
508 | method = aml_method("_EJ0", 1); | |
509 | aml_append(method, | |
510 | aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) | |
511 | ); | |
512 | aml_append(dev, method); | |
513 | aml_append(parent_scope, dev); | |
514 | ||
515 | build_append_pcihp_notify_entry(notify_method, slot); | |
b23046ab | 516 | } |
8dcf525a MT |
517 | continue; |
518 | } | |
99fd437d | 519 | |
8dcf525a MT |
520 | pc = PCI_DEVICE_GET_CLASS(pdev); |
521 | dc = DEVICE_GET_CLASS(pdev); | |
99fd437d | 522 | |
093a35e5 MT |
523 | /* When hotplug for bridges is enabled, bridges are |
524 | * described in ACPI separately (see build_pci_bus_end). | |
525 | * In this case they aren't themselves hot-pluggable. | |
a20275fa | 526 | * Hotplugged bridges *are* hot-pluggable. |
093a35e5 | 527 | */ |
b23046ab IM |
528 | bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && |
529 | !DEVICE(pdev)->hotplugged; | |
530 | ||
531 | hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; | |
093a35e5 | 532 | |
b23046ab IM |
533 | if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { |
534 | continue; | |
99fd437d MT |
535 | } |
536 | ||
62b52c26 IM |
537 | /* start to compose PCI slot descriptor */ |
538 | dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); | |
539 | aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); | |
540 | ||
8dcf525a | 541 | if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { |
62b52c26 IM |
542 | /* add VGA specific AML methods */ |
543 | int s3d; | |
544 | ||
8dcf525a | 545 | if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { |
62b52c26 | 546 | s3d = 3; |
b23046ab | 547 | } else { |
62b52c26 | 548 | s3d = 0; |
99fd437d | 549 | } |
62b52c26 IM |
550 | |
551 | method = aml_method("_S1D", 0); | |
552 | aml_append(method, aml_return(aml_int(0))); | |
553 | aml_append(dev, method); | |
554 | ||
555 | method = aml_method("_S2D", 0); | |
556 | aml_append(method, aml_return(aml_int(0))); | |
557 | aml_append(dev, method); | |
558 | ||
559 | method = aml_method("_S3D", 0); | |
560 | aml_append(method, aml_return(aml_int(s3d))); | |
561 | aml_append(dev, method); | |
b23046ab | 562 | } else if (hotplug_enabled_dev) { |
62b52c26 IM |
563 | /* add _SUN/_EJ0 to make slot hotpluggable */ |
564 | aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); | |
99fd437d | 565 | |
62b52c26 IM |
566 | method = aml_method("_EJ0", 1); |
567 | aml_append(method, | |
568 | aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) | |
569 | ); | |
570 | aml_append(dev, method); | |
571 | ||
572 | if (bsel) { | |
573 | build_append_pcihp_notify_entry(notify_method, slot); | |
574 | } | |
b23046ab | 575 | } else if (bridge_in_acpi) { |
62b52c26 IM |
576 | /* |
577 | * device is coldplugged bridge, | |
578 | * add child device descriptions into its scope | |
579 | */ | |
b23046ab | 580 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); |
b23046ab | 581 | |
62b52c26 | 582 | build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); |
8dcf525a | 583 | } |
62b52c26 IM |
584 | /* slot descriptor has been composed, add it into parent context */ |
585 | aml_append(parent_scope, dev); | |
8dcf525a MT |
586 | } |
587 | ||
588 | if (bsel) { | |
62b52c26 | 589 | aml_append(parent_scope, notify_method); |
99fd437d MT |
590 | } |
591 | ||
592 | /* Append PCNT method to notify about events on local and child buses. | |
593 | * Add unconditionally for root since DSDT expects it. | |
72c194f7 | 594 | */ |
62b52c26 | 595 | method = aml_method("PCNT", 0); |
99fd437d | 596 | |
b23046ab IM |
597 | /* If bus supports hotplug select it and notify about local events */ |
598 | if (bsel) { | |
62b52c26 IM |
599 | int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); |
600 | aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); | |
601 | aml_append(method, | |
602 | aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) | |
603 | ); | |
604 | aml_append(method, | |
605 | aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) | |
606 | ); | |
b23046ab | 607 | } |
99fd437d | 608 | |
b23046ab IM |
609 | /* Notify about child bus events in any case */ |
610 | if (pcihp_bridge_en) { | |
611 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
62b52c26 IM |
612 | int32_t devfn = sec->parent_dev->devfn; |
613 | ||
614 | aml_append(method, aml_name("^S%.02X.PCNT", devfn)); | |
99fd437d | 615 | } |
72c194f7 | 616 | } |
62b52c26 | 617 | aml_append(parent_scope, method); |
72c194f7 MT |
618 | } |
619 | ||
0d8935e3 MA |
620 | /* |
621 | * initialize_route - Initialize the interrupt routing rule | |
622 | * through a specific LINK: | |
623 | * if (lnk_idx == idx) | |
624 | * route using link 'link_name' | |
625 | */ | |
626 | static Aml *initialize_route(Aml *route, const char *link_name, | |
627 | Aml *lnk_idx, int idx) | |
628 | { | |
629 | Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); | |
630 | Aml *pkg = aml_package(4); | |
631 | ||
632 | aml_append(pkg, aml_int(0)); | |
633 | aml_append(pkg, aml_int(0)); | |
634 | aml_append(pkg, aml_name("%s", link_name)); | |
635 | aml_append(pkg, aml_int(0)); | |
636 | aml_append(if_ctx, aml_store(pkg, route)); | |
637 | ||
638 | return if_ctx; | |
639 | } | |
640 | ||
641 | /* | |
642 | * build_prt - Define interrupt rounting rules | |
643 | * | |
644 | * Returns an array of 128 routes, one for each device, | |
645 | * based on device location. | |
646 | * The main goal is to equaly distribute the interrupts | |
647 | * over the 4 existing ACPI links (works only for i440fx). | |
648 | * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". | |
649 | * | |
650 | */ | |
651 | static Aml *build_prt(void) | |
652 | { | |
653 | Aml *method, *while_ctx, *pin, *res; | |
654 | ||
655 | method = aml_method("_PRT", 0); | |
656 | res = aml_local(0); | |
657 | pin = aml_local(1); | |
658 | aml_append(method, aml_store(aml_package(128), res)); | |
659 | aml_append(method, aml_store(aml_int(0), pin)); | |
660 | ||
661 | /* while (pin < 128) */ | |
662 | while_ctx = aml_while(aml_lless(pin, aml_int(128))); | |
663 | { | |
664 | Aml *slot = aml_local(2); | |
665 | Aml *lnk_idx = aml_local(3); | |
666 | Aml *route = aml_local(4); | |
667 | ||
668 | /* slot = pin >> 2 */ | |
669 | aml_append(while_ctx, | |
670 | aml_store(aml_shiftright(pin, aml_int(2)), slot)); | |
671 | /* lnk_idx = (slot + pin) & 3 */ | |
672 | aml_append(while_ctx, | |
673 | aml_store(aml_and(aml_add(pin, slot), aml_int(3)), lnk_idx)); | |
674 | ||
675 | /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ | |
676 | aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); | |
677 | aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); | |
678 | aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); | |
679 | aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); | |
680 | ||
681 | /* route[0] = 0x[slot]FFFF */ | |
682 | aml_append(while_ctx, | |
683 | aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF)), | |
684 | aml_index(route, aml_int(0)))); | |
685 | /* route[1] = pin & 3 */ | |
686 | aml_append(while_ctx, | |
687 | aml_store(aml_and(pin, aml_int(3)), aml_index(route, aml_int(1)))); | |
688 | /* res[pin] = route */ | |
689 | aml_append(while_ctx, aml_store(route, aml_index(res, pin))); | |
690 | /* pin++ */ | |
691 | aml_append(while_ctx, aml_increment(pin)); | |
692 | } | |
693 | aml_append(method, while_ctx); | |
694 | /* return res*/ | |
695 | aml_append(method, aml_return(res)); | |
696 | ||
697 | return method; | |
698 | } | |
699 | ||
a43c6e27 MA |
700 | typedef struct CrsRangeEntry { |
701 | uint64_t base; | |
702 | uint64_t limit; | |
703 | } CrsRangeEntry; | |
704 | ||
705 | static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) | |
706 | { | |
707 | CrsRangeEntry *entry; | |
708 | ||
709 | entry = g_malloc(sizeof(*entry)); | |
710 | entry->base = base; | |
711 | entry->limit = limit; | |
712 | ||
713 | g_ptr_array_add(ranges, entry); | |
714 | } | |
715 | ||
716 | static void crs_range_free(gpointer data) | |
717 | { | |
718 | CrsRangeEntry *entry = (CrsRangeEntry *)data; | |
719 | g_free(entry); | |
720 | } | |
721 | ||
722 | static Aml *build_crs(PCIHostState *host, | |
723 | GPtrArray *io_ranges, GPtrArray *mem_ranges) | |
724 | { | |
725 | Aml *crs = aml_resource_template(); | |
726 | uint8_t max_bus = pci_bus_num(host->bus); | |
727 | uint8_t type; | |
728 | int devfn; | |
729 | ||
730 | for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { | |
731 | int i; | |
732 | uint64_t range_base, range_limit; | |
733 | PCIDevice *dev = host->bus->devices[devfn]; | |
734 | ||
735 | if (!dev) { | |
736 | continue; | |
737 | } | |
738 | ||
739 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
740 | PCIIORegion *r = &dev->io_regions[i]; | |
741 | ||
742 | range_base = r->addr; | |
743 | range_limit = r->addr + r->size - 1; | |
744 | ||
745 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { | |
746 | aml_append(crs, | |
747 | aml_word_io(aml_min_fixed, aml_max_fixed, | |
748 | aml_pos_decode, aml_entire_range, | |
749 | 0, | |
750 | range_base, | |
751 | range_limit, | |
752 | 0, | |
753 | range_limit - range_base + 1)); | |
754 | crs_range_insert(io_ranges, range_base, range_limit); | |
755 | } else { /* "memory" */ | |
756 | aml_append(crs, | |
757 | aml_dword_memory(aml_pos_decode, aml_min_fixed, | |
758 | aml_max_fixed, aml_non_cacheable, | |
759 | aml_ReadWrite, | |
760 | 0, | |
761 | range_base, | |
762 | range_limit, | |
763 | 0, | |
764 | range_limit - range_base + 1)); | |
765 | crs_range_insert(mem_ranges, range_base, range_limit); | |
766 | } | |
767 | } | |
768 | ||
769 | type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
770 | if (type == PCI_HEADER_TYPE_BRIDGE) { | |
771 | uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; | |
772 | if (subordinate > max_bus) { | |
773 | max_bus = subordinate; | |
774 | } | |
775 | ||
776 | range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); | |
777 | range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); | |
778 | aml_append(crs, | |
779 | aml_word_io(aml_min_fixed, aml_max_fixed, | |
780 | aml_pos_decode, aml_entire_range, | |
781 | 0, | |
782 | range_base, | |
783 | range_limit, | |
784 | 0, | |
785 | range_limit - range_base + 1)); | |
786 | crs_range_insert(io_ranges, range_base, range_limit); | |
787 | ||
788 | range_base = | |
789 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
790 | range_limit = | |
791 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
792 | aml_append(crs, | |
793 | aml_dword_memory(aml_pos_decode, aml_min_fixed, | |
794 | aml_max_fixed, aml_non_cacheable, | |
795 | aml_ReadWrite, | |
796 | 0, | |
797 | range_base, | |
798 | range_limit, | |
799 | 0, | |
800 | range_limit - range_base + 1)); | |
801 | crs_range_insert(mem_ranges, range_base, range_limit); | |
802 | ||
803 | range_base = | |
804 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
805 | range_limit = | |
806 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
807 | aml_append(crs, | |
808 | aml_dword_memory(aml_pos_decode, aml_min_fixed, | |
809 | aml_max_fixed, aml_non_cacheable, | |
810 | aml_ReadWrite, | |
811 | 0, | |
812 | range_base, | |
813 | range_limit, | |
814 | 0, | |
815 | range_limit - range_base + 1)); | |
816 | crs_range_insert(mem_ranges, range_base, range_limit); | |
817 | } | |
818 | } | |
819 | ||
820 | aml_append(crs, | |
821 | aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode, | |
822 | 0, | |
823 | pci_bus_num(host->bus), | |
824 | max_bus, | |
825 | 0, | |
826 | max_bus - pci_bus_num(host->bus) + 1)); | |
827 | ||
828 | return crs; | |
829 | } | |
830 | ||
72c194f7 MT |
831 | static void |
832 | build_ssdt(GArray *table_data, GArray *linker, | |
833 | AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, | |
834 | PcPciInfo *pci, PcGuestInfo *guest_info) | |
835 | { | |
bef3492d IM |
836 | MachineState *machine = MACHINE(qdev_get_machine()); |
837 | uint32_t nr_mem = machine->ram_slots; | |
2fd71f1b | 838 | unsigned acpi_cpus = guest_info->apic_id_limit; |
20843d16 | 839 | Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx; |
a4894206 | 840 | PCIBus *bus = NULL; |
a43c6e27 MA |
841 | GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free); |
842 | GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); | |
72c194f7 MT |
843 | int i; |
844 | ||
011bb749 | 845 | ssdt = init_aml_allocator(); |
2fd71f1b LE |
846 | /* The current AML generator can cover the APIC ID range [0..255], |
847 | * inclusive, for VCPU hotplug. */ | |
848 | QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); | |
849 | g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); | |
850 | ||
4ec8d2b3 IM |
851 | /* Reserve space for header */ |
852 | acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); | |
72c194f7 | 853 | |
a4894206 MA |
854 | /* Extra PCI root buses are implemented only for i440fx */ |
855 | bus = find_i440fx(); | |
856 | if (bus) { | |
857 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
858 | uint8_t bus_num = pci_bus_num(bus); | |
859 | ||
860 | /* look only for expander root buses */ | |
861 | if (!pci_bus_is_root(bus)) { | |
862 | continue; | |
863 | } | |
864 | ||
865 | scope = aml_scope("\\_SB"); | |
866 | dev = aml_device("PC%.02X", bus_num); | |
867 | aml_append(dev, | |
868 | aml_name_decl("_UID", aml_string("PC%.02X", bus_num))); | |
869 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A03"))); | |
870 | aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); | |
0d8935e3 | 871 | aml_append(dev, build_prt()); |
a43c6e27 MA |
872 | crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), |
873 | io_ranges, mem_ranges); | |
874 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
a4894206 MA |
875 | aml_append(scope, dev); |
876 | aml_append(ssdt, scope); | |
877 | } | |
a43c6e27 MA |
878 | |
879 | g_ptr_array_free(io_ranges, true); | |
880 | g_ptr_array_free(mem_ranges, true); | |
a4894206 MA |
881 | } |
882 | ||
500b11ea | 883 | scope = aml_scope("\\_SB.PCI0"); |
60efd429 IM |
884 | /* build PCI0._CRS */ |
885 | crs = aml_resource_template(); | |
886 | aml_append(crs, | |
ff80dc7f | 887 | aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, |
60efd429 | 888 | 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); |
ff80dc7f | 889 | aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); |
60efd429 IM |
890 | |
891 | aml_append(crs, | |
ff80dc7f SZ |
892 | aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, |
893 | AML_POS_DECODE, AML_ENTIRE_RANGE, | |
60efd429 | 894 | 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); |
d31c909e | 895 | aml_append(crs, |
ff80dc7f SZ |
896 | aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, |
897 | AML_POS_DECODE, AML_ENTIRE_RANGE, | |
d31c909e | 898 | 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); |
60efd429 | 899 | aml_append(crs, |
ff80dc7f SZ |
900 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, |
901 | AML_CACHEABLE, AML_READ_WRITE, | |
60efd429 IM |
902 | 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); |
903 | aml_append(crs, | |
ff80dc7f SZ |
904 | aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, |
905 | AML_NON_CACHEABLE, AML_READ_WRITE, | |
60efd429 IM |
906 | 0, pci->w32.begin, pci->w32.end - 1, 0, |
907 | pci->w32.end - pci->w32.begin)); | |
908 | if (pci->w64.begin) { | |
909 | aml_append(crs, | |
ff80dc7f SZ |
910 | aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, |
911 | AML_CACHEABLE, AML_READ_WRITE, | |
60efd429 IM |
912 | 0, pci->w64.begin, pci->w64.end - 1, 0, |
913 | pci->w64.end - pci->w64.begin)); | |
914 | } | |
915 | aml_append(scope, aml_name_decl("_CRS", crs)); | |
916 | ||
d31c909e IM |
917 | /* reserve GPE0 block resources */ |
918 | dev = aml_device("GPE0"); | |
919 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
920 | aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); | |
921 | /* device present, functioning, decoding, not shown in UI */ | |
922 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
923 | crs = aml_resource_template(); | |
924 | aml_append(crs, | |
ff80dc7f | 925 | aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) |
d31c909e IM |
926 | ); |
927 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
928 | aml_append(scope, dev); | |
929 | ||
500b11ea IM |
930 | /* reserve PCIHP resources */ |
931 | if (pm->pcihp_io_len) { | |
932 | dev = aml_device("PHPR"); | |
933 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
934 | aml_append(dev, | |
935 | aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); | |
936 | /* device present, functioning, decoding, not shown in UI */ | |
937 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
938 | crs = aml_resource_template(); | |
939 | aml_append(crs, | |
ff80dc7f | 940 | aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, |
500b11ea IM |
941 | pm->pcihp_io_len) |
942 | ); | |
943 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
944 | aml_append(scope, dev); | |
945 | } | |
946 | aml_append(ssdt, scope); | |
947 | ||
ebc3028f IM |
948 | /* create S3_ / S4_ / S5_ packages if necessary */ |
949 | scope = aml_scope("\\"); | |
950 | if (!pm->s3_disabled) { | |
951 | pkg = aml_package(4); | |
952 | aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ | |
953 | aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
954 | aml_append(pkg, aml_int(0)); /* reserved */ | |
955 | aml_append(pkg, aml_int(0)); /* reserved */ | |
956 | aml_append(scope, aml_name_decl("_S3", pkg)); | |
957 | } | |
958 | ||
959 | if (!pm->s4_disabled) { | |
960 | pkg = aml_package(4); | |
961 | aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ | |
962 | /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
963 | aml_append(pkg, aml_int(pm->s4_val)); | |
964 | aml_append(pkg, aml_int(0)); /* reserved */ | |
965 | aml_append(pkg, aml_int(0)); /* reserved */ | |
966 | aml_append(scope, aml_name_decl("_S4", pkg)); | |
967 | } | |
968 | ||
969 | pkg = aml_package(4); | |
970 | aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ | |
971 | aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ | |
972 | aml_append(pkg, aml_int(0)); /* reserved */ | |
973 | aml_append(pkg, aml_int(0)); /* reserved */ | |
974 | aml_append(scope, aml_name_decl("_S5", pkg)); | |
975 | aml_append(ssdt, scope); | |
976 | ||
8ac6f7a6 IM |
977 | if (misc->applesmc_io_base) { |
978 | scope = aml_scope("\\_SB.PCI0.ISA"); | |
979 | dev = aml_device("SMC"); | |
980 | ||
981 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); | |
982 | /* device present, functioning, decoding, not shown in UI */ | |
983 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
984 | ||
985 | crs = aml_resource_template(); | |
986 | aml_append(crs, | |
ff80dc7f | 987 | aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, |
8ac6f7a6 IM |
988 | 0x01, APPLESMC_MAX_DATA_LENGTH) |
989 | ); | |
990 | aml_append(crs, aml_irq_no_flags(6)); | |
991 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
992 | ||
993 | aml_append(scope, dev); | |
994 | aml_append(ssdt, scope); | |
995 | } | |
996 | ||
cd61cb2e IM |
997 | if (misc->pvpanic_port) { |
998 | scope = aml_scope("\\_SB.PCI0.ISA"); | |
999 | ||
2332333c | 1000 | dev = aml_device("PEVT"); |
e65bef69 | 1001 | aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); |
cd61cb2e IM |
1002 | |
1003 | crs = aml_resource_template(); | |
1004 | aml_append(crs, | |
ff80dc7f | 1005 | aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) |
cd61cb2e IM |
1006 | ); |
1007 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1008 | ||
ff80dc7f | 1009 | aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, |
cd61cb2e | 1010 | misc->pvpanic_port, 1)); |
ff80dc7f | 1011 | field = aml_field("PEOR", AML_BYTE_ACC, AML_PRESERVE); |
cd61cb2e IM |
1012 | aml_append(field, aml_named_field("PEPT", 8)); |
1013 | aml_append(dev, field); | |
1014 | ||
2332333c RK |
1015 | /* device present, functioning, decoding, not shown in UI */ |
1016 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1017 | ||
cd61cb2e IM |
1018 | method = aml_method("RDPT", 0); |
1019 | aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); | |
1020 | aml_append(method, aml_return(aml_local(0))); | |
1021 | aml_append(dev, method); | |
1022 | ||
1023 | method = aml_method("WRPT", 1); | |
1024 | aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); | |
1025 | aml_append(dev, method); | |
1026 | ||
1027 | aml_append(scope, dev); | |
1028 | aml_append(ssdt, scope); | |
1029 | } | |
1030 | ||
7824df38 | 1031 | sb_scope = aml_scope("\\_SB"); |
72c194f7 | 1032 | { |
ddf1ec2f IM |
1033 | /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ |
1034 | dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); | |
1035 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); | |
1036 | aml_append(dev, | |
1037 | aml_name_decl("_UID", aml_string("CPU Hotplug resources")) | |
1038 | ); | |
1039 | /* device present, functioning, decoding, not shown in UI */ | |
1040 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1041 | crs = aml_resource_template(); | |
1042 | aml_append(crs, | |
ff80dc7f | 1043 | aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, |
ddf1ec2f IM |
1044 | pm->cpu_hp_io_len) |
1045 | ); | |
1046 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1047 | aml_append(sb_scope, dev); | |
1048 | /* declare CPU hotplug MMIO region and PRS field to access it */ | |
1049 | aml_append(sb_scope, aml_operation_region( | |
ff80dc7f SZ |
1050 | "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); |
1051 | field = aml_field("PRST", AML_BYTE_ACC, AML_PRESERVE); | |
ddf1ec2f IM |
1052 | aml_append(field, aml_named_field("PRS", 256)); |
1053 | aml_append(sb_scope, field); | |
1054 | ||
72c194f7 MT |
1055 | /* build Processor object for each processor */ |
1056 | for (i = 0; i < acpi_cpus; i++) { | |
20843d16 IM |
1057 | dev = aml_processor(i, 0, 0, "CP%.02X", i); |
1058 | ||
1059 | method = aml_method("_MAT", 0); | |
1060 | aml_append(method, aml_return(aml_call1("CPMA", aml_int(i)))); | |
1061 | aml_append(dev, method); | |
1062 | ||
1063 | method = aml_method("_STA", 0); | |
1064 | aml_append(method, aml_return(aml_call1("CPST", aml_int(i)))); | |
1065 | aml_append(dev, method); | |
1066 | ||
1067 | method = aml_method("_EJ0", 1); | |
1068 | aml_append(method, | |
1069 | aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0))) | |
1070 | ); | |
1071 | aml_append(dev, method); | |
1072 | ||
1073 | aml_append(sb_scope, dev); | |
72c194f7 MT |
1074 | } |
1075 | ||
1076 | /* build this code: | |
1077 | * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} | |
1078 | */ | |
1079 | /* Arg0 = Processor ID = APIC ID */ | |
20843d16 IM |
1080 | method = aml_method("NTFY", 2); |
1081 | for (i = 0; i < acpi_cpus; i++) { | |
1082 | ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); | |
1083 | aml_append(ifctx, | |
1084 | aml_notify(aml_name("CP%.02X", i), aml_arg(1)) | |
1085 | ); | |
1086 | aml_append(method, ifctx); | |
1087 | } | |
1088 | aml_append(sb_scope, method); | |
1089 | ||
1090 | /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" | |
1091 | * | |
1092 | * Note: The ability to create variable-sized packages was first | |
e71fd764 | 1093 | * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages |
20843d16 IM |
1094 | * ith up to 255 elements. Windows guests up to win2k8 fail when |
1095 | * VarPackageOp is used. | |
1096 | */ | |
1097 | pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : | |
1098 | aml_varpackage(acpi_cpus); | |
72c194f7 | 1099 | |
20843d16 IM |
1100 | for (i = 0; i < acpi_cpus; i++) { |
1101 | uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; | |
1102 | aml_append(pkg, aml_int(b)); | |
72c194f7 | 1103 | } |
20843d16 | 1104 | aml_append(sb_scope, aml_name_decl("CPON", pkg)); |
72c194f7 | 1105 | |
8698c0c0 IM |
1106 | /* build memory devices */ |
1107 | assert(nr_mem <= ACPI_MAX_RAM_SLOTS); | |
2c6b94d8 IM |
1108 | scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); |
1109 | aml_append(scope, | |
1110 | aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) | |
1111 | ); | |
1112 | ||
1113 | crs = aml_resource_template(); | |
1114 | aml_append(crs, | |
ff80dc7f | 1115 | aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, |
2c6b94d8 IM |
1116 | pm->mem_hp_io_len) |
1117 | ); | |
1118 | aml_append(scope, aml_name_decl("_CRS", crs)); | |
1119 | ||
1120 | aml_append(scope, aml_operation_region( | |
ff80dc7f | 1121 | stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO, |
2c6b94d8 IM |
1122 | pm->mem_hp_io_base, pm->mem_hp_io_len) |
1123 | ); | |
1124 | ||
ff80dc7f SZ |
1125 | field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, |
1126 | AML_PRESERVE); | |
2c6b94d8 IM |
1127 | aml_append(field, /* read only */ |
1128 | aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); | |
1129 | aml_append(field, /* read only */ | |
1130 | aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); | |
1131 | aml_append(field, /* read only */ | |
1132 | aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); | |
1133 | aml_append(field, /* read only */ | |
1134 | aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); | |
1135 | aml_append(field, /* read only */ | |
1136 | aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); | |
1137 | aml_append(scope, field); | |
1138 | ||
ff80dc7f SZ |
1139 | field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC, |
1140 | AML_WRITE_AS_ZEROS); | |
2c6b94d8 IM |
1141 | aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); |
1142 | aml_append(field, /* 1 if enabled, read only */ | |
1143 | aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); | |
1144 | aml_append(field, | |
1145 | /*(read) 1 if has a insert event. (write) 1 to clear event */ | |
1146 | aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); | |
c06b2ffb ZG |
1147 | aml_append(field, |
1148 | /* (read) 1 if has a remove event. (write) 1 to clear event */ | |
1149 | aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1)); | |
1150 | aml_append(field, | |
1151 | /* initiates device eject, write only */ | |
1152 | aml_named_field(stringify(MEMORY_SLOT_EJECT), 1)); | |
2c6b94d8 IM |
1153 | aml_append(scope, field); |
1154 | ||
ff80dc7f SZ |
1155 | field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, |
1156 | AML_PRESERVE); | |
2c6b94d8 IM |
1157 | aml_append(field, /* DIMM selector, write only */ |
1158 | aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); | |
1159 | aml_append(field, /* _OST event code, write only */ | |
1160 | aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); | |
1161 | aml_append(field, /* _OST status code, write only */ | |
1162 | aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); | |
1163 | aml_append(scope, field); | |
1164 | ||
1165 | aml_append(sb_scope, scope); | |
8698c0c0 IM |
1166 | |
1167 | for (i = 0; i < nr_mem; i++) { | |
1168 | #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "." | |
1169 | const char *s; | |
1170 | ||
1171 | dev = aml_device("MP%02X", i); | |
1172 | aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); | |
1173 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); | |
bef3492d | 1174 | |
8698c0c0 IM |
1175 | method = aml_method("_CRS", 0); |
1176 | s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD); | |
1177 | aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); | |
1178 | aml_append(dev, method); | |
1179 | ||
1180 | method = aml_method("_STA", 0); | |
1181 | s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD); | |
1182 | aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); | |
1183 | aml_append(dev, method); | |
1184 | ||
1185 | method = aml_method("_PXM", 0); | |
1186 | s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD); | |
1187 | aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); | |
1188 | aml_append(dev, method); | |
1189 | ||
1190 | method = aml_method("_OST", 3); | |
1191 | s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD); | |
1192 | aml_append(method, aml_return(aml_call4( | |
1193 | s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) | |
1194 | ))); | |
1195 | aml_append(dev, method); | |
1196 | ||
c06b2ffb ZG |
1197 | method = aml_method("_EJ0", 1); |
1198 | s = BASEPATH stringify(MEMORY_SLOT_EJECT_METHOD); | |
1199 | aml_append(method, aml_return(aml_call2( | |
1200 | s, aml_name("_UID"), aml_arg(0)))); | |
1201 | aml_append(dev, method); | |
1202 | ||
8698c0c0 | 1203 | aml_append(sb_scope, dev); |
bef3492d IM |
1204 | } |
1205 | ||
8698c0c0 | 1206 | /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { |
853cff8e | 1207 | * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } |
8698c0c0 IM |
1208 | */ |
1209 | method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2); | |
1210 | for (i = 0; i < nr_mem; i++) { | |
1211 | ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); | |
1212 | aml_append(ifctx, | |
1213 | aml_notify(aml_name("MP%.02X", i), aml_arg(1)) | |
1214 | ); | |
1215 | aml_append(method, ifctx); | |
1216 | } | |
1217 | aml_append(sb_scope, method); | |
1218 | ||
72c194f7 | 1219 | { |
8dcf525a MT |
1220 | Object *pci_host; |
1221 | PCIBus *bus = NULL; | |
8dcf525a | 1222 | |
ca6c1855 MA |
1223 | pci_host = acpi_get_i386_pci_host(); |
1224 | if (pci_host) { | |
8dcf525a MT |
1225 | bus = PCI_HOST_BRIDGE(pci_host)->bus; |
1226 | } | |
72c194f7 | 1227 | |
99fd437d | 1228 | if (bus) { |
62b52c26 | 1229 | Aml *scope = aml_scope("PCI0"); |
99fd437d | 1230 | /* Scan all PCI buses. Generate tables to support hotplug. */ |
62b52c26 IM |
1231 | build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); |
1232 | aml_append(sb_scope, scope); | |
72c194f7 | 1233 | } |
72c194f7 | 1234 | } |
011bb749 | 1235 | aml_append(ssdt, sb_scope); |
72c194f7 MT |
1236 | } |
1237 | ||
011bb749 IM |
1238 | /* copy AML table into ACPI tables blob and patch header there */ |
1239 | g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); | |
72c194f7 | 1240 | build_header(linker, table_data, |
011bb749 IM |
1241 | (void *)(table_data->data + table_data->len - ssdt->buf->len), |
1242 | "SSDT", ssdt->buf->len, 1); | |
1243 | free_aml_allocator(); | |
72c194f7 MT |
1244 | } |
1245 | ||
1246 | static void | |
1247 | build_hpet(GArray *table_data, GArray *linker) | |
1248 | { | |
1249 | Acpi20Hpet *hpet; | |
1250 | ||
1251 | hpet = acpi_data_push(table_data, sizeof(*hpet)); | |
1252 | /* Note timer_block_id value must be kept in sync with value advertised by | |
1253 | * emulated hpet | |
1254 | */ | |
1255 | hpet->timer_block_id = cpu_to_le32(0x8086a201); | |
1256 | hpet->addr.address = cpu_to_le64(HPET_BASE); | |
1257 | build_header(linker, table_data, | |
821e3227 | 1258 | (void *)hpet, "HPET", sizeof(*hpet), 1); |
72c194f7 MT |
1259 | } |
1260 | ||
711b20b4 | 1261 | static void |
42a5b308 | 1262 | build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) |
711b20b4 SB |
1263 | { |
1264 | Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); | |
42a5b308 | 1265 | uint64_t log_area_start_address = acpi_data_len(tcpalog); |
711b20b4 SB |
1266 | |
1267 | tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); | |
1268 | tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); | |
1269 | tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); | |
1270 | ||
42a5b308 SB |
1271 | bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, |
1272 | false /* high memory */); | |
1273 | ||
711b20b4 SB |
1274 | /* log area start address to be filled by Guest linker */ |
1275 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, | |
42a5b308 | 1276 | ACPI_BUILD_TPMLOG_FILE, |
711b20b4 SB |
1277 | table_data, &tcpa->log_area_start_address, |
1278 | sizeof(tcpa->log_area_start_address)); | |
1279 | ||
1280 | build_header(linker, table_data, | |
1281 | (void *)tcpa, "TCPA", sizeof(*tcpa), 2); | |
1282 | ||
42a5b308 | 1283 | acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); |
711b20b4 SB |
1284 | } |
1285 | ||
1286 | static void | |
1287 | build_tpm_ssdt(GArray *table_data, GArray *linker) | |
1288 | { | |
1289 | void *tpm_ptr; | |
1290 | ||
1291 | tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml)); | |
1292 | memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml)); | |
1293 | } | |
1294 | ||
5cb18b3d SB |
1295 | static void |
1296 | build_tpm2(GArray *table_data, GArray *linker) | |
1297 | { | |
1298 | Acpi20TPM2 *tpm2_ptr; | |
1299 | void *tpm_ptr; | |
1300 | ||
1301 | tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm2_aml)); | |
1302 | memcpy(tpm_ptr, ssdt_tpm2_aml, sizeof(ssdt_tpm2_aml)); | |
1303 | ||
1304 | tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); | |
1305 | ||
1306 | tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); | |
1307 | tpm2_ptr->control_area_address = cpu_to_le64(0); | |
1308 | tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); | |
1309 | ||
1310 | build_header(linker, table_data, | |
1311 | (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4); | |
1312 | } | |
1313 | ||
04ed3ea8 IM |
1314 | typedef enum { |
1315 | MEM_AFFINITY_NOFLAGS = 0, | |
1316 | MEM_AFFINITY_ENABLED = (1 << 0), | |
1317 | MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), | |
1318 | MEM_AFFINITY_NON_VOLATILE = (1 << 2), | |
1319 | } MemoryAffinityFlags; | |
1320 | ||
72c194f7 | 1321 | static void |
04ed3ea8 IM |
1322 | acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, |
1323 | uint64_t len, int node, MemoryAffinityFlags flags) | |
72c194f7 MT |
1324 | { |
1325 | numamem->type = ACPI_SRAT_MEMORY; | |
1326 | numamem->length = sizeof(*numamem); | |
1327 | memset(numamem->proximity, 0, 4); | |
1328 | numamem->proximity[0] = node; | |
04ed3ea8 | 1329 | numamem->flags = cpu_to_le32(flags); |
72c194f7 MT |
1330 | numamem->base_addr = cpu_to_le64(base); |
1331 | numamem->range_length = cpu_to_le64(len); | |
1332 | } | |
1333 | ||
1334 | static void | |
dd0247e0 | 1335 | build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) |
72c194f7 MT |
1336 | { |
1337 | AcpiSystemResourceAffinityTable *srat; | |
1338 | AcpiSratProcessorAffinity *core; | |
1339 | AcpiSratMemoryAffinity *numamem; | |
1340 | ||
1341 | int i; | |
1342 | uint64_t curnode; | |
1343 | int srat_start, numa_start, slots; | |
1344 | uint64_t mem_len, mem_base, next_base; | |
cec65193 IM |
1345 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); |
1346 | ram_addr_t hotplugabble_address_space_size = | |
1347 | object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, | |
1348 | NULL); | |
72c194f7 MT |
1349 | |
1350 | srat_start = table_data->len; | |
1351 | ||
1352 | srat = acpi_data_push(table_data, sizeof *srat); | |
1353 | srat->reserved1 = cpu_to_le32(1); | |
1354 | core = (void *)(srat + 1); | |
1355 | ||
1356 | for (i = 0; i < guest_info->apic_id_limit; ++i) { | |
1357 | core = acpi_data_push(table_data, sizeof *core); | |
1358 | core->type = ACPI_SRAT_PROCESSOR; | |
1359 | core->length = sizeof(*core); | |
1360 | core->local_apic_id = i; | |
1361 | curnode = guest_info->node_cpu[i]; | |
1362 | core->proximity_lo = curnode; | |
1363 | memset(core->proximity_hi, 0, 3); | |
1364 | core->local_sapic_eid = 0; | |
dd0247e0 | 1365 | core->flags = cpu_to_le32(1); |
72c194f7 MT |
1366 | } |
1367 | ||
1368 | ||
1369 | /* the memory map is a bit tricky, it contains at least one hole | |
1370 | * from 640k-1M and possibly another one from 3.5G-4G. | |
1371 | */ | |
1372 | next_base = 0; | |
1373 | numa_start = table_data->len; | |
1374 | ||
1375 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
04ed3ea8 | 1376 | acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); |
72c194f7 MT |
1377 | next_base = 1024 * 1024; |
1378 | for (i = 1; i < guest_info->numa_nodes + 1; ++i) { | |
1379 | mem_base = next_base; | |
1380 | mem_len = guest_info->node_mem[i - 1]; | |
1381 | if (i == 1) { | |
1382 | mem_len -= 1024 * 1024; | |
1383 | } | |
1384 | next_base = mem_base + mem_len; | |
1385 | ||
1386 | /* Cut out the ACPI_PCI hole */ | |
4c8a949b EH |
1387 | if (mem_base <= guest_info->ram_size_below_4g && |
1388 | next_base > guest_info->ram_size_below_4g) { | |
1389 | mem_len -= next_base - guest_info->ram_size_below_4g; | |
72c194f7 MT |
1390 | if (mem_len > 0) { |
1391 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
04ed3ea8 IM |
1392 | acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, |
1393 | MEM_AFFINITY_ENABLED); | |
72c194f7 MT |
1394 | } |
1395 | mem_base = 1ULL << 32; | |
4c8a949b EH |
1396 | mem_len = next_base - guest_info->ram_size_below_4g; |
1397 | next_base += (1ULL << 32) - guest_info->ram_size_below_4g; | |
72c194f7 MT |
1398 | } |
1399 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
04ed3ea8 IM |
1400 | acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, |
1401 | MEM_AFFINITY_ENABLED); | |
72c194f7 MT |
1402 | } |
1403 | slots = (table_data->len - numa_start) / sizeof *numamem; | |
1404 | for (; slots < guest_info->numa_nodes + 2; slots++) { | |
1405 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
04ed3ea8 | 1406 | acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); |
72c194f7 MT |
1407 | } |
1408 | ||
cec65193 IM |
1409 | /* |
1410 | * Entry is required for Windows to enable memory hotplug in OS. | |
1411 | * Memory devices may override proximity set by this entry, | |
1412 | * providing _PXM method if necessary. | |
1413 | */ | |
1414 | if (hotplugabble_address_space_size) { | |
1415 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
1416 | acpi_build_srat_memory(numamem, pcms->hotplug_memory_base, | |
1417 | hotplugabble_address_space_size, 0, | |
1418 | MEM_AFFINITY_HOTPLUGGABLE | | |
1419 | MEM_AFFINITY_ENABLED); | |
1420 | } | |
1421 | ||
72c194f7 MT |
1422 | build_header(linker, table_data, |
1423 | (void *)(table_data->data + srat_start), | |
821e3227 | 1424 | "SRAT", |
72c194f7 MT |
1425 | table_data->len - srat_start, 1); |
1426 | } | |
1427 | ||
1428 | static void | |
1429 | build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) | |
1430 | { | |
1431 | AcpiTableMcfg *mcfg; | |
821e3227 | 1432 | const char *sig; |
72c194f7 MT |
1433 | int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); |
1434 | ||
1435 | mcfg = acpi_data_push(table_data, len); | |
1436 | mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); | |
1437 | /* Only a single allocation so no need to play with segments */ | |
1438 | mcfg->allocation[0].pci_segment = cpu_to_le16(0); | |
1439 | mcfg->allocation[0].start_bus_number = 0; | |
1440 | mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); | |
1441 | ||
1442 | /* MCFG is used for ECAM which can be enabled or disabled by guest. | |
1443 | * To avoid table size changes (which create migration issues), | |
1444 | * always create the table even if there are no allocations, | |
1445 | * but set the signature to a reserved value in this case. | |
1446 | * ACPI spec requires OSPMs to ignore such tables. | |
1447 | */ | |
1448 | if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { | |
821e3227 MT |
1449 | /* Reserved signature: ignored by OSPM */ |
1450 | sig = "QEMU"; | |
72c194f7 | 1451 | } else { |
821e3227 | 1452 | sig = "MCFG"; |
72c194f7 MT |
1453 | } |
1454 | build_header(linker, table_data, (void *)mcfg, sig, len, 1); | |
1455 | } | |
1456 | ||
d4eb9119 LT |
1457 | static void |
1458 | build_dmar_q35(GArray *table_data, GArray *linker) | |
1459 | { | |
1460 | int dmar_start = table_data->len; | |
1461 | ||
1462 | AcpiTableDmar *dmar; | |
1463 | AcpiDmarHardwareUnit *drhd; | |
1464 | ||
1465 | dmar = acpi_data_push(table_data, sizeof(*dmar)); | |
1466 | dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; | |
1467 | dmar->flags = 0; /* No intr_remap for now */ | |
1468 | ||
1469 | /* DMAR Remapping Hardware Unit Definition structure */ | |
1470 | drhd = acpi_data_push(table_data, sizeof(*drhd)); | |
1471 | drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); | |
1472 | drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ | |
1473 | drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; | |
1474 | drhd->pci_segment = cpu_to_le16(0); | |
1475 | drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); | |
1476 | ||
1477 | build_header(linker, table_data, (void *)(table_data->data + dmar_start), | |
1478 | "DMAR", table_data->len - dmar_start, 1); | |
1479 | } | |
1480 | ||
72c194f7 MT |
1481 | static void |
1482 | build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) | |
1483 | { | |
53db092a MT |
1484 | AcpiTableHeader *dsdt; |
1485 | ||
72c194f7 | 1486 | assert(misc->dsdt_code && misc->dsdt_size); |
53db092a | 1487 | |
72c194f7 MT |
1488 | dsdt = acpi_data_push(table_data, misc->dsdt_size); |
1489 | memcpy(dsdt, misc->dsdt_code, misc->dsdt_size); | |
53db092a MT |
1490 | |
1491 | memset(dsdt, 0, sizeof *dsdt); | |
821e3227 | 1492 | build_header(linker, table_data, dsdt, "DSDT", |
53db092a | 1493 | misc->dsdt_size, 1); |
72c194f7 MT |
1494 | } |
1495 | ||
72c194f7 MT |
1496 | static GArray * |
1497 | build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) | |
1498 | { | |
1499 | AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); | |
1500 | ||
d67aadcc | 1501 | bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, |
72c194f7 MT |
1502 | true /* fseg memory */); |
1503 | ||
821e3227 | 1504 | memcpy(&rsdp->signature, "RSD PTR ", 8); |
72c194f7 MT |
1505 | memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); |
1506 | rsdp->rsdt_physical_address = cpu_to_le32(rsdt); | |
1507 | /* Address to be filled by Guest linker */ | |
1508 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, | |
1509 | ACPI_BUILD_TABLE_FILE, | |
1510 | rsdp_table, &rsdp->rsdt_physical_address, | |
1511 | sizeof rsdp->rsdt_physical_address); | |
1512 | rsdp->checksum = 0; | |
1513 | /* Checksum to be filled by Guest linker */ | |
1514 | bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, | |
1515 | rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); | |
1516 | ||
1517 | return rsdp_table; | |
1518 | } | |
1519 | ||
72c194f7 MT |
1520 | typedef |
1521 | struct AcpiBuildState { | |
1522 | /* Copy of table in RAM (for patching). */ | |
339240b5 | 1523 | MemoryRegion *table_mr; |
72c194f7 MT |
1524 | /* Is table patched? */ |
1525 | uint8_t patched; | |
1526 | PcGuestInfo *guest_info; | |
d70414a5 | 1527 | void *rsdp; |
339240b5 PB |
1528 | MemoryRegion *rsdp_mr; |
1529 | MemoryRegion *linker_mr; | |
72c194f7 MT |
1530 | } AcpiBuildState; |
1531 | ||
1532 | static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) | |
1533 | { | |
1534 | Object *pci_host; | |
1535 | QObject *o; | |
72c194f7 | 1536 | |
ca6c1855 | 1537 | pci_host = acpi_get_i386_pci_host(); |
72c194f7 MT |
1538 | g_assert(pci_host); |
1539 | ||
1540 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); | |
1541 | if (!o) { | |
1542 | return false; | |
1543 | } | |
1544 | mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); | |
097a97a6 | 1545 | qobject_decref(o); |
72c194f7 MT |
1546 | |
1547 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); | |
1548 | assert(o); | |
1549 | mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); | |
097a97a6 | 1550 | qobject_decref(o); |
72c194f7 MT |
1551 | return true; |
1552 | } | |
1553 | ||
d4eb9119 LT |
1554 | static bool acpi_has_iommu(void) |
1555 | { | |
1556 | bool ambiguous; | |
1557 | Object *intel_iommu; | |
1558 | ||
1559 | intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, | |
1560 | &ambiguous); | |
1561 | return intel_iommu && !ambiguous; | |
1562 | } | |
1563 | ||
72c194f7 MT |
1564 | static |
1565 | void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) | |
1566 | { | |
1567 | GArray *table_offsets; | |
07fb6176 | 1568 | unsigned facs, ssdt, dsdt, rsdt; |
72c194f7 MT |
1569 | AcpiCpuInfo cpu; |
1570 | AcpiPmInfo pm; | |
1571 | AcpiMiscInfo misc; | |
1572 | AcpiMcfgInfo mcfg; | |
1573 | PcPciInfo pci; | |
1574 | uint8_t *u; | |
07fb6176 | 1575 | size_t aml_len = 0; |
7c2c1fa5 | 1576 | GArray *tables_blob = tables->table_data; |
72c194f7 MT |
1577 | |
1578 | acpi_get_cpu_info(&cpu); | |
1579 | acpi_get_pm_info(&pm); | |
1580 | acpi_get_dsdt(&misc); | |
72c194f7 MT |
1581 | acpi_get_misc_info(&misc); |
1582 | acpi_get_pci_info(&pci); | |
1583 | ||
1584 | table_offsets = g_array_new(false, true /* clear */, | |
1585 | sizeof(uint32_t)); | |
8b310fc4 | 1586 | ACPI_BUILD_DPRINTF("init ACPI tables\n"); |
72c194f7 MT |
1587 | |
1588 | bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, | |
1589 | 64 /* Ensure FACS is aligned */, | |
1590 | false /* high memory */); | |
1591 | ||
1592 | /* | |
1593 | * FACS is pointed to by FADT. | |
1594 | * We place it first since it's the only table that has alignment | |
1595 | * requirements. | |
1596 | */ | |
7c2c1fa5 IM |
1597 | facs = tables_blob->len; |
1598 | build_facs(tables_blob, tables->linker, guest_info); | |
72c194f7 MT |
1599 | |
1600 | /* DSDT is pointed to by FADT */ | |
7c2c1fa5 IM |
1601 | dsdt = tables_blob->len; |
1602 | build_dsdt(tables_blob, tables->linker, &misc); | |
72c194f7 | 1603 | |
07fb6176 PB |
1604 | /* Count the size of the DSDT and SSDT, we will need it for legacy |
1605 | * sizing of ACPI tables. | |
1606 | */ | |
7c2c1fa5 | 1607 | aml_len += tables_blob->len - dsdt; |
07fb6176 | 1608 | |
72c194f7 | 1609 | /* ACPI tables pointed to by RSDT */ |
7c2c1fa5 IM |
1610 | acpi_add_table(table_offsets, tables_blob); |
1611 | build_fadt(tables_blob, tables->linker, &pm, facs, dsdt); | |
72c194f7 | 1612 | |
7c2c1fa5 IM |
1613 | ssdt = tables_blob->len; |
1614 | acpi_add_table(table_offsets, tables_blob); | |
1615 | build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, | |
72c194f7 | 1616 | guest_info); |
7c2c1fa5 | 1617 | aml_len += tables_blob->len - ssdt; |
72c194f7 | 1618 | |
7c2c1fa5 IM |
1619 | acpi_add_table(table_offsets, tables_blob); |
1620 | build_madt(tables_blob, tables->linker, &cpu, guest_info); | |
9ac1c4c0 | 1621 | |
72c194f7 | 1622 | if (misc.has_hpet) { |
7c2c1fa5 IM |
1623 | acpi_add_table(table_offsets, tables_blob); |
1624 | build_hpet(tables_blob, tables->linker); | |
711b20b4 | 1625 | } |
5cb18b3d | 1626 | if (misc.tpm_version != TPM_VERSION_UNSPEC) { |
7c2c1fa5 IM |
1627 | acpi_add_table(table_offsets, tables_blob); |
1628 | build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); | |
711b20b4 | 1629 | |
7c2c1fa5 | 1630 | acpi_add_table(table_offsets, tables_blob); |
5cb18b3d SB |
1631 | switch (misc.tpm_version) { |
1632 | case TPM_VERSION_1_2: | |
1633 | build_tpm_ssdt(tables_blob, tables->linker); | |
1634 | break; | |
1635 | case TPM_VERSION_2_0: | |
1636 | build_tpm2(tables_blob, tables->linker); | |
1637 | break; | |
1638 | default: | |
1639 | assert(false); | |
1640 | } | |
72c194f7 MT |
1641 | } |
1642 | if (guest_info->numa_nodes) { | |
7c2c1fa5 IM |
1643 | acpi_add_table(table_offsets, tables_blob); |
1644 | build_srat(tables_blob, tables->linker, guest_info); | |
72c194f7 MT |
1645 | } |
1646 | if (acpi_get_mcfg(&mcfg)) { | |
7c2c1fa5 IM |
1647 | acpi_add_table(table_offsets, tables_blob); |
1648 | build_mcfg_q35(tables_blob, tables->linker, &mcfg); | |
72c194f7 | 1649 | } |
d4eb9119 | 1650 | if (acpi_has_iommu()) { |
7c2c1fa5 IM |
1651 | acpi_add_table(table_offsets, tables_blob); |
1652 | build_dmar_q35(tables_blob, tables->linker); | |
d4eb9119 | 1653 | } |
72c194f7 MT |
1654 | |
1655 | /* Add tables supplied by user (if any) */ | |
1656 | for (u = acpi_table_first(); u; u = acpi_table_next(u)) { | |
1657 | unsigned len = acpi_table_len(u); | |
1658 | ||
7c2c1fa5 IM |
1659 | acpi_add_table(table_offsets, tables_blob); |
1660 | g_array_append_vals(tables_blob, u, len); | |
72c194f7 MT |
1661 | } |
1662 | ||
1663 | /* RSDT is pointed to by RSDP */ | |
7c2c1fa5 IM |
1664 | rsdt = tables_blob->len; |
1665 | build_rsdt(tables_blob, tables->linker, table_offsets); | |
72c194f7 MT |
1666 | |
1667 | /* RSDP is in FSEG memory, so allocate it separately */ | |
1668 | build_rsdp(tables->rsdp, tables->linker, rsdt); | |
1669 | ||
07fb6176 | 1670 | /* We'll expose it all to Guest so we want to reduce |
72c194f7 | 1671 | * chance of size changes. |
07fb6176 PB |
1672 | * |
1673 | * We used to align the tables to 4k, but of course this would | |
1674 | * too simple to be enough. 4k turned out to be too small an | |
1675 | * alignment very soon, and in fact it is almost impossible to | |
1676 | * keep the table size stable for all (max_cpus, max_memory_slots) | |
1677 | * combinations. So the table size is always 64k for pc-i440fx-2.1 | |
1678 | * and we give an error if the table grows beyond that limit. | |
1679 | * | |
1680 | * We still have the problem of migrating from "-M pc-i440fx-2.0". For | |
1681 | * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables | |
1682 | * than 2.0 and we can always pad the smaller tables with zeros. We can | |
1683 | * then use the exact size of the 2.0 tables. | |
1684 | * | |
1685 | * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. | |
72c194f7 | 1686 | */ |
07fb6176 PB |
1687 | if (guest_info->legacy_acpi_table_size) { |
1688 | /* Subtracting aml_len gives the size of fixed tables. Then add the | |
1689 | * size of the PIIX4 DSDT/SSDT in QEMU 2.0. | |
1690 | */ | |
1691 | int legacy_aml_len = | |
1692 | guest_info->legacy_acpi_table_size + | |
1693 | ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; | |
1694 | int legacy_table_size = | |
7c2c1fa5 | 1695 | ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, |
07fb6176 | 1696 | ACPI_BUILD_ALIGN_SIZE); |
7c2c1fa5 | 1697 | if (tables_blob->len > legacy_table_size) { |
07fb6176 | 1698 | /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ |
868270f2 | 1699 | error_report("Warning: migration may not work."); |
07fb6176 | 1700 | } |
7c2c1fa5 | 1701 | g_array_set_size(tables_blob, legacy_table_size); |
07fb6176 | 1702 | } else { |
868270f2 | 1703 | /* Make sure we have a buffer in case we need to resize the tables. */ |
7c2c1fa5 | 1704 | if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { |
18045fb9 | 1705 | /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ |
868270f2 MT |
1706 | error_report("Warning: ACPI tables are larger than 64k."); |
1707 | error_report("Warning: migration may not work."); | |
1708 | error_report("Warning: please remove CPUs, NUMA nodes, " | |
1709 | "memory slots or PCI bridges."); | |
18045fb9 | 1710 | } |
7c2c1fa5 | 1711 | acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); |
07fb6176 | 1712 | } |
72c194f7 | 1713 | |
07fb6176 | 1714 | acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); |
72c194f7 MT |
1715 | |
1716 | /* Cleanup memory that's no longer used. */ | |
1717 | g_array_free(table_offsets, true); | |
1718 | } | |
1719 | ||
339240b5 | 1720 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) |
42d85900 MT |
1721 | { |
1722 | uint32_t size = acpi_data_len(data); | |
1723 | ||
1724 | /* Make sure RAM size is correct - in case it got changed e.g. by migration */ | |
339240b5 | 1725 | memory_region_ram_resize(mr, size, &error_abort); |
42d85900 | 1726 | |
339240b5 PB |
1727 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); |
1728 | memory_region_set_dirty(mr, 0, size); | |
42d85900 MT |
1729 | } |
1730 | ||
72c194f7 MT |
1731 | static void acpi_build_update(void *build_opaque, uint32_t offset) |
1732 | { | |
1733 | AcpiBuildState *build_state = build_opaque; | |
1734 | AcpiBuildTables tables; | |
1735 | ||
1736 | /* No state to update or already patched? Nothing to do. */ | |
1737 | if (!build_state || build_state->patched) { | |
1738 | return; | |
1739 | } | |
1740 | build_state->patched = 1; | |
1741 | ||
1742 | acpi_build_tables_init(&tables); | |
1743 | ||
1744 | acpi_build(build_state->guest_info, &tables); | |
1745 | ||
339240b5 | 1746 | acpi_ram_update(build_state->table_mr, tables.table_data); |
a1666142 | 1747 | |
42d85900 MT |
1748 | if (build_state->rsdp) { |
1749 | memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); | |
1750 | } else { | |
339240b5 | 1751 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); |
42d85900 | 1752 | } |
ad5b88b1 | 1753 | |
339240b5 | 1754 | acpi_ram_update(build_state->linker_mr, tables.linker); |
72c194f7 MT |
1755 | acpi_build_tables_cleanup(&tables, true); |
1756 | } | |
1757 | ||
1758 | static void acpi_build_reset(void *build_opaque) | |
1759 | { | |
1760 | AcpiBuildState *build_state = build_opaque; | |
1761 | build_state->patched = 0; | |
1762 | } | |
1763 | ||
339240b5 PB |
1764 | static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, |
1765 | GArray *blob, const char *name, | |
1766 | uint64_t max_size) | |
72c194f7 | 1767 | { |
a1666142 MT |
1768 | return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, |
1769 | name, acpi_build_update, build_state); | |
72c194f7 MT |
1770 | } |
1771 | ||
1772 | static const VMStateDescription vmstate_acpi_build = { | |
1773 | .name = "acpi_build", | |
1774 | .version_id = 1, | |
1775 | .minimum_version_id = 1, | |
d49805ae | 1776 | .fields = (VMStateField[]) { |
72c194f7 MT |
1777 | VMSTATE_UINT8(patched, AcpiBuildState), |
1778 | VMSTATE_END_OF_LIST() | |
1779 | }, | |
1780 | }; | |
1781 | ||
1782 | void acpi_setup(PcGuestInfo *guest_info) | |
1783 | { | |
1784 | AcpiBuildTables tables; | |
1785 | AcpiBuildState *build_state; | |
1786 | ||
1787 | if (!guest_info->fw_cfg) { | |
8b310fc4 | 1788 | ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); |
72c194f7 MT |
1789 | return; |
1790 | } | |
1791 | ||
1792 | if (!guest_info->has_acpi_build) { | |
8b310fc4 | 1793 | ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); |
72c194f7 MT |
1794 | return; |
1795 | } | |
1796 | ||
81adc513 | 1797 | if (!acpi_enabled) { |
8b310fc4 | 1798 | ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); |
81adc513 MT |
1799 | return; |
1800 | } | |
1801 | ||
72c194f7 MT |
1802 | build_state = g_malloc0(sizeof *build_state); |
1803 | ||
1804 | build_state->guest_info = guest_info; | |
1805 | ||
99fd437d MT |
1806 | acpi_set_pci_info(); |
1807 | ||
72c194f7 MT |
1808 | acpi_build_tables_init(&tables); |
1809 | acpi_build(build_state->guest_info, &tables); | |
1810 | ||
1811 | /* Now expose it all to Guest */ | |
339240b5 | 1812 | build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, |
a1666142 MT |
1813 | ACPI_BUILD_TABLE_FILE, |
1814 | ACPI_BUILD_TABLE_MAX_SIZE); | |
339240b5 | 1815 | assert(build_state->table_mr != NULL); |
72c194f7 | 1816 | |
339240b5 | 1817 | build_state->linker_mr = |
6e00619b | 1818 | acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); |
72c194f7 | 1819 | |
42a5b308 SB |
1820 | fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, |
1821 | tables.tcpalog->data, acpi_data_len(tables.tcpalog)); | |
1822 | ||
384fb32e | 1823 | if (!guest_info->rsdp_in_ram) { |
358774d7 IM |
1824 | /* |
1825 | * Keep for compatibility with old machine types. | |
1826 | * Though RSDP is small, its contents isn't immutable, so | |
afaa2e4b | 1827 | * we'll update it along with the rest of tables on guest access. |
358774d7 | 1828 | */ |
afaa2e4b MT |
1829 | uint32_t rsdp_size = acpi_data_len(tables.rsdp); |
1830 | ||
1831 | build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); | |
358774d7 IM |
1832 | fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE, |
1833 | acpi_build_update, build_state, | |
afaa2e4b | 1834 | build_state->rsdp, rsdp_size); |
339240b5 | 1835 | build_state->rsdp_mr = NULL; |
358774d7 | 1836 | } else { |
42d85900 | 1837 | build_state->rsdp = NULL; |
339240b5 | 1838 | build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, |
42d85900 | 1839 | ACPI_BUILD_RSDP_FILE, 0); |
358774d7 | 1840 | } |
72c194f7 MT |
1841 | |
1842 | qemu_register_reset(acpi_build_reset, build_state); | |
1843 | acpi_build_reset(build_state); | |
1844 | vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); | |
1845 | ||
1846 | /* Cleanup tables but don't free the memory: we track it | |
1847 | * in build_state. | |
1848 | */ | |
1849 | acpi_build_tables_cleanup(&tables, false); | |
1850 | } |