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72c194f7 MT |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
4 | * Copyright (C) 2006 Fabrice Bellard | |
5 | * Copyright (C) 2013 Red Hat Inc | |
6 | * | |
7 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | ||
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | ||
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include "acpi-build.h" | |
24 | #include <stddef.h> | |
25 | #include <glib.h> | |
26 | #include "qemu-common.h" | |
27 | #include "qemu/bitmap.h" | |
07fb6176 | 28 | #include "qemu/osdep.h" |
72c194f7 | 29 | #include "qemu/range.h" |
07fb6176 | 30 | #include "qemu/error-report.h" |
72c194f7 MT |
31 | #include "hw/pci/pci.h" |
32 | #include "qom/cpu.h" | |
33 | #include "hw/i386/pc.h" | |
34 | #include "target-i386/cpu.h" | |
35 | #include "hw/timer/hpet.h" | |
36 | #include "hw/i386/acpi-defs.h" | |
37 | #include "hw/acpi/acpi.h" | |
38 | #include "hw/nvram/fw_cfg.h" | |
0058ae1d | 39 | #include "hw/acpi/bios-linker-loader.h" |
72c194f7 | 40 | #include "hw/loader.h" |
15bce1b7 | 41 | #include "hw/isa/isa.h" |
bef3492d | 42 | #include "hw/acpi/memory_hotplug.h" |
711b20b4 SB |
43 | #include "sysemu/tpm.h" |
44 | #include "hw/acpi/tpm.h" | |
72c194f7 MT |
45 | |
46 | /* Supported chipsets: */ | |
47 | #include "hw/acpi/piix4.h" | |
99fd437d | 48 | #include "hw/acpi/pcihp.h" |
72c194f7 MT |
49 | #include "hw/i386/ich9.h" |
50 | #include "hw/pci/pci_bus.h" | |
51 | #include "hw/pci-host/q35.h" | |
d4eb9119 | 52 | #include "hw/i386/intel_iommu.h" |
72c194f7 MT |
53 | |
54 | #include "hw/i386/q35-acpi-dsdt.hex" | |
55 | #include "hw/i386/acpi-dsdt.hex" | |
56 | ||
19934e0e IM |
57 | #include "hw/acpi/aml-build.h" |
58 | ||
72c194f7 MT |
59 | #include "qapi/qmp/qint.h" |
60 | #include "qom/qom-qobject.h" | |
ad5b88b1 | 61 | #include "exec/ram_addr.h" |
72c194f7 | 62 | |
07fb6176 PB |
63 | /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and |
64 | * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows | |
65 | * a little bit, there should be plenty of free space since the DSDT | |
66 | * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. | |
67 | */ | |
68 | #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 | |
69 | #define ACPI_BUILD_ALIGN_SIZE 0x1000 | |
70 | ||
868270f2 | 71 | #define ACPI_BUILD_TABLE_SIZE 0x20000 |
18045fb9 | 72 | |
a1666142 MT |
73 | /* Reserve RAM space for tables: add another order of magnitude. */ |
74 | #define ACPI_BUILD_TABLE_MAX_SIZE 0x200000 | |
75 | ||
8b310fc4 GA |
76 | /* #define DEBUG_ACPI_BUILD */ |
77 | #ifdef DEBUG_ACPI_BUILD | |
78 | #define ACPI_BUILD_DPRINTF(fmt, ...) \ | |
79 | do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) | |
80 | #else | |
81 | #define ACPI_BUILD_DPRINTF(fmt, ...) | |
82 | #endif | |
83 | ||
72c194f7 | 84 | typedef struct AcpiCpuInfo { |
798325ed | 85 | DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); |
72c194f7 MT |
86 | } AcpiCpuInfo; |
87 | ||
88 | typedef struct AcpiMcfgInfo { | |
89 | uint64_t mcfg_base; | |
90 | uint32_t mcfg_size; | |
91 | } AcpiMcfgInfo; | |
92 | ||
93 | typedef struct AcpiPmInfo { | |
94 | bool s3_disabled; | |
95 | bool s4_disabled; | |
133a2da4 | 96 | bool pcihp_bridge_en; |
72c194f7 MT |
97 | uint8_t s4_val; |
98 | uint16_t sci_int; | |
99 | uint8_t acpi_enable_cmd; | |
100 | uint8_t acpi_disable_cmd; | |
101 | uint32_t gpe0_blk; | |
102 | uint32_t gpe0_blk_len; | |
103 | uint32_t io_base; | |
ddf1ec2f IM |
104 | uint16_t cpu_hp_io_base; |
105 | uint16_t cpu_hp_io_len; | |
2c6b94d8 IM |
106 | uint16_t mem_hp_io_base; |
107 | uint16_t mem_hp_io_len; | |
500b11ea IM |
108 | uint16_t pcihp_io_base; |
109 | uint16_t pcihp_io_len; | |
72c194f7 MT |
110 | } AcpiPmInfo; |
111 | ||
112 | typedef struct AcpiMiscInfo { | |
113 | bool has_hpet; | |
711b20b4 | 114 | bool has_tpm; |
72c194f7 MT |
115 | DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX); |
116 | const unsigned char *dsdt_code; | |
117 | unsigned dsdt_size; | |
118 | uint16_t pvpanic_port; | |
119 | } AcpiMiscInfo; | |
120 | ||
99fd437d MT |
121 | typedef struct AcpiBuildPciBusHotplugState { |
122 | GArray *device_table; | |
123 | GArray *notify_table; | |
124 | struct AcpiBuildPciBusHotplugState *parent; | |
133a2da4 | 125 | bool pcihp_bridge_en; |
99fd437d MT |
126 | } AcpiBuildPciBusHotplugState; |
127 | ||
72c194f7 MT |
128 | static void acpi_get_dsdt(AcpiMiscInfo *info) |
129 | { | |
8977557a | 130 | uint16_t *applesmc_sta; |
72c194f7 MT |
131 | Object *piix = piix4_pm_find(); |
132 | Object *lpc = ich9_lpc_find(); | |
133 | assert(!!piix != !!lpc); | |
134 | ||
135 | if (piix) { | |
136 | info->dsdt_code = AcpiDsdtAmlCode; | |
137 | info->dsdt_size = sizeof AcpiDsdtAmlCode; | |
8977557a | 138 | applesmc_sta = piix_dsdt_applesmc_sta; |
72c194f7 MT |
139 | } |
140 | if (lpc) { | |
141 | info->dsdt_code = Q35AcpiDsdtAmlCode; | |
142 | info->dsdt_size = sizeof Q35AcpiDsdtAmlCode; | |
8977557a | 143 | applesmc_sta = q35_dsdt_applesmc_sta; |
72c194f7 | 144 | } |
15bce1b7 GS |
145 | |
146 | /* Patch in appropriate value for AppleSMC _STA */ | |
8977557a GS |
147 | *(uint8_t *)(info->dsdt_code + *applesmc_sta) = |
148 | applesmc_find() ? 0x0b : 0x00; | |
72c194f7 MT |
149 | } |
150 | ||
151 | static | |
152 | int acpi_add_cpu_info(Object *o, void *opaque) | |
153 | { | |
154 | AcpiCpuInfo *cpu = opaque; | |
155 | uint64_t apic_id; | |
156 | ||
157 | if (object_dynamic_cast(o, TYPE_CPU)) { | |
158 | apic_id = object_property_get_int(o, "apic-id", NULL); | |
798325ed | 159 | assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); |
72c194f7 MT |
160 | |
161 | set_bit(apic_id, cpu->found_cpus); | |
162 | } | |
163 | ||
164 | object_child_foreach(o, acpi_add_cpu_info, opaque); | |
165 | return 0; | |
166 | } | |
167 | ||
168 | static void acpi_get_cpu_info(AcpiCpuInfo *cpu) | |
169 | { | |
170 | Object *root = object_get_root(); | |
171 | ||
172 | memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); | |
173 | object_child_foreach(root, acpi_add_cpu_info, cpu); | |
174 | } | |
175 | ||
176 | static void acpi_get_pm_info(AcpiPmInfo *pm) | |
177 | { | |
178 | Object *piix = piix4_pm_find(); | |
179 | Object *lpc = ich9_lpc_find(); | |
180 | Object *obj = NULL; | |
181 | QObject *o; | |
182 | ||
500b11ea IM |
183 | pm->pcihp_io_base = 0; |
184 | pm->pcihp_io_len = 0; | |
72c194f7 MT |
185 | if (piix) { |
186 | obj = piix; | |
ddf1ec2f | 187 | pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; |
500b11ea IM |
188 | pm->pcihp_io_base = |
189 | object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); | |
190 | pm->pcihp_io_len = | |
191 | object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); | |
72c194f7 MT |
192 | } |
193 | if (lpc) { | |
194 | obj = lpc; | |
ddf1ec2f | 195 | pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; |
72c194f7 MT |
196 | } |
197 | assert(obj); | |
198 | ||
ddf1ec2f | 199 | pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; |
2c6b94d8 IM |
200 | pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; |
201 | pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; | |
202 | ||
72c194f7 MT |
203 | /* Fill in optional s3/s4 related properties */ |
204 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); | |
205 | if (o) { | |
206 | pm->s3_disabled = qint_get_int(qobject_to_qint(o)); | |
207 | } else { | |
208 | pm->s3_disabled = false; | |
209 | } | |
097a97a6 | 210 | qobject_decref(o); |
72c194f7 MT |
211 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); |
212 | if (o) { | |
213 | pm->s4_disabled = qint_get_int(qobject_to_qint(o)); | |
214 | } else { | |
215 | pm->s4_disabled = false; | |
216 | } | |
097a97a6 | 217 | qobject_decref(o); |
72c194f7 MT |
218 | o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); |
219 | if (o) { | |
220 | pm->s4_val = qint_get_int(qobject_to_qint(o)); | |
221 | } else { | |
222 | pm->s4_val = false; | |
223 | } | |
097a97a6 | 224 | qobject_decref(o); |
72c194f7 MT |
225 | |
226 | /* Fill in mandatory properties */ | |
227 | pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); | |
228 | ||
229 | pm->acpi_enable_cmd = object_property_get_int(obj, | |
230 | ACPI_PM_PROP_ACPI_ENABLE_CMD, | |
231 | NULL); | |
232 | pm->acpi_disable_cmd = object_property_get_int(obj, | |
233 | ACPI_PM_PROP_ACPI_DISABLE_CMD, | |
234 | NULL); | |
235 | pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, | |
236 | NULL); | |
237 | pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, | |
238 | NULL); | |
239 | pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, | |
240 | NULL); | |
133a2da4 IM |
241 | pm->pcihp_bridge_en = |
242 | object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", | |
243 | NULL); | |
72c194f7 MT |
244 | } |
245 | ||
72c194f7 MT |
246 | static void acpi_get_misc_info(AcpiMiscInfo *info) |
247 | { | |
248 | info->has_hpet = hpet_find(); | |
711b20b4 | 249 | info->has_tpm = tpm_find(); |
72c194f7 MT |
250 | info->pvpanic_port = pvpanic_port(); |
251 | } | |
252 | ||
253 | static void acpi_get_pci_info(PcPciInfo *info) | |
254 | { | |
255 | Object *pci_host; | |
256 | bool ambiguous; | |
257 | ||
258 | pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); | |
259 | g_assert(!ambiguous); | |
260 | g_assert(pci_host); | |
261 | ||
262 | info->w32.begin = object_property_get_int(pci_host, | |
263 | PCI_HOST_PROP_PCI_HOLE_START, | |
264 | NULL); | |
265 | info->w32.end = object_property_get_int(pci_host, | |
266 | PCI_HOST_PROP_PCI_HOLE_END, | |
267 | NULL); | |
268 | info->w64.begin = object_property_get_int(pci_host, | |
269 | PCI_HOST_PROP_PCI_HOLE64_START, | |
270 | NULL); | |
271 | info->w64.end = object_property_get_int(pci_host, | |
272 | PCI_HOST_PROP_PCI_HOLE64_END, | |
273 | NULL); | |
274 | } | |
275 | ||
276 | #define ACPI_BUILD_APPNAME "Bochs" | |
277 | #define ACPI_BUILD_APPNAME6 "BOCHS " | |
278 | #define ACPI_BUILD_APPNAME4 "BXPC" | |
279 | ||
72c194f7 MT |
280 | #define ACPI_BUILD_TABLE_FILE "etc/acpi/tables" |
281 | #define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp" | |
42a5b308 | 282 | #define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log" |
72c194f7 MT |
283 | |
284 | static void | |
285 | build_header(GArray *linker, GArray *table_data, | |
821e3227 | 286 | AcpiTableHeader *h, const char *sig, int len, uint8_t rev) |
72c194f7 | 287 | { |
821e3227 | 288 | memcpy(&h->signature, sig, 4); |
72c194f7 MT |
289 | h->length = cpu_to_le32(len); |
290 | h->revision = rev; | |
291 | memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6); | |
292 | memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4); | |
821e3227 | 293 | memcpy(h->oem_table_id + 4, sig, 4); |
72c194f7 MT |
294 | h->oem_revision = cpu_to_le32(1); |
295 | memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4); | |
296 | h->asl_compiler_revision = cpu_to_le32(1); | |
297 | h->checksum = 0; | |
298 | /* Checksum to be filled in by Guest linker */ | |
299 | bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE, | |
300 | table_data->data, h, len, &h->checksum); | |
301 | } | |
302 | ||
99fd437d MT |
303 | static GArray *build_alloc_method(const char *name, uint8_t arg_count) |
304 | { | |
305 | GArray *method = build_alloc_array(); | |
306 | ||
eae8bded | 307 | build_append_namestring(method, "%s", name); |
99fd437d MT |
308 | build_append_byte(method, arg_count); /* MethodFlags: ArgCount */ |
309 | ||
310 | return method; | |
311 | } | |
312 | ||
313 | static void build_append_and_cleanup_method(GArray *device, GArray *method) | |
314 | { | |
315 | uint8_t op = 0x14; /* MethodOp */ | |
316 | ||
661875e9 | 317 | build_package(method, op); |
99fd437d MT |
318 | |
319 | build_append_array(device, method); | |
320 | build_free_array(method); | |
321 | } | |
322 | ||
99fd437d | 323 | /* End here */ |
72c194f7 MT |
324 | #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ |
325 | ||
326 | static inline void *acpi_data_push(GArray *table_data, unsigned size) | |
327 | { | |
328 | unsigned off = table_data->len; | |
329 | g_array_set_size(table_data, off + size); | |
330 | return table_data->data + off; | |
331 | } | |
332 | ||
333 | static unsigned acpi_data_len(GArray *table) | |
334 | { | |
134d42d6 | 335 | #if GLIB_CHECK_VERSION(2, 22, 0) |
b15654c2 MT |
336 | assert(g_array_get_element_size(table) == 1); |
337 | #endif | |
338 | return table->len; | |
72c194f7 MT |
339 | } |
340 | ||
341 | static void acpi_align_size(GArray *blob, unsigned align) | |
342 | { | |
343 | /* Align size to multiple of given size. This reduces the chance | |
344 | * we need to change size in the future (breaking cross version migration). | |
345 | */ | |
134d42d6 | 346 | g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); |
72c194f7 MT |
347 | } |
348 | ||
72c194f7 MT |
349 | static inline void acpi_add_table(GArray *table_offsets, GArray *table_data) |
350 | { | |
351 | uint32_t offset = cpu_to_le32(table_data->len); | |
352 | g_array_append_val(table_offsets, offset); | |
353 | } | |
354 | ||
355 | /* FACS */ | |
356 | static void | |
357 | build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) | |
358 | { | |
359 | AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); | |
821e3227 | 360 | memcpy(&facs->signature, "FACS", 4); |
72c194f7 MT |
361 | facs->length = cpu_to_le32(sizeof(*facs)); |
362 | } | |
363 | ||
364 | /* Load chipset information in FADT */ | |
365 | static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) | |
366 | { | |
367 | fadt->model = 1; | |
368 | fadt->reserved1 = 0; | |
369 | fadt->sci_int = cpu_to_le16(pm->sci_int); | |
370 | fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); | |
371 | fadt->acpi_enable = pm->acpi_enable_cmd; | |
372 | fadt->acpi_disable = pm->acpi_disable_cmd; | |
373 | /* EVT, CNT, TMR offset matches hw/acpi/core.c */ | |
374 | fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); | |
375 | fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); | |
376 | fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); | |
377 | fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); | |
378 | /* EVT, CNT, TMR length matches hw/acpi/core.c */ | |
379 | fadt->pm1_evt_len = 4; | |
380 | fadt->pm1_cnt_len = 2; | |
381 | fadt->pm_tmr_len = 4; | |
382 | fadt->gpe0_blk_len = pm->gpe0_blk_len; | |
383 | fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ | |
384 | fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ | |
385 | fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | | |
386 | (1 << ACPI_FADT_F_PROC_C1) | | |
387 | (1 << ACPI_FADT_F_SLP_BUTTON) | | |
388 | (1 << ACPI_FADT_F_RTC_S4)); | |
389 | fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); | |
07b81ed9 HZ |
390 | /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs |
391 | * For more than 8 CPUs, "Clustered Logical" mode has to be used | |
392 | */ | |
393 | if (max_cpus > 8) { | |
394 | fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); | |
395 | } | |
72c194f7 MT |
396 | } |
397 | ||
398 | ||
399 | /* FADT */ | |
400 | static void | |
401 | build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, | |
402 | unsigned facs, unsigned dsdt) | |
403 | { | |
404 | AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); | |
405 | ||
406 | fadt->firmware_ctrl = cpu_to_le32(facs); | |
407 | /* FACS address to be filled by Guest linker */ | |
408 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, | |
409 | ACPI_BUILD_TABLE_FILE, | |
410 | table_data, &fadt->firmware_ctrl, | |
411 | sizeof fadt->firmware_ctrl); | |
412 | ||
413 | fadt->dsdt = cpu_to_le32(dsdt); | |
414 | /* DSDT address to be filled by Guest linker */ | |
415 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, | |
416 | ACPI_BUILD_TABLE_FILE, | |
417 | table_data, &fadt->dsdt, | |
418 | sizeof fadt->dsdt); | |
419 | ||
420 | fadt_setup(fadt, pm); | |
421 | ||
422 | build_header(linker, table_data, | |
821e3227 | 423 | (void *)fadt, "FACP", sizeof(*fadt), 1); |
72c194f7 MT |
424 | } |
425 | ||
426 | static void | |
427 | build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, | |
428 | PcGuestInfo *guest_info) | |
429 | { | |
430 | int madt_start = table_data->len; | |
431 | ||
432 | AcpiMultipleApicTable *madt; | |
433 | AcpiMadtIoApic *io_apic; | |
434 | AcpiMadtIntsrcovr *intsrcovr; | |
435 | AcpiMadtLocalNmi *local_nmi; | |
436 | int i; | |
437 | ||
438 | madt = acpi_data_push(table_data, sizeof *madt); | |
439 | madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); | |
440 | madt->flags = cpu_to_le32(1); | |
441 | ||
442 | for (i = 0; i < guest_info->apic_id_limit; i++) { | |
443 | AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); | |
444 | apic->type = ACPI_APIC_PROCESSOR; | |
445 | apic->length = sizeof(*apic); | |
446 | apic->processor_id = i; | |
447 | apic->local_apic_id = i; | |
448 | if (test_bit(i, cpu->found_cpus)) { | |
449 | apic->flags = cpu_to_le32(1); | |
450 | } else { | |
451 | apic->flags = cpu_to_le32(0); | |
452 | } | |
453 | } | |
454 | io_apic = acpi_data_push(table_data, sizeof *io_apic); | |
455 | io_apic->type = ACPI_APIC_IO; | |
456 | io_apic->length = sizeof(*io_apic); | |
457 | #define ACPI_BUILD_IOAPIC_ID 0x0 | |
458 | io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; | |
459 | io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); | |
460 | io_apic->interrupt = cpu_to_le32(0); | |
461 | ||
462 | if (guest_info->apic_xrupt_override) { | |
463 | intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); | |
464 | intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; | |
465 | intsrcovr->length = sizeof(*intsrcovr); | |
466 | intsrcovr->source = 0; | |
467 | intsrcovr->gsi = cpu_to_le32(2); | |
468 | intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ | |
469 | } | |
470 | for (i = 1; i < 16; i++) { | |
471 | #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) | |
472 | if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { | |
473 | /* No need for a INT source override structure. */ | |
474 | continue; | |
475 | } | |
476 | intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); | |
477 | intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; | |
478 | intsrcovr->length = sizeof(*intsrcovr); | |
479 | intsrcovr->source = i; | |
480 | intsrcovr->gsi = cpu_to_le32(i); | |
481 | intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ | |
482 | } | |
483 | ||
484 | local_nmi = acpi_data_push(table_data, sizeof *local_nmi); | |
485 | local_nmi->type = ACPI_APIC_LOCAL_NMI; | |
486 | local_nmi->length = sizeof(*local_nmi); | |
487 | local_nmi->processor_id = 0xff; /* all processors */ | |
488 | local_nmi->flags = cpu_to_le16(0); | |
489 | local_nmi->lint = 1; /* ACPI_LINT1 */ | |
490 | ||
491 | build_header(linker, table_data, | |
821e3227 | 492 | (void *)(table_data->data + madt_start), "APIC", |
72c194f7 MT |
493 | table_data->len - madt_start, 1); |
494 | } | |
495 | ||
496 | /* Encode a hex value */ | |
497 | static inline char acpi_get_hex(uint32_t val) | |
498 | { | |
499 | val &= 0x0f; | |
500 | return (val <= 9) ? ('0' + val) : ('A' + val - 10); | |
501 | } | |
502 | ||
72c194f7 MT |
503 | /* 0x5B 0x82 DeviceOp PkgLength NameString */ |
504 | #define ACPI_PCIHP_OFFSET_HEX (*ssdt_pcihp_name - *ssdt_pcihp_start + 1) | |
505 | #define ACPI_PCIHP_OFFSET_ID (*ssdt_pcihp_id - *ssdt_pcihp_start) | |
506 | #define ACPI_PCIHP_OFFSET_ADR (*ssdt_pcihp_adr - *ssdt_pcihp_start) | |
507 | #define ACPI_PCIHP_OFFSET_EJ0 (*ssdt_pcihp_ej0 - *ssdt_pcihp_start) | |
508 | #define ACPI_PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start) | |
509 | #define ACPI_PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start) | |
510 | ||
8dcf525a MT |
511 | #define ACPI_PCINOHP_OFFSET_HEX (*ssdt_pcinohp_name - *ssdt_pcinohp_start + 1) |
512 | #define ACPI_PCINOHP_OFFSET_ADR (*ssdt_pcinohp_adr - *ssdt_pcinohp_start) | |
513 | #define ACPI_PCINOHP_SIZEOF (*ssdt_pcinohp_end - *ssdt_pcinohp_start) | |
514 | #define ACPI_PCINOHP_AML (ssdp_pcihp_aml + *ssdt_pcinohp_start) | |
515 | ||
516 | #define ACPI_PCIVGA_OFFSET_HEX (*ssdt_pcivga_name - *ssdt_pcivga_start + 1) | |
517 | #define ACPI_PCIVGA_OFFSET_ADR (*ssdt_pcivga_adr - *ssdt_pcivga_start) | |
518 | #define ACPI_PCIVGA_SIZEOF (*ssdt_pcivga_end - *ssdt_pcivga_start) | |
519 | #define ACPI_PCIVGA_AML (ssdp_pcihp_aml + *ssdt_pcivga_start) | |
520 | ||
521 | #define ACPI_PCIQXL_OFFSET_HEX (*ssdt_pciqxl_name - *ssdt_pciqxl_start + 1) | |
522 | #define ACPI_PCIQXL_OFFSET_ADR (*ssdt_pciqxl_adr - *ssdt_pciqxl_start) | |
523 | #define ACPI_PCIQXL_SIZEOF (*ssdt_pciqxl_end - *ssdt_pciqxl_start) | |
524 | #define ACPI_PCIQXL_AML (ssdp_pcihp_aml + *ssdt_pciqxl_start) | |
525 | ||
72c194f7 MT |
526 | #define ACPI_SSDT_SIGNATURE 0x54445353 /* SSDT */ |
527 | #define ACPI_SSDT_HEADER_LENGTH 36 | |
528 | ||
529 | #include "hw/i386/ssdt-misc.hex" | |
530 | #include "hw/i386/ssdt-pcihp.hex" | |
711b20b4 | 531 | #include "hw/i386/ssdt-tpm.hex" |
72c194f7 | 532 | |
99fd437d | 533 | static void patch_pcihp(int slot, uint8_t *ssdt_ptr) |
72c194f7 | 534 | { |
99fd437d MT |
535 | unsigned devfn = PCI_DEVFN(slot, 0); |
536 | ||
537 | ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4); | |
538 | ssdt_ptr[ACPI_PCIHP_OFFSET_HEX + 1] = acpi_get_hex(devfn); | |
72c194f7 MT |
539 | ssdt_ptr[ACPI_PCIHP_OFFSET_ID] = slot; |
540 | ssdt_ptr[ACPI_PCIHP_OFFSET_ADR + 2] = slot; | |
99fd437d MT |
541 | } |
542 | ||
8dcf525a MT |
543 | static void patch_pcinohp(int slot, uint8_t *ssdt_ptr) |
544 | { | |
545 | unsigned devfn = PCI_DEVFN(slot, 0); | |
546 | ||
547 | ssdt_ptr[ACPI_PCINOHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4); | |
548 | ssdt_ptr[ACPI_PCINOHP_OFFSET_HEX + 1] = acpi_get_hex(devfn); | |
549 | ssdt_ptr[ACPI_PCINOHP_OFFSET_ADR + 2] = slot; | |
550 | } | |
551 | ||
552 | static void patch_pcivga(int slot, uint8_t *ssdt_ptr) | |
553 | { | |
554 | unsigned devfn = PCI_DEVFN(slot, 0); | |
555 | ||
556 | ssdt_ptr[ACPI_PCIVGA_OFFSET_HEX] = acpi_get_hex(devfn >> 4); | |
557 | ssdt_ptr[ACPI_PCIVGA_OFFSET_HEX + 1] = acpi_get_hex(devfn); | |
558 | ssdt_ptr[ACPI_PCIVGA_OFFSET_ADR + 2] = slot; | |
559 | } | |
560 | ||
561 | static void patch_pciqxl(int slot, uint8_t *ssdt_ptr) | |
562 | { | |
563 | unsigned devfn = PCI_DEVFN(slot, 0); | |
564 | ||
565 | ssdt_ptr[ACPI_PCIQXL_OFFSET_HEX] = acpi_get_hex(devfn >> 4); | |
566 | ssdt_ptr[ACPI_PCIQXL_OFFSET_HEX + 1] = acpi_get_hex(devfn); | |
567 | ssdt_ptr[ACPI_PCIQXL_OFFSET_ADR + 2] = slot; | |
568 | } | |
569 | ||
99fd437d MT |
570 | /* Assign BSEL property to all buses. In the future, this can be changed |
571 | * to only assign to buses that support hotplug. | |
572 | */ | |
573 | static void *acpi_set_bsel(PCIBus *bus, void *opaque) | |
574 | { | |
575 | unsigned *bsel_alloc = opaque; | |
576 | unsigned *bus_bsel; | |
577 | ||
39b888bd | 578 | if (qbus_is_hotpluggable(BUS(bus))) { |
99fd437d MT |
579 | bus_bsel = g_malloc(sizeof *bus_bsel); |
580 | ||
581 | *bus_bsel = (*bsel_alloc)++; | |
582 | object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, | |
583 | bus_bsel, NULL); | |
584 | } | |
585 | ||
586 | return bsel_alloc; | |
587 | } | |
588 | ||
589 | static void acpi_set_pci_info(void) | |
590 | { | |
591 | PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ | |
592 | unsigned bsel_alloc = 0; | |
593 | ||
594 | if (bus) { | |
595 | /* Scan all PCI buses. Set property to enable acpi based hotplug. */ | |
596 | pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); | |
597 | } | |
598 | } | |
599 | ||
600 | static void build_pci_bus_state_init(AcpiBuildPciBusHotplugState *state, | |
133a2da4 IM |
601 | AcpiBuildPciBusHotplugState *parent, |
602 | bool pcihp_bridge_en) | |
99fd437d MT |
603 | { |
604 | state->parent = parent; | |
605 | state->device_table = build_alloc_array(); | |
606 | state->notify_table = build_alloc_array(); | |
133a2da4 | 607 | state->pcihp_bridge_en = pcihp_bridge_en; |
99fd437d MT |
608 | } |
609 | ||
610 | static void build_pci_bus_state_cleanup(AcpiBuildPciBusHotplugState *state) | |
611 | { | |
612 | build_free_array(state->device_table); | |
613 | build_free_array(state->notify_table); | |
614 | } | |
615 | ||
616 | static void *build_pci_bus_begin(PCIBus *bus, void *parent_state) | |
617 | { | |
618 | AcpiBuildPciBusHotplugState *parent = parent_state; | |
619 | AcpiBuildPciBusHotplugState *child = g_malloc(sizeof *child); | |
620 | ||
133a2da4 | 621 | build_pci_bus_state_init(child, parent, parent->pcihp_bridge_en); |
99fd437d MT |
622 | |
623 | return child; | |
624 | } | |
625 | ||
626 | static void build_pci_bus_end(PCIBus *bus, void *bus_state) | |
627 | { | |
628 | AcpiBuildPciBusHotplugState *child = bus_state; | |
629 | AcpiBuildPciBusHotplugState *parent = child->parent; | |
630 | GArray *bus_table = build_alloc_array(); | |
631 | DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX); | |
8dcf525a MT |
632 | DECLARE_BITMAP(slot_device_present, PCI_SLOT_MAX); |
633 | DECLARE_BITMAP(slot_device_system, PCI_SLOT_MAX); | |
634 | DECLARE_BITMAP(slot_device_vga, PCI_SLOT_MAX); | |
635 | DECLARE_BITMAP(slot_device_qxl, PCI_SLOT_MAX); | |
99fd437d MT |
636 | uint8_t op; |
637 | int i; | |
638 | QObject *bsel; | |
639 | GArray *method; | |
640 | bool bus_hotplug_support = false; | |
641 | ||
133a2da4 | 642 | /* |
093a35e5 MT |
643 | * Skip bridge subtree creation if bridge hotplug is disabled |
644 | * to make acpi tables compatible with legacy machine types. | |
a20275fa | 645 | * Skip creation for hotplugged bridges as well. |
093a35e5 | 646 | */ |
a20275fa MT |
647 | if (bus->parent_dev && (!child->pcihp_bridge_en || |
648 | DEVICE(bus->parent_dev)->hotplugged)) { | |
16771613 MT |
649 | build_free_array(bus_table); |
650 | build_pci_bus_state_cleanup(child); | |
651 | g_free(child); | |
133a2da4 IM |
652 | return; |
653 | } | |
654 | ||
99fd437d MT |
655 | if (bus->parent_dev) { |
656 | op = 0x82; /* DeviceOp */ | |
eae8bded | 657 | build_append_namestring(bus_table, "S%.02X", |
99fd437d MT |
658 | bus->parent_dev->devfn); |
659 | build_append_byte(bus_table, 0x08); /* NameOp */ | |
eae8bded | 660 | build_append_namestring(bus_table, "_SUN"); |
295a515d | 661 | build_append_int(bus_table, PCI_SLOT(bus->parent_dev->devfn)); |
99fd437d | 662 | build_append_byte(bus_table, 0x08); /* NameOp */ |
eae8bded | 663 | build_append_namestring(bus_table, "_ADR"); |
295a515d IM |
664 | build_append_int(bus_table, (PCI_SLOT(bus->parent_dev->devfn) << 16) | |
665 | PCI_FUNC(bus->parent_dev->devfn)); | |
99fd437d MT |
666 | } else { |
667 | op = 0x10; /* ScopeOp */; | |
eae8bded | 668 | build_append_namestring(bus_table, "PCI0"); |
99fd437d | 669 | } |
72c194f7 | 670 | |
99fd437d MT |
671 | bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); |
672 | if (bsel) { | |
673 | build_append_byte(bus_table, 0x08); /* NameOp */ | |
eae8bded | 674 | build_append_namestring(bus_table, "BSEL"); |
99fd437d | 675 | build_append_int(bus_table, qint_get_int(qobject_to_qint(bsel))); |
99fd437d | 676 | memset(slot_hotplug_enable, 0xff, sizeof slot_hotplug_enable); |
8dcf525a MT |
677 | } else { |
678 | /* No bsel - no slots are hot-pluggable */ | |
679 | memset(slot_hotplug_enable, 0x00, sizeof slot_hotplug_enable); | |
680 | } | |
99fd437d | 681 | |
8dcf525a MT |
682 | memset(slot_device_present, 0x00, sizeof slot_device_present); |
683 | memset(slot_device_system, 0x00, sizeof slot_device_present); | |
684 | memset(slot_device_vga, 0x00, sizeof slot_device_vga); | |
685 | memset(slot_device_qxl, 0x00, sizeof slot_device_qxl); | |
99fd437d | 686 | |
8dcf525a MT |
687 | for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { |
688 | DeviceClass *dc; | |
689 | PCIDeviceClass *pc; | |
690 | PCIDevice *pdev = bus->devices[i]; | |
691 | int slot = PCI_SLOT(i); | |
093a35e5 | 692 | bool bridge_in_acpi; |
99fd437d | 693 | |
8dcf525a MT |
694 | if (!pdev) { |
695 | continue; | |
696 | } | |
99fd437d | 697 | |
8dcf525a MT |
698 | set_bit(slot, slot_device_present); |
699 | pc = PCI_DEVICE_GET_CLASS(pdev); | |
700 | dc = DEVICE_GET_CLASS(pdev); | |
99fd437d | 701 | |
093a35e5 MT |
702 | /* When hotplug for bridges is enabled, bridges are |
703 | * described in ACPI separately (see build_pci_bus_end). | |
704 | * In this case they aren't themselves hot-pluggable. | |
a20275fa | 705 | * Hotplugged bridges *are* hot-pluggable. |
093a35e5 | 706 | */ |
a20275fa MT |
707 | bridge_in_acpi = pc->is_bridge && child->pcihp_bridge_en && |
708 | !DEVICE(pdev)->hotplugged; | |
093a35e5 MT |
709 | |
710 | if (pc->class_id == PCI_CLASS_BRIDGE_ISA || bridge_in_acpi) { | |
8dcf525a | 711 | set_bit(slot, slot_device_system); |
99fd437d MT |
712 | } |
713 | ||
8dcf525a MT |
714 | if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { |
715 | set_bit(slot, slot_device_vga); | |
716 | ||
717 | if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { | |
718 | set_bit(slot, slot_device_qxl); | |
99fd437d MT |
719 | } |
720 | } | |
721 | ||
093a35e5 | 722 | if (!dc->hotpluggable || bridge_in_acpi) { |
8dcf525a MT |
723 | clear_bit(slot, slot_hotplug_enable); |
724 | } | |
725 | } | |
726 | ||
727 | /* Append Device object for each slot */ | |
728 | for (i = 0; i < PCI_SLOT_MAX; i++) { | |
729 | bool can_eject = test_bit(i, slot_hotplug_enable); | |
730 | bool present = test_bit(i, slot_device_present); | |
731 | bool vga = test_bit(i, slot_device_vga); | |
732 | bool qxl = test_bit(i, slot_device_qxl); | |
733 | bool system = test_bit(i, slot_device_system); | |
734 | if (can_eject) { | |
735 | void *pcihp = acpi_data_push(bus_table, | |
736 | ACPI_PCIHP_SIZEOF); | |
737 | memcpy(pcihp, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF); | |
738 | patch_pcihp(i, pcihp); | |
739 | bus_hotplug_support = true; | |
740 | } else if (qxl) { | |
741 | void *pcihp = acpi_data_push(bus_table, | |
742 | ACPI_PCIQXL_SIZEOF); | |
743 | memcpy(pcihp, ACPI_PCIQXL_AML, ACPI_PCIQXL_SIZEOF); | |
744 | patch_pciqxl(i, pcihp); | |
745 | } else if (vga) { | |
746 | void *pcihp = acpi_data_push(bus_table, | |
747 | ACPI_PCIVGA_SIZEOF); | |
748 | memcpy(pcihp, ACPI_PCIVGA_AML, ACPI_PCIVGA_SIZEOF); | |
749 | patch_pcivga(i, pcihp); | |
750 | } else if (system) { | |
b89834f4 | 751 | /* Nothing to do: system devices are in DSDT or in SSDT above. */ |
8dcf525a MT |
752 | } else if (present) { |
753 | void *pcihp = acpi_data_push(bus_table, | |
754 | ACPI_PCINOHP_SIZEOF); | |
755 | memcpy(pcihp, ACPI_PCINOHP_AML, ACPI_PCINOHP_SIZEOF); | |
756 | patch_pcinohp(i, pcihp); | |
757 | } | |
758 | } | |
759 | ||
760 | if (bsel) { | |
99fd437d MT |
761 | method = build_alloc_method("DVNT", 2); |
762 | ||
763 | for (i = 0; i < PCI_SLOT_MAX; i++) { | |
764 | GArray *notify; | |
765 | uint8_t op; | |
766 | ||
767 | if (!test_bit(i, slot_hotplug_enable)) { | |
768 | continue; | |
769 | } | |
770 | ||
771 | notify = build_alloc_array(); | |
772 | op = 0xA0; /* IfOp */ | |
773 | ||
774 | build_append_byte(notify, 0x7B); /* AndOp */ | |
775 | build_append_byte(notify, 0x68); /* Arg0Op */ | |
d9631b90 | 776 | build_append_int(notify, 0x1U << i); |
99fd437d MT |
777 | build_append_byte(notify, 0x00); /* NullName */ |
778 | build_append_byte(notify, 0x86); /* NotifyOp */ | |
eae8bded | 779 | build_append_namestring(notify, "S%.02X", PCI_DEVFN(i, 0)); |
99fd437d MT |
780 | build_append_byte(notify, 0x69); /* Arg1Op */ |
781 | ||
782 | /* Pack it up */ | |
661875e9 | 783 | build_package(notify, op); |
99fd437d MT |
784 | |
785 | build_append_array(method, notify); | |
786 | ||
787 | build_free_array(notify); | |
788 | } | |
789 | ||
790 | build_append_and_cleanup_method(bus_table, method); | |
791 | } | |
792 | ||
793 | /* Append PCNT method to notify about events on local and child buses. | |
794 | * Add unconditionally for root since DSDT expects it. | |
72c194f7 | 795 | */ |
99fd437d MT |
796 | if (bus_hotplug_support || child->notify_table->len || !bus->parent_dev) { |
797 | method = build_alloc_method("PCNT", 0); | |
798 | ||
799 | /* If bus supports hotplug select it and notify about local events */ | |
800 | if (bsel) { | |
801 | build_append_byte(method, 0x70); /* StoreOp */ | |
802 | build_append_int(method, qint_get_int(qobject_to_qint(bsel))); | |
eae8bded IM |
803 | build_append_namestring(method, "BNUM"); |
804 | build_append_namestring(method, "DVNT"); | |
805 | build_append_namestring(method, "PCIU"); | |
99fd437d | 806 | build_append_int(method, 1); /* Device Check */ |
eae8bded IM |
807 | build_append_namestring(method, "DVNT"); |
808 | build_append_namestring(method, "PCID"); | |
99fd437d MT |
809 | build_append_int(method, 3); /* Eject Request */ |
810 | } | |
811 | ||
812 | /* Notify about child bus events in any case */ | |
813 | build_append_array(method, child->notify_table); | |
814 | ||
815 | build_append_and_cleanup_method(bus_table, method); | |
816 | ||
817 | /* Append description of child buses */ | |
818 | build_append_array(bus_table, child->device_table); | |
819 | ||
820 | /* Pack it up */ | |
821 | if (bus->parent_dev) { | |
822 | build_extop_package(bus_table, op); | |
823 | } else { | |
661875e9 | 824 | build_package(bus_table, op); |
99fd437d | 825 | } |
72c194f7 | 826 | |
99fd437d MT |
827 | /* Append our bus description to parent table */ |
828 | build_append_array(parent->device_table, bus_table); | |
829 | ||
830 | /* Also tell parent how to notify us, invoking PCNT method. | |
831 | * At the moment this is not needed for root as we have a single root. | |
832 | */ | |
833 | if (bus->parent_dev) { | |
eae8bded IM |
834 | build_append_namestring(parent->notify_table, "^PCNT.S%.02X", |
835 | bus->parent_dev->devfn); | |
99fd437d | 836 | } |
72c194f7 | 837 | } |
99fd437d | 838 | |
097a97a6 | 839 | qobject_decref(bsel); |
99fd437d MT |
840 | build_free_array(bus_table); |
841 | build_pci_bus_state_cleanup(child); | |
842 | g_free(child); | |
72c194f7 MT |
843 | } |
844 | ||
72c194f7 MT |
845 | static void |
846 | build_ssdt(GArray *table_data, GArray *linker, | |
847 | AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, | |
848 | PcPciInfo *pci, PcGuestInfo *guest_info) | |
849 | { | |
bef3492d IM |
850 | MachineState *machine = MACHINE(qdev_get_machine()); |
851 | uint32_t nr_mem = machine->ram_slots; | |
2fd71f1b | 852 | unsigned acpi_cpus = guest_info->apic_id_limit; |
72c194f7 | 853 | uint8_t *ssdt_ptr; |
20843d16 | 854 | Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx; |
72c194f7 MT |
855 | int i; |
856 | ||
011bb749 | 857 | ssdt = init_aml_allocator(); |
2fd71f1b LE |
858 | /* The current AML generator can cover the APIC ID range [0..255], |
859 | * inclusive, for VCPU hotplug. */ | |
860 | QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); | |
861 | g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); | |
862 | ||
72c194f7 | 863 | /* Copy header and patch values in the S3_ / S4_ / S5_ packages */ |
011bb749 | 864 | ssdt_ptr = acpi_data_push(ssdt->buf, sizeof(ssdp_misc_aml)); |
72c194f7 | 865 | memcpy(ssdt_ptr, ssdp_misc_aml, sizeof(ssdp_misc_aml)); |
72c194f7 | 866 | |
500b11ea | 867 | scope = aml_scope("\\_SB.PCI0"); |
60efd429 IM |
868 | /* build PCI0._CRS */ |
869 | crs = aml_resource_template(); | |
870 | aml_append(crs, | |
871 | aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode, | |
872 | 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); | |
873 | aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)); | |
874 | ||
875 | aml_append(crs, | |
876 | aml_word_io(aml_min_fixed, aml_max_fixed, | |
877 | aml_pos_decode, aml_entire_range, | |
878 | 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); | |
d31c909e IM |
879 | aml_append(crs, |
880 | aml_word_io(aml_min_fixed, aml_max_fixed, | |
881 | aml_pos_decode, aml_entire_range, | |
882 | 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); | |
60efd429 IM |
883 | aml_append(crs, |
884 | aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, | |
885 | aml_cacheable, aml_ReadWrite, | |
886 | 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); | |
887 | aml_append(crs, | |
888 | aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, | |
889 | aml_non_cacheable, aml_ReadWrite, | |
890 | 0, pci->w32.begin, pci->w32.end - 1, 0, | |
891 | pci->w32.end - pci->w32.begin)); | |
892 | if (pci->w64.begin) { | |
893 | aml_append(crs, | |
894 | aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, | |
895 | aml_cacheable, aml_ReadWrite, | |
896 | 0, pci->w64.begin, pci->w64.end - 1, 0, | |
897 | pci->w64.end - pci->w64.begin)); | |
898 | } | |
899 | aml_append(scope, aml_name_decl("_CRS", crs)); | |
900 | ||
d31c909e IM |
901 | /* reserve GPE0 block resources */ |
902 | dev = aml_device("GPE0"); | |
903 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
904 | aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); | |
905 | /* device present, functioning, decoding, not shown in UI */ | |
906 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
907 | crs = aml_resource_template(); | |
908 | aml_append(crs, | |
909 | aml_io(aml_decode16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) | |
910 | ); | |
911 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
912 | aml_append(scope, dev); | |
913 | ||
500b11ea IM |
914 | /* reserve PCIHP resources */ |
915 | if (pm->pcihp_io_len) { | |
916 | dev = aml_device("PHPR"); | |
917 | aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); | |
918 | aml_append(dev, | |
919 | aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); | |
920 | /* device present, functioning, decoding, not shown in UI */ | |
921 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
922 | crs = aml_resource_template(); | |
923 | aml_append(crs, | |
924 | aml_io(aml_decode16, pm->pcihp_io_base, pm->pcihp_io_base, 1, | |
925 | pm->pcihp_io_len) | |
926 | ); | |
927 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
928 | aml_append(scope, dev); | |
929 | } | |
930 | aml_append(ssdt, scope); | |
931 | ||
ebc3028f IM |
932 | /* create S3_ / S4_ / S5_ packages if necessary */ |
933 | scope = aml_scope("\\"); | |
934 | if (!pm->s3_disabled) { | |
935 | pkg = aml_package(4); | |
936 | aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ | |
937 | aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
938 | aml_append(pkg, aml_int(0)); /* reserved */ | |
939 | aml_append(pkg, aml_int(0)); /* reserved */ | |
940 | aml_append(scope, aml_name_decl("_S3", pkg)); | |
941 | } | |
942 | ||
943 | if (!pm->s4_disabled) { | |
944 | pkg = aml_package(4); | |
945 | aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ | |
946 | /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ | |
947 | aml_append(pkg, aml_int(pm->s4_val)); | |
948 | aml_append(pkg, aml_int(0)); /* reserved */ | |
949 | aml_append(pkg, aml_int(0)); /* reserved */ | |
950 | aml_append(scope, aml_name_decl("_S4", pkg)); | |
951 | } | |
952 | ||
953 | pkg = aml_package(4); | |
954 | aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ | |
955 | aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ | |
956 | aml_append(pkg, aml_int(0)); /* reserved */ | |
957 | aml_append(pkg, aml_int(0)); /* reserved */ | |
958 | aml_append(scope, aml_name_decl("_S5", pkg)); | |
959 | aml_append(ssdt, scope); | |
960 | ||
cd61cb2e IM |
961 | if (misc->pvpanic_port) { |
962 | scope = aml_scope("\\_SB.PCI0.ISA"); | |
963 | ||
964 | dev = aml_device("PEVR"); | |
965 | aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); | |
966 | ||
967 | crs = aml_resource_template(); | |
968 | aml_append(crs, | |
969 | aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) | |
970 | ); | |
971 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
972 | ||
973 | aml_append(dev, aml_operation_region("PEOR", aml_system_io, | |
974 | misc->pvpanic_port, 1)); | |
975 | field = aml_field("PEOR", aml_byte_acc); | |
976 | aml_append(field, aml_named_field("PEPT", 8)); | |
977 | aml_append(dev, field); | |
978 | ||
979 | method = aml_method("RDPT", 0); | |
980 | aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); | |
981 | aml_append(method, aml_return(aml_local(0))); | |
982 | aml_append(dev, method); | |
983 | ||
984 | method = aml_method("WRPT", 1); | |
985 | aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); | |
986 | aml_append(dev, method); | |
987 | ||
988 | aml_append(scope, dev); | |
989 | aml_append(ssdt, scope); | |
990 | } | |
991 | ||
011bb749 | 992 | sb_scope = aml_scope("_SB"); |
72c194f7 | 993 | { |
ddf1ec2f IM |
994 | /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ |
995 | dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); | |
996 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); | |
997 | aml_append(dev, | |
998 | aml_name_decl("_UID", aml_string("CPU Hotplug resources")) | |
999 | ); | |
1000 | /* device present, functioning, decoding, not shown in UI */ | |
1001 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
1002 | crs = aml_resource_template(); | |
1003 | aml_append(crs, | |
1004 | aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, | |
1005 | pm->cpu_hp_io_len) | |
1006 | ); | |
1007 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1008 | aml_append(sb_scope, dev); | |
1009 | /* declare CPU hotplug MMIO region and PRS field to access it */ | |
1010 | aml_append(sb_scope, aml_operation_region( | |
1011 | "PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); | |
1012 | field = aml_field("PRST", aml_byte_acc); | |
1013 | aml_append(field, aml_named_field("PRS", 256)); | |
1014 | aml_append(sb_scope, field); | |
1015 | ||
72c194f7 MT |
1016 | /* build Processor object for each processor */ |
1017 | for (i = 0; i < acpi_cpus; i++) { | |
20843d16 IM |
1018 | dev = aml_processor(i, 0, 0, "CP%.02X", i); |
1019 | ||
1020 | method = aml_method("_MAT", 0); | |
1021 | aml_append(method, aml_return(aml_call1("CPMA", aml_int(i)))); | |
1022 | aml_append(dev, method); | |
1023 | ||
1024 | method = aml_method("_STA", 0); | |
1025 | aml_append(method, aml_return(aml_call1("CPST", aml_int(i)))); | |
1026 | aml_append(dev, method); | |
1027 | ||
1028 | method = aml_method("_EJ0", 1); | |
1029 | aml_append(method, | |
1030 | aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0))) | |
1031 | ); | |
1032 | aml_append(dev, method); | |
1033 | ||
1034 | aml_append(sb_scope, dev); | |
72c194f7 MT |
1035 | } |
1036 | ||
1037 | /* build this code: | |
1038 | * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} | |
1039 | */ | |
1040 | /* Arg0 = Processor ID = APIC ID */ | |
20843d16 IM |
1041 | method = aml_method("NTFY", 2); |
1042 | for (i = 0; i < acpi_cpus; i++) { | |
1043 | ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); | |
1044 | aml_append(ifctx, | |
1045 | aml_notify(aml_name("CP%.02X", i), aml_arg(1)) | |
1046 | ); | |
1047 | aml_append(method, ifctx); | |
1048 | } | |
1049 | aml_append(sb_scope, method); | |
1050 | ||
1051 | /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" | |
1052 | * | |
1053 | * Note: The ability to create variable-sized packages was first | |
1054 | * ntroduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages | |
1055 | * ith up to 255 elements. Windows guests up to win2k8 fail when | |
1056 | * VarPackageOp is used. | |
1057 | */ | |
1058 | pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : | |
1059 | aml_varpackage(acpi_cpus); | |
72c194f7 | 1060 | |
20843d16 IM |
1061 | for (i = 0; i < acpi_cpus; i++) { |
1062 | uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; | |
1063 | aml_append(pkg, aml_int(b)); | |
72c194f7 | 1064 | } |
20843d16 | 1065 | aml_append(sb_scope, aml_name_decl("CPON", pkg)); |
72c194f7 | 1066 | |
8698c0c0 IM |
1067 | /* build memory devices */ |
1068 | assert(nr_mem <= ACPI_MAX_RAM_SLOTS); | |
2c6b94d8 IM |
1069 | scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); |
1070 | aml_append(scope, | |
1071 | aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) | |
1072 | ); | |
1073 | ||
1074 | crs = aml_resource_template(); | |
1075 | aml_append(crs, | |
1076 | aml_io(aml_decode16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, | |
1077 | pm->mem_hp_io_len) | |
1078 | ); | |
1079 | aml_append(scope, aml_name_decl("_CRS", crs)); | |
1080 | ||
1081 | aml_append(scope, aml_operation_region( | |
1082 | stringify(MEMORY_HOTPLUG_IO_REGION), aml_system_io, | |
1083 | pm->mem_hp_io_base, pm->mem_hp_io_len) | |
1084 | ); | |
1085 | ||
1086 | field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc); | |
1087 | aml_append(field, /* read only */ | |
1088 | aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); | |
1089 | aml_append(field, /* read only */ | |
1090 | aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); | |
1091 | aml_append(field, /* read only */ | |
1092 | aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); | |
1093 | aml_append(field, /* read only */ | |
1094 | aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); | |
1095 | aml_append(field, /* read only */ | |
1096 | aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); | |
1097 | aml_append(scope, field); | |
1098 | ||
1099 | field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_byte_acc); | |
1100 | aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); | |
1101 | aml_append(field, /* 1 if enabled, read only */ | |
1102 | aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); | |
1103 | aml_append(field, | |
1104 | /*(read) 1 if has a insert event. (write) 1 to clear event */ | |
1105 | aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); | |
1106 | aml_append(scope, field); | |
1107 | ||
1108 | field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc); | |
1109 | aml_append(field, /* DIMM selector, write only */ | |
1110 | aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); | |
1111 | aml_append(field, /* _OST event code, write only */ | |
1112 | aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); | |
1113 | aml_append(field, /* _OST status code, write only */ | |
1114 | aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); | |
1115 | aml_append(scope, field); | |
1116 | ||
1117 | aml_append(sb_scope, scope); | |
8698c0c0 IM |
1118 | |
1119 | for (i = 0; i < nr_mem; i++) { | |
1120 | #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "." | |
1121 | const char *s; | |
1122 | ||
1123 | dev = aml_device("MP%02X", i); | |
1124 | aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); | |
1125 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); | |
bef3492d | 1126 | |
8698c0c0 IM |
1127 | method = aml_method("_CRS", 0); |
1128 | s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD); | |
1129 | aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); | |
1130 | aml_append(dev, method); | |
1131 | ||
1132 | method = aml_method("_STA", 0); | |
1133 | s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD); | |
1134 | aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); | |
1135 | aml_append(dev, method); | |
1136 | ||
1137 | method = aml_method("_PXM", 0); | |
1138 | s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD); | |
1139 | aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); | |
1140 | aml_append(dev, method); | |
1141 | ||
1142 | method = aml_method("_OST", 3); | |
1143 | s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD); | |
1144 | aml_append(method, aml_return(aml_call4( | |
1145 | s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) | |
1146 | ))); | |
1147 | aml_append(dev, method); | |
1148 | ||
1149 | aml_append(sb_scope, dev); | |
bef3492d IM |
1150 | } |
1151 | ||
8698c0c0 IM |
1152 | /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { |
1153 | * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... | |
1154 | */ | |
1155 | method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2); | |
1156 | for (i = 0; i < nr_mem; i++) { | |
1157 | ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); | |
1158 | aml_append(ifctx, | |
1159 | aml_notify(aml_name("MP%.02X", i), aml_arg(1)) | |
1160 | ); | |
1161 | aml_append(method, ifctx); | |
1162 | } | |
1163 | aml_append(sb_scope, method); | |
1164 | ||
72c194f7 | 1165 | { |
99fd437d | 1166 | AcpiBuildPciBusHotplugState hotplug_state; |
8dcf525a MT |
1167 | Object *pci_host; |
1168 | PCIBus *bus = NULL; | |
1169 | bool ambiguous; | |
1170 | ||
1171 | pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); | |
1172 | if (!ambiguous && pci_host) { | |
1173 | bus = PCI_HOST_BRIDGE(pci_host)->bus; | |
1174 | } | |
72c194f7 | 1175 | |
133a2da4 | 1176 | build_pci_bus_state_init(&hotplug_state, NULL, pm->pcihp_bridge_en); |
72c194f7 | 1177 | |
99fd437d MT |
1178 | if (bus) { |
1179 | /* Scan all PCI buses. Generate tables to support hotplug. */ | |
1180 | pci_for_each_bus_depth_first(bus, build_pci_bus_begin, | |
1181 | build_pci_bus_end, &hotplug_state); | |
72c194f7 MT |
1182 | } |
1183 | ||
011bb749 | 1184 | build_append_array(sb_scope->buf, hotplug_state.device_table); |
99fd437d | 1185 | build_pci_bus_state_cleanup(&hotplug_state); |
72c194f7 | 1186 | } |
011bb749 | 1187 | aml_append(ssdt, sb_scope); |
72c194f7 MT |
1188 | } |
1189 | ||
011bb749 IM |
1190 | /* copy AML table into ACPI tables blob and patch header there */ |
1191 | g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); | |
72c194f7 | 1192 | build_header(linker, table_data, |
011bb749 IM |
1193 | (void *)(table_data->data + table_data->len - ssdt->buf->len), |
1194 | "SSDT", ssdt->buf->len, 1); | |
1195 | free_aml_allocator(); | |
72c194f7 MT |
1196 | } |
1197 | ||
1198 | static void | |
1199 | build_hpet(GArray *table_data, GArray *linker) | |
1200 | { | |
1201 | Acpi20Hpet *hpet; | |
1202 | ||
1203 | hpet = acpi_data_push(table_data, sizeof(*hpet)); | |
1204 | /* Note timer_block_id value must be kept in sync with value advertised by | |
1205 | * emulated hpet | |
1206 | */ | |
1207 | hpet->timer_block_id = cpu_to_le32(0x8086a201); | |
1208 | hpet->addr.address = cpu_to_le64(HPET_BASE); | |
1209 | build_header(linker, table_data, | |
821e3227 | 1210 | (void *)hpet, "HPET", sizeof(*hpet), 1); |
72c194f7 MT |
1211 | } |
1212 | ||
711b20b4 | 1213 | static void |
42a5b308 | 1214 | build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) |
711b20b4 SB |
1215 | { |
1216 | Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); | |
42a5b308 | 1217 | uint64_t log_area_start_address = acpi_data_len(tcpalog); |
711b20b4 SB |
1218 | |
1219 | tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); | |
1220 | tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); | |
1221 | tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); | |
1222 | ||
42a5b308 SB |
1223 | bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, |
1224 | false /* high memory */); | |
1225 | ||
711b20b4 SB |
1226 | /* log area start address to be filled by Guest linker */ |
1227 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, | |
42a5b308 | 1228 | ACPI_BUILD_TPMLOG_FILE, |
711b20b4 SB |
1229 | table_data, &tcpa->log_area_start_address, |
1230 | sizeof(tcpa->log_area_start_address)); | |
1231 | ||
1232 | build_header(linker, table_data, | |
1233 | (void *)tcpa, "TCPA", sizeof(*tcpa), 2); | |
1234 | ||
42a5b308 | 1235 | acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); |
711b20b4 SB |
1236 | } |
1237 | ||
1238 | static void | |
1239 | build_tpm_ssdt(GArray *table_data, GArray *linker) | |
1240 | { | |
1241 | void *tpm_ptr; | |
1242 | ||
1243 | tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml)); | |
1244 | memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml)); | |
1245 | } | |
1246 | ||
04ed3ea8 IM |
1247 | typedef enum { |
1248 | MEM_AFFINITY_NOFLAGS = 0, | |
1249 | MEM_AFFINITY_ENABLED = (1 << 0), | |
1250 | MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), | |
1251 | MEM_AFFINITY_NON_VOLATILE = (1 << 2), | |
1252 | } MemoryAffinityFlags; | |
1253 | ||
72c194f7 | 1254 | static void |
04ed3ea8 IM |
1255 | acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, |
1256 | uint64_t len, int node, MemoryAffinityFlags flags) | |
72c194f7 MT |
1257 | { |
1258 | numamem->type = ACPI_SRAT_MEMORY; | |
1259 | numamem->length = sizeof(*numamem); | |
1260 | memset(numamem->proximity, 0, 4); | |
1261 | numamem->proximity[0] = node; | |
04ed3ea8 | 1262 | numamem->flags = cpu_to_le32(flags); |
72c194f7 MT |
1263 | numamem->base_addr = cpu_to_le64(base); |
1264 | numamem->range_length = cpu_to_le64(len); | |
1265 | } | |
1266 | ||
1267 | static void | |
dd0247e0 | 1268 | build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) |
72c194f7 MT |
1269 | { |
1270 | AcpiSystemResourceAffinityTable *srat; | |
1271 | AcpiSratProcessorAffinity *core; | |
1272 | AcpiSratMemoryAffinity *numamem; | |
1273 | ||
1274 | int i; | |
1275 | uint64_t curnode; | |
1276 | int srat_start, numa_start, slots; | |
1277 | uint64_t mem_len, mem_base, next_base; | |
cec65193 IM |
1278 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); |
1279 | ram_addr_t hotplugabble_address_space_size = | |
1280 | object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, | |
1281 | NULL); | |
72c194f7 MT |
1282 | |
1283 | srat_start = table_data->len; | |
1284 | ||
1285 | srat = acpi_data_push(table_data, sizeof *srat); | |
1286 | srat->reserved1 = cpu_to_le32(1); | |
1287 | core = (void *)(srat + 1); | |
1288 | ||
1289 | for (i = 0; i < guest_info->apic_id_limit; ++i) { | |
1290 | core = acpi_data_push(table_data, sizeof *core); | |
1291 | core->type = ACPI_SRAT_PROCESSOR; | |
1292 | core->length = sizeof(*core); | |
1293 | core->local_apic_id = i; | |
1294 | curnode = guest_info->node_cpu[i]; | |
1295 | core->proximity_lo = curnode; | |
1296 | memset(core->proximity_hi, 0, 3); | |
1297 | core->local_sapic_eid = 0; | |
dd0247e0 | 1298 | core->flags = cpu_to_le32(1); |
72c194f7 MT |
1299 | } |
1300 | ||
1301 | ||
1302 | /* the memory map is a bit tricky, it contains at least one hole | |
1303 | * from 640k-1M and possibly another one from 3.5G-4G. | |
1304 | */ | |
1305 | next_base = 0; | |
1306 | numa_start = table_data->len; | |
1307 | ||
1308 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
04ed3ea8 | 1309 | acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); |
72c194f7 MT |
1310 | next_base = 1024 * 1024; |
1311 | for (i = 1; i < guest_info->numa_nodes + 1; ++i) { | |
1312 | mem_base = next_base; | |
1313 | mem_len = guest_info->node_mem[i - 1]; | |
1314 | if (i == 1) { | |
1315 | mem_len -= 1024 * 1024; | |
1316 | } | |
1317 | next_base = mem_base + mem_len; | |
1318 | ||
1319 | /* Cut out the ACPI_PCI hole */ | |
4c8a949b EH |
1320 | if (mem_base <= guest_info->ram_size_below_4g && |
1321 | next_base > guest_info->ram_size_below_4g) { | |
1322 | mem_len -= next_base - guest_info->ram_size_below_4g; | |
72c194f7 MT |
1323 | if (mem_len > 0) { |
1324 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
04ed3ea8 IM |
1325 | acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, |
1326 | MEM_AFFINITY_ENABLED); | |
72c194f7 MT |
1327 | } |
1328 | mem_base = 1ULL << 32; | |
4c8a949b EH |
1329 | mem_len = next_base - guest_info->ram_size_below_4g; |
1330 | next_base += (1ULL << 32) - guest_info->ram_size_below_4g; | |
72c194f7 MT |
1331 | } |
1332 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
04ed3ea8 IM |
1333 | acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, |
1334 | MEM_AFFINITY_ENABLED); | |
72c194f7 MT |
1335 | } |
1336 | slots = (table_data->len - numa_start) / sizeof *numamem; | |
1337 | for (; slots < guest_info->numa_nodes + 2; slots++) { | |
1338 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
04ed3ea8 | 1339 | acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); |
72c194f7 MT |
1340 | } |
1341 | ||
cec65193 IM |
1342 | /* |
1343 | * Entry is required for Windows to enable memory hotplug in OS. | |
1344 | * Memory devices may override proximity set by this entry, | |
1345 | * providing _PXM method if necessary. | |
1346 | */ | |
1347 | if (hotplugabble_address_space_size) { | |
1348 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
1349 | acpi_build_srat_memory(numamem, pcms->hotplug_memory_base, | |
1350 | hotplugabble_address_space_size, 0, | |
1351 | MEM_AFFINITY_HOTPLUGGABLE | | |
1352 | MEM_AFFINITY_ENABLED); | |
1353 | } | |
1354 | ||
72c194f7 MT |
1355 | build_header(linker, table_data, |
1356 | (void *)(table_data->data + srat_start), | |
821e3227 | 1357 | "SRAT", |
72c194f7 MT |
1358 | table_data->len - srat_start, 1); |
1359 | } | |
1360 | ||
1361 | static void | |
1362 | build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) | |
1363 | { | |
1364 | AcpiTableMcfg *mcfg; | |
821e3227 | 1365 | const char *sig; |
72c194f7 MT |
1366 | int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); |
1367 | ||
1368 | mcfg = acpi_data_push(table_data, len); | |
1369 | mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); | |
1370 | /* Only a single allocation so no need to play with segments */ | |
1371 | mcfg->allocation[0].pci_segment = cpu_to_le16(0); | |
1372 | mcfg->allocation[0].start_bus_number = 0; | |
1373 | mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); | |
1374 | ||
1375 | /* MCFG is used for ECAM which can be enabled or disabled by guest. | |
1376 | * To avoid table size changes (which create migration issues), | |
1377 | * always create the table even if there are no allocations, | |
1378 | * but set the signature to a reserved value in this case. | |
1379 | * ACPI spec requires OSPMs to ignore such tables. | |
1380 | */ | |
1381 | if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { | |
821e3227 MT |
1382 | /* Reserved signature: ignored by OSPM */ |
1383 | sig = "QEMU"; | |
72c194f7 | 1384 | } else { |
821e3227 | 1385 | sig = "MCFG"; |
72c194f7 MT |
1386 | } |
1387 | build_header(linker, table_data, (void *)mcfg, sig, len, 1); | |
1388 | } | |
1389 | ||
d4eb9119 LT |
1390 | static void |
1391 | build_dmar_q35(GArray *table_data, GArray *linker) | |
1392 | { | |
1393 | int dmar_start = table_data->len; | |
1394 | ||
1395 | AcpiTableDmar *dmar; | |
1396 | AcpiDmarHardwareUnit *drhd; | |
1397 | ||
1398 | dmar = acpi_data_push(table_data, sizeof(*dmar)); | |
1399 | dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; | |
1400 | dmar->flags = 0; /* No intr_remap for now */ | |
1401 | ||
1402 | /* DMAR Remapping Hardware Unit Definition structure */ | |
1403 | drhd = acpi_data_push(table_data, sizeof(*drhd)); | |
1404 | drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); | |
1405 | drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ | |
1406 | drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; | |
1407 | drhd->pci_segment = cpu_to_le16(0); | |
1408 | drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); | |
1409 | ||
1410 | build_header(linker, table_data, (void *)(table_data->data + dmar_start), | |
1411 | "DMAR", table_data->len - dmar_start, 1); | |
1412 | } | |
1413 | ||
72c194f7 MT |
1414 | static void |
1415 | build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) | |
1416 | { | |
53db092a MT |
1417 | AcpiTableHeader *dsdt; |
1418 | ||
72c194f7 | 1419 | assert(misc->dsdt_code && misc->dsdt_size); |
53db092a | 1420 | |
72c194f7 MT |
1421 | dsdt = acpi_data_push(table_data, misc->dsdt_size); |
1422 | memcpy(dsdt, misc->dsdt_code, misc->dsdt_size); | |
53db092a MT |
1423 | |
1424 | memset(dsdt, 0, sizeof *dsdt); | |
821e3227 | 1425 | build_header(linker, table_data, dsdt, "DSDT", |
53db092a | 1426 | misc->dsdt_size, 1); |
72c194f7 MT |
1427 | } |
1428 | ||
1429 | /* Build final rsdt table */ | |
1430 | static void | |
1431 | build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets) | |
1432 | { | |
1433 | AcpiRsdtDescriptorRev1 *rsdt; | |
1434 | size_t rsdt_len; | |
1435 | int i; | |
1436 | ||
1437 | rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len; | |
1438 | rsdt = acpi_data_push(table_data, rsdt_len); | |
1439 | memcpy(rsdt->table_offset_entry, table_offsets->data, | |
1440 | sizeof(uint32_t) * table_offsets->len); | |
1441 | for (i = 0; i < table_offsets->len; ++i) { | |
1442 | /* rsdt->table_offset_entry to be filled by Guest linker */ | |
1443 | bios_linker_loader_add_pointer(linker, | |
1444 | ACPI_BUILD_TABLE_FILE, | |
1445 | ACPI_BUILD_TABLE_FILE, | |
1446 | table_data, &rsdt->table_offset_entry[i], | |
1447 | sizeof(uint32_t)); | |
1448 | } | |
1449 | build_header(linker, table_data, | |
821e3227 | 1450 | (void *)rsdt, "RSDT", rsdt_len, 1); |
72c194f7 MT |
1451 | } |
1452 | ||
1453 | static GArray * | |
1454 | build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) | |
1455 | { | |
1456 | AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); | |
1457 | ||
d67aadcc | 1458 | bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, |
72c194f7 MT |
1459 | true /* fseg memory */); |
1460 | ||
821e3227 | 1461 | memcpy(&rsdp->signature, "RSD PTR ", 8); |
72c194f7 MT |
1462 | memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); |
1463 | rsdp->rsdt_physical_address = cpu_to_le32(rsdt); | |
1464 | /* Address to be filled by Guest linker */ | |
1465 | bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, | |
1466 | ACPI_BUILD_TABLE_FILE, | |
1467 | rsdp_table, &rsdp->rsdt_physical_address, | |
1468 | sizeof rsdp->rsdt_physical_address); | |
1469 | rsdp->checksum = 0; | |
1470 | /* Checksum to be filled by Guest linker */ | |
1471 | bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, | |
1472 | rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); | |
1473 | ||
1474 | return rsdp_table; | |
1475 | } | |
1476 | ||
1477 | typedef | |
1478 | struct AcpiBuildTables { | |
1479 | GArray *table_data; | |
1480 | GArray *rsdp; | |
42a5b308 | 1481 | GArray *tcpalog; |
72c194f7 MT |
1482 | GArray *linker; |
1483 | } AcpiBuildTables; | |
1484 | ||
1485 | static inline void acpi_build_tables_init(AcpiBuildTables *tables) | |
1486 | { | |
1487 | tables->rsdp = g_array_new(false, true /* clear */, 1); | |
1488 | tables->table_data = g_array_new(false, true /* clear */, 1); | |
42a5b308 | 1489 | tables->tcpalog = g_array_new(false, true /* clear */, 1); |
72c194f7 MT |
1490 | tables->linker = bios_linker_loader_init(); |
1491 | } | |
1492 | ||
1493 | static inline void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) | |
1494 | { | |
1495 | void *linker_data = bios_linker_loader_cleanup(tables->linker); | |
ac369a77 | 1496 | g_free(linker_data); |
afaa2e4b | 1497 | g_array_free(tables->rsdp, true); |
ac369a77 | 1498 | g_array_free(tables->table_data, true); |
42a5b308 | 1499 | g_array_free(tables->tcpalog, mfre); |
72c194f7 MT |
1500 | } |
1501 | ||
1502 | typedef | |
1503 | struct AcpiBuildState { | |
1504 | /* Copy of table in RAM (for patching). */ | |
ad5b88b1 | 1505 | ram_addr_t table_ram; |
72c194f7 MT |
1506 | /* Is table patched? */ |
1507 | uint8_t patched; | |
1508 | PcGuestInfo *guest_info; | |
d70414a5 | 1509 | void *rsdp; |
42d85900 | 1510 | ram_addr_t rsdp_ram; |
6e00619b | 1511 | ram_addr_t linker_ram; |
72c194f7 MT |
1512 | } AcpiBuildState; |
1513 | ||
1514 | static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) | |
1515 | { | |
1516 | Object *pci_host; | |
1517 | QObject *o; | |
1518 | bool ambiguous; | |
1519 | ||
1520 | pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); | |
1521 | g_assert(!ambiguous); | |
1522 | g_assert(pci_host); | |
1523 | ||
1524 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); | |
1525 | if (!o) { | |
1526 | return false; | |
1527 | } | |
1528 | mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); | |
097a97a6 | 1529 | qobject_decref(o); |
72c194f7 MT |
1530 | |
1531 | o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); | |
1532 | assert(o); | |
1533 | mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); | |
097a97a6 | 1534 | qobject_decref(o); |
72c194f7 MT |
1535 | return true; |
1536 | } | |
1537 | ||
d4eb9119 LT |
1538 | static bool acpi_has_iommu(void) |
1539 | { | |
1540 | bool ambiguous; | |
1541 | Object *intel_iommu; | |
1542 | ||
1543 | intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, | |
1544 | &ambiguous); | |
1545 | return intel_iommu && !ambiguous; | |
1546 | } | |
1547 | ||
72c194f7 MT |
1548 | static |
1549 | void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) | |
1550 | { | |
1551 | GArray *table_offsets; | |
07fb6176 | 1552 | unsigned facs, ssdt, dsdt, rsdt; |
72c194f7 MT |
1553 | AcpiCpuInfo cpu; |
1554 | AcpiPmInfo pm; | |
1555 | AcpiMiscInfo misc; | |
1556 | AcpiMcfgInfo mcfg; | |
1557 | PcPciInfo pci; | |
1558 | uint8_t *u; | |
07fb6176 | 1559 | size_t aml_len = 0; |
7c2c1fa5 | 1560 | GArray *tables_blob = tables->table_data; |
72c194f7 MT |
1561 | |
1562 | acpi_get_cpu_info(&cpu); | |
1563 | acpi_get_pm_info(&pm); | |
1564 | acpi_get_dsdt(&misc); | |
72c194f7 MT |
1565 | acpi_get_misc_info(&misc); |
1566 | acpi_get_pci_info(&pci); | |
1567 | ||
1568 | table_offsets = g_array_new(false, true /* clear */, | |
1569 | sizeof(uint32_t)); | |
8b310fc4 | 1570 | ACPI_BUILD_DPRINTF("init ACPI tables\n"); |
72c194f7 MT |
1571 | |
1572 | bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, | |
1573 | 64 /* Ensure FACS is aligned */, | |
1574 | false /* high memory */); | |
1575 | ||
1576 | /* | |
1577 | * FACS is pointed to by FADT. | |
1578 | * We place it first since it's the only table that has alignment | |
1579 | * requirements. | |
1580 | */ | |
7c2c1fa5 IM |
1581 | facs = tables_blob->len; |
1582 | build_facs(tables_blob, tables->linker, guest_info); | |
72c194f7 MT |
1583 | |
1584 | /* DSDT is pointed to by FADT */ | |
7c2c1fa5 IM |
1585 | dsdt = tables_blob->len; |
1586 | build_dsdt(tables_blob, tables->linker, &misc); | |
72c194f7 | 1587 | |
07fb6176 PB |
1588 | /* Count the size of the DSDT and SSDT, we will need it for legacy |
1589 | * sizing of ACPI tables. | |
1590 | */ | |
7c2c1fa5 | 1591 | aml_len += tables_blob->len - dsdt; |
07fb6176 | 1592 | |
72c194f7 | 1593 | /* ACPI tables pointed to by RSDT */ |
7c2c1fa5 IM |
1594 | acpi_add_table(table_offsets, tables_blob); |
1595 | build_fadt(tables_blob, tables->linker, &pm, facs, dsdt); | |
72c194f7 | 1596 | |
7c2c1fa5 IM |
1597 | ssdt = tables_blob->len; |
1598 | acpi_add_table(table_offsets, tables_blob); | |
1599 | build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, | |
72c194f7 | 1600 | guest_info); |
7c2c1fa5 | 1601 | aml_len += tables_blob->len - ssdt; |
72c194f7 | 1602 | |
7c2c1fa5 IM |
1603 | acpi_add_table(table_offsets, tables_blob); |
1604 | build_madt(tables_blob, tables->linker, &cpu, guest_info); | |
9ac1c4c0 | 1605 | |
72c194f7 | 1606 | if (misc.has_hpet) { |
7c2c1fa5 IM |
1607 | acpi_add_table(table_offsets, tables_blob); |
1608 | build_hpet(tables_blob, tables->linker); | |
711b20b4 SB |
1609 | } |
1610 | if (misc.has_tpm) { | |
7c2c1fa5 IM |
1611 | acpi_add_table(table_offsets, tables_blob); |
1612 | build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); | |
711b20b4 | 1613 | |
7c2c1fa5 IM |
1614 | acpi_add_table(table_offsets, tables_blob); |
1615 | build_tpm_ssdt(tables_blob, tables->linker); | |
72c194f7 MT |
1616 | } |
1617 | if (guest_info->numa_nodes) { | |
7c2c1fa5 IM |
1618 | acpi_add_table(table_offsets, tables_blob); |
1619 | build_srat(tables_blob, tables->linker, guest_info); | |
72c194f7 MT |
1620 | } |
1621 | if (acpi_get_mcfg(&mcfg)) { | |
7c2c1fa5 IM |
1622 | acpi_add_table(table_offsets, tables_blob); |
1623 | build_mcfg_q35(tables_blob, tables->linker, &mcfg); | |
72c194f7 | 1624 | } |
d4eb9119 | 1625 | if (acpi_has_iommu()) { |
7c2c1fa5 IM |
1626 | acpi_add_table(table_offsets, tables_blob); |
1627 | build_dmar_q35(tables_blob, tables->linker); | |
d4eb9119 | 1628 | } |
72c194f7 MT |
1629 | |
1630 | /* Add tables supplied by user (if any) */ | |
1631 | for (u = acpi_table_first(); u; u = acpi_table_next(u)) { | |
1632 | unsigned len = acpi_table_len(u); | |
1633 | ||
7c2c1fa5 IM |
1634 | acpi_add_table(table_offsets, tables_blob); |
1635 | g_array_append_vals(tables_blob, u, len); | |
72c194f7 MT |
1636 | } |
1637 | ||
1638 | /* RSDT is pointed to by RSDP */ | |
7c2c1fa5 IM |
1639 | rsdt = tables_blob->len; |
1640 | build_rsdt(tables_blob, tables->linker, table_offsets); | |
72c194f7 MT |
1641 | |
1642 | /* RSDP is in FSEG memory, so allocate it separately */ | |
1643 | build_rsdp(tables->rsdp, tables->linker, rsdt); | |
1644 | ||
07fb6176 | 1645 | /* We'll expose it all to Guest so we want to reduce |
72c194f7 | 1646 | * chance of size changes. |
07fb6176 PB |
1647 | * |
1648 | * We used to align the tables to 4k, but of course this would | |
1649 | * too simple to be enough. 4k turned out to be too small an | |
1650 | * alignment very soon, and in fact it is almost impossible to | |
1651 | * keep the table size stable for all (max_cpus, max_memory_slots) | |
1652 | * combinations. So the table size is always 64k for pc-i440fx-2.1 | |
1653 | * and we give an error if the table grows beyond that limit. | |
1654 | * | |
1655 | * We still have the problem of migrating from "-M pc-i440fx-2.0". For | |
1656 | * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables | |
1657 | * than 2.0 and we can always pad the smaller tables with zeros. We can | |
1658 | * then use the exact size of the 2.0 tables. | |
1659 | * | |
1660 | * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. | |
72c194f7 | 1661 | */ |
07fb6176 PB |
1662 | if (guest_info->legacy_acpi_table_size) { |
1663 | /* Subtracting aml_len gives the size of fixed tables. Then add the | |
1664 | * size of the PIIX4 DSDT/SSDT in QEMU 2.0. | |
1665 | */ | |
1666 | int legacy_aml_len = | |
1667 | guest_info->legacy_acpi_table_size + | |
1668 | ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; | |
1669 | int legacy_table_size = | |
7c2c1fa5 | 1670 | ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, |
07fb6176 | 1671 | ACPI_BUILD_ALIGN_SIZE); |
7c2c1fa5 | 1672 | if (tables_blob->len > legacy_table_size) { |
07fb6176 | 1673 | /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ |
868270f2 | 1674 | error_report("Warning: migration may not work."); |
07fb6176 | 1675 | } |
7c2c1fa5 | 1676 | g_array_set_size(tables_blob, legacy_table_size); |
07fb6176 | 1677 | } else { |
868270f2 | 1678 | /* Make sure we have a buffer in case we need to resize the tables. */ |
7c2c1fa5 | 1679 | if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { |
18045fb9 | 1680 | /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ |
868270f2 MT |
1681 | error_report("Warning: ACPI tables are larger than 64k."); |
1682 | error_report("Warning: migration may not work."); | |
1683 | error_report("Warning: please remove CPUs, NUMA nodes, " | |
1684 | "memory slots or PCI bridges."); | |
18045fb9 | 1685 | } |
7c2c1fa5 | 1686 | acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); |
07fb6176 | 1687 | } |
72c194f7 | 1688 | |
07fb6176 | 1689 | acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); |
72c194f7 MT |
1690 | |
1691 | /* Cleanup memory that's no longer used. */ | |
1692 | g_array_free(table_offsets, true); | |
1693 | } | |
1694 | ||
42d85900 MT |
1695 | static void acpi_ram_update(ram_addr_t ram, GArray *data) |
1696 | { | |
1697 | uint32_t size = acpi_data_len(data); | |
1698 | ||
1699 | /* Make sure RAM size is correct - in case it got changed e.g. by migration */ | |
1700 | qemu_ram_resize(ram, size, &error_abort); | |
1701 | ||
1702 | memcpy(qemu_get_ram_ptr(ram), data->data, size); | |
1703 | cpu_physical_memory_set_dirty_range_nocode(ram, size); | |
1704 | } | |
1705 | ||
72c194f7 MT |
1706 | static void acpi_build_update(void *build_opaque, uint32_t offset) |
1707 | { | |
1708 | AcpiBuildState *build_state = build_opaque; | |
1709 | AcpiBuildTables tables; | |
1710 | ||
1711 | /* No state to update or already patched? Nothing to do. */ | |
1712 | if (!build_state || build_state->patched) { | |
1713 | return; | |
1714 | } | |
1715 | build_state->patched = 1; | |
1716 | ||
1717 | acpi_build_tables_init(&tables); | |
1718 | ||
1719 | acpi_build(build_state->guest_info, &tables); | |
1720 | ||
42d85900 | 1721 | acpi_ram_update(build_state->table_ram, tables.table_data); |
a1666142 | 1722 | |
42d85900 MT |
1723 | if (build_state->rsdp) { |
1724 | memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); | |
1725 | } else { | |
1726 | acpi_ram_update(build_state->rsdp_ram, tables.rsdp); | |
1727 | } | |
ad5b88b1 | 1728 | |
42d85900 | 1729 | acpi_ram_update(build_state->linker_ram, tables.linker); |
72c194f7 MT |
1730 | acpi_build_tables_cleanup(&tables, true); |
1731 | } | |
1732 | ||
1733 | static void acpi_build_reset(void *build_opaque) | |
1734 | { | |
1735 | AcpiBuildState *build_state = build_opaque; | |
1736 | build_state->patched = 0; | |
1737 | } | |
1738 | ||
ad5b88b1 | 1739 | static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob, |
a1666142 | 1740 | const char *name, uint64_t max_size) |
72c194f7 | 1741 | { |
a1666142 MT |
1742 | return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, |
1743 | name, acpi_build_update, build_state); | |
72c194f7 MT |
1744 | } |
1745 | ||
1746 | static const VMStateDescription vmstate_acpi_build = { | |
1747 | .name = "acpi_build", | |
1748 | .version_id = 1, | |
1749 | .minimum_version_id = 1, | |
d49805ae | 1750 | .fields = (VMStateField[]) { |
72c194f7 MT |
1751 | VMSTATE_UINT8(patched, AcpiBuildState), |
1752 | VMSTATE_END_OF_LIST() | |
1753 | }, | |
1754 | }; | |
1755 | ||
1756 | void acpi_setup(PcGuestInfo *guest_info) | |
1757 | { | |
1758 | AcpiBuildTables tables; | |
1759 | AcpiBuildState *build_state; | |
1760 | ||
1761 | if (!guest_info->fw_cfg) { | |
8b310fc4 | 1762 | ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); |
72c194f7 MT |
1763 | return; |
1764 | } | |
1765 | ||
1766 | if (!guest_info->has_acpi_build) { | |
8b310fc4 | 1767 | ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); |
72c194f7 MT |
1768 | return; |
1769 | } | |
1770 | ||
81adc513 | 1771 | if (!acpi_enabled) { |
8b310fc4 | 1772 | ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); |
81adc513 MT |
1773 | return; |
1774 | } | |
1775 | ||
72c194f7 MT |
1776 | build_state = g_malloc0(sizeof *build_state); |
1777 | ||
1778 | build_state->guest_info = guest_info; | |
1779 | ||
99fd437d MT |
1780 | acpi_set_pci_info(); |
1781 | ||
72c194f7 MT |
1782 | acpi_build_tables_init(&tables); |
1783 | acpi_build(build_state->guest_info, &tables); | |
1784 | ||
1785 | /* Now expose it all to Guest */ | |
1786 | build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data, | |
a1666142 MT |
1787 | ACPI_BUILD_TABLE_FILE, |
1788 | ACPI_BUILD_TABLE_MAX_SIZE); | |
ad5b88b1 | 1789 | assert(build_state->table_ram != RAM_ADDR_MAX); |
72c194f7 | 1790 | |
6e00619b IM |
1791 | build_state->linker_ram = |
1792 | acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); | |
72c194f7 | 1793 | |
42a5b308 SB |
1794 | fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, |
1795 | tables.tcpalog->data, acpi_data_len(tables.tcpalog)); | |
1796 | ||
384fb32e | 1797 | if (!guest_info->rsdp_in_ram) { |
358774d7 IM |
1798 | /* |
1799 | * Keep for compatibility with old machine types. | |
1800 | * Though RSDP is small, its contents isn't immutable, so | |
afaa2e4b | 1801 | * we'll update it along with the rest of tables on guest access. |
358774d7 | 1802 | */ |
afaa2e4b MT |
1803 | uint32_t rsdp_size = acpi_data_len(tables.rsdp); |
1804 | ||
1805 | build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); | |
358774d7 IM |
1806 | fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE, |
1807 | acpi_build_update, build_state, | |
afaa2e4b | 1808 | build_state->rsdp, rsdp_size); |
42d85900 | 1809 | build_state->rsdp_ram = (ram_addr_t)-1; |
358774d7 | 1810 | } else { |
42d85900 MT |
1811 | build_state->rsdp = NULL; |
1812 | build_state->rsdp_ram = acpi_add_rom_blob(build_state, tables.rsdp, | |
1813 | ACPI_BUILD_RSDP_FILE, 0); | |
358774d7 | 1814 | } |
72c194f7 MT |
1815 | |
1816 | qemu_register_reset(acpi_build_reset, build_state); | |
1817 | acpi_build_reset(build_state); | |
1818 | vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); | |
1819 | ||
1820 | /* Cleanup tables but don't free the memory: we track it | |
1821 | * in build_state. | |
1822 | */ | |
1823 | acpi_build_tables_cleanup(&tables, false); | |
1824 | } |