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acpi: enable INTR for DMAR report structure
[mirror_qemu.git] / hw / i386 / acpi-build.c
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72c194f7
MT		 1/* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
b6a0aa05 23#include "qemu/osdep.h"
da34e65c 24#include "qapi/error.h"
72c194f7 25#include "acpi-build.h"
72c194f7
MT		 26#include "qemu-common.h"
27#include "qemu/bitmap.h"
07fb6176 28#include "qemu/error-report.h"
72c194f7
MT		 29#include "hw/pci/pci.h"
30#include "qom/cpu.h"
31#include "hw/i386/pc.h"
32#include "target-i386/cpu.h"
33#include "hw/timer/hpet.h"
395e5fb4 34#include "hw/acpi/acpi-defs.h"
72c194f7 35#include "hw/acpi/acpi.h"
679dd1a9 36#include "hw/acpi/cpu.h"
72c194f7 37#include "hw/nvram/fw_cfg.h"
0058ae1d 38#include "hw/acpi/bios-linker-loader.h"
72c194f7 39#include "hw/loader.h"
15bce1b7 40#include "hw/isa/isa.h"
27b9fc54 41#include "hw/block/fdc.h"
bef3492d 42#include "hw/acpi/memory_hotplug.h"
711b20b4
SB		 43#include "sysemu/tpm.h"
44#include "hw/acpi/tpm.h"
5cb18b3d 45#include "sysemu/tpm_backend.h"
f070efa8 46#include "hw/timer/mc146818rtc_regs.h"
1f3aba37 47#include "sysemu/numa.h"
72c194f7
MT		 48
49/* Supported chipsets: */
50#include "hw/acpi/piix4.h"
99fd437d 51#include "hw/acpi/pcihp.h"
72c194f7
MT		 52#include "hw/i386/ich9.h"
53#include "hw/pci/pci_bus.h"
54#include "hw/pci-host/q35.h"
1cf5fd57 55#include "hw/i386/x86-iommu.h"
a57d708d 56#include "hw/timer/hpet.h"
72c194f7 57
19934e0e
IM		 58#include "hw/acpi/aml-build.h"
59
72c194f7
MT		 60#include "qapi/qmp/qint.h"
61#include "qom/qom-qobject.h"
d46114f9 62#include "hw/i386/x86-iommu.h"
72c194f7 63
86e91dd7
CM		 64#include "hw/acpi/ipmi.h"
65
07fb6176
PB		 66/* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
67 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
68 * a little bit, there should be plenty of free space since the DSDT
69 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
70 */
71#define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
72#define ACPI_BUILD_ALIGN_SIZE 0x1000
73
868270f2 74#define ACPI_BUILD_TABLE_SIZE 0x20000
18045fb9 75
8b310fc4
GA		 76/* #define DEBUG_ACPI_BUILD */
77#ifdef DEBUG_ACPI_BUILD
78#define ACPI_BUILD_DPRINTF(fmt, ...) \
79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
80#else
81#define ACPI_BUILD_DPRINTF(fmt, ...)
82#endif
83
72c194f7
MT		 84typedef struct AcpiMcfgInfo {
85 uint64_t mcfg_base;
86 uint32_t mcfg_size;
87} AcpiMcfgInfo;
88
89typedef struct AcpiPmInfo {
90 bool s3_disabled;
91 bool s4_disabled;
133a2da4 92 bool pcihp_bridge_en;
72c194f7
MT		 93 uint8_t s4_val;
94 uint16_t sci_int;
95 uint8_t acpi_enable_cmd;
96 uint8_t acpi_disable_cmd;
97 uint32_t gpe0_blk;
98 uint32_t gpe0_blk_len;
99 uint32_t io_base;
ddf1ec2f 100 uint16_t cpu_hp_io_base;
2c6b94d8
IM		 101 uint16_t mem_hp_io_base;
102 uint16_t mem_hp_io_len;
500b11ea
IM		 103 uint16_t pcihp_io_base;
104 uint16_t pcihp_io_len;
72c194f7
MT		 105} AcpiPmInfo;
106
107typedef struct AcpiMiscInfo {
e4db2798 108 bool is_piix4;
72c194f7 109 bool has_hpet;
5cb18b3d 110 TPMVersion tpm_version;
72c194f7
MT		 111 const unsigned char *dsdt_code;
112 unsigned dsdt_size;
113 uint16_t pvpanic_port;
8ac6f7a6 114 uint16_t applesmc_io_base;
72c194f7
MT		 115} AcpiMiscInfo;
116
99fd437d
MT		 117typedef struct AcpiBuildPciBusHotplugState {
118 GArray *device_table;
119 GArray *notify_table;
120 struct AcpiBuildPciBusHotplugState *parent;
133a2da4 121 bool pcihp_bridge_en;
99fd437d
MT		 122} AcpiBuildPciBusHotplugState;
123
72c194f7
MT		 124static void acpi_get_pm_info(AcpiPmInfo *pm)
125{
126 Object *piix = piix4_pm_find();
127 Object *lpc = ich9_lpc_find();
128 Object *obj = NULL;
129 QObject *o;
130
94aaca64 131 pm->cpu_hp_io_base = 0;
500b11ea
IM		 132 pm->pcihp_io_base = 0;
133 pm->pcihp_io_len = 0;
72c194f7
MT		 134 if (piix) {
135 obj = piix;
ddf1ec2f 136 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
500b11ea
IM		 137 pm->pcihp_io_base =
138 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
139 pm->pcihp_io_len =
140 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
72c194f7
MT		 141 }
142 if (lpc) {
143 obj = lpc;
ddf1ec2f 144 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
72c194f7
MT		 145 }
146 assert(obj);
147
2c6b94d8
IM		 148 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
149 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
150
72c194f7
MT		 151 /* Fill in optional s3/s4 related properties */
152 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
153 if (o) {
154 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
155 } else {
156 pm->s3_disabled = false;
157 }
097a97a6 158 qobject_decref(o);
72c194f7
MT		 159 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
160 if (o) {
161 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
162 } else {
163 pm->s4_disabled = false;
164 }
097a97a6 165 qobject_decref(o);
72c194f7
MT		 166 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
167 if (o) {
168 pm->s4_val = qint_get_int(qobject_to_qint(o));
169 } else {
170 pm->s4_val = false;
171 }
097a97a6 172 qobject_decref(o);
72c194f7
MT		 173
174 /* Fill in mandatory properties */
175 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
176
177 pm->acpi_enable_cmd = object_property_get_int(obj,
178 ACPI_PM_PROP_ACPI_ENABLE_CMD,
179 NULL);
180 pm->acpi_disable_cmd = object_property_get_int(obj,
181 ACPI_PM_PROP_ACPI_DISABLE_CMD,
182 NULL);
183 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
184 NULL);
185 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
186 NULL);
187 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
188 NULL);
133a2da4
IM		 189 pm->pcihp_bridge_en =
190 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
191 NULL);
72c194f7
MT		 192}
193
72c194f7
MT		 194static void acpi_get_misc_info(AcpiMiscInfo *info)
195{
3db119da
IM		 196 Object *piix = piix4_pm_find();
197 Object *lpc = ich9_lpc_find();
198 assert(!!piix != !!lpc);
199
200 if (piix) {
201 info->is_piix4 = true;
202 }
203 if (lpc) {
204 info->is_piix4 = false;
205 }
206
72c194f7 207 info->has_hpet = hpet_find();
5cb18b3d 208 info->tpm_version = tpm_get_version();
72c194f7 209 info->pvpanic_port = pvpanic_port();
8ac6f7a6 210 info->applesmc_io_base = applesmc_port();
72c194f7
MT		 211}
212
ca6c1855
MA		 213/*
214 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
215 * On i386 arch we only have two pci hosts, so we can look only for them.
216 */
217static Object *acpi_get_i386_pci_host(void)
218{
219 PCIHostState *host;
220
221 host = OBJECT_CHECK(PCIHostState,
222 object_resolve_path("/machine/i440fx", NULL),
223 TYPE_PCI_HOST_BRIDGE);
224 if (!host) {
225 host = OBJECT_CHECK(PCIHostState,
226 object_resolve_path("/machine/q35", NULL),
227 TYPE_PCI_HOST_BRIDGE);
228 }
229
230 return OBJECT(host);
231}
232
01c9742d 233static void acpi_get_pci_holes(Range *hole, Range *hole64)
72c194f7
MT		 234{
235 Object *pci_host;
72c194f7 236
ca6c1855 237 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 238 g_assert(pci_host);
239
a0efbf16
MA		 240 range_set_bounds1(hole,
241 object_property_get_int(pci_host,
242 PCI_HOST_PROP_PCI_HOLE_START,
243 NULL),
244 object_property_get_int(pci_host,
245 PCI_HOST_PROP_PCI_HOLE_END,
246 NULL));
247 range_set_bounds1(hole64,
248 object_property_get_int(pci_host,
249 PCI_HOST_PROP_PCI_HOLE64_START,
250 NULL),
251 object_property_get_int(pci_host,
252 PCI_HOST_PROP_PCI_HOLE64_END,
253 NULL));
72c194f7
MT		 254}
255
72c194f7
MT		 256#define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
257
72c194f7
MT		 258static void acpi_align_size(GArray *blob, unsigned align)
259{
260 /* Align size to multiple of given size. This reduces the chance
261 * we need to change size in the future (breaking cross version migration).
262 */
134d42d6 263 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
72c194f7
MT		 264}
265
72c194f7
MT		 266/* FACS */
267static void
0e9b9eda 268build_facs(GArray *table_data, BIOSLinker *linker)
72c194f7
MT		 269{
270 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
821e3227 271 memcpy(&facs->signature, "FACS", 4);
72c194f7
MT		 272 facs->length = cpu_to_le32(sizeof(*facs));
273}
274
275/* Load chipset information in FADT */
276static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
277{
278 fadt->model = 1;
279 fadt->reserved1 = 0;
280 fadt->sci_int = cpu_to_le16(pm->sci_int);
281 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
282 fadt->acpi_enable = pm->acpi_enable_cmd;
283 fadt->acpi_disable = pm->acpi_disable_cmd;
284 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
285 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
286 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
287 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
288 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
289 /* EVT, CNT, TMR length matches hw/acpi/core.c */
290 fadt->pm1_evt_len = 4;
291 fadt->pm1_cnt_len = 2;
292 fadt->pm_tmr_len = 4;
293 fadt->gpe0_blk_len = pm->gpe0_blk_len;
294 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
295 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
296 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
297 (1 << ACPI_FADT_F_PROC_C1) |
298 (1 << ACPI_FADT_F_SLP_BUTTON) |
299 (1 << ACPI_FADT_F_RTC_S4));
300 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
07b81ed9
HZ		 301 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
302 * For more than 8 CPUs, "Clustered Logical" mode has to be used
303 */
304 if (max_cpus > 8) {
305 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
306 }
f070efa8 307 fadt->century = RTC_CENTURY;
72c194f7
MT		 308}
309
310
311/* FADT */
312static void
0e9b9eda 313build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
4678124b 314 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset,
ae123749 315 const char *oem_id, const char *oem_table_id)
72c194f7
MT		 316{
317 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
4678124b
IM		 318 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data;
319 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
72c194f7 320
72c194f7 321 /* FACS address to be filled by Guest linker */
4678124b
IM		 322 bios_linker_loader_add_pointer(linker,
323 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
324 ACPI_BUILD_TABLE_FILE, facs_tbl_offset);
72c194f7 325
72c194f7 326 /* DSDT address to be filled by Guest linker */
72c194f7 327 fadt_setup(fadt, pm);
4678124b
IM		 328 bios_linker_loader_add_pointer(linker,
329 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
330 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
72c194f7
MT		 331
332 build_header(linker, table_data,
ae123749 333 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
72c194f7
MT		 334}
335
ac35f13b
IM		 336void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
337 CPUArchIdList *apic_ids, GArray *entry)
338{
339 int apic_id;
340 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
341
342 apic_id = apic_ids->cpus[uid].arch_id;
343 apic->type = ACPI_APIC_PROCESSOR;
344 apic->length = sizeof(*apic);
345 apic->processor_id = uid;
346 apic->local_apic_id = apic_id;
347 if (apic_ids->cpus[uid].cpu != NULL) {
348 apic->flags = cpu_to_le32(1);
349 } else {
350 /* ACPI spec says that LAPIC entry for non present
351 * CPU may be omitted from MADT or it must be marked
352 * as disabled. However omitting non present CPU from
353 * MADT breaks hotplug on linux. So possible CPUs
354 * should be put in MADT but kept disabled.
355 */
356 apic->flags = cpu_to_le32(0);
357 }
358}
359
72c194f7 360static void
0e9b9eda 361build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
72c194f7 362{
907e7c94
IM		 363 MachineClass *mc = MACHINE_GET_CLASS(pcms);
364 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
72c194f7 365 int madt_start = table_data->len;
ac35f13b
IM		 366 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
367 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
72c194f7
MT		 368
369 AcpiMultipleApicTable *madt;
370 AcpiMadtIoApic *io_apic;
371 AcpiMadtIntsrcovr *intsrcovr;
372 AcpiMadtLocalNmi *local_nmi;
373 int i;
374
375 madt = acpi_data_push(table_data, sizeof *madt);
376 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
377 madt->flags = cpu_to_le32(1);
378
907e7c94 379 for (i = 0; i < apic_ids->len; i++) {
ac35f13b 380 adevc->madt_cpu(adev, i, apic_ids, table_data);
72c194f7 381 }
907e7c94
IM		 382 g_free(apic_ids);
383
72c194f7
MT		 384 io_apic = acpi_data_push(table_data, sizeof *io_apic);
385 io_apic->type = ACPI_APIC_IO;
386 io_apic->length = sizeof(*io_apic);
387#define ACPI_BUILD_IOAPIC_ID 0x0
388 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
389 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
390 io_apic->interrupt = cpu_to_le32(0);
391
dd4c2f01 392 if (pcms->apic_xrupt_override) {
72c194f7
MT		 393 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
394 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
395 intsrcovr->length = sizeof(*intsrcovr);
396 intsrcovr->source = 0;
397 intsrcovr->gsi = cpu_to_le32(2);
398 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
399 }
400 for (i = 1; i < 16; i++) {
401#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
402 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
403 /* No need for a INT source override structure. */
404 continue;
405 }
406 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
407 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
408 intsrcovr->length = sizeof(*intsrcovr);
409 intsrcovr->source = i;
410 intsrcovr->gsi = cpu_to_le32(i);
411 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
412 }
413
414 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
415 local_nmi->type = ACPI_APIC_LOCAL_NMI;
416 local_nmi->length = sizeof(*local_nmi);
417 local_nmi->processor_id = 0xff; /* all processors */
418 local_nmi->flags = cpu_to_le16(0);
419 local_nmi->lint = 1; /* ACPI_LINT1 */
420
421 build_header(linker, table_data,
821e3227 422 (void *)(table_data->data + madt_start), "APIC",
37ad223c 423 table_data->len - madt_start, 1, NULL, NULL);
72c194f7
MT		 424}
425
99fd437d
MT		 426/* Assign BSEL property to all buses. In the future, this can be changed
427 * to only assign to buses that support hotplug.
428 */
429static void *acpi_set_bsel(PCIBus *bus, void *opaque)
430{
431 unsigned *bsel_alloc = opaque;
432 unsigned *bus_bsel;
433
39b888bd 434 if (qbus_is_hotpluggable(BUS(bus))) {
99fd437d
MT		 435 bus_bsel = g_malloc(sizeof *bus_bsel);
436
437 *bus_bsel = (*bsel_alloc)++;
438 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
439 bus_bsel, NULL);
440 }
441
442 return bsel_alloc;
443}
444
445static void acpi_set_pci_info(void)
446{
447 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
448 unsigned bsel_alloc = 0;
449
450 if (bus) {
451 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
452 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
453 }
454}
455
62b52c26 456static void build_append_pcihp_notify_entry(Aml *method, int slot)
99fd437d 457{
62b52c26
IM		 458 Aml *if_ctx;
459 int32_t devfn = PCI_DEVFN(slot, 0);
460
5530427f 461 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
62b52c26
IM		 462 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
463 aml_append(method, if_ctx);
99fd437d
MT		 464}
465
62b52c26 466static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
b23046ab 467 bool pcihp_bridge_en)
99fd437d 468{
62b52c26 469 Aml *dev, *notify_method, *method;
99fd437d 470 QObject *bsel;
b23046ab
IM		 471 PCIBus *sec;
472 int i;
133a2da4 473
99fd437d
MT		 474 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
475 if (bsel) {
62b52c26
IM		 476 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
477
478 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
4dbfc881 479 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
8dcf525a 480 }
99fd437d 481
8dcf525a
MT		 482 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
483 DeviceClass *dc;
484 PCIDeviceClass *pc;
485 PCIDevice *pdev = bus->devices[i];
486 int slot = PCI_SLOT(i);
b23046ab 487 bool hotplug_enabled_dev;
093a35e5 488 bool bridge_in_acpi;
99fd437d 489
8dcf525a 490 if (!pdev) {
b23046ab 491 if (bsel) { /* add hotplug slots for non present devices */
62b52c26
IM		 492 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
493 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
494 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
4dbfc881 495 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 496 aml_append(method,
497 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
498 );
499 aml_append(dev, method);
500 aml_append(parent_scope, dev);
501
502 build_append_pcihp_notify_entry(notify_method, slot);
b23046ab 503 }
8dcf525a
MT		 504 continue;
505 }
99fd437d 506
8dcf525a
MT		 507 pc = PCI_DEVICE_GET_CLASS(pdev);
508 dc = DEVICE_GET_CLASS(pdev);
99fd437d 509
093a35e5
MT		 510 /* When hotplug for bridges is enabled, bridges are
511 * described in ACPI separately (see build_pci_bus_end).
512 * In this case they aren't themselves hot-pluggable.
a20275fa 513 * Hotplugged bridges *are* hot-pluggable.
093a35e5 514 */
b23046ab
IM		 515 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
516 !DEVICE(pdev)->hotplugged;
517
518 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
093a35e5 519
b23046ab
IM		 520 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
521 continue;
99fd437d
MT		 522 }
523
62b52c26
IM		 524 /* start to compose PCI slot descriptor */
525 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
526 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
527
8dcf525a 528 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
62b52c26
IM		 529 /* add VGA specific AML methods */
530 int s3d;
531
8dcf525a 532 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
62b52c26 533 s3d = 3;
b23046ab 534 } else {
62b52c26 535 s3d = 0;
99fd437d 536 }
62b52c26 537
4dbfc881 538 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 539 aml_append(method, aml_return(aml_int(0)));
540 aml_append(dev, method);
541
4dbfc881 542 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 543 aml_append(method, aml_return(aml_int(0)));
544 aml_append(dev, method);
545
4dbfc881 546 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 547 aml_append(method, aml_return(aml_int(s3d)));
548 aml_append(dev, method);
b23046ab 549 } else if (hotplug_enabled_dev) {
62b52c26
IM		 550 /* add _SUN/_EJ0 to make slot hotpluggable */
551 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
99fd437d 552
4dbfc881 553 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 554 aml_append(method,
555 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
556 );
557 aml_append(dev, method);
558
559 if (bsel) {
560 build_append_pcihp_notify_entry(notify_method, slot);
561 }
b23046ab 562 } else if (bridge_in_acpi) {
62b52c26
IM		 563 /*
564 * device is coldplugged bridge,
565 * add child device descriptions into its scope
566 */
b23046ab 567 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
b23046ab 568
62b52c26 569 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
8dcf525a 570 }
62b52c26
IM		 571 /* slot descriptor has been composed, add it into parent context */
572 aml_append(parent_scope, dev);
8dcf525a
MT		 573 }
574
575 if (bsel) {
62b52c26 576 aml_append(parent_scope, notify_method);
99fd437d
MT		 577 }
578
579 /* Append PCNT method to notify about events on local and child buses.
580 * Add unconditionally for root since DSDT expects it.
72c194f7 581 */
4dbfc881 582 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
99fd437d 583
b23046ab
IM		 584 /* If bus supports hotplug select it and notify about local events */
585 if (bsel) {
62b52c26
IM		 586 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
587 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
588 aml_append(method,
589 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
590 );
591 aml_append(method,
592 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
593 );
b23046ab 594 }
99fd437d 595
b23046ab
IM		 596 /* Notify about child bus events in any case */
597 if (pcihp_bridge_en) {
598 QLIST_FOREACH(sec, &bus->child, sibling) {
62b52c26
IM		 599 int32_t devfn = sec->parent_dev->devfn;
600
601 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
99fd437d 602 }
72c194f7 603 }
62b52c26 604 aml_append(parent_scope, method);
d370dfa9 605 qobject_decref(bsel);
72c194f7
MT		 606}
607
196e2137
IM		 608/**
609 * build_prt_entry:
610 * @link_name: link name for PCI route entry
611 *
612 * build AML package containing a PCI route entry for @link_name
613 */
614static Aml *build_prt_entry(const char *link_name)
615{
616 Aml *a_zero = aml_int(0);
617 Aml *pkg = aml_package(4);
618 aml_append(pkg, a_zero);
619 aml_append(pkg, a_zero);
620 aml_append(pkg, aml_name("%s", link_name));
621 aml_append(pkg, a_zero);
622 return pkg;
623}
624
0d8935e3
MA		 625/*
626 * initialize_route - Initialize the interrupt routing rule
627 * through a specific LINK:
628 * if (lnk_idx == idx)
629 * route using link 'link_name'
630 */
631static Aml *initialize_route(Aml *route, const char *link_name,
632 Aml *lnk_idx, int idx)
633{
634 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
196e2137 635 Aml *pkg = build_prt_entry(link_name);
0d8935e3 636
0d8935e3
MA		 637 aml_append(if_ctx, aml_store(pkg, route));
638
639 return if_ctx;
640}
641
642/*
643 * build_prt - Define interrupt rounting rules
644 *
645 * Returns an array of 128 routes, one for each device,
646 * based on device location.
647 * The main goal is to equaly distribute the interrupts
648 * over the 4 existing ACPI links (works only for i440fx).
649 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
650 *
651 */
196e2137 652static Aml *build_prt(bool is_pci0_prt)
0d8935e3
MA		 653{
654 Aml *method, *while_ctx, *pin, *res;
655
4dbfc881 656 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
0d8935e3
MA		 657 res = aml_local(0);
658 pin = aml_local(1);
659 aml_append(method, aml_store(aml_package(128), res));
660 aml_append(method, aml_store(aml_int(0), pin));
661
662 /* while (pin < 128) */
663 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
664 {
665 Aml *slot = aml_local(2);
666 Aml *lnk_idx = aml_local(3);
667 Aml *route = aml_local(4);
668
669 /* slot = pin >> 2 */
670 aml_append(while_ctx,
c360639a 671 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
0d8935e3
MA		 672 /* lnk_idx = (slot + pin) & 3 */
673 aml_append(while_ctx,
5530427f
IM		 674 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
675 lnk_idx));
0d8935e3
MA		 676
677 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
678 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
196e2137
IM		 679 if (is_pci0_prt) {
680 Aml *if_device_1, *if_pin_4, *else_pin_4;
681
682 /* device 1 is the power-management device, needs SCI */
683 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
684 {
685 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
686 {
687 aml_append(if_pin_4,
688 aml_store(build_prt_entry("LNKS"), route));
689 }
690 aml_append(if_device_1, if_pin_4);
691 else_pin_4 = aml_else();
692 {
693 aml_append(else_pin_4,
694 aml_store(build_prt_entry("LNKA"), route));
695 }
696 aml_append(if_device_1, else_pin_4);
697 }
698 aml_append(while_ctx, if_device_1);
699 } else {
700 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
701 }
0d8935e3
MA		 702 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
703 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
704
705 /* route[0] = 0x[slot]FFFF */
706 aml_append(while_ctx,
ca3df95d
IM		 707 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
708 NULL),
0d8935e3
MA		 709 aml_index(route, aml_int(0))));
710 /* route[1] = pin & 3 */
711 aml_append(while_ctx,
5530427f
IM		 712 aml_store(aml_and(pin, aml_int(3), NULL),
713 aml_index(route, aml_int(1))));
0d8935e3
MA		 714 /* res[pin] = route */
715 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
716 /* pin++ */
717 aml_append(while_ctx, aml_increment(pin));
718 }
719 aml_append(method, while_ctx);
720 /* return res*/
721 aml_append(method, aml_return(res));
722
723 return method;
724}
725
a43c6e27
MA		 726typedef struct CrsRangeEntry {
727 uint64_t base;
728 uint64_t limit;
729} CrsRangeEntry;
730
731static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
732{
733 CrsRangeEntry *entry;
734
735 entry = g_malloc(sizeof(*entry));
736 entry->base = base;
737 entry->limit = limit;
738
739 g_ptr_array_add(ranges, entry);
740}
741
742static void crs_range_free(gpointer data)
743{
744 CrsRangeEntry *entry = (CrsRangeEntry *)data;
745 g_free(entry);
746}
747
dcdca296
MA		 748static gint crs_range_compare(gconstpointer a, gconstpointer b)
749{
750 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
751 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
752
753 return (int64_t)entry_a->base - (int64_t)entry_b->base;
754}
755
756/*
757 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
758 * interval, computes the 'free' ranges from the same interval.
759 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
760 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
761 */
762static void crs_replace_with_free_ranges(GPtrArray *ranges,
763 uint64_t start, uint64_t end)
764{
765 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
766 uint64_t free_base = start;
767 int i;
768
769 g_ptr_array_sort(ranges, crs_range_compare);
770 for (i = 0; i < ranges->len; i++) {
771 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
772
773 if (free_base < used->base) {
774 crs_range_insert(free_ranges, free_base, used->base - 1);
775 }
776
777 free_base = used->limit + 1;
778 }
779
780 if (free_base < end) {
781 crs_range_insert(free_ranges, free_base, end);
782 }
783
784 g_ptr_array_set_size(ranges, 0);
785 for (i = 0; i < free_ranges->len; i++) {
786 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
787 }
788
789 g_ptr_array_free(free_ranges, false);
790}
791
d7fd0e69
MA		 792/*
793 * crs_range_merge - merges adjacent ranges in the given array.
794 * Array elements are deleted and replaced with the merged ranges.
795 */
796static void crs_range_merge(GPtrArray *range)
797{
798 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
799 CrsRangeEntry *entry;
800 uint64_t range_base, range_limit;
801 int i;
802
803 if (!range->len) {
804 return;
805 }
806
807 g_ptr_array_sort(range, crs_range_compare);
808
809 entry = g_ptr_array_index(range, 0);
810 range_base = entry->base;
811 range_limit = entry->limit;
812 for (i = 1; i < range->len; i++) {
813 entry = g_ptr_array_index(range, i);
814 if (entry->base - 1 == range_limit) {
815 range_limit = entry->limit;
816 } else {
817 crs_range_insert(tmp, range_base, range_limit);
818 range_base = entry->base;
819 range_limit = entry->limit;
820 }
821 }
822 crs_range_insert(tmp, range_base, range_limit);
823
824 g_ptr_array_set_size(range, 0);
825 for (i = 0; i < tmp->len; i++) {
826 entry = g_ptr_array_index(tmp, i);
827 crs_range_insert(range, entry->base, entry->limit);
828 }
829 g_ptr_array_free(tmp, true);
830}
831
a43c6e27
MA		 832static Aml *build_crs(PCIHostState *host,
833 GPtrArray *io_ranges, GPtrArray *mem_ranges)
834{
835 Aml *crs = aml_resource_template();
d7fd0e69
MA		 836 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
837 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
838 CrsRangeEntry *entry;
a43c6e27
MA		 839 uint8_t max_bus = pci_bus_num(host->bus);
840 uint8_t type;
841 int devfn;
d7fd0e69 842 int i;
a43c6e27
MA		 843
844 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
a43c6e27
MA		 845 uint64_t range_base, range_limit;
846 PCIDevice *dev = host->bus->devices[devfn];
847
848 if (!dev) {
849 continue;
850 }
851
852 for (i = 0; i < PCI_NUM_REGIONS; i++) {
853 PCIIORegion *r = &dev->io_regions[i];
854
855 range_base = r->addr;
856 range_limit = r->addr + r->size - 1;
857
0f6dd8e1
MA		 858 /*
859 * Work-around for old bioses
860 * that do not support multiple root buses
861 */
862 if (!range_base || range_base > range_limit) {
863 continue;
864 }
865
a43c6e27 866 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
d7fd0e69 867 crs_range_insert(host_io_ranges, range_base, range_limit);
a43c6e27 868 } else { /* "memory" */
d7fd0e69 869 crs_range_insert(host_mem_ranges, range_base, range_limit);
a43c6e27
MA		 870 }
871 }
872
873 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
874 if (type == PCI_HEADER_TYPE_BRIDGE) {
875 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
876 if (subordinate > max_bus) {
877 max_bus = subordinate;
878 }
879
880 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
881 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
0f6dd8e1
MA		 882
883 /*
884 * Work-around for old bioses
885 * that do not support multiple root buses
886 */
4ebc736e 887 if (range_base && range_base <= range_limit) {
d7fd0e69 888 crs_range_insert(host_io_ranges, range_base, range_limit);
0f6dd8e1 889 }
a43c6e27
MA		 890
891 range_base =
892 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
893 range_limit =
894 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
0f6dd8e1
MA		 895
896 /*
897 * Work-around for old bioses
898 * that do not support multiple root buses
899 */
4ebc736e 900 if (range_base && range_base <= range_limit) {
d7fd0e69 901 crs_range_insert(host_mem_ranges, range_base, range_limit);
4ebc736e 902 }
a43c6e27
MA		 903
904 range_base =
905 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
906 range_limit =
907 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
0f6dd8e1
MA		 908
909 /*
910 * Work-around for old bioses
911 * that do not support multiple root buses
912 */
4ebc736e 913 if (range_base && range_base <= range_limit) {
d7fd0e69 914 crs_range_insert(host_mem_ranges, range_base, range_limit);
0f6dd8e1 915 }
a43c6e27
MA		 916 }
917 }
918
d7fd0e69
MA		 919 crs_range_merge(host_io_ranges);
920 for (i = 0; i < host_io_ranges->len; i++) {
921 entry = g_ptr_array_index(host_io_ranges, i);
922 aml_append(crs,
923 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
924 AML_POS_DECODE, AML_ENTIRE_RANGE,
925 0, entry->base, entry->limit, 0,
926 entry->limit - entry->base + 1));
927 crs_range_insert(io_ranges, entry->base, entry->limit);
928 }
929 g_ptr_array_free(host_io_ranges, true);
930
931 crs_range_merge(host_mem_ranges);
932 for (i = 0; i < host_mem_ranges->len; i++) {
933 entry = g_ptr_array_index(host_mem_ranges, i);
934 aml_append(crs,
935 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
936 AML_MAX_FIXED, AML_NON_CACHEABLE,
937 AML_READ_WRITE,
938 0, entry->base, entry->limit, 0,
939 entry->limit - entry->base + 1));
940 crs_range_insert(mem_ranges, entry->base, entry->limit);
941 }
942 g_ptr_array_free(host_mem_ranges, true);
943
a43c6e27 944 aml_append(crs,
dcdca296 945 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
a43c6e27
MA		 946 0,
947 pci_bus_num(host->bus),
948 max_bus,
949 0,
950 max_bus - pci_bus_num(host->bus) + 1));
951
952 return crs;
953}
954
f177d40a
IM		 955static void build_memory_devices(Aml *sb_scope, int nr_mem,
956 uint16_t io_base, uint16_t io_len)
957{
958 int i;
959 Aml *scope;
960 Aml *crs;
961 Aml *field;
962 Aml *dev;
963 Aml *method;
964 Aml *ifctx;
965
966 /* build memory devices */
967 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
f84548dd 968 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
f177d40a 969 aml_append(scope,
f84548dd 970 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
f177d40a
IM		 971 );
972
973 crs = aml_resource_template();
974 aml_append(crs,
975 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
976 );
977 aml_append(scope, aml_name_decl("_CRS", crs));
978
979 aml_append(scope, aml_operation_region(
f84548dd 980 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
3f3009c0 981 aml_int(io_base), io_len)
f177d40a
IM		 982 );
983
f84548dd 984 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
f177d40a
IM		 985 AML_NOLOCK, AML_PRESERVE);
986 aml_append(field, /* read only */
f84548dd 987 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
f177d40a 988 aml_append(field, /* read only */
f84548dd 989 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
f177d40a 990 aml_append(field, /* read only */
f84548dd 991 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
f177d40a 992 aml_append(field, /* read only */
f84548dd 993 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
f177d40a 994 aml_append(field, /* read only */
f84548dd 995 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
f177d40a
IM		 996 aml_append(scope, field);
997
f84548dd 998 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
f177d40a
IM		 999 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1000 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1001 aml_append(field, /* 1 if enabled, read only */
f84548dd 1002 aml_named_field(MEMORY_SLOT_ENABLED, 1));
f177d40a
IM		 1003 aml_append(field,
1004 /*(read) 1 if has a insert event. (write) 1 to clear event */
f84548dd 1005 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
f177d40a
IM		 1006 aml_append(field,
1007 /* (read) 1 if has a remove event. (write) 1 to clear event */
f84548dd 1008 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
f177d40a
IM		 1009 aml_append(field,
1010 /* initiates device eject, write only */
f84548dd 1011 aml_named_field(MEMORY_SLOT_EJECT, 1));
f177d40a
IM		 1012 aml_append(scope, field);
1013
f84548dd 1014 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
f177d40a
IM		 1015 AML_NOLOCK, AML_PRESERVE);
1016 aml_append(field, /* DIMM selector, write only */
f84548dd 1017 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
f177d40a 1018 aml_append(field, /* _OST event code, write only */
f84548dd 1019 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
f177d40a 1020 aml_append(field, /* _OST status code, write only */
f84548dd 1021 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
f177d40a
IM		 1022 aml_append(scope, field);
1023 aml_append(sb_scope, scope);
1024
1025 for (i = 0; i < nr_mem; i++) {
f84548dd 1026 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
f177d40a
IM		 1027 const char *s;
1028
1029 dev = aml_device("MP%02X", i);
1030 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1031 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1032
1033 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
f84548dd 1034 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
f177d40a
IM		 1035 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1036 aml_append(dev, method);
1037
1038 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
f84548dd 1039 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
f177d40a
IM		 1040 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1041 aml_append(dev, method);
1042
1043 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
f84548dd 1044 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
f177d40a
IM		 1045 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1046 aml_append(dev, method);
1047
1048 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
f84548dd
IM		 1049 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1050
f177d40a
IM		 1051 aml_append(method, aml_return(aml_call4(
1052 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1053 )));
1054 aml_append(dev, method);
1055
1056 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
f84548dd 1057 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
f177d40a
IM		 1058 aml_append(method, aml_return(aml_call2(
1059 s, aml_name("_UID"), aml_arg(0))));
1060 aml_append(dev, method);
1061
1062 aml_append(sb_scope, dev);
1063 }
1064
1065 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1066 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1067 */
f84548dd 1068 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
f177d40a
IM		 1069 for (i = 0; i < nr_mem; i++) {
1070 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1071 aml_append(ifctx,
1072 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1073 );
1074 aml_append(method, ifctx);
1075 }
1076 aml_append(sb_scope, method);
1077}
1078
a57d708d
IM		 1079static void build_hpet_aml(Aml *table)
1080{
1081 Aml *crs;
1082 Aml *field;
1083 Aml *method;
1084 Aml *if_ctx;
1085 Aml *scope = aml_scope("_SB");
1086 Aml *dev = aml_device("HPET");
1087 Aml *zero = aml_int(0);
1088 Aml *id = aml_local(0);
1089 Aml *period = aml_local(1);
1090
1091 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1092 aml_append(dev, aml_name_decl("_UID", zero));
1093
1094 aml_append(dev,
3f3009c0
XG		 1095 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1096 HPET_LEN));
a57d708d
IM		 1097 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1098 aml_append(field, aml_named_field("VEND", 32));
1099 aml_append(field, aml_named_field("PRD", 32));
1100 aml_append(dev, field);
1101
1102 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1103 aml_append(method, aml_store(aml_name("VEND"), id));
1104 aml_append(method, aml_store(aml_name("PRD"), period));
1105 aml_append(method, aml_shiftright(id, aml_int(16), id));
1106 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1107 aml_equal(id, aml_int(0xffff))));
1108 {
1109 aml_append(if_ctx, aml_return(zero));
1110 }
1111 aml_append(method, if_ctx);
1112
1113 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1114 aml_lgreater(period, aml_int(100000000))));
1115 {
1116 aml_append(if_ctx, aml_return(zero));
1117 }
1118 aml_append(method, if_ctx);
1119
1120 aml_append(method, aml_return(aml_int(0x0F)));
1121 aml_append(dev, method);
1122
1123 crs = aml_resource_template();
1124 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1125 aml_append(dev, aml_name_decl("_CRS", crs));
1126
1127 aml_append(scope, dev);
1128 aml_append(table, scope);
1129}
1130
27b9fc54 1131static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
95ed7e97 1132{
27b9fc54
RK		 1133 Aml *dev, *fdi;
1134 uint8_t maxc, maxh, maxs;
1135
1136 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1137
1138 dev = aml_device("FLP%c", 'A' + idx);
1139
1140 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1141
1142 fdi = aml_package(16);
1143 aml_append(fdi, aml_int(idx)); /* Drive Number */
1144 aml_append(fdi,
1145 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1146 /*
1147 * the values below are the limits of the drive, and are thus independent
1148 * of the inserted media
1149 */
1150 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1151 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1152 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1153 /*
1154 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1155 * the drive type, so shall we
1156 */
1157 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1158 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1159 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1160 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1161 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1162 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1163 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1164 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1165 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1166 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1167 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1168
1169 aml_append(dev, aml_name_decl("_FDI", fdi));
1170 return dev;
1171}
1172
1173static Aml *build_fdc_device_aml(ISADevice *fdc)
1174{
1175 int i;
95ed7e97
IM		 1176 Aml *dev;
1177 Aml *crs;
95ed7e97 1178
27b9fc54
RK		 1179#define ACPI_FDE_MAX_FD 4
1180 uint32_t fde_buf[5] = {
1181 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1182 cpu_to_le32(2) /* tape presence (2 == never present) */
1183 };
1184
95ed7e97
IM		 1185 dev = aml_device("FDC0");
1186 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1187
95ed7e97
IM		 1188 crs = aml_resource_template();
1189 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1190 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1191 aml_append(crs, aml_irq_no_flags(6));
1192 aml_append(crs,
1193 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1194 aml_append(dev, aml_name_decl("_CRS", crs));
1195
27b9fc54
RK		 1196 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1197 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1198
1199 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1200 fde_buf[i] = cpu_to_le32(1); /* drive present */
1201 aml_append(dev, build_fdinfo_aml(i, type));
1202 }
1203 }
1204 aml_append(dev, aml_name_decl("_FDE",
1205 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1206
95ed7e97
IM		 1207 return dev;
1208}
1209
ee135849
IM		 1210static Aml *build_rtc_device_aml(void)
1211{
1212 Aml *dev;
1213 Aml *crs;
1214
1215 dev = aml_device("RTC");
1216 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1217 crs = aml_resource_template();
1218 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1219 aml_append(crs, aml_irq_no_flags(8));
1220 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
95ed7e97 1221 aml_append(dev, aml_name_decl("_CRS", crs));
f58190e2
IM		 1222
1223 return dev;
1224}
1225
1226static Aml *build_kbd_device_aml(void)
1227{
1228 Aml *dev;
1229 Aml *crs;
1230 Aml *method;
1231
1232 dev = aml_device("KBD");
1233 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1234
1235 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1236 aml_append(method, aml_return(aml_int(0x0f)));
1237 aml_append(dev, method);
1238
1239 crs = aml_resource_template();
1240 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1241 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1242 aml_append(crs, aml_irq_no_flags(1));
ee135849
IM		 1243 aml_append(dev, aml_name_decl("_CRS", crs));
1244
1245 return dev;
1246}
1247
c355cb2c
IM		 1248static Aml *build_mouse_device_aml(void)
1249{
1250 Aml *dev;
1251 Aml *crs;
1252 Aml *method;
1253
1254 dev = aml_device("MOU");
1255 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1256
1257 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1258 aml_append(method, aml_return(aml_int(0x0f)));
1259 aml_append(dev, method);
1260
1261 crs = aml_resource_template();
1262 aml_append(crs, aml_irq_no_flags(12));
1263 aml_append(dev, aml_name_decl("_CRS", crs));
1264
1265 return dev;
1266}
1267
8b1da5f8
IM		 1268static Aml *build_lpt_device_aml(void)
1269{
1270 Aml *dev;
1271 Aml *crs;
1272 Aml *method;
1273 Aml *if_ctx;
1274 Aml *else_ctx;
1275 Aml *zero = aml_int(0);
1276 Aml *is_present = aml_local(0);
1277
1278 dev = aml_device("LPT");
1279 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1280
1281 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1282 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1283 if_ctx = aml_if(aml_equal(is_present, zero));
1284 {
1285 aml_append(if_ctx, aml_return(aml_int(0x00)));
1286 }
1287 aml_append(method, if_ctx);
1288 else_ctx = aml_else();
1289 {
1290 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1291 }
1292 aml_append(method, else_ctx);
1293 aml_append(dev, method);
1294
1295 crs = aml_resource_template();
1296 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1297 aml_append(crs, aml_irq_no_flags(7));
1298 aml_append(dev, aml_name_decl("_CRS", crs));
1299
1300 return dev;
1301}
1302
28f1f0e9
IM		 1303static Aml *build_com_device_aml(uint8_t uid)
1304{
1305 Aml *dev;
1306 Aml *crs;
1307 Aml *method;
1308 Aml *if_ctx;
1309 Aml *else_ctx;
1310 Aml *zero = aml_int(0);
1311 Aml *is_present = aml_local(0);
1312 const char *enabled_field = "CAEN";
1313 uint8_t irq = 4;
1314 uint16_t io_port = 0x03F8;
1315
1316 assert(uid == 1 || uid == 2);
1317 if (uid == 2) {
1318 enabled_field = "CBEN";
1319 irq = 3;
1320 io_port = 0x02F8;
1321 }
1322
1323 dev = aml_device("COM%d", uid);
1324 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1325 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1326
1327 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1328 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1329 if_ctx = aml_if(aml_equal(is_present, zero));
1330 {
1331 aml_append(if_ctx, aml_return(aml_int(0x00)));
1332 }
1333 aml_append(method, if_ctx);
1334 else_ctx = aml_else();
1335 {
1336 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1337 }
1338 aml_append(method, else_ctx);
1339 aml_append(dev, method);
1340
1341 crs = aml_resource_template();
1342 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1343 aml_append(crs, aml_irq_no_flags(irq));
1344 aml_append(dev, aml_name_decl("_CRS", crs));
1345
1346 return dev;
1347}
1348
ee135849
IM		 1349static void build_isa_devices_aml(Aml *table)
1350{
27b9fc54 1351 ISADevice *fdc = pc_find_fdc0();
86e91dd7 1352 bool ambiguous;
27b9fc54 1353
ee135849 1354 Aml *scope = aml_scope("_SB.PCI0.ISA");
86e91dd7 1355 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
ee135849
IM		 1356
1357 aml_append(scope, build_rtc_device_aml());
f58190e2 1358 aml_append(scope, build_kbd_device_aml());
c355cb2c 1359 aml_append(scope, build_mouse_device_aml());
27b9fc54
RK		 1360 if (fdc) {
1361 aml_append(scope, build_fdc_device_aml(fdc));
9b613f4e 1362 }
8b1da5f8 1363 aml_append(scope, build_lpt_device_aml());
28f1f0e9
IM		 1364 aml_append(scope, build_com_device_aml(1));
1365 aml_append(scope, build_com_device_aml(2));
ee135849 1366
86e91dd7
CM		 1367 if (ambiguous) {
1368 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1369 } else if (!obj) {
1370 error_report("No ISA bus, unable to define IPMI ACPI data");
1371 } else {
1372 build_acpi_ipmi_devices(scope, BUS(obj));
1373 }
1374
ee135849
IM		 1375 aml_append(table, scope);
1376}
1377
3892a2b7
IM		 1378static void build_dbg_aml(Aml *table)
1379{
1380 Aml *field;
1381 Aml *method;
1382 Aml *while_ctx;
1383 Aml *scope = aml_scope("\\");
1384 Aml *buf = aml_local(0);
1385 Aml *len = aml_local(1);
1386 Aml *idx = aml_local(2);
1387
1388 aml_append(scope,
3f3009c0 1389 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
3892a2b7
IM		 1390 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1391 aml_append(field, aml_named_field("DBGB", 8));
1392 aml_append(scope, field);
1393
1394 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1395
1396 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1397 aml_append(method, aml_to_buffer(buf, buf));
1398 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1399 aml_append(method, aml_store(aml_int(0), idx));
1400
1401 while_ctx = aml_while(aml_lless(idx, len));
1402 aml_append(while_ctx,
1403 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1404 aml_append(while_ctx, aml_increment(idx));
1405 aml_append(method, while_ctx);
1406
1407 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1408 aml_append(scope, method);
1409
1410 aml_append(table, scope);
1411}
1412
c35b6e80
IM		 1413static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1414{
1415 Aml *dev;
1416 Aml *crs;
1417 Aml *method;
1418 uint32_t irqs[] = {5, 10, 11};
1419
1420 dev = aml_device("%s", name);
1421 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1422 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1423
1424 crs = aml_resource_template();
1425 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1426 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1427 aml_append(dev, aml_name_decl("_PRS", crs));
1428
1429 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1430 aml_append(method, aml_return(aml_call1("IQST", reg)));
1431 aml_append(dev, method);
1432
1433 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1434 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1435 aml_append(dev, method);
1436
1437 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1438 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1439 aml_append(dev, method);
1440
1441 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1442 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1443 aml_append(method, aml_store(aml_name("PRRI"), reg));
1444 aml_append(dev, method);
1445
1446 return dev;
1447 }
1448
80b32df5
IM		 1449static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1450{
1451 Aml *dev;
1452 Aml *crs;
1453 Aml *method;
1454 uint32_t irqs;
1455
1456 dev = aml_device("%s", name);
1457 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1458 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1459
1460 crs = aml_resource_template();
1461 irqs = gsi;
1462 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1463 AML_SHARED, &irqs, 1));
1464 aml_append(dev, aml_name_decl("_PRS", crs));
1465
1466 aml_append(dev, aml_name_decl("_CRS", crs));
1467
c82f503d
MA		 1468 /*
1469 * _DIS can be no-op because the interrupt cannot be disabled.
1470 */
1471 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1472 aml_append(dev, method);
1473
80b32df5
IM		 1474 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1475 aml_append(dev, method);
1476
1477 return dev;
1478}
1479
16682a9d
IM		 1480/* _CRS method - get current settings */
1481static Aml *build_iqcr_method(bool is_piix4)
1482{
1483 Aml *if_ctx;
1484 uint32_t irqs;
1485 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1486 Aml *crs = aml_resource_template();
1487
1488 irqs = 0;
1489 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1490 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1491 aml_append(method, aml_name_decl("PRR0", crs));
1492
1493 aml_append(method,
1494 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1495
1496 if (is_piix4) {
1497 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1498 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1499 aml_append(method, if_ctx);
1500 } else {
1501 aml_append(method,
1502 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1503 aml_name("PRRI")));
1504 }
1505
1506 aml_append(method, aml_return(aml_name("PRR0")));
1507 return method;
1508}
1509
78e1ad05
IM		 1510/* _STA method - get status */
1511static Aml *build_irq_status_method(void)
1512{
1513 Aml *if_ctx;
1514 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1515
1516 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1517 aml_append(if_ctx, aml_return(aml_int(0x09)));
1518 aml_append(method, if_ctx);
1519 aml_append(method, aml_return(aml_int(0x0B)));
1520 return method;
1521}
1522
e4db2798
IM		 1523static void build_piix4_pci0_int(Aml *table)
1524{
c35b6e80
IM		 1525 Aml *dev;
1526 Aml *crs;
e4db2798 1527 Aml *field;
c35b6e80
IM		 1528 Aml *method;
1529 uint32_t irqs;
e4db2798 1530 Aml *sb_scope = aml_scope("_SB");
196e2137
IM		 1531 Aml *pci0_scope = aml_scope("PCI0");
1532
1533 aml_append(pci0_scope, build_prt(true));
1534 aml_append(sb_scope, pci0_scope);
e4db2798
IM		 1535
1536 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1537 aml_append(field, aml_named_field("PRQ0", 8));
1538 aml_append(field, aml_named_field("PRQ1", 8));
1539 aml_append(field, aml_named_field("PRQ2", 8));
1540 aml_append(field, aml_named_field("PRQ3", 8));
1541 aml_append(sb_scope, field);
1542
78e1ad05 1543 aml_append(sb_scope, build_irq_status_method());
16682a9d 1544 aml_append(sb_scope, build_iqcr_method(true));
100681cc 1545
c35b6e80
IM		 1546 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1547 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1548 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1549 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1550
1551 dev = aml_device("LNKS");
1552 {
1553 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1554 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1555
1556 crs = aml_resource_template();
1557 irqs = 9;
1558 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1559 AML_ACTIVE_HIGH, AML_SHARED,
1560 &irqs, 1));
1561 aml_append(dev, aml_name_decl("_PRS", crs));
1562
1563 /* The SCI cannot be disabled and is always attached to GSI 9,
1564 * so these are no-ops. We only need this link to override the
1565 * polarity to active high and match the content of the MADT.
1566 */
1567 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1568 aml_append(method, aml_return(aml_int(0x0b)));
1569 aml_append(dev, method);
1570
1571 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1572 aml_append(dev, method);
1573
1574 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1575 aml_append(method, aml_return(aml_name("_PRS")));
1576 aml_append(dev, method);
1577
1578 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1579 aml_append(dev, method);
1580 }
1581 aml_append(sb_scope, dev);
1582
e4db2798
IM		 1583 aml_append(table, sb_scope);
1584}
1585
22b5b8bf
IM		 1586static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1587{
1588 int i;
1589 int head;
1590 Aml *pkg;
1591 char base = name[3] < 'E' ? 'A' : 'E';
1592 char *s = g_strdup(name);
1593 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1594
1595 assert(strlen(s) == 4);
1596
1597 head = name[3] - base;
1598 for (i = 0; i < 4; i++) {
1599 if (head + i > 3) {
1600 head = i * -1;
1601 }
1602 s[3] = base + head + i;
1603 pkg = aml_package(4);
1604 aml_append(pkg, a_nr);
1605 aml_append(pkg, aml_int(i));
1606 aml_append(pkg, aml_name("%s", s));
1607 aml_append(pkg, aml_int(0));
1608 aml_append(ctx, pkg);
1609 }
1610 g_free(s);
1611}
1612
1613static Aml *build_q35_routing_table(const char *str)
1614{
1615 int i;
1616 Aml *pkg;
1617 char *name = g_strdup_printf("%s ", str);
1618
1619 pkg = aml_package(128);
1620 for (i = 0; i < 0x18; i++) {
1621 name[3] = 'E' + (i & 0x3);
1622 append_q35_prt_entry(pkg, i, name);
1623 }
1624
1625 name[3] = 'E';
1626 append_q35_prt_entry(pkg, 0x18, name);
1627
1628 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1629 for (i = 0x0019; i < 0x1e; i++) {
1630 name[3] = 'A';
1631 append_q35_prt_entry(pkg, i, name);
1632 }
1633
1634 /* PCIe->PCI bridge. use PIRQ[E-H] */
1635 name[3] = 'E';
1636 append_q35_prt_entry(pkg, 0x1e, name);
1637 name[3] = 'A';
1638 append_q35_prt_entry(pkg, 0x1f, name);
1639
1640 g_free(name);
1641 return pkg;
1642}
1643
80b32df5
IM		 1644static void build_q35_pci0_int(Aml *table)
1645{
41f95a52 1646 Aml *field;
0dafe3b3 1647 Aml *method;
80b32df5 1648 Aml *sb_scope = aml_scope("_SB");
0dafe3b3
IM		 1649 Aml *pci0_scope = aml_scope("PCI0");
1650
e9fce798
IM		 1651 /* Zero => PIC mode, One => APIC Mode */
1652 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1653 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1654 {
1655 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1656 }
1657 aml_append(table, method);
1658
65aef4de
IM		 1659 aml_append(pci0_scope,
1660 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
22b5b8bf
IM		 1661 aml_append(pci0_scope,
1662 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1663
0dafe3b3
IM		 1664 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1665 {
1666 Aml *if_ctx;
1667 Aml *else_ctx;
1668
1669 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1670 section 6.2.8.1 */
1671 /* Note: we provide the same info as the PCI routing
1672 table of the Bochs BIOS */
1673 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1674 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1675 aml_append(method, if_ctx);
1676 else_ctx = aml_else();
1677 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1678 aml_append(method, else_ctx);
1679 }
1680 aml_append(pci0_scope, method);
1681 aml_append(sb_scope, pci0_scope);
80b32df5 1682
41f95a52
IM		 1683 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1684 aml_append(field, aml_named_field("PRQA", 8));
1685 aml_append(field, aml_named_field("PRQB", 8));
1686 aml_append(field, aml_named_field("PRQC", 8));
1687 aml_append(field, aml_named_field("PRQD", 8));
1688 aml_append(field, aml_reserved_field(0x20));
1689 aml_append(field, aml_named_field("PRQE", 8));
1690 aml_append(field, aml_named_field("PRQF", 8));
1691 aml_append(field, aml_named_field("PRQG", 8));
1692 aml_append(field, aml_named_field("PRQH", 8));
1693 aml_append(sb_scope, field);
1694
78e1ad05 1695 aml_append(sb_scope, build_irq_status_method());
16682a9d
IM		 1696 aml_append(sb_scope, build_iqcr_method(false));
1697
12e3b1f7
IM		 1698 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1699 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1700 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1701 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1702 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1703 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1704 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1705 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1706
6a991e07
MA		 1707 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1708 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1709 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1710 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1711 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1712 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1713 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1714 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
80b32df5
IM		 1715
1716 aml_append(table, sb_scope);
1717}
1718
41f95a52
IM		 1719static void build_q35_isa_bridge(Aml *table)
1720{
1721 Aml *dev;
1722 Aml *scope;
1723 Aml *field;
1724
1725 scope = aml_scope("_SB.PCI0");
1726 dev = aml_device("ISA");
1727 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1728
1729 /* ICH9 PCI to ISA irq remapping */
1730 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
3f3009c0 1731 aml_int(0x60), 0x0C));
41f95a52
IM		 1732
1733 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
3f3009c0 1734 aml_int(0x80), 0x02));
41f95a52
IM		 1735 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1736 aml_append(field, aml_named_field("COMA", 3));
1737 aml_append(field, aml_reserved_field(1));
1738 aml_append(field, aml_named_field("COMB", 3));
1739 aml_append(field, aml_reserved_field(1));
1740 aml_append(field, aml_named_field("LPTD", 2));
41f95a52
IM		 1741 aml_append(dev, field);
1742
1743 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
3f3009c0 1744 aml_int(0x82), 0x02));
41f95a52
IM		 1745 /* enable bits */
1746 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1747 aml_append(field, aml_named_field("CAEN", 1));
1748 aml_append(field, aml_named_field("CBEN", 1));
1749 aml_append(field, aml_named_field("LPEN", 1));
41f95a52
IM		 1750 aml_append(dev, field);
1751
1752 aml_append(scope, dev);
1753 aml_append(table, scope);
1754}
1755
e4db2798
IM		 1756static void build_piix4_pm(Aml *table)
1757{
1758 Aml *dev;
1759 Aml *scope;
1760
1761 scope = aml_scope("_SB.PCI0");
1762 dev = aml_device("PX13");
1763 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1764
1765 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
3f3009c0 1766 aml_int(0x00), 0xff));
e4db2798
IM		 1767 aml_append(scope, dev);
1768 aml_append(table, scope);
1769}
1770
1771static void build_piix4_isa_bridge(Aml *table)
1772{
1773 Aml *dev;
1774 Aml *scope;
1775 Aml *field;
1776
1777 scope = aml_scope("_SB.PCI0");
1778 dev = aml_device("ISA");
1779 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1780
1781 /* PIIX PCI to ISA irq remapping */
1782 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
3f3009c0 1783 aml_int(0x60), 0x04));
e4db2798
IM		 1784 /* enable bits */
1785 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1786 /* Offset(0x5f),, 7, */
1787 aml_append(field, aml_reserved_field(0x2f8));
1788 aml_append(field, aml_reserved_field(7));
1789 aml_append(field, aml_named_field("LPEN", 1));
1790 /* Offset(0x67),, 3, */
1791 aml_append(field, aml_reserved_field(0x38));
1792 aml_append(field, aml_reserved_field(3));
1793 aml_append(field, aml_named_field("CAEN", 1));
1794 aml_append(field, aml_reserved_field(3));
1795 aml_append(field, aml_named_field("CBEN", 1));
1796 aml_append(dev, field);
e4db2798
IM		 1797
1798 aml_append(scope, dev);
1799 aml_append(table, scope);
1800}
1801
b616ec4d
IM		 1802static void build_piix4_pci_hotplug(Aml *table)
1803{
1804 Aml *scope;
1805 Aml *field;
1806 Aml *method;
1807
1808 scope = aml_scope("_SB.PCI0");
1809
1810 aml_append(scope,
3f3009c0 1811 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
b616ec4d
IM		 1812 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1813 aml_append(field, aml_named_field("PCIU", 32));
1814 aml_append(field, aml_named_field("PCID", 32));
1815 aml_append(scope, field);
1816
1817 aml_append(scope,
3f3009c0 1818 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
b616ec4d
IM		 1819 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1820 aml_append(field, aml_named_field("B0EJ", 32));
1821 aml_append(scope, field);
1822
1823 aml_append(scope,
3f3009c0 1824 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
b616ec4d
IM		 1825 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1826 aml_append(field, aml_named_field("BNUM", 32));
1827 aml_append(scope, field);
1828
1829 aml_append(scope, aml_mutex("BLCK", 0));
1830
1831 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1832 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1833 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1834 aml_append(method,
1835 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1836 aml_append(method, aml_release(aml_name("BLCK")));
1837 aml_append(method, aml_return(aml_int(0)));
1838 aml_append(scope, method);
1839
1840 aml_append(table, scope);
1841}
1842
f97a88a8
IM		 1843static Aml *build_q35_osc_method(void)
1844{
1845 Aml *if_ctx;
1846 Aml *if_ctx2;
1847 Aml *else_ctx;
1848 Aml *method;
1849 Aml *a_cwd1 = aml_name("CDW1");
1850 Aml *a_ctrl = aml_name("CTRL");
1851
1852 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1853 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1854
1855 if_ctx = aml_if(aml_equal(
1856 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1857 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1858 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1859
1860 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1861 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1862
1863 /*
1864 * Always allow native PME, AER (no dependencies)
1865 * Never allow SHPC (no SHPC controller in this system)
1866 */
1867 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1868
1869 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1870 /* Unknown revision */
1871 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1872 aml_append(if_ctx, if_ctx2);
1873
1874 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1875 /* Capabilities bits were masked */
1876 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1877 aml_append(if_ctx, if_ctx2);
1878
1879 /* Update DWORD3 in the buffer */
1880 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1881 aml_append(method, if_ctx);
1882
1883 else_ctx = aml_else();
1884 /* Unrecognized UUID */
1885 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1886 aml_append(method, else_ctx);
1887
1888 aml_append(method, aml_return(aml_arg(3)));
1889 return method;
1890}
b616ec4d 1891
72c194f7 1892static void
0e9b9eda 1893build_dsdt(GArray *table_data, BIOSLinker *linker,
adcb89d5 1894 AcpiPmInfo *pm, AcpiMiscInfo *misc,
01c9742d 1895 Range *pci_hole, Range *pci_hole64, MachineState *machine)
72c194f7 1896{
41fa5c04
IM		 1897 CrsRangeEntry *entry;
1898 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1899 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1900 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
fb306ffe 1901 PCMachineState *pcms = PC_MACHINE(machine);
679dd1a9 1902 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
bef3492d 1903 uint32_t nr_mem = machine->ram_slots;
dcdca296 1904 int root_bus_limit = 0xFF;
41fa5c04 1905 PCIBus *bus = NULL;
72c194f7
MT		 1906 int i;
1907
41fa5c04 1908 dsdt = init_aml_allocator();
2fd71f1b 1909
4ec8d2b3 1910 /* Reserve space for header */
41fa5c04
IM		 1911 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1912
1913 build_dbg_aml(dsdt);
1914 if (misc->is_piix4) {
1915 sb_scope = aml_scope("_SB");
1916 dev = aml_device("PCI0");
1917 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1918 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1919 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1920 aml_append(sb_scope, dev);
1921 aml_append(dsdt, sb_scope);
1922
1923 build_hpet_aml(dsdt);
1924 build_piix4_pm(dsdt);
1925 build_piix4_isa_bridge(dsdt);
1926 build_isa_devices_aml(dsdt);
1927 build_piix4_pci_hotplug(dsdt);
1928 build_piix4_pci0_int(dsdt);
1929 } else {
1930 sb_scope = aml_scope("_SB");
1931 aml_append(sb_scope,
3f3009c0 1932 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
41fa5c04 1933 aml_append(sb_scope,
3f3009c0 1934 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
41fa5c04
IM		 1935 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1936 aml_append(field, aml_named_field("PCIB", 8));
1937 aml_append(sb_scope, field);
1938 aml_append(dsdt, sb_scope);
1939
1940 sb_scope = aml_scope("_SB");
1941 dev = aml_device("PCI0");
1942 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1943 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1944 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1945 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1946 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
1947 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
1948 aml_append(dev, build_q35_osc_method());
1949 aml_append(sb_scope, dev);
1950 aml_append(dsdt, sb_scope);
1951
1952 build_hpet_aml(dsdt);
1953 build_q35_isa_bridge(dsdt);
1954 build_isa_devices_aml(dsdt);
1955 build_q35_pci0_int(dsdt);
1956 }
1957
679dd1a9
IM		 1958 if (pcmc->legacy_cpu_hotplug) {
1959 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1960 } else {
1961 CPUHotplugFeatures opts = {
1962 .apci_1_compatible = true, .has_legacy_cphp = true
1963 };
1964 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1965 "\\_SB.PCI0", "\\_GPE._E02");
1966 }
41fa5c04
IM		 1967 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
1968 pm->mem_hp_io_len);
1969
1970 scope = aml_scope("_GPE");
1971 {
1972 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1973
41fa5c04
IM		 1974 if (misc->is_piix4) {
1975 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1976 aml_append(method,
1977 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1978 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1979 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1980 aml_append(scope, method);
41fa5c04
IM		 1981 }
1982
41fa5c04
IM		 1983 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
1984 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
1985 aml_append(scope, method);
41fa5c04
IM		 1986 }
1987 aml_append(dsdt, scope);
72c194f7 1988
81ed6482 1989 bus = PC_MACHINE(machine)->bus;
a4894206
MA		 1990 if (bus) {
1991 QLIST_FOREACH(bus, &bus->child, sibling) {
1992 uint8_t bus_num = pci_bus_num(bus);
0e79e51a 1993 uint8_t numa_node = pci_bus_numa_node(bus);
a4894206
MA		 1994
1995 /* look only for expander root buses */
1996 if (!pci_bus_is_root(bus)) {
1997 continue;
1998 }
1999
dcdca296
MA		 2000 if (bus_num < root_bus_limit) {
2001 root_bus_limit = bus_num - 1;
2002 }
2003
a4894206
MA		 2004 scope = aml_scope("\\_SB");
2005 dev = aml_device("PC%.02X", bus_num);
c96d9286
LE		 2006 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
2007 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
a4894206 2008 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
0e79e51a
MA		 2009
2010 if (numa_node != NUMA_NODE_UNASSIGNED) {
2011 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2012 }
2013
196e2137 2014 aml_append(dev, build_prt(false));
a43c6e27
MA		 2015 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
2016 io_ranges, mem_ranges);
2017 aml_append(dev, aml_name_decl("_CRS", crs));
a4894206 2018 aml_append(scope, dev);
41fa5c04 2019 aml_append(dsdt, scope);
a4894206
MA		 2020 }
2021 }
2022
500b11ea 2023 scope = aml_scope("\\_SB.PCI0");
60efd429
IM		 2024 /* build PCI0._CRS */
2025 crs = aml_resource_template();
2026 aml_append(crs,
ff80dc7f 2027 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
dcdca296
MA		 2028 0x0000, 0x0, root_bus_limit,
2029 0x0000, root_bus_limit + 1));
ff80dc7f 2030 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
60efd429
IM		 2031
2032 aml_append(crs,
ff80dc7f
SZ		 2033 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2034 AML_POS_DECODE, AML_ENTIRE_RANGE,
60efd429 2035 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
dcdca296
MA		 2036
2037 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
2038 for (i = 0; i < io_ranges->len; i++) {
2039 entry = g_ptr_array_index(io_ranges, i);
2040 aml_append(crs,
2041 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2042 AML_POS_DECODE, AML_ENTIRE_RANGE,
2043 0x0000, entry->base, entry->limit,
2044 0x0000, entry->limit - entry->base + 1));
2045 }
2046
60efd429 2047 aml_append(crs,
ff80dc7f
SZ		 2048 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2049 AML_CACHEABLE, AML_READ_WRITE,
60efd429 2050 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
dcdca296 2051
01c9742d 2052 crs_replace_with_free_ranges(mem_ranges,
a0efbf16
MA		 2053 range_lob(pci_hole),
2054 range_upb(pci_hole));
dcdca296
MA		 2055 for (i = 0; i < mem_ranges->len; i++) {
2056 entry = g_ptr_array_index(mem_ranges, i);
2057 aml_append(crs,
2058 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2059 AML_NON_CACHEABLE, AML_READ_WRITE,
2060 0, entry->base, entry->limit,
2061 0, entry->limit - entry->base + 1));
2062 }
2063
a0efbf16 2064 if (!range_is_empty(pci_hole64)) {
60efd429 2065 aml_append(crs,
ff80dc7f
SZ		 2066 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2067 AML_CACHEABLE, AML_READ_WRITE,
a0efbf16
MA		 2068 0, range_lob(pci_hole64), range_upb(pci_hole64), 0,
2069 range_upb(pci_hole64) + 1 - range_lob(pci_hole64)));
60efd429 2070 }
2b1c2e8e
IM		 2071
2072 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2073 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2074 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2075 }
60efd429
IM		 2076 aml_append(scope, aml_name_decl("_CRS", crs));
2077
d31c909e
IM		 2078 /* reserve GPE0 block resources */
2079 dev = aml_device("GPE0");
2080 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2081 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2082 /* device present, functioning, decoding, not shown in UI */
2083 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2084 crs = aml_resource_template();
2085 aml_append(crs,
ff80dc7f 2086 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
d31c909e
IM		 2087 );
2088 aml_append(dev, aml_name_decl("_CRS", crs));
2089 aml_append(scope, dev);
2090
dcdca296
MA		 2091 g_ptr_array_free(io_ranges, true);
2092 g_ptr_array_free(mem_ranges, true);
2093
500b11ea
IM		 2094 /* reserve PCIHP resources */
2095 if (pm->pcihp_io_len) {
2096 dev = aml_device("PHPR");
2097 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2098 aml_append(dev,
2099 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2100 /* device present, functioning, decoding, not shown in UI */
2101 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2102 crs = aml_resource_template();
2103 aml_append(crs,
ff80dc7f 2104 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
500b11ea
IM		 2105 pm->pcihp_io_len)
2106 );
2107 aml_append(dev, aml_name_decl("_CRS", crs));
2108 aml_append(scope, dev);
2109 }
41fa5c04 2110 aml_append(dsdt, scope);
500b11ea 2111
ebc3028f
IM		 2112 /* create S3_ / S4_ / S5_ packages if necessary */
2113 scope = aml_scope("\\");
2114 if (!pm->s3_disabled) {
2115 pkg = aml_package(4);
2116 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2117 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2118 aml_append(pkg, aml_int(0)); /* reserved */
2119 aml_append(pkg, aml_int(0)); /* reserved */
2120 aml_append(scope, aml_name_decl("_S3", pkg));
2121 }
2122
2123 if (!pm->s4_disabled) {
2124 pkg = aml_package(4);
2125 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2126 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2127 aml_append(pkg, aml_int(pm->s4_val));
2128 aml_append(pkg, aml_int(0)); /* reserved */
2129 aml_append(pkg, aml_int(0)); /* reserved */
2130 aml_append(scope, aml_name_decl("_S4", pkg));
2131 }
2132
2133 pkg = aml_package(4);
2134 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2135 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2136 aml_append(pkg, aml_int(0)); /* reserved */
2137 aml_append(pkg, aml_int(0)); /* reserved */
2138 aml_append(scope, aml_name_decl("_S5", pkg));
41fa5c04 2139 aml_append(dsdt, scope);
ebc3028f 2140
e2ec7568
GS		 2141 /* create fw_cfg node, unconditionally */
2142 {
2143 /* when using port i/o, the 8-bit data register *always* overlaps
2144 * with half of the 16-bit control register. Hence, the total size
2145 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2146 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2147 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2148 "dma_enabled", NULL) ?
2149 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2150 FW_CFG_CTL_SIZE;
2151
2152 scope = aml_scope("\\_SB.PCI0");
2153 dev = aml_device("FWCF");
2154
2155 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2156
2157 /* device present, functioning, decoding, not shown in UI */
2158 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2159
2160 crs = aml_resource_template();
2161 aml_append(crs,
2162 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2163 );
2164 aml_append(dev, aml_name_decl("_CRS", crs));
2165
2166 aml_append(scope, dev);
2167 aml_append(dsdt, scope);
2168 }
2169
8ac6f7a6
IM		 2170 if (misc->applesmc_io_base) {
2171 scope = aml_scope("\\_SB.PCI0.ISA");
2172 dev = aml_device("SMC");
2173
2174 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2175 /* device present, functioning, decoding, not shown in UI */
2176 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2177
2178 crs = aml_resource_template();
2179 aml_append(crs,
ff80dc7f 2180 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
8ac6f7a6
IM		 2181 0x01, APPLESMC_MAX_DATA_LENGTH)
2182 );
2183 aml_append(crs, aml_irq_no_flags(6));
2184 aml_append(dev, aml_name_decl("_CRS", crs));
2185
2186 aml_append(scope, dev);
41fa5c04 2187 aml_append(dsdt, scope);
8ac6f7a6
IM		 2188 }
2189
cd61cb2e
IM		 2190 if (misc->pvpanic_port) {
2191 scope = aml_scope("\\_SB.PCI0.ISA");
2192
2332333c 2193 dev = aml_device("PEVT");
e65bef69 2194 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
cd61cb2e
IM		 2195
2196 crs = aml_resource_template();
2197 aml_append(crs,
ff80dc7f 2198 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
cd61cb2e
IM		 2199 );
2200 aml_append(dev, aml_name_decl("_CRS", crs));
2201
ff80dc7f 2202 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
3f3009c0 2203 aml_int(misc->pvpanic_port), 1));
36de884a 2204 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
cd61cb2e
IM		 2205 aml_append(field, aml_named_field("PEPT", 8));
2206 aml_append(dev, field);
2207
8ef3ea25
GH		 2208 /* device present, functioning, decoding, shown in UI */
2209 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2332333c 2210
4dbfc881 2211 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
cd61cb2e
IM		 2212 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2213 aml_append(method, aml_return(aml_local(0)));
2214 aml_append(dev, method);
2215
4dbfc881 2216 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
cd61cb2e
IM		 2217 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2218 aml_append(dev, method);
2219
2220 aml_append(scope, dev);
41fa5c04 2221 aml_append(dsdt, scope);
cd61cb2e
IM		 2222 }
2223
7824df38 2224 sb_scope = aml_scope("\\_SB");
72c194f7 2225 {
f177d40a
IM		 2226 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2227 pm->mem_hp_io_len);
8698c0c0 2228
72c194f7 2229 {
8dcf525a
MT		 2230 Object *pci_host;
2231 PCIBus *bus = NULL;
8dcf525a 2232
ca6c1855
MA		 2233 pci_host = acpi_get_i386_pci_host();
2234 if (pci_host) {
8dcf525a
MT		 2235 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2236 }
72c194f7 2237
99fd437d 2238 if (bus) {
62b52c26 2239 Aml *scope = aml_scope("PCI0");
99fd437d 2240 /* Scan all PCI buses. Generate tables to support hotplug. */
62b52c26 2241 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
72d97b3a
IM		 2242
2243 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2244 dev = aml_device("ISA.TPM");
2245 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2246 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2247 crs = aml_resource_template();
2248 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2249 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
52e38eb0
IM		 2250 /*
2251 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2252 Rewrite to take IRQ from TPM device model and
2253 fix default IRQ value there to use some unused IRQ
2254 */
2255 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
72d97b3a
IM		 2256 aml_append(dev, aml_name_decl("_CRS", crs));
2257 aml_append(scope, dev);
2258 }
2259
62b52c26 2260 aml_append(sb_scope, scope);
72c194f7 2261 }
72c194f7 2262 }
41fa5c04 2263 aml_append(dsdt, sb_scope);
72c194f7
MT		 2264 }
2265
011bb749 2266 /* copy AML table into ACPI tables blob and patch header there */
41fa5c04 2267 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
72c194f7 2268 build_header(linker, table_data,
41fa5c04 2269 (void *)(table_data->data + table_data->len - dsdt->buf->len),
37ad223c 2270 "DSDT", dsdt->buf->len, 1, NULL, NULL);
011bb749 2271 free_aml_allocator();
72c194f7
MT		 2272}
2273
2274static void
0e9b9eda 2275build_hpet(GArray *table_data, BIOSLinker *linker)
72c194f7
MT		 2276{
2277 Acpi20Hpet *hpet;
2278
2279 hpet = acpi_data_push(table_data, sizeof(*hpet));
2280 /* Note timer_block_id value must be kept in sync with value advertised by
2281 * emulated hpet
2282 */
2283 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2284 hpet->addr.address = cpu_to_le64(HPET_BASE);
2285 build_header(linker, table_data,
37ad223c 2286 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
72c194f7
MT		 2287}
2288
711b20b4 2289static void
0e9b9eda 2290build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
711b20b4
SB		 2291{
2292 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
4678124b
IM		 2293 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2294 unsigned log_addr_offset =
2295 (char *)&tcpa->log_area_start_address - table_data->data;
711b20b4
SB		 2296
2297 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2298 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
9774ccf7 2299 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
711b20b4 2300
ad9671b8 2301 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
42a5b308
SB		 2302 false /* high memory */);
2303
711b20b4 2304 /* log area start address to be filled by Guest linker */
4678124b
IM		 2305 bios_linker_loader_add_pointer(linker,
2306 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2307 ACPI_BUILD_TPMLOG_FILE, 0);
711b20b4
SB		 2308
2309 build_header(linker, table_data,
37ad223c 2310 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
711b20b4
SB		 2311}
2312
5cb18b3d 2313static void
0e9b9eda 2314build_tpm2(GArray *table_data, BIOSLinker *linker)
5cb18b3d
SB		 2315{
2316 Acpi20TPM2 *tpm2_ptr;
5cb18b3d
SB		 2317
2318 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2319
2320 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2321 tpm2_ptr->control_area_address = cpu_to_le64(0);
2322 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2323
2324 build_header(linker, table_data,
37ad223c 2325 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
5cb18b3d
SB		 2326}
2327
72c194f7 2328static void
0e9b9eda 2329build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
72c194f7
MT		 2330{
2331 AcpiSystemResourceAffinityTable *srat;
2332 AcpiSratProcessorAffinity *core;
2333 AcpiSratMemoryAffinity *numamem;
2334
2335 int i;
72c194f7
MT		 2336 int srat_start, numa_start, slots;
2337 uint64_t mem_len, mem_base, next_base;
5803fce3
IM		 2338 MachineClass *mc = MACHINE_GET_CLASS(machine);
2339 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
3d3ebcad 2340 PCMachineState *pcms = PC_MACHINE(machine);
cec65193
IM		 2341 ram_addr_t hotplugabble_address_space_size =
2342 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2343 NULL);
72c194f7
MT		 2344
2345 srat_start = table_data->len;
2346
2347 srat = acpi_data_push(table_data, sizeof *srat);
2348 srat->reserved1 = cpu_to_le32(1);
72c194f7 2349
5803fce3 2350 for (i = 0; i < apic_ids->len; i++) {
1f3aba37 2351 int j;
5803fce3
IM		 2352 int apic_id = apic_ids->cpus[i].arch_id;
2353
72c194f7 2354 core = acpi_data_push(table_data, sizeof *core);
e6e400d5 2355 core->type = ACPI_SRAT_PROCESSOR_APIC;
72c194f7 2356 core->length = sizeof(*core);
5803fce3 2357 core->local_apic_id = apic_id;
1f3aba37
IM		 2358 for (j = 0; j < nb_numa_nodes; j++) {
2359 if (test_bit(i, numa_info[j].node_cpu)) {
2360 core->proximity_lo = j;
2361 break;
2362 }
2363 }
72c194f7
MT		 2364 memset(core->proximity_hi, 0, 3);
2365 core->local_sapic_eid = 0;
dd0247e0 2366 core->flags = cpu_to_le32(1);
72c194f7
MT		 2367 }
2368
2369
2370 /* the memory map is a bit tricky, it contains at least one hole
2371 * from 640k-1M and possibly another one from 3.5G-4G.
2372 */
2373 next_base = 0;
2374 numa_start = table_data->len;
2375
2376 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136 2377 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED);
72c194f7 2378 next_base = 1024 * 1024;
dd4c2f01 2379 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
72c194f7 2380 mem_base = next_base;
dd4c2f01 2381 mem_len = pcms->node_mem[i - 1];
72c194f7
MT		 2382 if (i == 1) {
2383 mem_len -= 1024 * 1024;
2384 }
2385 next_base = mem_base + mem_len;
2386
2387 /* Cut out the ACPI_PCI hole */
5299f1c7
EH		 2388 if (mem_base <= pcms->below_4g_mem_size &&
2389 next_base > pcms->below_4g_mem_size) {
2390 mem_len -= next_base - pcms->below_4g_mem_size;
72c194f7
MT		 2391 if (mem_len > 0) {
2392 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136
SZ		 2393 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2394 MEM_AFFINITY_ENABLED);
72c194f7
MT		 2395 }
2396 mem_base = 1ULL << 32;
5299f1c7
EH		 2397 mem_len = next_base - pcms->below_4g_mem_size;
2398 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
72c194f7
MT		 2399 }
2400 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136
SZ		 2401 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2402 MEM_AFFINITY_ENABLED);
72c194f7
MT		 2403 }
2404 slots = (table_data->len - numa_start) / sizeof *numamem;
dd4c2f01 2405 for (; slots < pcms->numa_nodes + 2; slots++) {
72c194f7 2406 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136 2407 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
72c194f7
MT		 2408 }
2409
cec65193
IM		 2410 /*
2411 * Entry is required for Windows to enable memory hotplug in OS.
2412 * Memory devices may override proximity set by this entry,
2413 * providing _PXM method if necessary.
2414 */
2415 if (hotplugabble_address_space_size) {
2416 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136
SZ		 2417 build_srat_memory(numamem, pcms->hotplug_memory.base,
2418 hotplugabble_address_space_size, 0,
2419 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
cec65193
IM		 2420 }
2421
72c194f7
MT		 2422 build_header(linker, table_data,
2423 (void *)(table_data->data + srat_start),
821e3227 2424 "SRAT",
37ad223c 2425 table_data->len - srat_start, 1, NULL, NULL);
5803fce3 2426 g_free(apic_ids);
72c194f7
MT		 2427}
2428
2429static void
0e9b9eda 2430build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
72c194f7
MT		 2431{
2432 AcpiTableMcfg *mcfg;
821e3227 2433 const char *sig;
72c194f7
MT		 2434 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2435
2436 mcfg = acpi_data_push(table_data, len);
2437 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2438 /* Only a single allocation so no need to play with segments */
2439 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2440 mcfg->allocation[0].start_bus_number = 0;
2441 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2442
2443 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2444 * To avoid table size changes (which create migration issues),
2445 * always create the table even if there are no allocations,
2446 * but set the signature to a reserved value in this case.
2447 * ACPI spec requires OSPMs to ignore such tables.
2448 */
2449 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
821e3227
MT		 2450 /* Reserved signature: ignored by OSPM */
2451 sig = "QEMU";
72c194f7 2452 } else {
821e3227 2453 sig = "MCFG";
72c194f7 2454 }
37ad223c 2455 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
72c194f7
MT		 2456}
2457
d46114f9
PX		 2458/*
2459 * VT-d spec 8.1 DMA Remapping Reporting Structure
2460 * (version Oct. 2014 or later)
2461 */
d4eb9119 2462static void
0e9b9eda 2463build_dmar_q35(GArray *table_data, BIOSLinker *linker)
d4eb9119
LT		 2464{
2465 int dmar_start = table_data->len;
2466
2467 AcpiTableDmar *dmar;
2468 AcpiDmarHardwareUnit *drhd;
d46114f9
PX		 2469 uint8_t dmar_flags = 0;
2470 X86IOMMUState *iommu = x86_iommu_get_default();
2471
2472 assert(iommu);
2473 if (iommu->intr_supported) {
2474 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2475 }
d4eb9119
LT		 2476
2477 dmar = acpi_data_push(table_data, sizeof(*dmar));
2478 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
d46114f9 2479 dmar->flags = dmar_flags;
d4eb9119
LT		 2480
2481 /* DMAR Remapping Hardware Unit Definition structure */
2482 drhd = acpi_data_push(table_data, sizeof(*drhd));
2483 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2484 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
2485 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2486 drhd->pci_segment = cpu_to_le16(0);
2487 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2488
2489 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
37ad223c 2490 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
d4eb9119
LT		 2491}
2492
72c194f7 2493static GArray *
4678124b 2494build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
72c194f7
MT		 2495{
2496 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
4678124b
IM		 2497 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2498 unsigned rsdt_pa_offset =
2499 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
72c194f7 2500
ad9671b8 2501 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
72c194f7
MT		 2502 true /* fseg memory */);
2503
821e3227 2504 memcpy(&rsdp->signature, "RSD PTR ", 8);
72c194f7 2505 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
72c194f7 2506 /* Address to be filled by Guest linker */
4678124b
IM		 2507 bios_linker_loader_add_pointer(linker,
2508 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2509 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2510
72c194f7
MT		 2511 /* Checksum to be filled by Guest linker */
2512 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
28213cb6
IM		 2513 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2514 (char *)&rsdp->checksum - rsdp_table->data);
72c194f7
MT		 2515
2516 return rsdp_table;
2517}
2518
72c194f7
MT		 2519typedef
2520struct AcpiBuildState {
2521 /* Copy of table in RAM (for patching). */
339240b5 2522 MemoryRegion *table_mr;
72c194f7
MT		 2523 /* Is table patched? */
2524 uint8_t patched;
d70414a5 2525 void *rsdp;
339240b5
PB		 2526 MemoryRegion *rsdp_mr;
2527 MemoryRegion *linker_mr;
72c194f7
MT		 2528} AcpiBuildState;
2529
2530static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2531{
2532 Object *pci_host;
2533 QObject *o;
72c194f7 2534
ca6c1855 2535 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 2536 g_assert(pci_host);
2537
2538 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2539 if (!o) {
2540 return false;
2541 }
2542 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
097a97a6 2543 qobject_decref(o);
72c194f7
MT		 2544
2545 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2546 assert(o);
2547 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
097a97a6 2548 qobject_decref(o);
72c194f7
MT		 2549 return true;
2550}
2551
d4eb9119
LT		 2552static bool acpi_has_iommu(void)
2553{
1cf5fd57 2554 return !!x86_iommu_get_default();
d4eb9119
LT		 2555}
2556
72c194f7 2557static
3d3ebcad 2558void acpi_build(AcpiBuildTables *tables, MachineState *machine)
72c194f7 2559{
3d3ebcad 2560 PCMachineState *pcms = PC_MACHINE(machine);
bb292f5a 2561 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72c194f7 2562 GArray *table_offsets;
41fa5c04 2563 unsigned facs, dsdt, rsdt, fadt;
72c194f7
MT		 2564 AcpiPmInfo pm;
2565 AcpiMiscInfo misc;
2566 AcpiMcfgInfo mcfg;
01c9742d 2567 Range pci_hole, pci_hole64;
72c194f7 2568 uint8_t *u;
07fb6176 2569 size_t aml_len = 0;
7c2c1fa5 2570 GArray *tables_blob = tables->table_data;
ae123749 2571 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
72c194f7 2572
72c194f7 2573 acpi_get_pm_info(&pm);
72c194f7 2574 acpi_get_misc_info(&misc);
01c9742d 2575 acpi_get_pci_holes(&pci_hole, &pci_hole64);
ae123749 2576 acpi_get_slic_oem(&slic_oem);
72c194f7
MT		 2577
2578 table_offsets = g_array_new(false, true /* clear */,
2579 sizeof(uint32_t));
8b310fc4 2580 ACPI_BUILD_DPRINTF("init ACPI tables\n");
72c194f7 2581
ad9671b8
IM		 2582 bios_linker_loader_alloc(tables->linker,
2583 ACPI_BUILD_TABLE_FILE, tables_blob,
72c194f7
MT		 2584 64 /* Ensure FACS is aligned */,
2585 false /* high memory */);
2586
2587 /*
2588 * FACS is pointed to by FADT.
2589 * We place it first since it's the only table that has alignment
2590 * requirements.
2591 */
7c2c1fa5 2592 facs = tables_blob->len;
fb306ffe 2593 build_facs(tables_blob, tables->linker);
72c194f7
MT		 2594
2595 /* DSDT is pointed to by FADT */
7c2c1fa5 2596 dsdt = tables_blob->len;
01c9742d
MA		 2597 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2598 &pci_hole, &pci_hole64, machine);
72c194f7 2599
07fb6176
PB		 2600 /* Count the size of the DSDT and SSDT, we will need it for legacy
2601 * sizing of ACPI tables.
2602 */
7c2c1fa5 2603 aml_len += tables_blob->len - dsdt;
07fb6176 2604
72c194f7 2605 /* ACPI tables pointed to by RSDT */
41fa5c04 2606 fadt = tables_blob->len;
7c2c1fa5 2607 acpi_add_table(table_offsets, tables_blob);
ae123749
LE		 2608 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2609 slic_oem.id, slic_oem.table_id);
41fa5c04 2610 aml_len += tables_blob->len - fadt;
72c194f7 2611
7c2c1fa5 2612 acpi_add_table(table_offsets, tables_blob);
907e7c94 2613 build_madt(tables_blob, tables->linker, pcms);
9ac1c4c0 2614
72c194f7 2615 if (misc.has_hpet) {
7c2c1fa5
IM		 2616 acpi_add_table(table_offsets, tables_blob);
2617 build_hpet(tables_blob, tables->linker);
711b20b4 2618 }
5cb18b3d 2619 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
7c2c1fa5
IM		 2620 acpi_add_table(table_offsets, tables_blob);
2621 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
711b20b4 2622
72d97b3a
IM		 2623 if (misc.tpm_version == TPM_VERSION_2_0) {
2624 acpi_add_table(table_offsets, tables_blob);
5cb18b3d 2625 build_tpm2(tables_blob, tables->linker);
5cb18b3d 2626 }
72c194f7 2627 }
dd4c2f01 2628 if (pcms->numa_nodes) {
7c2c1fa5 2629 acpi_add_table(table_offsets, tables_blob);
3d3ebcad 2630 build_srat(tables_blob, tables->linker, machine);
72c194f7
MT		 2631 }
2632 if (acpi_get_mcfg(&mcfg)) {
7c2c1fa5
IM		 2633 acpi_add_table(table_offsets, tables_blob);
2634 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
72c194f7 2635 }
d4eb9119 2636 if (acpi_has_iommu()) {
7c2c1fa5
IM		 2637 acpi_add_table(table_offsets, tables_blob);
2638 build_dmar_q35(tables_blob, tables->linker);
d4eb9119 2639 }
5fe79386 2640 if (pcms->acpi_nvdimm_state.is_enabled) {
ad9671b8
IM		 2641 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2642 pcms->acpi_nvdimm_state.dsm_mem);
87252e1b
XG		 2643 }
2644
72c194f7
MT		 2645 /* Add tables supplied by user (if any) */
2646 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2647 unsigned len = acpi_table_len(u);
2648
7c2c1fa5
IM		 2649 acpi_add_table(table_offsets, tables_blob);
2650 g_array_append_vals(tables_blob, u, len);
72c194f7
MT		 2651 }
2652
2653 /* RSDT is pointed to by RSDP */
7c2c1fa5 2654 rsdt = tables_blob->len;
ae123749
LE		 2655 build_rsdt(tables_blob, tables->linker, table_offsets,
2656 slic_oem.id, slic_oem.table_id);
72c194f7
MT		 2657
2658 /* RSDP is in FSEG memory, so allocate it separately */
2659 build_rsdp(tables->rsdp, tables->linker, rsdt);
2660
07fb6176 2661 /* We'll expose it all to Guest so we want to reduce
72c194f7 2662 * chance of size changes.
07fb6176
PB		 2663 *
2664 * We used to align the tables to 4k, but of course this would
2665 * too simple to be enough. 4k turned out to be too small an
2666 * alignment very soon, and in fact it is almost impossible to
2667 * keep the table size stable for all (max_cpus, max_memory_slots)
2668 * combinations. So the table size is always 64k for pc-i440fx-2.1
2669 * and we give an error if the table grows beyond that limit.
2670 *
2671 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2672 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2673 * than 2.0 and we can always pad the smaller tables with zeros. We can
2674 * then use the exact size of the 2.0 tables.
2675 *
2676 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
72c194f7 2677 */
bb292f5a 2678 if (pcmc->legacy_acpi_table_size) {
07fb6176
PB		 2679 /* Subtracting aml_len gives the size of fixed tables. Then add the
2680 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2681 */
2682 int legacy_aml_len =
bb292f5a 2683 pcmc->legacy_acpi_table_size +
07fb6176
PB		 2684 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2685 int legacy_table_size =
7c2c1fa5 2686 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
07fb6176 2687 ACPI_BUILD_ALIGN_SIZE);
7c2c1fa5 2688 if (tables_blob->len > legacy_table_size) {
07fb6176 2689 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
868270f2 2690 error_report("Warning: migration may not work.");
07fb6176 2691 }
7c2c1fa5 2692 g_array_set_size(tables_blob, legacy_table_size);
07fb6176 2693 } else {
868270f2 2694 /* Make sure we have a buffer in case we need to resize the tables. */
7c2c1fa5 2695 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
18045fb9 2696 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
868270f2
MT		 2697 error_report("Warning: ACPI tables are larger than 64k.");
2698 error_report("Warning: migration may not work.");
2699 error_report("Warning: please remove CPUs, NUMA nodes, "
2700 "memory slots or PCI bridges.");
18045fb9 2701 }
7c2c1fa5 2702 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
07fb6176 2703 }
72c194f7 2704
0e9b9eda 2705 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
72c194f7
MT		 2706
2707 /* Cleanup memory that's no longer used. */
2708 g_array_free(table_offsets, true);
2709}
2710
339240b5 2711static void acpi_ram_update(MemoryRegion *mr, GArray *data)
42d85900
MT		 2712{
2713 uint32_t size = acpi_data_len(data);
2714
2715 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
339240b5 2716 memory_region_ram_resize(mr, size, &error_abort);
42d85900 2717
339240b5
PB		 2718 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2719 memory_region_set_dirty(mr, 0, size);
42d85900
MT		 2720}
2721
3f8752b4 2722static void acpi_build_update(void *build_opaque)
72c194f7
MT		 2723{
2724 AcpiBuildState *build_state = build_opaque;
2725 AcpiBuildTables tables;
2726
2727 /* No state to update or already patched? Nothing to do. */
2728 if (!build_state || build_state->patched) {
2729 return;
2730 }
2731 build_state->patched = 1;
2732
2733 acpi_build_tables_init(&tables);
2734
3d3ebcad 2735 acpi_build(&tables, MACHINE(qdev_get_machine()));
72c194f7 2736
339240b5 2737 acpi_ram_update(build_state->table_mr, tables.table_data);
a1666142 2738
42d85900
MT		 2739 if (build_state->rsdp) {
2740 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2741 } else {
339240b5 2742 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
42d85900 2743 }
ad5b88b1 2744
0e9b9eda 2745 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
72c194f7
MT		 2746 acpi_build_tables_cleanup(&tables, true);
2747}
2748
2749static void acpi_build_reset(void *build_opaque)
2750{
2751 AcpiBuildState *build_state = build_opaque;
2752 build_state->patched = 0;
2753}
2754
339240b5
PB		 2755static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2756 GArray *blob, const char *name,
2757 uint64_t max_size)
72c194f7 2758{
a1666142
MT		 2759 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2760 name, acpi_build_update, build_state);
72c194f7
MT		 2761}
2762
2763static const VMStateDescription vmstate_acpi_build = {
2764 .name = "acpi_build",
2765 .version_id = 1,
2766 .minimum_version_id = 1,
d49805ae 2767 .fields = (VMStateField[]) {
72c194f7
MT		 2768 VMSTATE_UINT8(patched, AcpiBuildState),
2769 VMSTATE_END_OF_LIST()
2770 },
2771};
2772
fb306ffe 2773void acpi_setup(void)
72c194f7 2774{
fb306ffe 2775 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
bb292f5a 2776 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72c194f7
MT		 2777 AcpiBuildTables tables;
2778 AcpiBuildState *build_state;
2779
f264d360 2780 if (!pcms->fw_cfg) {
8b310fc4 2781 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
72c194f7
MT		 2782 return;
2783 }
2784
bb292f5a 2785 if (!pcmc->has_acpi_build) {
8b310fc4 2786 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
72c194f7
MT		 2787 return;
2788 }
2789
81adc513 2790 if (!acpi_enabled) {
8b310fc4 2791 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
81adc513
MT		 2792 return;
2793 }
2794
72c194f7
MT		 2795 build_state = g_malloc0(sizeof *build_state);
2796
99fd437d
MT		 2797 acpi_set_pci_info();
2798
72c194f7 2799 acpi_build_tables_init(&tables);
3d3ebcad 2800 acpi_build(&tables, MACHINE(pcms));
72c194f7
MT		 2801
2802 /* Now expose it all to Guest */
339240b5 2803 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
a1666142
MT		 2804 ACPI_BUILD_TABLE_FILE,
2805 ACPI_BUILD_TABLE_MAX_SIZE);
339240b5 2806 assert(build_state->table_mr != NULL);
72c194f7 2807
339240b5 2808 build_state->linker_mr =
0e9b9eda
IM		 2809 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2810 "etc/table-loader", 0);
72c194f7 2811
f264d360 2812 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
42a5b308
SB		 2813 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2814
bb292f5a 2815 if (!pcmc->rsdp_in_ram) {
358774d7
IM		 2816 /*
2817 * Keep for compatibility with old machine types.
2818 * Though RSDP is small, its contents isn't immutable, so
afaa2e4b 2819 * we'll update it along with the rest of tables on guest access.
358774d7 2820 */
afaa2e4b
MT		 2821 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2822
2823 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
f264d360 2824 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
358774d7 2825 acpi_build_update, build_state,
afaa2e4b 2826 build_state->rsdp, rsdp_size);
339240b5 2827 build_state->rsdp_mr = NULL;
358774d7 2828 } else {
42d85900 2829 build_state->rsdp = NULL;
339240b5 2830 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
42d85900 2831 ACPI_BUILD_RSDP_FILE, 0);
358774d7 2832 }
72c194f7
MT		 2833
2834 qemu_register_reset(acpi_build_reset, build_state);
2835 acpi_build_reset(build_state);
2836 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2837
2838 /* Cleanup tables but don't free the memory: we track it
2839 * in build_state.
2840 */
2841 acpi_build_tables_cleanup(&tables, false);
2842}
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