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q35: acpi: do not create dummy MCFG table
[mirror_qemu.git] / hw / i386 / acpi-build.c
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72c194f7
MT		 1/* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
b6a0aa05 23#include "qemu/osdep.h"
da34e65c 24#include "qapi/error.h"
15280c36 25#include "qapi/qmp/qnum.h"
72c194f7 26#include "acpi-build.h"
72c194f7
MT		 27#include "qemu-common.h"
28#include "qemu/bitmap.h"
07fb6176 29#include "qemu/error-report.h"
72c194f7
MT		 30#include "hw/pci/pci.h"
31#include "qom/cpu.h"
fcf5ef2a 32#include "target/i386/cpu.h"
0d5d8a3a 33#include "hw/misc/pvpanic.h"
72c194f7 34#include "hw/timer/hpet.h"
395e5fb4 35#include "hw/acpi/acpi-defs.h"
72c194f7 36#include "hw/acpi/acpi.h"
679dd1a9 37#include "hw/acpi/cpu.h"
81c48dd7 38#include "hw/acpi/piix4.h"
72c194f7 39#include "hw/nvram/fw_cfg.h"
0058ae1d 40#include "hw/acpi/bios-linker-loader.h"
72c194f7 41#include "hw/loader.h"
15bce1b7 42#include "hw/isa/isa.h"
27b9fc54 43#include "hw/block/fdc.h"
bef3492d 44#include "hw/acpi/memory_hotplug.h"
711b20b4
SB		 45#include "sysemu/tpm.h"
46#include "hw/acpi/tpm.h"
d03637bc 47#include "hw/acpi/vmgenid.h"
5cb18b3d 48#include "sysemu/tpm_backend.h"
f070efa8 49#include "hw/timer/mc146818rtc_regs.h"
2cc0e2e8 50#include "hw/mem/memory-device.h"
1f3aba37 51#include "sysemu/numa.h"
72c194f7
MT		 52
53/* Supported chipsets: */
54#include "hw/acpi/piix4.h"
99fd437d 55#include "hw/acpi/pcihp.h"
72c194f7
MT		 56#include "hw/i386/ich9.h"
57#include "hw/pci/pci_bus.h"
58#include "hw/pci-host/q35.h"
1cf5fd57 59#include "hw/i386/x86-iommu.h"
72c194f7 60
19934e0e
IM		 61#include "hw/acpi/aml-build.h"
62
72c194f7 63#include "qom/qom-qobject.h"
fb9f5926
DK		 64#include "hw/i386/amd_iommu.h"
65#include "hw/i386/intel_iommu.h"
72c194f7 66
86e91dd7
CM		 67#include "hw/acpi/ipmi.h"
68
07fb6176
PB		 69/* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
70 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
71 * a little bit, there should be plenty of free space since the DSDT
72 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
73 */
74#define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
75#define ACPI_BUILD_ALIGN_SIZE 0x1000
76
868270f2 77#define ACPI_BUILD_TABLE_SIZE 0x20000
18045fb9 78
8b310fc4
GA		 79/* #define DEBUG_ACPI_BUILD */
80#ifdef DEBUG_ACPI_BUILD
81#define ACPI_BUILD_DPRINTF(fmt, ...) \
82 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
83#else
84#define ACPI_BUILD_DPRINTF(fmt, ...)
85#endif
86
cfc13df4
PX		 87/* Default IOAPIC ID */
88#define ACPI_BUILD_IOAPIC_ID 0x0
89
72c194f7
MT		 90typedef struct AcpiMcfgInfo {
91 uint64_t mcfg_base;
92 uint32_t mcfg_size;
93} AcpiMcfgInfo;
94
95typedef struct AcpiPmInfo {
96 bool s3_disabled;
97 bool s4_disabled;
133a2da4 98 bool pcihp_bridge_en;
72c194f7 99 uint8_t s4_val;
937d1b58 100 AcpiFadtData fadt;
ddf1ec2f 101 uint16_t cpu_hp_io_base;
500b11ea
IM		 102 uint16_t pcihp_io_base;
103 uint16_t pcihp_io_len;
72c194f7
MT		 104} AcpiPmInfo;
105
106typedef struct AcpiMiscInfo {
e4db2798 107 bool is_piix4;
72c194f7 108 bool has_hpet;
5cb18b3d 109 TPMVersion tpm_version;
72c194f7
MT		 110 const unsigned char *dsdt_code;
111 unsigned dsdt_size;
112 uint16_t pvpanic_port;
8ac6f7a6 113 uint16_t applesmc_io_base;
72c194f7
MT		 114} AcpiMiscInfo;
115
99fd437d
MT		 116typedef struct AcpiBuildPciBusHotplugState {
117 GArray *device_table;
118 GArray *notify_table;
119 struct AcpiBuildPciBusHotplugState *parent;
133a2da4 120 bool pcihp_bridge_en;
99fd437d
MT		 121} AcpiBuildPciBusHotplugState;
122
0fe24669
SB		 123typedef struct FwCfgTPMConfig {
124 uint32_t tpmppi_address;
125 uint8_t tpm_version;
126 uint8_t tpmppi_version;
127} QEMU_PACKED FwCfgTPMConfig;
128
937d1b58
IM		 129static void init_common_fadt_data(Object *o, AcpiFadtData *data)
130{
131 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
132 AmlAddressSpace as = AML_AS_SYSTEM_IO;
133 AcpiFadtData fadt = {
134 .rev = 3,
135 .flags =
136 (1 << ACPI_FADT_F_WBINVD) |
137 (1 << ACPI_FADT_F_PROC_C1) |
138 (1 << ACPI_FADT_F_SLP_BUTTON) |
139 (1 << ACPI_FADT_F_RTC_S4) |
140 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
141 /* APIC destination mode ("Flat Logical") has an upper limit of 8
142 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
143 * used
144 */
145 ((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
146 .int_model = 1 /* Multiple APIC */,
147 .rtc_century = RTC_CENTURY,
148 .plvl2_lat = 0xfff /* C2 state not supported */,
149 .plvl3_lat = 0xfff /* C3 state not supported */,
150 .smi_cmd = ACPI_PORT_SMI_CMD,
151 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
152 .acpi_enable_cmd =
153 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
154 .acpi_disable_cmd =
155 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
156 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
157 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
158 .address = io + 0x04 },
159 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
160 .gpe0_blk = { .space_id = as, .bit_width =
161 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
162 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
163 },
164 };
165 *data = fadt;
166}
167
81c48dd7
PMD		 168static Object *object_resolve_type_unambiguous(const char *typename)
169{
170 bool ambig;
171 Object *o = object_resolve_path_type("", typename, &ambig);
172
173 if (ambig || !o) {
174 return NULL;
175 }
176 return o;
177}
178
72c194f7
MT		 179static void acpi_get_pm_info(AcpiPmInfo *pm)
180{
81c48dd7
PMD		 181 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
182 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
697155cd 183 Object *obj = piix ? piix : lpc;
72c194f7 184 QObject *o;
94aaca64 185 pm->cpu_hp_io_base = 0;
500b11ea
IM		 186 pm->pcihp_io_base = 0;
187 pm->pcihp_io_len = 0;
937d1b58 188
6fa5171f 189 assert(obj);
937d1b58 190 init_common_fadt_data(obj, &pm->fadt);
72c194f7 191 if (piix) {
3a3fcc75 192 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
937d1b58 193 pm->fadt.rev = 1;
ddf1ec2f 194 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
500b11ea 195 pm->pcihp_io_base =
35f91e50 196 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
500b11ea 197 pm->pcihp_io_len =
35f91e50 198 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
72c194f7
MT		 199 }
200 if (lpc) {
937d1b58
IM		 201 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
202 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
203 pm->fadt.reset_reg = r;
204 pm->fadt.reset_val = 0xf;
205 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
ddf1ec2f 206 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
72c194f7 207 }
72c194f7 208
937d1b58
IM		 209 /* The above need not be conditional on machine type because the reset port
210 * happens to be the same on PIIX (pc) and ICH9 (q35). */
211 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
212
72c194f7
MT		 213 /* Fill in optional s3/s4 related properties */
214 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
215 if (o) {
7dc847eb 216 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
72c194f7
MT		 217 } else {
218 pm->s3_disabled = false;
219 }
cb3e7f08 220 qobject_unref(o);
72c194f7
MT		 221 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
222 if (o) {
7dc847eb 223 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
72c194f7
MT		 224 } else {
225 pm->s4_disabled = false;
226 }
cb3e7f08 227 qobject_unref(o);
72c194f7
MT		 228 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
229 if (o) {
7dc847eb 230 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
72c194f7
MT		 231 } else {
232 pm->s4_val = false;
233 }
cb3e7f08 234 qobject_unref(o);
72c194f7 235
133a2da4
IM		 236 pm->pcihp_bridge_en =
237 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
238 NULL);
72c194f7
MT		 239}
240
72c194f7
MT		 241static void acpi_get_misc_info(AcpiMiscInfo *info)
242{
81c48dd7
PMD		 243 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
244 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
3db119da
IM		 245 assert(!!piix != !!lpc);
246
247 if (piix) {
248 info->is_piix4 = true;
249 }
250 if (lpc) {
251 info->is_piix4 = false;
252 }
253
72c194f7 254 info->has_hpet = hpet_find();
3dfd5a2a 255 info->tpm_version = tpm_get_version(tpm_find());
72c194f7 256 info->pvpanic_port = pvpanic_port();
8ac6f7a6 257 info->applesmc_io_base = applesmc_port();
72c194f7
MT		 258}
259
ca6c1855
MA		 260/*
261 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
262 * On i386 arch we only have two pci hosts, so we can look only for them.
263 */
264static Object *acpi_get_i386_pci_host(void)
265{
266 PCIHostState *host;
267
268 host = OBJECT_CHECK(PCIHostState,
269 object_resolve_path("/machine/i440fx", NULL),
270 TYPE_PCI_HOST_BRIDGE);
271 if (!host) {
272 host = OBJECT_CHECK(PCIHostState,
273 object_resolve_path("/machine/q35", NULL),
274 TYPE_PCI_HOST_BRIDGE);
275 }
276
277 return OBJECT(host);
278}
279
01c9742d 280static void acpi_get_pci_holes(Range *hole, Range *hole64)
72c194f7
MT		 281{
282 Object *pci_host;
72c194f7 283
ca6c1855 284 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 285 g_assert(pci_host);
286
a0efbf16 287 range_set_bounds1(hole,
60555365
MAL		 288 object_property_get_uint(pci_host,
289 PCI_HOST_PROP_PCI_HOLE_START,
290 NULL),
291 object_property_get_uint(pci_host,
292 PCI_HOST_PROP_PCI_HOLE_END,
293 NULL));
a0efbf16 294 range_set_bounds1(hole64,
60555365
MAL		 295 object_property_get_uint(pci_host,
296 PCI_HOST_PROP_PCI_HOLE64_START,
297 NULL),
298 object_property_get_uint(pci_host,
299 PCI_HOST_PROP_PCI_HOLE64_END,
300 NULL));
72c194f7
MT		 301}
302
72c194f7
MT		 303static void acpi_align_size(GArray *blob, unsigned align)
304{
305 /* Align size to multiple of given size. This reduces the chance
306 * we need to change size in the future (breaking cross version migration).
307 */
134d42d6 308 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
72c194f7
MT		 309}
310
72c194f7
MT		 311/* FACS */
312static void
009180bd 313build_facs(GArray *table_data)
72c194f7
MT		 314{
315 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
821e3227 316 memcpy(&facs->signature, "FACS", 4);
72c194f7
MT		 317 facs->length = cpu_to_le32(sizeof(*facs));
318}
319
ac35f13b 320void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
80e5db30 321 const CPUArchIdList *apic_ids, GArray *entry)
ac35f13b 322{
e2c95939
IM		 323 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
324
325 /* ACPI spec says that LAPIC entry for non present
326 * CPU may be omitted from MADT or it must be marked
327 * as disabled. However omitting non present CPU from
328 * MADT breaks hotplug on linux. So possible CPUs
329 * should be put in MADT but kept disabled.
330 */
331 if (apic_id < 255) {
332 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
333
334 apic->type = ACPI_APIC_PROCESSOR;
335 apic->length = sizeof(*apic);
336 apic->processor_id = uid;
337 apic->local_apic_id = apic_id;
338 if (apic_ids->cpus[uid].cpu != NULL) {
339 apic->flags = cpu_to_le32(1);
340 } else {
341 apic->flags = cpu_to_le32(0);
342 }
ac35f13b 343 } else {
e2c95939
IM		 344 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
345
346 apic->type = ACPI_APIC_LOCAL_X2APIC;
347 apic->length = sizeof(*apic);
348 apic->uid = cpu_to_le32(uid);
349 apic->x2apic_id = cpu_to_le32(apic_id);
350 if (apic_ids->cpus[uid].cpu != NULL) {
351 apic->flags = cpu_to_le32(1);
352 } else {
353 apic->flags = cpu_to_le32(0);
354 }
ac35f13b
IM		 355 }
356}
357
72c194f7 358static void
0e9b9eda 359build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
72c194f7 360{
907e7c94 361 MachineClass *mc = MACHINE_GET_CLASS(pcms);
80e5db30 362 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
72c194f7 363 int madt_start = table_data->len;
ac35f13b
IM		 364 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
365 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
e2c95939 366 bool x2apic_mode = false;
72c194f7
MT		 367
368 AcpiMultipleApicTable *madt;
369 AcpiMadtIoApic *io_apic;
370 AcpiMadtIntsrcovr *intsrcovr;
72c194f7
MT		 371 int i;
372
373 madt = acpi_data_push(table_data, sizeof *madt);
374 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
375 madt->flags = cpu_to_le32(1);
376
907e7c94 377 for (i = 0; i < apic_ids->len; i++) {
ac35f13b 378 adevc->madt_cpu(adev, i, apic_ids, table_data);
e2c95939
IM		 379 if (apic_ids->cpus[i].arch_id > 254) {
380 x2apic_mode = true;
381 }
72c194f7 382 }
907e7c94 383
72c194f7
MT		 384 io_apic = acpi_data_push(table_data, sizeof *io_apic);
385 io_apic->type = ACPI_APIC_IO;
386 io_apic->length = sizeof(*io_apic);
72c194f7
MT		 387 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
388 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
389 io_apic->interrupt = cpu_to_le32(0);
390
dd4c2f01 391 if (pcms->apic_xrupt_override) {
72c194f7
MT		 392 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
393 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
394 intsrcovr->length = sizeof(*intsrcovr);
395 intsrcovr->source = 0;
396 intsrcovr->gsi = cpu_to_le32(2);
397 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
398 }
399 for (i = 1; i < 16; i++) {
400#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
401 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
402 /* No need for a INT source override structure. */
403 continue;
404 }
405 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
406 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
407 intsrcovr->length = sizeof(*intsrcovr);
408 intsrcovr->source = i;
409 intsrcovr->gsi = cpu_to_le32(i);
410 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
411 }
412
e2c95939
IM		 413 if (x2apic_mode) {
414 AcpiMadtLocalX2ApicNmi *local_nmi;
415
416 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
417 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
418 local_nmi->length = sizeof(*local_nmi);
419 local_nmi->uid = 0xFFFFFFFF; /* all processors */
420 local_nmi->flags = cpu_to_le16(0);
421 local_nmi->lint = 1; /* ACPI_LINT1 */
422 } else {
423 AcpiMadtLocalNmi *local_nmi;
424
425 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
426 local_nmi->type = ACPI_APIC_LOCAL_NMI;
427 local_nmi->length = sizeof(*local_nmi);
428 local_nmi->processor_id = 0xff; /* all processors */
429 local_nmi->flags = cpu_to_le16(0);
430 local_nmi->lint = 1; /* ACPI_LINT1 */
431 }
72c194f7
MT		 432
433 build_header(linker, table_data,
821e3227 434 (void *)(table_data->data + madt_start), "APIC",
37ad223c 435 table_data->len - madt_start, 1, NULL, NULL);
72c194f7
MT		 436}
437
62b52c26 438static void build_append_pcihp_notify_entry(Aml *method, int slot)
99fd437d 439{
62b52c26
IM		 440 Aml *if_ctx;
441 int32_t devfn = PCI_DEVFN(slot, 0);
442
5530427f 443 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
62b52c26
IM		 444 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
445 aml_append(method, if_ctx);
99fd437d
MT		 446}
447
62b52c26 448static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
b23046ab 449 bool pcihp_bridge_en)
99fd437d 450{
7dc847eb 451 Aml *dev, *notify_method = NULL, *method;
99fd437d 452 QObject *bsel;
b23046ab
IM		 453 PCIBus *sec;
454 int i;
133a2da4 455
99fd437d
MT		 456 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
457 if (bsel) {
7dc847eb 458 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
62b52c26
IM		 459
460 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
4dbfc881 461 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
8dcf525a 462 }
99fd437d 463
8dcf525a
MT		 464 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
465 DeviceClass *dc;
466 PCIDeviceClass *pc;
467 PCIDevice *pdev = bus->devices[i];
468 int slot = PCI_SLOT(i);
b23046ab 469 bool hotplug_enabled_dev;
093a35e5 470 bool bridge_in_acpi;
99fd437d 471
8dcf525a 472 if (!pdev) {
b23046ab 473 if (bsel) { /* add hotplug slots for non present devices */
62b52c26
IM		 474 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
475 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
476 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
4dbfc881 477 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 478 aml_append(method,
479 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
480 );
481 aml_append(dev, method);
482 aml_append(parent_scope, dev);
483
484 build_append_pcihp_notify_entry(notify_method, slot);
b23046ab 485 }
8dcf525a
MT		 486 continue;
487 }
99fd437d 488
8dcf525a
MT		 489 pc = PCI_DEVICE_GET_CLASS(pdev);
490 dc = DEVICE_GET_CLASS(pdev);
99fd437d 491
093a35e5
MT		 492 /* When hotplug for bridges is enabled, bridges are
493 * described in ACPI separately (see build_pci_bus_end).
494 * In this case they aren't themselves hot-pluggable.
a20275fa 495 * Hotplugged bridges *are* hot-pluggable.
093a35e5 496 */
b23046ab
IM		 497 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
498 !DEVICE(pdev)->hotplugged;
499
500 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
093a35e5 501
b23046ab
IM		 502 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
503 continue;
99fd437d
MT		 504 }
505
62b52c26
IM		 506 /* start to compose PCI slot descriptor */
507 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
508 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
509
8dcf525a 510 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
62b52c26
IM		 511 /* add VGA specific AML methods */
512 int s3d;
513
8dcf525a 514 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
62b52c26 515 s3d = 3;
b23046ab 516 } else {
62b52c26 517 s3d = 0;
99fd437d 518 }
62b52c26 519
4dbfc881 520 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 521 aml_append(method, aml_return(aml_int(0)));
522 aml_append(dev, method);
523
4dbfc881 524 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 525 aml_append(method, aml_return(aml_int(0)));
526 aml_append(dev, method);
527
4dbfc881 528 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 529 aml_append(method, aml_return(aml_int(s3d)));
530 aml_append(dev, method);
b23046ab 531 } else if (hotplug_enabled_dev) {
62b52c26
IM		 532 /* add _SUN/_EJ0 to make slot hotpluggable */
533 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
99fd437d 534
4dbfc881 535 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 536 aml_append(method,
537 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
538 );
539 aml_append(dev, method);
540
541 if (bsel) {
542 build_append_pcihp_notify_entry(notify_method, slot);
543 }
b23046ab 544 } else if (bridge_in_acpi) {
62b52c26
IM		 545 /*
546 * device is coldplugged bridge,
547 * add child device descriptions into its scope
548 */
b23046ab 549 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
b23046ab 550
62b52c26 551 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
8dcf525a 552 }
62b52c26
IM		 553 /* slot descriptor has been composed, add it into parent context */
554 aml_append(parent_scope, dev);
8dcf525a
MT		 555 }
556
557 if (bsel) {
62b52c26 558 aml_append(parent_scope, notify_method);
99fd437d
MT		 559 }
560
561 /* Append PCNT method to notify about events on local and child buses.
562 * Add unconditionally for root since DSDT expects it.
72c194f7 563 */
4dbfc881 564 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
99fd437d 565
b23046ab
IM		 566 /* If bus supports hotplug select it and notify about local events */
567 if (bsel) {
7dc847eb 568 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
01b2ffce 569
62b52c26
IM		 570 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
571 aml_append(method,
572 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
573 );
574 aml_append(method,
575 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
576 );
b23046ab 577 }
99fd437d 578
b23046ab
IM		 579 /* Notify about child bus events in any case */
580 if (pcihp_bridge_en) {
581 QLIST_FOREACH(sec, &bus->child, sibling) {
62b52c26
IM		 582 int32_t devfn = sec->parent_dev->devfn;
583
c99cb18e
MA		 584 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
585 continue;
586 }
587
62b52c26 588 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
99fd437d 589 }
72c194f7 590 }
62b52c26 591 aml_append(parent_scope, method);
cb3e7f08 592 qobject_unref(bsel);
72c194f7
MT		 593}
594
196e2137
IM		 595/**
596 * build_prt_entry:
597 * @link_name: link name for PCI route entry
598 *
599 * build AML package containing a PCI route entry for @link_name
600 */
601static Aml *build_prt_entry(const char *link_name)
602{
603 Aml *a_zero = aml_int(0);
604 Aml *pkg = aml_package(4);
605 aml_append(pkg, a_zero);
606 aml_append(pkg, a_zero);
607 aml_append(pkg, aml_name("%s", link_name));
608 aml_append(pkg, a_zero);
609 return pkg;
610}
611
0d8935e3
MA		 612/*
613 * initialize_route - Initialize the interrupt routing rule
614 * through a specific LINK:
615 * if (lnk_idx == idx)
616 * route using link 'link_name'
617 */
618static Aml *initialize_route(Aml *route, const char *link_name,
619 Aml *lnk_idx, int idx)
620{
621 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
196e2137 622 Aml *pkg = build_prt_entry(link_name);
0d8935e3 623
0d8935e3
MA		 624 aml_append(if_ctx, aml_store(pkg, route));
625
626 return if_ctx;
627}
628
629/*
630 * build_prt - Define interrupt rounting rules
631 *
632 * Returns an array of 128 routes, one for each device,
633 * based on device location.
634 * The main goal is to equaly distribute the interrupts
635 * over the 4 existing ACPI links (works only for i440fx).
636 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
637 *
638 */
196e2137 639static Aml *build_prt(bool is_pci0_prt)
0d8935e3
MA		 640{
641 Aml *method, *while_ctx, *pin, *res;
642
4dbfc881 643 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
0d8935e3
MA		 644 res = aml_local(0);
645 pin = aml_local(1);
646 aml_append(method, aml_store(aml_package(128), res));
647 aml_append(method, aml_store(aml_int(0), pin));
648
649 /* while (pin < 128) */
650 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
651 {
652 Aml *slot = aml_local(2);
653 Aml *lnk_idx = aml_local(3);
654 Aml *route = aml_local(4);
655
656 /* slot = pin >> 2 */
657 aml_append(while_ctx,
c360639a 658 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
0d8935e3
MA		 659 /* lnk_idx = (slot + pin) & 3 */
660 aml_append(while_ctx,
5530427f
IM		 661 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
662 lnk_idx));
0d8935e3
MA		 663
664 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
665 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
196e2137
IM		 666 if (is_pci0_prt) {
667 Aml *if_device_1, *if_pin_4, *else_pin_4;
668
669 /* device 1 is the power-management device, needs SCI */
670 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
671 {
672 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
673 {
674 aml_append(if_pin_4,
675 aml_store(build_prt_entry("LNKS"), route));
676 }
677 aml_append(if_device_1, if_pin_4);
678 else_pin_4 = aml_else();
679 {
680 aml_append(else_pin_4,
681 aml_store(build_prt_entry("LNKA"), route));
682 }
683 aml_append(if_device_1, else_pin_4);
684 }
685 aml_append(while_ctx, if_device_1);
686 } else {
687 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
688 }
0d8935e3
MA		 689 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
690 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
691
692 /* route[0] = 0x[slot]FFFF */
693 aml_append(while_ctx,
ca3df95d
IM		 694 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
695 NULL),
0d8935e3
MA		 696 aml_index(route, aml_int(0))));
697 /* route[1] = pin & 3 */
698 aml_append(while_ctx,
5530427f
IM		 699 aml_store(aml_and(pin, aml_int(3), NULL),
700 aml_index(route, aml_int(1))));
0d8935e3
MA		 701 /* res[pin] = route */
702 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
703 /* pin++ */
704 aml_append(while_ctx, aml_increment(pin));
705 }
706 aml_append(method, while_ctx);
707 /* return res*/
708 aml_append(method, aml_return(res));
709
710 return method;
711}
712
a43c6e27
MA		 713typedef struct CrsRangeEntry {
714 uint64_t base;
715 uint64_t limit;
716} CrsRangeEntry;
717
718static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
719{
720 CrsRangeEntry *entry;
721
722 entry = g_malloc(sizeof(*entry));
723 entry->base = base;
724 entry->limit = limit;
725
726 g_ptr_array_add(ranges, entry);
727}
728
729static void crs_range_free(gpointer data)
730{
731 CrsRangeEntry *entry = (CrsRangeEntry *)data;
732 g_free(entry);
733}
734
2df5a7b5
MA		 735typedef struct CrsRangeSet {
736 GPtrArray *io_ranges;
737 GPtrArray *mem_ranges;
16de88a4 738 GPtrArray *mem_64bit_ranges;
2df5a7b5
MA		 739 } CrsRangeSet;
740
741static void crs_range_set_init(CrsRangeSet *range_set)
742{
743 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
744 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
16de88a4
MA		 745 range_set->mem_64bit_ranges =
746 g_ptr_array_new_with_free_func(crs_range_free);
2df5a7b5
MA		 747}
748
749static void crs_range_set_free(CrsRangeSet *range_set)
750{
751 g_ptr_array_free(range_set->io_ranges, true);
752 g_ptr_array_free(range_set->mem_ranges, true);
16de88a4 753 g_ptr_array_free(range_set->mem_64bit_ranges, true);
2df5a7b5
MA		 754}
755
dcdca296
MA		 756static gint crs_range_compare(gconstpointer a, gconstpointer b)
757{
758 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
759 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
760
761 return (int64_t)entry_a->base - (int64_t)entry_b->base;
762}
763
764/*
765 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
766 * interval, computes the 'free' ranges from the same interval.
767 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
768 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
769 */
770static void crs_replace_with_free_ranges(GPtrArray *ranges,
771 uint64_t start, uint64_t end)
772{
354fb471 773 GPtrArray *free_ranges = g_ptr_array_new();
dcdca296
MA		 774 uint64_t free_base = start;
775 int i;
776
777 g_ptr_array_sort(ranges, crs_range_compare);
778 for (i = 0; i < ranges->len; i++) {
779 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
780
781 if (free_base < used->base) {
782 crs_range_insert(free_ranges, free_base, used->base - 1);
783 }
784
785 free_base = used->limit + 1;
786 }
787
788 if (free_base < end) {
789 crs_range_insert(free_ranges, free_base, end);
790 }
791
792 g_ptr_array_set_size(ranges, 0);
793 for (i = 0; i < free_ranges->len; i++) {
794 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
795 }
796
354fb471 797 g_ptr_array_free(free_ranges, true);
dcdca296
MA		 798}
799
d7fd0e69
MA		 800/*
801 * crs_range_merge - merges adjacent ranges in the given array.
802 * Array elements are deleted and replaced with the merged ranges.
803 */
804static void crs_range_merge(GPtrArray *range)
805{
806 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
807 CrsRangeEntry *entry;
808 uint64_t range_base, range_limit;
809 int i;
810
811 if (!range->len) {
812 return;
813 }
814
815 g_ptr_array_sort(range, crs_range_compare);
816
817 entry = g_ptr_array_index(range, 0);
818 range_base = entry->base;
819 range_limit = entry->limit;
820 for (i = 1; i < range->len; i++) {
821 entry = g_ptr_array_index(range, i);
822 if (entry->base - 1 == range_limit) {
823 range_limit = entry->limit;
824 } else {
825 crs_range_insert(tmp, range_base, range_limit);
826 range_base = entry->base;
827 range_limit = entry->limit;
828 }
829 }
830 crs_range_insert(tmp, range_base, range_limit);
831
832 g_ptr_array_set_size(range, 0);
833 for (i = 0; i < tmp->len; i++) {
834 entry = g_ptr_array_index(tmp, i);
835 crs_range_insert(range, entry->base, entry->limit);
836 }
837 g_ptr_array_free(tmp, true);
838}
839
2df5a7b5 840static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
a43c6e27
MA		 841{
842 Aml *crs = aml_resource_template();
2df5a7b5 843 CrsRangeSet temp_range_set;
d7fd0e69 844 CrsRangeEntry *entry;
a43c6e27
MA		 845 uint8_t max_bus = pci_bus_num(host->bus);
846 uint8_t type;
847 int devfn;
d7fd0e69 848 int i;
a43c6e27 849
2df5a7b5 850 crs_range_set_init(&temp_range_set);
a43c6e27 851 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
a43c6e27
MA		 852 uint64_t range_base, range_limit;
853 PCIDevice *dev = host->bus->devices[devfn];
854
855 if (!dev) {
856 continue;
857 }
858
859 for (i = 0; i < PCI_NUM_REGIONS; i++) {
860 PCIIORegion *r = &dev->io_regions[i];
861
862 range_base = r->addr;
863 range_limit = r->addr + r->size - 1;
864
0f6dd8e1
MA		 865 /*
866 * Work-around for old bioses
867 * that do not support multiple root buses
868 */
869 if (!range_base || range_base > range_limit) {
870 continue;
871 }
872
a43c6e27 873 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
2df5a7b5
MA		 874 crs_range_insert(temp_range_set.io_ranges,
875 range_base, range_limit);
a43c6e27 876 } else { /* "memory" */
2df5a7b5
MA		 877 crs_range_insert(temp_range_set.mem_ranges,
878 range_base, range_limit);
a43c6e27
MA		 879 }
880 }
881
882 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
883 if (type == PCI_HEADER_TYPE_BRIDGE) {
884 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
885 if (subordinate > max_bus) {
886 max_bus = subordinate;
887 }
888
889 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
890 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
0f6dd8e1
MA		 891
892 /*
893 * Work-around for old bioses
894 * that do not support multiple root buses
895 */
4ebc736e 896 if (range_base && range_base <= range_limit) {
2df5a7b5
MA		 897 crs_range_insert(temp_range_set.io_ranges,
898 range_base, range_limit);
0f6dd8e1 899 }
a43c6e27
MA		 900
901 range_base =
902 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
903 range_limit =
904 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
0f6dd8e1
MA		 905
906 /*
907 * Work-around for old bioses
908 * that do not support multiple root buses
909 */
4ebc736e 910 if (range_base && range_base <= range_limit) {
16de88a4
MA		 911 uint64_t length = range_limit - range_base + 1;
912 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
913 crs_range_insert(temp_range_set.mem_ranges,
914 range_base, range_limit);
915 } else {
916 crs_range_insert(temp_range_set.mem_64bit_ranges,
917 range_base, range_limit);
918 }
4ebc736e 919 }
a43c6e27
MA		 920
921 range_base =
922 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
923 range_limit =
924 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
0f6dd8e1
MA		 925
926 /*
927 * Work-around for old bioses
928 * that do not support multiple root buses
929 */
4ebc736e 930 if (range_base && range_base <= range_limit) {
16de88a4
MA		 931 uint64_t length = range_limit - range_base + 1;
932 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
933 crs_range_insert(temp_range_set.mem_ranges,
934 range_base, range_limit);
935 } else {
936 crs_range_insert(temp_range_set.mem_64bit_ranges,
937 range_base, range_limit);
938 }
0f6dd8e1 939 }
a43c6e27
MA		 940 }
941 }
942
2df5a7b5
MA		 943 crs_range_merge(temp_range_set.io_ranges);
944 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
945 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
d7fd0e69
MA		 946 aml_append(crs,
947 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
948 AML_POS_DECODE, AML_ENTIRE_RANGE,
949 0, entry->base, entry->limit, 0,
950 entry->limit - entry->base + 1));
2df5a7b5 951 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
d7fd0e69 952 }
d7fd0e69 953
2df5a7b5
MA		 954 crs_range_merge(temp_range_set.mem_ranges);
955 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
956 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
d7fd0e69
MA		 957 aml_append(crs,
958 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
959 AML_MAX_FIXED, AML_NON_CACHEABLE,
960 AML_READ_WRITE,
961 0, entry->base, entry->limit, 0,
962 entry->limit - entry->base + 1));
2df5a7b5 963 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
d7fd0e69 964 }
2df5a7b5 965
16de88a4
MA		 966 crs_range_merge(temp_range_set.mem_64bit_ranges);
967 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
968 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
969 aml_append(crs,
970 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
971 AML_MAX_FIXED, AML_NON_CACHEABLE,
972 AML_READ_WRITE,
973 0, entry->base, entry->limit, 0,
974 entry->limit - entry->base + 1));
975 crs_range_insert(range_set->mem_64bit_ranges,
976 entry->base, entry->limit);
977 }
978
2df5a7b5 979 crs_range_set_free(&temp_range_set);
d7fd0e69 980
a43c6e27 981 aml_append(crs,
dcdca296 982 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
a43c6e27
MA		 983 0,
984 pci_bus_num(host->bus),
985 max_bus,
986 0,
987 max_bus - pci_bus_num(host->bus) + 1));
988
989 return crs;
990}
991
a57d708d
IM		 992static void build_hpet_aml(Aml *table)
993{
994 Aml *crs;
995 Aml *field;
996 Aml *method;
997 Aml *if_ctx;
998 Aml *scope = aml_scope("_SB");
999 Aml *dev = aml_device("HPET");
1000 Aml *zero = aml_int(0);
1001 Aml *id = aml_local(0);
1002 Aml *period = aml_local(1);
1003
1004 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1005 aml_append(dev, aml_name_decl("_UID", zero));
1006
1007 aml_append(dev,
3f3009c0
XG		 1008 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1009 HPET_LEN));
a57d708d
IM		 1010 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1011 aml_append(field, aml_named_field("VEND", 32));
1012 aml_append(field, aml_named_field("PRD", 32));
1013 aml_append(dev, field);
1014
1015 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1016 aml_append(method, aml_store(aml_name("VEND"), id));
1017 aml_append(method, aml_store(aml_name("PRD"), period));
1018 aml_append(method, aml_shiftright(id, aml_int(16), id));
1019 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1020 aml_equal(id, aml_int(0xffff))));
1021 {
1022 aml_append(if_ctx, aml_return(zero));
1023 }
1024 aml_append(method, if_ctx);
1025
1026 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1027 aml_lgreater(period, aml_int(100000000))));
1028 {
1029 aml_append(if_ctx, aml_return(zero));
1030 }
1031 aml_append(method, if_ctx);
1032
1033 aml_append(method, aml_return(aml_int(0x0F)));
1034 aml_append(dev, method);
1035
1036 crs = aml_resource_template();
1037 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1038 aml_append(dev, aml_name_decl("_CRS", crs));
1039
1040 aml_append(scope, dev);
1041 aml_append(table, scope);
1042}
1043
27b9fc54 1044static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
95ed7e97 1045{
27b9fc54
RK		 1046 Aml *dev, *fdi;
1047 uint8_t maxc, maxh, maxs;
1048
1049 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1050
1051 dev = aml_device("FLP%c", 'A' + idx);
1052
1053 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1054
1055 fdi = aml_package(16);
1056 aml_append(fdi, aml_int(idx)); /* Drive Number */
1057 aml_append(fdi,
1058 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1059 /*
1060 * the values below are the limits of the drive, and are thus independent
1061 * of the inserted media
1062 */
1063 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1064 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1065 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1066 /*
1067 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1068 * the drive type, so shall we
1069 */
1070 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1071 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1072 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1073 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1074 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1075 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1076 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1077 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1078 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1079 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1080 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1081
1082 aml_append(dev, aml_name_decl("_FDI", fdi));
1083 return dev;
1084}
1085
1086static Aml *build_fdc_device_aml(ISADevice *fdc)
1087{
1088 int i;
95ed7e97
IM		 1089 Aml *dev;
1090 Aml *crs;
95ed7e97 1091
27b9fc54
RK		 1092#define ACPI_FDE_MAX_FD 4
1093 uint32_t fde_buf[5] = {
1094 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1095 cpu_to_le32(2) /* tape presence (2 == never present) */
1096 };
1097
95ed7e97
IM		 1098 dev = aml_device("FDC0");
1099 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1100
95ed7e97
IM		 1101 crs = aml_resource_template();
1102 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1103 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1104 aml_append(crs, aml_irq_no_flags(6));
1105 aml_append(crs,
1106 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1107 aml_append(dev, aml_name_decl("_CRS", crs));
1108
27b9fc54
RK		 1109 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1110 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1111
1112 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1113 fde_buf[i] = cpu_to_le32(1); /* drive present */
1114 aml_append(dev, build_fdinfo_aml(i, type));
1115 }
1116 }
1117 aml_append(dev, aml_name_decl("_FDE",
1118 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1119
95ed7e97
IM		 1120 return dev;
1121}
1122
ee135849
IM		 1123static Aml *build_rtc_device_aml(void)
1124{
1125 Aml *dev;
1126 Aml *crs;
1127
1128 dev = aml_device("RTC");
1129 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1130 crs = aml_resource_template();
1131 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1132 aml_append(crs, aml_irq_no_flags(8));
1133 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
95ed7e97 1134 aml_append(dev, aml_name_decl("_CRS", crs));
f58190e2
IM		 1135
1136 return dev;
1137}
1138
1139static Aml *build_kbd_device_aml(void)
1140{
1141 Aml *dev;
1142 Aml *crs;
1143 Aml *method;
1144
1145 dev = aml_device("KBD");
1146 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1147
1148 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1149 aml_append(method, aml_return(aml_int(0x0f)));
1150 aml_append(dev, method);
1151
1152 crs = aml_resource_template();
1153 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1154 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1155 aml_append(crs, aml_irq_no_flags(1));
ee135849
IM		 1156 aml_append(dev, aml_name_decl("_CRS", crs));
1157
1158 return dev;
1159}
1160
c355cb2c
IM		 1161static Aml *build_mouse_device_aml(void)
1162{
1163 Aml *dev;
1164 Aml *crs;
1165 Aml *method;
1166
1167 dev = aml_device("MOU");
1168 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1169
1170 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1171 aml_append(method, aml_return(aml_int(0x0f)));
1172 aml_append(dev, method);
1173
1174 crs = aml_resource_template();
1175 aml_append(crs, aml_irq_no_flags(12));
1176 aml_append(dev, aml_name_decl("_CRS", crs));
1177
1178 return dev;
1179}
1180
8b1da5f8
IM		 1181static Aml *build_lpt_device_aml(void)
1182{
1183 Aml *dev;
1184 Aml *crs;
1185 Aml *method;
1186 Aml *if_ctx;
1187 Aml *else_ctx;
1188 Aml *zero = aml_int(0);
1189 Aml *is_present = aml_local(0);
1190
1191 dev = aml_device("LPT");
1192 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1193
1194 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1195 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1196 if_ctx = aml_if(aml_equal(is_present, zero));
1197 {
1198 aml_append(if_ctx, aml_return(aml_int(0x00)));
1199 }
1200 aml_append(method, if_ctx);
1201 else_ctx = aml_else();
1202 {
1203 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1204 }
1205 aml_append(method, else_ctx);
1206 aml_append(dev, method);
1207
1208 crs = aml_resource_template();
1209 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1210 aml_append(crs, aml_irq_no_flags(7));
1211 aml_append(dev, aml_name_decl("_CRS", crs));
1212
1213 return dev;
1214}
1215
28f1f0e9
IM		 1216static Aml *build_com_device_aml(uint8_t uid)
1217{
1218 Aml *dev;
1219 Aml *crs;
1220 Aml *method;
1221 Aml *if_ctx;
1222 Aml *else_ctx;
1223 Aml *zero = aml_int(0);
1224 Aml *is_present = aml_local(0);
1225 const char *enabled_field = "CAEN";
1226 uint8_t irq = 4;
1227 uint16_t io_port = 0x03F8;
1228
1229 assert(uid == 1 || uid == 2);
1230 if (uid == 2) {
1231 enabled_field = "CBEN";
1232 irq = 3;
1233 io_port = 0x02F8;
1234 }
1235
1236 dev = aml_device("COM%d", uid);
1237 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1238 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1239
1240 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1241 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1242 if_ctx = aml_if(aml_equal(is_present, zero));
1243 {
1244 aml_append(if_ctx, aml_return(aml_int(0x00)));
1245 }
1246 aml_append(method, if_ctx);
1247 else_ctx = aml_else();
1248 {
1249 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1250 }
1251 aml_append(method, else_ctx);
1252 aml_append(dev, method);
1253
1254 crs = aml_resource_template();
1255 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1256 aml_append(crs, aml_irq_no_flags(irq));
1257 aml_append(dev, aml_name_decl("_CRS", crs));
1258
1259 return dev;
1260}
1261
ee135849
IM		 1262static void build_isa_devices_aml(Aml *table)
1263{
27b9fc54 1264 ISADevice *fdc = pc_find_fdc0();
86e91dd7 1265 bool ambiguous;
27b9fc54 1266
ee135849 1267 Aml *scope = aml_scope("_SB.PCI0.ISA");
86e91dd7 1268 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
ee135849
IM		 1269
1270 aml_append(scope, build_rtc_device_aml());
f58190e2 1271 aml_append(scope, build_kbd_device_aml());
c355cb2c 1272 aml_append(scope, build_mouse_device_aml());
27b9fc54
RK		 1273 if (fdc) {
1274 aml_append(scope, build_fdc_device_aml(fdc));
9b613f4e 1275 }
8b1da5f8 1276 aml_append(scope, build_lpt_device_aml());
28f1f0e9
IM		 1277 aml_append(scope, build_com_device_aml(1));
1278 aml_append(scope, build_com_device_aml(2));
ee135849 1279
86e91dd7
CM		 1280 if (ambiguous) {
1281 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1282 } else if (!obj) {
1283 error_report("No ISA bus, unable to define IPMI ACPI data");
1284 } else {
1285 build_acpi_ipmi_devices(scope, BUS(obj));
1286 }
1287
ee135849
IM		 1288 aml_append(table, scope);
1289}
1290
3892a2b7
IM		 1291static void build_dbg_aml(Aml *table)
1292{
1293 Aml *field;
1294 Aml *method;
1295 Aml *while_ctx;
1296 Aml *scope = aml_scope("\\");
1297 Aml *buf = aml_local(0);
1298 Aml *len = aml_local(1);
1299 Aml *idx = aml_local(2);
1300
1301 aml_append(scope,
3f3009c0 1302 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
3892a2b7
IM		 1303 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1304 aml_append(field, aml_named_field("DBGB", 8));
1305 aml_append(scope, field);
1306
1307 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1308
1309 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1310 aml_append(method, aml_to_buffer(buf, buf));
1311 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1312 aml_append(method, aml_store(aml_int(0), idx));
1313
1314 while_ctx = aml_while(aml_lless(idx, len));
1315 aml_append(while_ctx,
1316 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1317 aml_append(while_ctx, aml_increment(idx));
1318 aml_append(method, while_ctx);
1319
1320 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1321 aml_append(scope, method);
1322
1323 aml_append(table, scope);
1324}
1325
c35b6e80
IM		 1326static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1327{
1328 Aml *dev;
1329 Aml *crs;
1330 Aml *method;
1331 uint32_t irqs[] = {5, 10, 11};
1332
1333 dev = aml_device("%s", name);
1334 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1335 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1336
1337 crs = aml_resource_template();
1338 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1339 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1340 aml_append(dev, aml_name_decl("_PRS", crs));
1341
1342 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1343 aml_append(method, aml_return(aml_call1("IQST", reg)));
1344 aml_append(dev, method);
1345
1346 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1347 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1348 aml_append(dev, method);
1349
1350 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1351 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1352 aml_append(dev, method);
1353
1354 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1355 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1356 aml_append(method, aml_store(aml_name("PRRI"), reg));
1357 aml_append(dev, method);
1358
1359 return dev;
1360 }
1361
80b32df5
IM		 1362static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1363{
1364 Aml *dev;
1365 Aml *crs;
1366 Aml *method;
1367 uint32_t irqs;
1368
1369 dev = aml_device("%s", name);
1370 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1371 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1372
1373 crs = aml_resource_template();
1374 irqs = gsi;
1375 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1376 AML_SHARED, &irqs, 1));
1377 aml_append(dev, aml_name_decl("_PRS", crs));
1378
1379 aml_append(dev, aml_name_decl("_CRS", crs));
1380
c82f503d
MA		 1381 /*
1382 * _DIS can be no-op because the interrupt cannot be disabled.
1383 */
1384 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1385 aml_append(dev, method);
1386
80b32df5
IM		 1387 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1388 aml_append(dev, method);
1389
1390 return dev;
1391}
1392
16682a9d
IM		 1393/* _CRS method - get current settings */
1394static Aml *build_iqcr_method(bool is_piix4)
1395{
1396 Aml *if_ctx;
1397 uint32_t irqs;
1398 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1399 Aml *crs = aml_resource_template();
1400
1401 irqs = 0;
1402 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1403 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1404 aml_append(method, aml_name_decl("PRR0", crs));
1405
1406 aml_append(method,
1407 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1408
1409 if (is_piix4) {
1410 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1411 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1412 aml_append(method, if_ctx);
1413 } else {
1414 aml_append(method,
1415 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1416 aml_name("PRRI")));
1417 }
1418
1419 aml_append(method, aml_return(aml_name("PRR0")));
1420 return method;
1421}
1422
78e1ad05
IM		 1423/* _STA method - get status */
1424static Aml *build_irq_status_method(void)
1425{
1426 Aml *if_ctx;
1427 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1428
1429 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1430 aml_append(if_ctx, aml_return(aml_int(0x09)));
1431 aml_append(method, if_ctx);
1432 aml_append(method, aml_return(aml_int(0x0B)));
1433 return method;
1434}
1435
e4db2798
IM		 1436static void build_piix4_pci0_int(Aml *table)
1437{
c35b6e80
IM		 1438 Aml *dev;
1439 Aml *crs;
e4db2798 1440 Aml *field;
c35b6e80
IM		 1441 Aml *method;
1442 uint32_t irqs;
e4db2798 1443 Aml *sb_scope = aml_scope("_SB");
196e2137
IM		 1444 Aml *pci0_scope = aml_scope("PCI0");
1445
1446 aml_append(pci0_scope, build_prt(true));
1447 aml_append(sb_scope, pci0_scope);
e4db2798
IM		 1448
1449 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1450 aml_append(field, aml_named_field("PRQ0", 8));
1451 aml_append(field, aml_named_field("PRQ1", 8));
1452 aml_append(field, aml_named_field("PRQ2", 8));
1453 aml_append(field, aml_named_field("PRQ3", 8));
1454 aml_append(sb_scope, field);
1455
78e1ad05 1456 aml_append(sb_scope, build_irq_status_method());
16682a9d 1457 aml_append(sb_scope, build_iqcr_method(true));
100681cc 1458
c35b6e80
IM		 1459 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1460 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1461 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1462 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1463
1464 dev = aml_device("LNKS");
1465 {
1466 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1467 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1468
1469 crs = aml_resource_template();
1470 irqs = 9;
1471 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1472 AML_ACTIVE_HIGH, AML_SHARED,
1473 &irqs, 1));
1474 aml_append(dev, aml_name_decl("_PRS", crs));
1475
1476 /* The SCI cannot be disabled and is always attached to GSI 9,
1477 * so these are no-ops. We only need this link to override the
1478 * polarity to active high and match the content of the MADT.
1479 */
1480 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1481 aml_append(method, aml_return(aml_int(0x0b)));
1482 aml_append(dev, method);
1483
1484 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1485 aml_append(dev, method);
1486
1487 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1488 aml_append(method, aml_return(aml_name("_PRS")));
1489 aml_append(dev, method);
1490
1491 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1492 aml_append(dev, method);
1493 }
1494 aml_append(sb_scope, dev);
1495
e4db2798
IM		 1496 aml_append(table, sb_scope);
1497}
1498
22b5b8bf
IM		 1499static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1500{
1501 int i;
1502 int head;
1503 Aml *pkg;
1504 char base = name[3] < 'E' ? 'A' : 'E';
1505 char *s = g_strdup(name);
1506 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1507
1508 assert(strlen(s) == 4);
1509
1510 head = name[3] - base;
1511 for (i = 0; i < 4; i++) {
1512 if (head + i > 3) {
1513 head = i * -1;
1514 }
1515 s[3] = base + head + i;
1516 pkg = aml_package(4);
1517 aml_append(pkg, a_nr);
1518 aml_append(pkg, aml_int(i));
1519 aml_append(pkg, aml_name("%s", s));
1520 aml_append(pkg, aml_int(0));
1521 aml_append(ctx, pkg);
1522 }
1523 g_free(s);
1524}
1525
1526static Aml *build_q35_routing_table(const char *str)
1527{
1528 int i;
1529 Aml *pkg;
1530 char *name = g_strdup_printf("%s ", str);
1531
1532 pkg = aml_package(128);
1533 for (i = 0; i < 0x18; i++) {
1534 name[3] = 'E' + (i & 0x3);
1535 append_q35_prt_entry(pkg, i, name);
1536 }
1537
1538 name[3] = 'E';
1539 append_q35_prt_entry(pkg, 0x18, name);
1540
1541 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1542 for (i = 0x0019; i < 0x1e; i++) {
1543 name[3] = 'A';
1544 append_q35_prt_entry(pkg, i, name);
1545 }
1546
1547 /* PCIe->PCI bridge. use PIRQ[E-H] */
1548 name[3] = 'E';
1549 append_q35_prt_entry(pkg, 0x1e, name);
1550 name[3] = 'A';
1551 append_q35_prt_entry(pkg, 0x1f, name);
1552
1553 g_free(name);
1554 return pkg;
1555}
1556
80b32df5
IM		 1557static void build_q35_pci0_int(Aml *table)
1558{
41f95a52 1559 Aml *field;
0dafe3b3 1560 Aml *method;
80b32df5 1561 Aml *sb_scope = aml_scope("_SB");
0dafe3b3
IM		 1562 Aml *pci0_scope = aml_scope("PCI0");
1563
e9fce798
IM		 1564 /* Zero => PIC mode, One => APIC Mode */
1565 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1566 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1567 {
1568 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1569 }
1570 aml_append(table, method);
1571
65aef4de
IM		 1572 aml_append(pci0_scope,
1573 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
22b5b8bf
IM		 1574 aml_append(pci0_scope,
1575 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1576
0dafe3b3
IM		 1577 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1578 {
1579 Aml *if_ctx;
1580 Aml *else_ctx;
1581
1582 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1583 section 6.2.8.1 */
1584 /* Note: we provide the same info as the PCI routing
1585 table of the Bochs BIOS */
1586 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1587 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1588 aml_append(method, if_ctx);
1589 else_ctx = aml_else();
1590 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1591 aml_append(method, else_ctx);
1592 }
1593 aml_append(pci0_scope, method);
1594 aml_append(sb_scope, pci0_scope);
80b32df5 1595
41f95a52
IM		 1596 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1597 aml_append(field, aml_named_field("PRQA", 8));
1598 aml_append(field, aml_named_field("PRQB", 8));
1599 aml_append(field, aml_named_field("PRQC", 8));
1600 aml_append(field, aml_named_field("PRQD", 8));
1601 aml_append(field, aml_reserved_field(0x20));
1602 aml_append(field, aml_named_field("PRQE", 8));
1603 aml_append(field, aml_named_field("PRQF", 8));
1604 aml_append(field, aml_named_field("PRQG", 8));
1605 aml_append(field, aml_named_field("PRQH", 8));
1606 aml_append(sb_scope, field);
1607
78e1ad05 1608 aml_append(sb_scope, build_irq_status_method());
16682a9d
IM		 1609 aml_append(sb_scope, build_iqcr_method(false));
1610
12e3b1f7
IM		 1611 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1612 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1613 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1614 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1615 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1616 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1617 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1618 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1619
6a991e07
MA		 1620 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1621 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1622 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1623 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1624 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1625 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1626 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1627 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
80b32df5
IM		 1628
1629 aml_append(table, sb_scope);
1630}
1631
41f95a52
IM		 1632static void build_q35_isa_bridge(Aml *table)
1633{
1634 Aml *dev;
1635 Aml *scope;
1636 Aml *field;
1637
1638 scope = aml_scope("_SB.PCI0");
1639 dev = aml_device("ISA");
1640 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1641
1642 /* ICH9 PCI to ISA irq remapping */
1643 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
3f3009c0 1644 aml_int(0x60), 0x0C));
41f95a52
IM		 1645
1646 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
3f3009c0 1647 aml_int(0x80), 0x02));
41f95a52
IM		 1648 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1649 aml_append(field, aml_named_field("COMA", 3));
1650 aml_append(field, aml_reserved_field(1));
1651 aml_append(field, aml_named_field("COMB", 3));
1652 aml_append(field, aml_reserved_field(1));
1653 aml_append(field, aml_named_field("LPTD", 2));
41f95a52
IM		 1654 aml_append(dev, field);
1655
1656 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
3f3009c0 1657 aml_int(0x82), 0x02));
41f95a52
IM		 1658 /* enable bits */
1659 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1660 aml_append(field, aml_named_field("CAEN", 1));
1661 aml_append(field, aml_named_field("CBEN", 1));
1662 aml_append(field, aml_named_field("LPEN", 1));
41f95a52
IM		 1663 aml_append(dev, field);
1664
1665 aml_append(scope, dev);
1666 aml_append(table, scope);
1667}
1668
e4db2798
IM		 1669static void build_piix4_pm(Aml *table)
1670{
1671 Aml *dev;
1672 Aml *scope;
1673
1674 scope = aml_scope("_SB.PCI0");
1675 dev = aml_device("PX13");
1676 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1677
1678 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
3f3009c0 1679 aml_int(0x00), 0xff));
e4db2798
IM		 1680 aml_append(scope, dev);
1681 aml_append(table, scope);
1682}
1683
1684static void build_piix4_isa_bridge(Aml *table)
1685{
1686 Aml *dev;
1687 Aml *scope;
1688 Aml *field;
1689
1690 scope = aml_scope("_SB.PCI0");
1691 dev = aml_device("ISA");
1692 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1693
1694 /* PIIX PCI to ISA irq remapping */
1695 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
3f3009c0 1696 aml_int(0x60), 0x04));
e4db2798
IM		 1697 /* enable bits */
1698 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1699 /* Offset(0x5f),, 7, */
1700 aml_append(field, aml_reserved_field(0x2f8));
1701 aml_append(field, aml_reserved_field(7));
1702 aml_append(field, aml_named_field("LPEN", 1));
1703 /* Offset(0x67),, 3, */
1704 aml_append(field, aml_reserved_field(0x38));
1705 aml_append(field, aml_reserved_field(3));
1706 aml_append(field, aml_named_field("CAEN", 1));
1707 aml_append(field, aml_reserved_field(3));
1708 aml_append(field, aml_named_field("CBEN", 1));
1709 aml_append(dev, field);
e4db2798
IM		 1710
1711 aml_append(scope, dev);
1712 aml_append(table, scope);
1713}
1714
b616ec4d
IM		 1715static void build_piix4_pci_hotplug(Aml *table)
1716{
1717 Aml *scope;
1718 Aml *field;
1719 Aml *method;
1720
1721 scope = aml_scope("_SB.PCI0");
1722
1723 aml_append(scope,
3f3009c0 1724 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
b616ec4d
IM		 1725 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1726 aml_append(field, aml_named_field("PCIU", 32));
1727 aml_append(field, aml_named_field("PCID", 32));
1728 aml_append(scope, field);
1729
1730 aml_append(scope,
3f3009c0 1731 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
b616ec4d
IM		 1732 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1733 aml_append(field, aml_named_field("B0EJ", 32));
1734 aml_append(scope, field);
1735
1736 aml_append(scope,
3f3009c0 1737 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
b616ec4d
IM		 1738 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1739 aml_append(field, aml_named_field("BNUM", 32));
1740 aml_append(scope, field);
1741
1742 aml_append(scope, aml_mutex("BLCK", 0));
1743
1744 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1745 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1746 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1747 aml_append(method,
1748 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1749 aml_append(method, aml_release(aml_name("BLCK")));
1750 aml_append(method, aml_return(aml_int(0)));
1751 aml_append(scope, method);
1752
1753 aml_append(table, scope);
1754}
1755
f97a88a8
IM		 1756static Aml *build_q35_osc_method(void)
1757{
1758 Aml *if_ctx;
1759 Aml *if_ctx2;
1760 Aml *else_ctx;
1761 Aml *method;
1762 Aml *a_cwd1 = aml_name("CDW1");
b3c782db 1763 Aml *a_ctrl = aml_local(0);
f97a88a8
IM		 1764
1765 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1766 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1767
1768 if_ctx = aml_if(aml_equal(
1769 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1770 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1771 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1772
f97a88a8
IM		 1773 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1774
1775 /*
1776 * Always allow native PME, AER (no dependencies)
a41c78c1 1777 * Allow SHPC (PCI bridges can have SHPC controller)
f97a88a8 1778 */
a41c78c1 1779 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
f97a88a8
IM		 1780
1781 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1782 /* Unknown revision */
1783 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1784 aml_append(if_ctx, if_ctx2);
1785
1786 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1787 /* Capabilities bits were masked */
1788 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1789 aml_append(if_ctx, if_ctx2);
1790
1791 /* Update DWORD3 in the buffer */
1792 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1793 aml_append(method, if_ctx);
1794
1795 else_ctx = aml_else();
1796 /* Unrecognized UUID */
1797 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1798 aml_append(method, else_ctx);
1799
1800 aml_append(method, aml_return(aml_arg(3)));
1801 return method;
1802}
b616ec4d 1803
72c194f7 1804static void
0e9b9eda 1805build_dsdt(GArray *table_data, BIOSLinker *linker,
adcb89d5 1806 AcpiPmInfo *pm, AcpiMiscInfo *misc,
01c9742d 1807 Range *pci_hole, Range *pci_hole64, MachineState *machine)
72c194f7 1808{
41fa5c04
IM		 1809 CrsRangeEntry *entry;
1810 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
2df5a7b5 1811 CrsRangeSet crs_range_set;
fb306ffe 1812 PCMachineState *pcms = PC_MACHINE(machine);
679dd1a9 1813 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
bef3492d 1814 uint32_t nr_mem = machine->ram_slots;
dcdca296 1815 int root_bus_limit = 0xFF;
41fa5c04 1816 PCIBus *bus = NULL;
ac6dd31e 1817 TPMIf *tpm = tpm_find();
72c194f7
MT		 1818 int i;
1819
41fa5c04 1820 dsdt = init_aml_allocator();
2fd71f1b 1821
4ec8d2b3 1822 /* Reserve space for header */
41fa5c04
IM		 1823 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1824
1825 build_dbg_aml(dsdt);
1826 if (misc->is_piix4) {
1827 sb_scope = aml_scope("_SB");
1828 dev = aml_device("PCI0");
1829 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1830 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1831 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1832 aml_append(sb_scope, dev);
1833 aml_append(dsdt, sb_scope);
1834
1835 build_hpet_aml(dsdt);
1836 build_piix4_pm(dsdt);
1837 build_piix4_isa_bridge(dsdt);
1838 build_isa_devices_aml(dsdt);
1839 build_piix4_pci_hotplug(dsdt);
1840 build_piix4_pci0_int(dsdt);
1841 } else {
41fa5c04
IM		 1842 sb_scope = aml_scope("_SB");
1843 dev = aml_device("PCI0");
1844 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1845 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1846 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1847 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
41fa5c04
IM		 1848 aml_append(dev, build_q35_osc_method());
1849 aml_append(sb_scope, dev);
1850 aml_append(dsdt, sb_scope);
1851
1852 build_hpet_aml(dsdt);
1853 build_q35_isa_bridge(dsdt);
1854 build_isa_devices_aml(dsdt);
1855 build_q35_pci0_int(dsdt);
1856 }
1857
679dd1a9
IM		 1858 if (pcmc->legacy_cpu_hotplug) {
1859 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1860 } else {
1861 CPUHotplugFeatures opts = {
89cb0c04 1862 .acpi_1_compatible = true, .has_legacy_cphp = true
679dd1a9
IM		 1863 };
1864 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1865 "\\_SB.PCI0", "\\_GPE._E02");
1866 }
80db0e78 1867 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03");
41fa5c04
IM		 1868
1869 scope = aml_scope("_GPE");
1870 {
1871 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1872
41fa5c04
IM		 1873 if (misc->is_piix4) {
1874 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1875 aml_append(method,
1876 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1877 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1878 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1879 aml_append(scope, method);
41fa5c04
IM		 1880 }
1881
f6a0d06b 1882 if (machine->nvdimms_state->is_enabled) {
b097cc52
XG		 1883 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1884 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1885 aml_int(0x80)));
1886 aml_append(scope, method);
1887 }
41fa5c04
IM		 1888 }
1889 aml_append(dsdt, scope);
72c194f7 1890
2df5a7b5 1891 crs_range_set_init(&crs_range_set);
81ed6482 1892 bus = PC_MACHINE(machine)->bus;
a4894206
MA		 1893 if (bus) {
1894 QLIST_FOREACH(bus, &bus->child, sibling) {
1895 uint8_t bus_num = pci_bus_num(bus);
0e79e51a 1896 uint8_t numa_node = pci_bus_numa_node(bus);
a4894206
MA		 1897
1898 /* look only for expander root buses */
1899 if (!pci_bus_is_root(bus)) {
1900 continue;
1901 }
1902
dcdca296
MA		 1903 if (bus_num < root_bus_limit) {
1904 root_bus_limit = bus_num - 1;
1905 }
1906
a4894206
MA		 1907 scope = aml_scope("\\_SB");
1908 dev = aml_device("PC%.02X", bus_num);
c96d9286
LE		 1909 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1910 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
a4894206 1911 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
077dd742
MA		 1912 if (pci_bus_is_express(bus)) {
1913 aml_append(dev, build_q35_osc_method());
1914 }
0e79e51a
MA		 1915
1916 if (numa_node != NUMA_NODE_UNASSIGNED) {
1917 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1918 }
1919
196e2137 1920 aml_append(dev, build_prt(false));
2df5a7b5 1921 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
a43c6e27 1922 aml_append(dev, aml_name_decl("_CRS", crs));
a4894206 1923 aml_append(scope, dev);
41fa5c04 1924 aml_append(dsdt, scope);
a4894206
MA		 1925 }
1926 }
1927
500b11ea 1928 scope = aml_scope("\\_SB.PCI0");
60efd429
IM		 1929 /* build PCI0._CRS */
1930 crs = aml_resource_template();
1931 aml_append(crs,
ff80dc7f 1932 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
dcdca296
MA		 1933 0x0000, 0x0, root_bus_limit,
1934 0x0000, root_bus_limit + 1));
ff80dc7f 1935 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
60efd429
IM		 1936
1937 aml_append(crs,
ff80dc7f
SZ		 1938 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1939 AML_POS_DECODE, AML_ENTIRE_RANGE,
60efd429 1940 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
dcdca296 1941
2df5a7b5
MA		 1942 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1943 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1944 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
dcdca296
MA		 1945 aml_append(crs,
1946 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1947 AML_POS_DECODE, AML_ENTIRE_RANGE,
1948 0x0000, entry->base, entry->limit,
1949 0x0000, entry->limit - entry->base + 1));
1950 }
1951
60efd429 1952 aml_append(crs,
ff80dc7f
SZ		 1953 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1954 AML_CACHEABLE, AML_READ_WRITE,
60efd429 1955 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
dcdca296 1956
2df5a7b5 1957 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
a0efbf16
MA		 1958 range_lob(pci_hole),
1959 range_upb(pci_hole));
2df5a7b5
MA		 1960 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1961 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
dcdca296
MA		 1962 aml_append(crs,
1963 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1964 AML_NON_CACHEABLE, AML_READ_WRITE,
1965 0, entry->base, entry->limit,
1966 0, entry->limit - entry->base + 1));
1967 }
1968
a0efbf16 1969 if (!range_is_empty(pci_hole64)) {
16de88a4
MA		 1970 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1971 range_lob(pci_hole64),
1972 range_upb(pci_hole64));
1973 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1974 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1975 aml_append(crs,
1976 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1977 AML_MAX_FIXED,
1978 AML_CACHEABLE, AML_READ_WRITE,
1979 0, entry->base, entry->limit,
1980 0, entry->limit - entry->base + 1));
1981 }
60efd429 1982 }
2b1c2e8e 1983
ff5ce21e 1984 if (TPM_IS_TIS(tpm_find())) {
2b1c2e8e
IM		 1985 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1986 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1987 }
60efd429
IM		 1988 aml_append(scope, aml_name_decl("_CRS", crs));
1989
d31c909e
IM		 1990 /* reserve GPE0 block resources */
1991 dev = aml_device("GPE0");
1992 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1993 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1994 /* device present, functioning, decoding, not shown in UI */
1995 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1996 crs = aml_resource_template();
1997 aml_append(crs,
937d1b58
IM		 1998 aml_io(
1999 AML_DECODE16,
2000 pm->fadt.gpe0_blk.address,
2001 pm->fadt.gpe0_blk.address,
2002 1,
2003 pm->fadt.gpe0_blk.bit_width / 8)
d31c909e
IM		 2004 );
2005 aml_append(dev, aml_name_decl("_CRS", crs));
2006 aml_append(scope, dev);
2007
2df5a7b5 2008 crs_range_set_free(&crs_range_set);
dcdca296 2009
500b11ea
IM		 2010 /* reserve PCIHP resources */
2011 if (pm->pcihp_io_len) {
2012 dev = aml_device("PHPR");
2013 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2014 aml_append(dev,
2015 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2016 /* device present, functioning, decoding, not shown in UI */
2017 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2018 crs = aml_resource_template();
2019 aml_append(crs,
ff80dc7f 2020 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
500b11ea
IM		 2021 pm->pcihp_io_len)
2022 );
2023 aml_append(dev, aml_name_decl("_CRS", crs));
2024 aml_append(scope, dev);
2025 }
41fa5c04 2026 aml_append(dsdt, scope);
500b11ea 2027
ebc3028f
IM		 2028 /* create S3_ / S4_ / S5_ packages if necessary */
2029 scope = aml_scope("\\");
2030 if (!pm->s3_disabled) {
2031 pkg = aml_package(4);
2032 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2033 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2034 aml_append(pkg, aml_int(0)); /* reserved */
2035 aml_append(pkg, aml_int(0)); /* reserved */
2036 aml_append(scope, aml_name_decl("_S3", pkg));
2037 }
2038
2039 if (!pm->s4_disabled) {
2040 pkg = aml_package(4);
2041 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2042 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2043 aml_append(pkg, aml_int(pm->s4_val));
2044 aml_append(pkg, aml_int(0)); /* reserved */
2045 aml_append(pkg, aml_int(0)); /* reserved */
2046 aml_append(scope, aml_name_decl("_S4", pkg));
2047 }
2048
2049 pkg = aml_package(4);
2050 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2051 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2052 aml_append(pkg, aml_int(0)); /* reserved */
2053 aml_append(pkg, aml_int(0)); /* reserved */
2054 aml_append(scope, aml_name_decl("_S5", pkg));
41fa5c04 2055 aml_append(dsdt, scope);
ebc3028f 2056
e2ec7568
GS		 2057 /* create fw_cfg node, unconditionally */
2058 {
2059 /* when using port i/o, the 8-bit data register *always* overlaps
2060 * with half of the 16-bit control register. Hence, the total size
2061 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2062 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2063 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2064 "dma_enabled", NULL) ?
2065 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2066 FW_CFG_CTL_SIZE;
2067
2068 scope = aml_scope("\\_SB.PCI0");
2069 dev = aml_device("FWCF");
2070
2071 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2072
2073 /* device present, functioning, decoding, not shown in UI */
2074 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2075
2076 crs = aml_resource_template();
2077 aml_append(crs,
2078 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2079 );
2080 aml_append(dev, aml_name_decl("_CRS", crs));
2081
2082 aml_append(scope, dev);
2083 aml_append(dsdt, scope);
2084 }
2085
8ac6f7a6
IM		 2086 if (misc->applesmc_io_base) {
2087 scope = aml_scope("\\_SB.PCI0.ISA");
2088 dev = aml_device("SMC");
2089
2090 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2091 /* device present, functioning, decoding, not shown in UI */
2092 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2093
2094 crs = aml_resource_template();
2095 aml_append(crs,
ff80dc7f 2096 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
8ac6f7a6
IM		 2097 0x01, APPLESMC_MAX_DATA_LENGTH)
2098 );
2099 aml_append(crs, aml_irq_no_flags(6));
2100 aml_append(dev, aml_name_decl("_CRS", crs));
2101
2102 aml_append(scope, dev);
41fa5c04 2103 aml_append(dsdt, scope);
8ac6f7a6
IM		 2104 }
2105
cd61cb2e
IM		 2106 if (misc->pvpanic_port) {
2107 scope = aml_scope("\\_SB.PCI0.ISA");
2108
2332333c 2109 dev = aml_device("PEVT");
e65bef69 2110 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
cd61cb2e
IM		 2111
2112 crs = aml_resource_template();
2113 aml_append(crs,
ff80dc7f 2114 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
cd61cb2e
IM		 2115 );
2116 aml_append(dev, aml_name_decl("_CRS", crs));
2117
ff80dc7f 2118 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
3f3009c0 2119 aml_int(misc->pvpanic_port), 1));
36de884a 2120 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
cd61cb2e
IM		 2121 aml_append(field, aml_named_field("PEPT", 8));
2122 aml_append(dev, field);
2123
8ef3ea25
GH		 2124 /* device present, functioning, decoding, shown in UI */
2125 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2332333c 2126
4dbfc881 2127 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
cd61cb2e
IM		 2128 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2129 aml_append(method, aml_return(aml_local(0)));
2130 aml_append(dev, method);
2131
4dbfc881 2132 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
cd61cb2e
IM		 2133 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2134 aml_append(dev, method);
2135
2136 aml_append(scope, dev);
41fa5c04 2137 aml_append(dsdt, scope);
cd61cb2e
IM		 2138 }
2139
7824df38 2140 sb_scope = aml_scope("\\_SB");
72c194f7 2141 {
8b35ab27
IM		 2142 Object *pci_host;
2143 PCIBus *bus = NULL;
8698c0c0 2144
8b35ab27
IM		 2145 pci_host = acpi_get_i386_pci_host();
2146 if (pci_host) {
2147 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2148 }
8dcf525a 2149
8b35ab27
IM		 2150 if (bus) {
2151 Aml *scope = aml_scope("PCI0");
2152 /* Scan all PCI buses. Generate tables to support hotplug. */
2153 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2154
ac6dd31e 2155 if (TPM_IS_TIS(tpm)) {
24cf5413
SB		 2156 if (misc->tpm_version == TPM_VERSION_2_0) {
2157 dev = aml_device("TPM");
2158 aml_append(dev, aml_name_decl("_HID",
2159 aml_string("MSFT0101")));
2160 } else {
2161 dev = aml_device("ISA.TPM");
2162 aml_append(dev, aml_name_decl("_HID",
2163 aml_eisaid("PNP0C31")));
2164 }
2165
8b35ab27
IM		 2166 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2167 crs = aml_resource_template();
2168 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2169 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2170 /*
2171 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2172 Rewrite to take IRQ from TPM device model and
2173 fix default IRQ value there to use some unused IRQ
2174 */
2175 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2176 aml_append(dev, aml_name_decl("_CRS", crs));
ac6dd31e
SB		 2177
2178 tpm_build_ppi_acpi(tpm, dev);
2179
8b35ab27 2180 aml_append(scope, dev);
8dcf525a 2181 }
72c194f7 2182
8b35ab27 2183 aml_append(sb_scope, scope);
72c194f7 2184 }
72c194f7 2185 }
4ab6cb4c 2186
ac6dd31e 2187 if (TPM_IS_CRB(tpm)) {
4ab6cb4c
MAL		 2188 dev = aml_device("TPM");
2189 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
2190 crs = aml_resource_template();
2191 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
2192 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
2193 aml_append(dev, aml_name_decl("_CRS", crs));
2194
2195 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
2196 aml_append(method, aml_return(aml_int(0x0f)));
2197 aml_append(dev, method);
2198
ac6dd31e
SB		 2199 tpm_build_ppi_acpi(tpm, dev);
2200
4ab6cb4c
MAL		 2201 aml_append(sb_scope, dev);
2202 }
2203
8b35ab27 2204 aml_append(dsdt, sb_scope);
72c194f7 2205
011bb749 2206 /* copy AML table into ACPI tables blob and patch header there */
41fa5c04 2207 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
72c194f7 2208 build_header(linker, table_data,
41fa5c04 2209 (void *)(table_data->data + table_data->len - dsdt->buf->len),
37ad223c 2210 "DSDT", dsdt->buf->len, 1, NULL, NULL);
011bb749 2211 free_aml_allocator();
72c194f7
MT		 2212}
2213
2214static void
0e9b9eda 2215build_hpet(GArray *table_data, BIOSLinker *linker)
72c194f7
MT		 2216{
2217 Acpi20Hpet *hpet;
2218
2219 hpet = acpi_data_push(table_data, sizeof(*hpet));
2220 /* Note timer_block_id value must be kept in sync with value advertised by
2221 * emulated hpet
2222 */
2223 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2224 hpet->addr.address = cpu_to_le64(HPET_BASE);
2225 build_header(linker, table_data,
37ad223c 2226 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
72c194f7
MT		 2227}
2228
711b20b4 2229static void
0e9b9eda 2230build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
711b20b4
SB		 2231{
2232 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
4678124b
IM		 2233 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2234 unsigned log_addr_offset =
2235 (char *)&tcpa->log_area_start_address - table_data->data;
711b20b4
SB		 2236
2237 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2238 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
9774ccf7 2239 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
711b20b4 2240
ad9671b8 2241 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
42a5b308
SB		 2242 false /* high memory */);
2243
711b20b4 2244 /* log area start address to be filled by Guest linker */
4678124b
IM		 2245 bios_linker_loader_add_pointer(linker,
2246 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2247 ACPI_BUILD_TPMLOG_FILE, 0);
711b20b4
SB		 2248
2249 build_header(linker, table_data,
37ad223c 2250 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
711b20b4
SB		 2251}
2252
5cb18b3d 2253static void
4a42fa0e 2254build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
5cb18b3d 2255{
4a42fa0e
SB		 2256 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2257 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
2258 unsigned log_addr_offset =
2259 (char *)&tpm2_ptr->log_area_start_address - table_data->data;
5cb18b3d
SB		 2260
2261 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
ff5ce21e
MAL		 2262 if (TPM_IS_TIS(tpm_find())) {
2263 tpm2_ptr->control_area_address = cpu_to_le64(0);
2264 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
4ab6cb4c
MAL		 2265 } else if (TPM_IS_CRB(tpm_find())) {
2266 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL);
2267 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB);
ff5ce21e
MAL		 2268 } else {
2269 g_warn_if_reached();
2270 }
5cb18b3d 2271
4ab6cb4c
MAL		 2272 tpm2_ptr->log_area_minimum_length =
2273 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2274
2275 /* log area start address to be filled by Guest linker */
2276 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2277 log_addr_offset, log_addr_size,
2278 ACPI_BUILD_TPMLOG_FILE, 0);
5cb18b3d 2279 build_header(linker, table_data,
37ad223c 2280 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
5cb18b3d
SB		 2281}
2282
d471bf3e
PB		 2283#define HOLE_640K_START (640 * KiB)
2284#define HOLE_640K_END (1 * MiB)
4926403c 2285
72c194f7 2286static void
0e9b9eda 2287build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
72c194f7
MT		 2288{
2289 AcpiSystemResourceAffinityTable *srat;
72c194f7
MT		 2290 AcpiSratMemoryAffinity *numamem;
2291
2292 int i;
72c194f7
MT		 2293 int srat_start, numa_start, slots;
2294 uint64_t mem_len, mem_base, next_base;
5803fce3 2295 MachineClass *mc = MACHINE_GET_CLASS(machine);
80e5db30 2296 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
3d3ebcad 2297 PCMachineState *pcms = PC_MACHINE(machine);
cec65193 2298 ram_addr_t hotplugabble_address_space_size =
f2ffbe2b 2299 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
cec65193 2300 NULL);
72c194f7
MT		 2301
2302 srat_start = table_data->len;
2303
2304 srat = acpi_data_push(table_data, sizeof *srat);
2305 srat->reserved1 = cpu_to_le32(1);
72c194f7 2306
5803fce3 2307 for (i = 0; i < apic_ids->len; i++) {
d41f3e75 2308 int node_id = apic_ids->cpus[i].props.node_id;
5eff33a2 2309 uint32_t apic_id = apic_ids->cpus[i].arch_id;
5803fce3 2310
5eff33a2
IM		 2311 if (apic_id < 255) {
2312 AcpiSratProcessorAffinity *core;
2313
2314 core = acpi_data_push(table_data, sizeof *core);
2315 core->type = ACPI_SRAT_PROCESSOR_APIC;
2316 core->length = sizeof(*core);
2317 core->local_apic_id = apic_id;
ea265072 2318 core->proximity_lo = node_id;
5eff33a2
IM		 2319 memset(core->proximity_hi, 0, 3);
2320 core->local_sapic_eid = 0;
2321 core->flags = cpu_to_le32(1);
2322 } else {
2323 AcpiSratProcessorX2ApicAffinity *core;
2324
2325 core = acpi_data_push(table_data, sizeof *core);
2326 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2327 core->length = sizeof(*core);
2328 core->x2apic_id = cpu_to_le32(apic_id);
ea265072 2329 core->proximity_domain = cpu_to_le32(node_id);
5eff33a2 2330 core->flags = cpu_to_le32(1);
1f3aba37 2331 }
72c194f7
MT		 2332 }
2333
2334
2335 /* the memory map is a bit tricky, it contains at least one hole
2336 * from 640k-1M and possibly another one from 3.5G-4G.
2337 */
2338 next_base = 0;
2339 numa_start = table_data->len;
2340
dd4c2f01 2341 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
72c194f7 2342 mem_base = next_base;
dd4c2f01 2343 mem_len = pcms->node_mem[i - 1];
72c194f7
MT		 2344 next_base = mem_base + mem_len;
2345
4926403c
EH		 2346 /* Cut out the 640K hole */
2347 if (mem_base <= HOLE_640K_START &&
2348 next_base > HOLE_640K_START) {
2349 mem_len -= next_base - HOLE_640K_START;
2350 if (mem_len > 0) {
2351 numamem = acpi_data_push(table_data, sizeof *numamem);
2352 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2353 MEM_AFFINITY_ENABLED);
2354 }
2355
2356 /* Check for the rare case: 640K < RAM < 1M */
2357 if (next_base <= HOLE_640K_END) {
2358 next_base = HOLE_640K_END;
2359 continue;
2360 }
2361 mem_base = HOLE_640K_END;
2362 mem_len = next_base - HOLE_640K_END;
2363 }
2364
72c194f7 2365 /* Cut out the ACPI_PCI hole */
5299f1c7
EH		 2366 if (mem_base <= pcms->below_4g_mem_size &&
2367 next_base > pcms->below_4g_mem_size) {
2368 mem_len -= next_base - pcms->below_4g_mem_size;
72c194f7
MT		 2369 if (mem_len > 0) {
2370 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136
SZ		 2371 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2372 MEM_AFFINITY_ENABLED);
72c194f7
MT		 2373 }
2374 mem_base = 1ULL << 32;
5299f1c7 2375 mem_len = next_base - pcms->below_4g_mem_size;
6cf6fe39 2376 next_base = mem_base + mem_len;
72c194f7 2377 }
16b42263
DL		 2378
2379 if (mem_len > 0) {
2380 numamem = acpi_data_push(table_data, sizeof *numamem);
2381 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2382 MEM_AFFINITY_ENABLED);
2383 }
72c194f7
MT		 2384 }
2385 slots = (table_data->len - numa_start) / sizeof *numamem;
dd4c2f01 2386 for (; slots < pcms->numa_nodes + 2; slots++) {
72c194f7 2387 numamem = acpi_data_push(table_data, sizeof *numamem);
64b83136 2388 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
72c194f7
MT		 2389 }
2390
dbb6da8b
IM		 2391 /*
2392 * Entry is required for Windows to enable memory hotplug in OS
2393 * and for Linux to enable SWIOTLB when booted with less than
2394 * 4G of RAM. Windows works better if the entry sets proximity
2395 * to the highest NUMA node in the machine.
2396 * Memory devices may override proximity set by this entry,
2397 * providing _PXM method if necessary.
2398 */
cec65193 2399 if (hotplugabble_address_space_size) {
dbb6da8b
IM		 2400 numamem = acpi_data_push(table_data, sizeof *numamem);
2401 build_srat_memory(numamem, machine->device_memory->base,
2402 hotplugabble_address_space_size, pcms->numa_nodes - 1,
2403 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
cec65193
IM		 2404 }
2405
72c194f7
MT		 2406 build_header(linker, table_data,
2407 (void *)(table_data->data + srat_start),
821e3227 2408 "SRAT",
37ad223c 2409 table_data->len - srat_start, 1, NULL, NULL);
72c194f7
MT		 2410}
2411
2412static void
0e9b9eda 2413build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
72c194f7
MT		 2414{
2415 AcpiTableMcfg *mcfg;
72c194f7
MT		 2416 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2417
2418 mcfg = acpi_data_push(table_data, len);
2419 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2420 /* Only a single allocation so no need to play with segments */
2421 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2422 mcfg->allocation[0].start_bus_number = 0;
2423 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2424
fe4970ad 2425 build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL, NULL);
72c194f7
MT		 2426}
2427
d46114f9
PX		 2428/*
2429 * VT-d spec 8.1 DMA Remapping Reporting Structure
2430 * (version Oct. 2014 or later)
2431 */
d4eb9119 2432static void
0e9b9eda 2433build_dmar_q35(GArray *table_data, BIOSLinker *linker)
d4eb9119
LT		 2434{
2435 int dmar_start = table_data->len;
2436
2437 AcpiTableDmar *dmar;
2438 AcpiDmarHardwareUnit *drhd;
bd2baacc 2439 AcpiDmarRootPortATS *atsr;
d46114f9
PX		 2440 uint8_t dmar_flags = 0;
2441 X86IOMMUState *iommu = x86_iommu_get_default();
cfc13df4
PX		 2442 AcpiDmarDeviceScope *scope = NULL;
2443 /* Root complex IOAPIC use one path[0] only */
2444 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
37f51384 2445 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
d46114f9
PX		 2446
2447 assert(iommu);
a924b3d8 2448 if (x86_iommu_ir_supported(iommu)) {
d46114f9
PX		 2449 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2450 }
d4eb9119
LT		 2451
2452 dmar = acpi_data_push(table_data, sizeof(*dmar));
37f51384 2453 dmar->host_address_width = intel_iommu->aw_bits - 1;
d46114f9 2454 dmar->flags = dmar_flags;
d4eb9119
LT		 2455
2456 /* DMAR Remapping Hardware Unit Definition structure */
cfc13df4 2457 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
d4eb9119 2458 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
cfc13df4 2459 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
d4eb9119
LT		 2460 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2461 drhd->pci_segment = cpu_to_le16(0);
2462 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2463
cfc13df4
PX		 2464 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2465 * 8.3.1 (version Oct. 2014 or later). */
2466 scope = &drhd->scope[0];
2467 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2468 scope->length = ioapic_scope_size;
2469 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2470 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
1b39bc1c
PX		 2471 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2472 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
cfc13df4 2473
bd2baacc
JW		 2474 if (iommu->dt_supported) {
2475 atsr = acpi_data_push(table_data, sizeof(*atsr));
2476 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2477 atsr->length = cpu_to_le16(sizeof(*atsr));
2478 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2479 atsr->pci_segment = cpu_to_le16(0);
2480 }
2481
d4eb9119 2482 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
37ad223c 2483 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
d4eb9119 2484}
fb9f5926
DK		 2485/*
2486 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2487 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2488 */
c028818d
BS		 2489#define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2490
fb9f5926
DK		 2491static void
2492build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2493{
c028818d 2494 int ivhd_table_len = 28;
fb9f5926
DK		 2495 int iommu_start = table_data->len;
2496 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2497
2498 /* IVRS header */
2499 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2500 /* IVinfo - IO virtualization information common to all
2501 * IOMMU units in a system
2502 */
2503 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2504 /* reserved */
2505 build_append_int_noprefix(table_data, 0, 8);
2506
2507 /* IVHD definition - type 10h */
2508 build_append_int_noprefix(table_data, 0x10, 1);
2509 /* virtualization flags */
2510 build_append_int_noprefix(table_data,
2511 (1UL << 0) | /* HtTunEn */
2512 (1UL << 4) | /* iotblSup */
2513 (1UL << 6) | /* PrefSup */
2514 (1UL << 7), /* PPRSup */
2515 1);
c028818d
BS		 2516
2517 /*
2518 * When interrupt remapping is supported, we add a special IVHD device
2519 * for type IO-APIC.
2520 */
a924b3d8 2521 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
c028818d
BS		 2522 ivhd_table_len += 8;
2523 }
fb9f5926 2524 /* IVHD length */
c028818d 2525 build_append_int_noprefix(table_data, ivhd_table_len, 2);
fb9f5926
DK		 2526 /* DeviceID */
2527 build_append_int_noprefix(table_data, s->devid, 2);
2528 /* Capability offset */
2529 build_append_int_noprefix(table_data, s->capab_offset, 2);
2530 /* IOMMU base address */
2531 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2532 /* PCI Segment Group */
2533 build_append_int_noprefix(table_data, 0, 2);
2534 /* IOMMU info */
2535 build_append_int_noprefix(table_data, 0, 2);
2536 /* IOMMU Feature Reporting */
2537 build_append_int_noprefix(table_data,
2538 (48UL << 30) | /* HATS */
2539 (48UL << 28) | /* GATS */
12499b23
BS		 2540 (1UL << 2) | /* GTSup */
2541 (1UL << 6), /* GASup */
fb9f5926
DK		 2542 4);
2543 /*
2544 * Type 1 device entry reporting all devices
2545 * These are 4-byte device entries currently reporting the range of
2546 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2547 */
2548 build_append_int_noprefix(table_data, 0x0000001, 4);
2549
c028818d
BS		 2550 /*
2551 * Add a special IVHD device type.
2552 * Refer to spec - Table 95: IVHD device entry type codes
2553 *
2554 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2555 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2556 */
a924b3d8 2557 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
c028818d
BS		 2558 build_append_int_noprefix(table_data,
2559 (0x1ull << 56) | /* type IOAPIC */
2560 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2561 0x48, /* special device */
2562 8);
2563 }
2564
fb9f5926
DK		 2565 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2566 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2567}
d4eb9119 2568
72c194f7
MT		 2569typedef
2570struct AcpiBuildState {
2571 /* Copy of table in RAM (for patching). */
339240b5 2572 MemoryRegion *table_mr;
72c194f7
MT		 2573 /* Is table patched? */
2574 uint8_t patched;
d70414a5 2575 void *rsdp;
339240b5
PB		 2576 MemoryRegion *rsdp_mr;
2577 MemoryRegion *linker_mr;
72c194f7
MT		 2578} AcpiBuildState;
2579
2580static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2581{
2582 Object *pci_host;
2583 QObject *o;
72c194f7 2584
ca6c1855 2585 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 2586 g_assert(pci_host);
2587
2588 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2589 if (!o) {
2590 return false;
2591 }
7dc847eb 2592 mcfg->mcfg_base = qnum_get_uint(qobject_to(QNum, o));
cb3e7f08 2593 qobject_unref(o);
fe4970ad
IM		 2594 if (mcfg->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2595 return false;
2596 }
72c194f7
MT		 2597
2598 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2599 assert(o);
7dc847eb 2600 mcfg->mcfg_size = qnum_get_uint(qobject_to(QNum, o));
cb3e7f08 2601 qobject_unref(o);
72c194f7
MT		 2602 return true;
2603}
2604
2605static
3d3ebcad 2606void acpi_build(AcpiBuildTables *tables, MachineState *machine)
72c194f7 2607{
3d3ebcad 2608 PCMachineState *pcms = PC_MACHINE(machine);
bb292f5a 2609 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72c194f7 2610 GArray *table_offsets;
41fa5c04 2611 unsigned facs, dsdt, rsdt, fadt;
72c194f7
MT		 2612 AcpiPmInfo pm;
2613 AcpiMiscInfo misc;
2614 AcpiMcfgInfo mcfg;
01c9742d 2615 Range pci_hole, pci_hole64;
72c194f7 2616 uint8_t *u;
07fb6176 2617 size_t aml_len = 0;
7c2c1fa5 2618 GArray *tables_blob = tables->table_data;
ae123749 2619 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
d03637bc 2620 Object *vmgenid_dev;
72c194f7 2621
72c194f7 2622 acpi_get_pm_info(&pm);
72c194f7 2623 acpi_get_misc_info(&misc);
01c9742d 2624 acpi_get_pci_holes(&pci_hole, &pci_hole64);
ae123749 2625 acpi_get_slic_oem(&slic_oem);
72c194f7
MT		 2626
2627 table_offsets = g_array_new(false, true /* clear */,
2628 sizeof(uint32_t));
8b310fc4 2629 ACPI_BUILD_DPRINTF("init ACPI tables\n");
72c194f7 2630
ad9671b8
IM		 2631 bios_linker_loader_alloc(tables->linker,
2632 ACPI_BUILD_TABLE_FILE, tables_blob,
72c194f7
MT		 2633 64 /* Ensure FACS is aligned */,
2634 false /* high memory */);
2635
2636 /*
2637 * FACS is pointed to by FADT.
2638 * We place it first since it's the only table that has alignment
2639 * requirements.
2640 */
7c2c1fa5 2641 facs = tables_blob->len;
009180bd 2642 build_facs(tables_blob);
72c194f7
MT		 2643
2644 /* DSDT is pointed to by FADT */
7c2c1fa5 2645 dsdt = tables_blob->len;
01c9742d
MA		 2646 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2647 &pci_hole, &pci_hole64, machine);
72c194f7 2648
07fb6176
PB		 2649 /* Count the size of the DSDT and SSDT, we will need it for legacy
2650 * sizing of ACPI tables.
2651 */
7c2c1fa5 2652 aml_len += tables_blob->len - dsdt;
07fb6176 2653
72c194f7 2654 /* ACPI tables pointed to by RSDT */
41fa5c04 2655 fadt = tables_blob->len;
7c2c1fa5 2656 acpi_add_table(table_offsets, tables_blob);
937d1b58
IM		 2657 pm.fadt.facs_tbl_offset = &facs;
2658 pm.fadt.dsdt_tbl_offset = &dsdt;
2659 pm.fadt.xdsdt_tbl_offset = &dsdt;
2660 build_fadt(tables_blob, tables->linker, &pm.fadt,
ae123749 2661 slic_oem.id, slic_oem.table_id);
41fa5c04 2662 aml_len += tables_blob->len - fadt;
72c194f7 2663
7c2c1fa5 2664 acpi_add_table(table_offsets, tables_blob);
907e7c94 2665 build_madt(tables_blob, tables->linker, pcms);
9ac1c4c0 2666
d03637bc
BW		 2667 vmgenid_dev = find_vmgenid_dev();
2668 if (vmgenid_dev) {
2669 acpi_add_table(table_offsets, tables_blob);
2670 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2671 tables->vmgenid, tables->linker);
2672 }
2673
72c194f7 2674 if (misc.has_hpet) {
7c2c1fa5
IM		 2675 acpi_add_table(table_offsets, tables_blob);
2676 build_hpet(tables_blob, tables->linker);
711b20b4 2677 }
5cb18b3d 2678 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
7c2c1fa5
IM		 2679 acpi_add_table(table_offsets, tables_blob);
2680 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
711b20b4 2681
72d97b3a
IM		 2682 if (misc.tpm_version == TPM_VERSION_2_0) {
2683 acpi_add_table(table_offsets, tables_blob);
4a42fa0e 2684 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
5cb18b3d 2685 }
72c194f7 2686 }
dd4c2f01 2687 if (pcms->numa_nodes) {
7c2c1fa5 2688 acpi_add_table(table_offsets, tables_blob);
3d3ebcad 2689 build_srat(tables_blob, tables->linker, machine);
0f203430
HC		 2690 if (have_numa_distance) {
2691 acpi_add_table(table_offsets, tables_blob);
2692 build_slit(tables_blob, tables->linker);
2693 }
72c194f7
MT		 2694 }
2695 if (acpi_get_mcfg(&mcfg)) {
7c2c1fa5
IM		 2696 acpi_add_table(table_offsets, tables_blob);
2697 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
72c194f7 2698 }
fb9f5926
DK		 2699 if (x86_iommu_get_default()) {
2700 IommuType IOMMUType = x86_iommu_get_type();
2701 if (IOMMUType == TYPE_AMD) {
2702 acpi_add_table(table_offsets, tables_blob);
2703 build_amd_iommu(tables_blob, tables->linker);
2704 } else if (IOMMUType == TYPE_INTEL) {
2705 acpi_add_table(table_offsets, tables_blob);
2706 build_dmar_q35(tables_blob, tables->linker);
2707 }
d4eb9119 2708 }
f6a0d06b 2709 if (machine->nvdimms_state->is_enabled) {
ad9671b8 2710 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
f6a0d06b 2711 machine->nvdimms_state, machine->ram_slots);
87252e1b
XG		 2712 }
2713
72c194f7
MT		 2714 /* Add tables supplied by user (if any) */
2715 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2716 unsigned len = acpi_table_len(u);
2717
7c2c1fa5
IM		 2718 acpi_add_table(table_offsets, tables_blob);
2719 g_array_append_vals(tables_blob, u, len);
72c194f7
MT		 2720 }
2721
2722 /* RSDT is pointed to by RSDP */
7c2c1fa5 2723 rsdt = tables_blob->len;
ae123749
LE		 2724 build_rsdt(tables_blob, tables->linker, table_offsets,
2725 slic_oem.id, slic_oem.table_id);
72c194f7
MT		 2726
2727 /* RSDP is in FSEG memory, so allocate it separately */
a46ce1c2
SO		 2728 {
2729 AcpiRsdpData rsdp_data = {
2730 .revision = 0,
2731 .oem_id = ACPI_BUILD_APPNAME6,
2732 .xsdt_tbl_offset = NULL,
2733 .rsdt_tbl_offset = &rsdt,
2734 };
2735 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2736 if (!pcmc->rsdp_in_ram) {
2737 /* We used to allocate some extra space for RSDP revision 2 but
2738 * only used the RSDP revision 0 space. The extra bytes were
2739 * zeroed out and not used.
2740 * Here we continue wasting those extra 16 bytes to make sure we
2741 * don't break migration for machine types 2.2 and older due to
2742 * RSDP blob size mismatch.
2743 */
2744 build_append_int_noprefix(tables->rsdp, 0, 16);
2745 }
2746 }
72c194f7 2747
07fb6176 2748 /* We'll expose it all to Guest so we want to reduce
72c194f7 2749 * chance of size changes.
07fb6176
PB		 2750 *
2751 * We used to align the tables to 4k, but of course this would
2752 * too simple to be enough. 4k turned out to be too small an
2753 * alignment very soon, and in fact it is almost impossible to
2754 * keep the table size stable for all (max_cpus, max_memory_slots)
2755 * combinations. So the table size is always 64k for pc-i440fx-2.1
2756 * and we give an error if the table grows beyond that limit.
2757 *
2758 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2759 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2760 * than 2.0 and we can always pad the smaller tables with zeros. We can
2761 * then use the exact size of the 2.0 tables.
2762 *
2763 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
72c194f7 2764 */
bb292f5a 2765 if (pcmc->legacy_acpi_table_size) {
07fb6176
PB		 2766 /* Subtracting aml_len gives the size of fixed tables. Then add the
2767 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2768 */
2769 int legacy_aml_len =
bb292f5a 2770 pcmc->legacy_acpi_table_size +
4b5b47ab 2771 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit;
07fb6176 2772 int legacy_table_size =
7c2c1fa5 2773 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
07fb6176 2774 ACPI_BUILD_ALIGN_SIZE);
7c2c1fa5 2775 if (tables_blob->len > legacy_table_size) {
07fb6176 2776 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
9e5d2c52
AF		 2777 warn_report("ACPI table size %u exceeds %d bytes,"
2778 " migration may not work",
2779 tables_blob->len, legacy_table_size);
2780 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2781 " or PCI bridges.");
07fb6176 2782 }
7c2c1fa5 2783 g_array_set_size(tables_blob, legacy_table_size);
07fb6176 2784 } else {
868270f2 2785 /* Make sure we have a buffer in case we need to resize the tables. */
7c2c1fa5 2786 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
18045fb9 2787 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
9e5d2c52
AF		 2788 warn_report("ACPI table size %u exceeds %d bytes,"
2789 " migration may not work",
2790 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2791 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2792 " or PCI bridges.");
18045fb9 2793 }
7c2c1fa5 2794 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
07fb6176 2795 }
72c194f7 2796
0e9b9eda 2797 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
72c194f7
MT		 2798
2799 /* Cleanup memory that's no longer used. */
2800 g_array_free(table_offsets, true);
2801}
2802
339240b5 2803static void acpi_ram_update(MemoryRegion *mr, GArray *data)
42d85900
MT		 2804{
2805 uint32_t size = acpi_data_len(data);
2806
2807 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
339240b5 2808 memory_region_ram_resize(mr, size, &error_abort);
42d85900 2809
339240b5
PB		 2810 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2811 memory_region_set_dirty(mr, 0, size);
42d85900
MT		 2812}
2813
3f8752b4 2814static void acpi_build_update(void *build_opaque)
72c194f7
MT		 2815{
2816 AcpiBuildState *build_state = build_opaque;
2817 AcpiBuildTables tables;
2818
2819 /* No state to update or already patched? Nothing to do. */
2820 if (!build_state || build_state->patched) {
2821 return;
2822 }
2823 build_state->patched = 1;
2824
2825 acpi_build_tables_init(&tables);
2826
3d3ebcad 2827 acpi_build(&tables, MACHINE(qdev_get_machine()));
72c194f7 2828
339240b5 2829 acpi_ram_update(build_state->table_mr, tables.table_data);
a1666142 2830
42d85900
MT		 2831 if (build_state->rsdp) {
2832 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2833 } else {
339240b5 2834 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
42d85900 2835 }
ad5b88b1 2836
0e9b9eda 2837 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
72c194f7
MT		 2838 acpi_build_tables_cleanup(&tables, true);
2839}
2840
2841static void acpi_build_reset(void *build_opaque)
2842{
2843 AcpiBuildState *build_state = build_opaque;
2844 build_state->patched = 0;
2845}
2846
339240b5
PB		 2847static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2848 GArray *blob, const char *name,
2849 uint64_t max_size)
72c194f7 2850{
a1666142 2851 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
baf2d5bf 2852 name, acpi_build_update, build_state, NULL, true);
72c194f7
MT		 2853}
2854
2855static const VMStateDescription vmstate_acpi_build = {
2856 .name = "acpi_build",
2857 .version_id = 1,
2858 .minimum_version_id = 1,
d49805ae 2859 .fields = (VMStateField[]) {
72c194f7
MT		 2860 VMSTATE_UINT8(patched, AcpiBuildState),
2861 VMSTATE_END_OF_LIST()
2862 },
2863};
2864
fb306ffe 2865void acpi_setup(void)
72c194f7 2866{
fb306ffe 2867 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
bb292f5a 2868 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72c194f7
MT		 2869 AcpiBuildTables tables;
2870 AcpiBuildState *build_state;
d03637bc 2871 Object *vmgenid_dev;
0fe24669
SB		 2872 TPMIf *tpm;
2873 static FwCfgTPMConfig tpm_config;
72c194f7 2874
f264d360 2875 if (!pcms->fw_cfg) {
8b310fc4 2876 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
72c194f7
MT		 2877 return;
2878 }
2879
021746c1 2880 if (!pcms->acpi_build_enabled) {
8b310fc4 2881 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
72c194f7
MT		 2882 return;
2883 }
2884
81adc513 2885 if (!acpi_enabled) {
8b310fc4 2886 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
81adc513
MT		 2887 return;
2888 }
2889
72c194f7
MT		 2890 build_state = g_malloc0(sizeof *build_state);
2891
72c194f7 2892 acpi_build_tables_init(&tables);
3d3ebcad 2893 acpi_build(&tables, MACHINE(pcms));
72c194f7
MT		 2894
2895 /* Now expose it all to Guest */
339240b5 2896 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
a1666142
MT		 2897 ACPI_BUILD_TABLE_FILE,
2898 ACPI_BUILD_TABLE_MAX_SIZE);
339240b5 2899 assert(build_state->table_mr != NULL);
72c194f7 2900
339240b5 2901 build_state->linker_mr =
0e9b9eda
IM		 2902 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2903 "etc/table-loader", 0);
72c194f7 2904
f264d360 2905 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
42a5b308
SB		 2906 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2907
0fe24669
SB		 2908 tpm = tpm_find();
2909 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2910 tpm_config = (FwCfgTPMConfig) {
2911 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2912 .tpm_version = tpm_get_version(tpm),
ac6dd31e 2913 .tpmppi_version = TPM_PPI_VERSION_1_30
0fe24669
SB		 2914 };
2915 fw_cfg_add_file(pcms->fw_cfg, "etc/tpm/config",
2916 &tpm_config, sizeof tpm_config);
2917 }
2918
d03637bc
BW		 2919 vmgenid_dev = find_vmgenid_dev();
2920 if (vmgenid_dev) {
2921 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg,
2922 tables.vmgenid);
2923 }
2924
bb292f5a 2925 if (!pcmc->rsdp_in_ram) {
358774d7
IM		 2926 /*
2927 * Keep for compatibility with old machine types.
2928 * Though RSDP is small, its contents isn't immutable, so
afaa2e4b 2929 * we'll update it along with the rest of tables on guest access.
358774d7 2930 */
afaa2e4b
MT		 2931 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2932
2933 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
f264d360 2934 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
5f9252f7 2935 acpi_build_update, NULL, build_state,
baf2d5bf 2936 build_state->rsdp, rsdp_size, true);
339240b5 2937 build_state->rsdp_mr = NULL;
358774d7 2938 } else {
42d85900 2939 build_state->rsdp = NULL;
339240b5 2940 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
42d85900 2941 ACPI_BUILD_RSDP_FILE, 0);
358774d7 2942 }
72c194f7
MT		 2943
2944 qemu_register_reset(acpi_build_reset, build_state);
2945 acpi_build_reset(build_state);
2946 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2947
2948 /* Cleanup tables but don't free the memory: we track it
2949 * in build_state.
2950 */
2951 acpi_build_tables_cleanup(&tables, false);
2952}
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