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a39c1d47 JK |
1 | /* |
2 | * KVM in-kernel IOPIC support | |
3 | * | |
4 | * Copyright (c) 2011 Siemens AG | |
5 | * | |
6 | * Authors: | |
7 | * Jan Kiszka <jan.kiszka@siemens.com> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL version 2. | |
10 | * See the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
b6a0aa05 | 13 | #include "qemu/osdep.h" |
d665d696 | 14 | #include "monitor/monitor.h" |
0d09e41a PB |
15 | #include "hw/i386/pc.h" |
16 | #include "hw/i386/ioapic_internal.h" | |
17 | #include "hw/i386/apic_internal.h" | |
9c17d615 | 18 | #include "sysemu/kvm.h" |
a39c1d47 | 19 | |
d8ee0384 JB |
20 | /* PC Utility function */ |
21 | void kvm_pc_setup_irq_routing(bool pci_enabled) | |
22 | { | |
23 | KVMState *s = kvm_state; | |
24 | int i; | |
25 | ||
26 | if (kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) { | |
27 | for (i = 0; i < 8; ++i) { | |
28 | if (i == 2) { | |
29 | continue; | |
30 | } | |
31 | kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i); | |
32 | } | |
33 | for (i = 8; i < 16; ++i) { | |
34 | kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8); | |
35 | } | |
36 | if (pci_enabled) { | |
37 | for (i = 0; i < 24; ++i) { | |
38 | if (i == 0) { | |
39 | kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2); | |
40 | } else if (i != 2) { | |
41 | kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i); | |
42 | } | |
43 | } | |
44 | } | |
cb925cf9 | 45 | kvm_irqchip_commit_routes(s); |
d8ee0384 JB |
46 | } |
47 | } | |
48 | ||
49 | void kvm_pc_gsi_handler(void *opaque, int n, int level) | |
50 | { | |
51 | GSIState *s = opaque; | |
52 | ||
53 | if (n < ISA_NUM_IRQS) { | |
54 | /* Kernel will forward to both PIC and IOAPIC */ | |
55 | qemu_set_irq(s->i8259_irq[n], level); | |
56 | } else { | |
57 | qemu_set_irq(s->ioapic_irq[n], level); | |
58 | } | |
59 | } | |
60 | ||
a39c1d47 JK |
61 | typedef struct KVMIOAPICState KVMIOAPICState; |
62 | ||
63 | struct KVMIOAPICState { | |
64 | IOAPICCommonState ioapic; | |
65 | uint32_t kvm_gsi_base; | |
66 | }; | |
67 | ||
68 | static void kvm_ioapic_get(IOAPICCommonState *s) | |
69 | { | |
70 | struct kvm_irqchip chip; | |
71 | struct kvm_ioapic_state *kioapic; | |
72 | int ret, i; | |
73 | ||
74 | chip.chip_id = KVM_IRQCHIP_IOAPIC; | |
75 | ret = kvm_vm_ioctl(kvm_state, KVM_GET_IRQCHIP, &chip); | |
76 | if (ret < 0) { | |
77 | fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(ret)); | |
78 | abort(); | |
79 | } | |
80 | ||
81 | kioapic = &chip.chip.ioapic; | |
82 | ||
83 | s->id = kioapic->id; | |
84 | s->ioregsel = kioapic->ioregsel; | |
85 | s->irr = kioapic->irr; | |
86 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
87 | s->ioredtbl[i] = kioapic->redirtbl[i].bits; | |
88 | } | |
89 | } | |
90 | ||
91 | static void kvm_ioapic_put(IOAPICCommonState *s) | |
92 | { | |
93 | struct kvm_irqchip chip; | |
94 | struct kvm_ioapic_state *kioapic; | |
95 | int ret, i; | |
96 | ||
97 | chip.chip_id = KVM_IRQCHIP_IOAPIC; | |
98 | kioapic = &chip.chip.ioapic; | |
99 | ||
100 | kioapic->id = s->id; | |
101 | kioapic->ioregsel = s->ioregsel; | |
102 | kioapic->base_address = s->busdev.mmio[0].addr; | |
103 | kioapic->irr = s->irr; | |
104 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
105 | kioapic->redirtbl[i].bits = s->ioredtbl[i]; | |
106 | } | |
107 | ||
108 | ret = kvm_vm_ioctl(kvm_state, KVM_SET_IRQCHIP, &chip); | |
109 | if (ret < 0) { | |
110 | fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(ret)); | |
111 | abort(); | |
112 | } | |
113 | } | |
114 | ||
115 | static void kvm_ioapic_reset(DeviceState *dev) | |
116 | { | |
b3119631 | 117 | IOAPICCommonState *s = IOAPIC_COMMON(dev); |
a39c1d47 JK |
118 | |
119 | ioapic_reset_common(dev); | |
120 | kvm_ioapic_put(s); | |
121 | } | |
122 | ||
123 | static void kvm_ioapic_set_irq(void *opaque, int irq, int level) | |
124 | { | |
125 | KVMIOAPICState *s = opaque; | |
cce5405e | 126 | IOAPICCommonState *common = IOAPIC_COMMON(s); |
a39c1d47 JK |
127 | int delivered; |
128 | ||
cce5405e | 129 | ioapic_stat_update_irq(common, irq, level); |
3889c3fa | 130 | delivered = kvm_set_irq(kvm_state, s->kvm_gsi_base + irq, level); |
a39c1d47 JK |
131 | apic_report_irq_delivered(delivered); |
132 | } | |
133 | ||
db0f8888 | 134 | static void kvm_ioapic_realize(DeviceState *dev, Error **errp) |
a39c1d47 | 135 | { |
db0f8888 | 136 | IOAPICCommonState *s = IOAPIC_COMMON(dev); |
f9771858 | 137 | |
257a7430 | 138 | memory_region_init_io(&s->io_memory, OBJECT(dev), NULL, NULL, "kvm-ioapic", 0x1000); |
b7a4104b PX |
139 | /* |
140 | * KVM ioapic only supports 0x11 now. This will only be used when | |
141 | * we want to dump ioapic version. | |
142 | */ | |
143 | s->version = 0x11; | |
a39c1d47 | 144 | |
f9771858 | 145 | qdev_init_gpio_in(dev, kvm_ioapic_set_irq, IOAPIC_NUM_PINS); |
a39c1d47 JK |
146 | } |
147 | ||
39bffca2 AL |
148 | static Property kvm_ioapic_properties[] = { |
149 | DEFINE_PROP_UINT32("gsi_base", KVMIOAPICState, kvm_gsi_base, 0), | |
150 | DEFINE_PROP_END_OF_LIST() | |
151 | }; | |
152 | ||
999e12bb AL |
153 | static void kvm_ioapic_class_init(ObjectClass *klass, void *data) |
154 | { | |
155 | IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass); | |
39bffca2 | 156 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 157 | |
db0f8888 | 158 | k->realize = kvm_ioapic_realize; |
999e12bb AL |
159 | k->pre_save = kvm_ioapic_get; |
160 | k->post_load = kvm_ioapic_put; | |
39bffca2 AL |
161 | dc->reset = kvm_ioapic_reset; |
162 | dc->props = kvm_ioapic_properties; | |
999e12bb AL |
163 | } |
164 | ||
8c43a6f0 | 165 | static const TypeInfo kvm_ioapic_info = { |
999e12bb | 166 | .name = "kvm-ioapic", |
39bffca2 AL |
167 | .parent = TYPE_IOAPIC_COMMON, |
168 | .instance_size = sizeof(KVMIOAPICState), | |
999e12bb | 169 | .class_init = kvm_ioapic_class_init, |
a39c1d47 JK |
170 | }; |
171 | ||
83f7d43a | 172 | static void kvm_ioapic_register_types(void) |
a39c1d47 | 173 | { |
39bffca2 | 174 | type_register_static(&kvm_ioapic_info); |
a39c1d47 JK |
175 | } |
176 | ||
83f7d43a | 177 | type_init(kvm_ioapic_register_types) |