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e5ad936b JK |
1 | /* |
2 | * TPR optimization for 32-bit Windows guests (XP and Server 2003) | |
3 | * | |
4 | * Copyright (C) 2007-2008 Qumranet Technologies | |
5 | * Copyright (C) 2012 Jan Kiszka, Siemens AG | |
6 | * | |
7 | * This work is licensed under the terms of the GNU GPL version 2, or | |
8 | * (at your option) any later version. See the COPYING file in the | |
9 | * top-level directory. | |
10 | */ | |
b6a0aa05 | 11 | #include "qemu/osdep.h" |
33c11879 PB |
12 | #include "qemu-common.h" |
13 | #include "cpu.h" | |
9c17d615 PB |
14 | #include "sysemu/sysemu.h" |
15 | #include "sysemu/cpus.h" | |
16 | #include "sysemu/kvm.h" | |
0d09e41a | 17 | #include "hw/i386/apic_internal.h" |
5f8df3ce | 18 | #include "hw/sysbus.h" |
e5ad936b | 19 | |
e5ad936b JK |
20 | #define VAPIC_IO_PORT 0x7e |
21 | ||
22 | #define VAPIC_CPU_SHIFT 7 | |
23 | ||
24 | #define ROM_BLOCK_SIZE 512 | |
25 | #define ROM_BLOCK_MASK (~(ROM_BLOCK_SIZE - 1)) | |
26 | ||
27 | typedef enum VAPICMode { | |
28 | VAPIC_INACTIVE = 0, | |
29 | VAPIC_ACTIVE = 1, | |
30 | VAPIC_STANDBY = 2, | |
31 | } VAPICMode; | |
32 | ||
33 | typedef struct VAPICHandlers { | |
34 | uint32_t set_tpr; | |
35 | uint32_t set_tpr_eax; | |
36 | uint32_t get_tpr[8]; | |
37 | uint32_t get_tpr_stack; | |
38 | } QEMU_PACKED VAPICHandlers; | |
39 | ||
40 | typedef struct GuestROMState { | |
41 | char signature[8]; | |
42 | uint32_t vaddr; | |
43 | uint32_t fixup_start; | |
44 | uint32_t fixup_end; | |
45 | uint32_t vapic_vaddr; | |
46 | uint32_t vapic_size; | |
47 | uint32_t vcpu_shift; | |
48 | uint32_t real_tpr_addr; | |
49 | VAPICHandlers up; | |
50 | VAPICHandlers mp; | |
51 | } QEMU_PACKED GuestROMState; | |
52 | ||
53 | typedef struct VAPICROMState { | |
54 | SysBusDevice busdev; | |
55 | MemoryRegion io; | |
56 | MemoryRegion rom; | |
57 | uint32_t state; | |
58 | uint32_t rom_state_paddr; | |
59 | uint32_t rom_state_vaddr; | |
60 | uint32_t vapic_paddr; | |
61 | uint32_t real_tpr_addr; | |
62 | GuestROMState rom_state; | |
63 | size_t rom_size; | |
64 | bool rom_mapped_writable; | |
a6dead43 | 65 | VMChangeStateEntry *vmsentry; |
e5ad936b JK |
66 | } VAPICROMState; |
67 | ||
f1fc3e66 IM |
68 | #define TYPE_VAPIC "kvmvapic" |
69 | #define VAPIC(obj) OBJECT_CHECK(VAPICROMState, (obj), TYPE_VAPIC) | |
70 | ||
e5ad936b JK |
71 | #define TPR_INSTR_ABS_MODRM 0x1 |
72 | #define TPR_INSTR_MATCH_MODRM_REG 0x2 | |
73 | ||
74 | typedef struct TPRInstruction { | |
75 | uint8_t opcode; | |
76 | uint8_t modrm_reg; | |
77 | unsigned int flags; | |
78 | TPRAccess access; | |
79 | size_t length; | |
80 | off_t addr_offset; | |
81 | } TPRInstruction; | |
82 | ||
83 | /* must be sorted by length, shortest first */ | |
84 | static const TPRInstruction tpr_instr[] = { | |
85 | { /* mov abs to eax */ | |
86 | .opcode = 0xa1, | |
87 | .access = TPR_ACCESS_READ, | |
88 | .length = 5, | |
89 | .addr_offset = 1, | |
90 | }, | |
91 | { /* mov eax to abs */ | |
92 | .opcode = 0xa3, | |
93 | .access = TPR_ACCESS_WRITE, | |
94 | .length = 5, | |
95 | .addr_offset = 1, | |
96 | }, | |
97 | { /* mov r32 to r/m32 */ | |
98 | .opcode = 0x89, | |
99 | .flags = TPR_INSTR_ABS_MODRM, | |
100 | .access = TPR_ACCESS_WRITE, | |
101 | .length = 6, | |
102 | .addr_offset = 2, | |
103 | }, | |
104 | { /* mov r/m32 to r32 */ | |
105 | .opcode = 0x8b, | |
106 | .flags = TPR_INSTR_ABS_MODRM, | |
107 | .access = TPR_ACCESS_READ, | |
108 | .length = 6, | |
109 | .addr_offset = 2, | |
110 | }, | |
111 | { /* push r/m32 */ | |
112 | .opcode = 0xff, | |
113 | .modrm_reg = 6, | |
114 | .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG, | |
115 | .access = TPR_ACCESS_READ, | |
116 | .length = 6, | |
117 | .addr_offset = 2, | |
118 | }, | |
119 | { /* mov imm32, r/m32 (c7/0) */ | |
120 | .opcode = 0xc7, | |
121 | .modrm_reg = 0, | |
122 | .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG, | |
123 | .access = TPR_ACCESS_WRITE, | |
124 | .length = 10, | |
125 | .addr_offset = 2, | |
126 | }, | |
127 | }; | |
128 | ||
129 | static void read_guest_rom_state(VAPICROMState *s) | |
130 | { | |
eb6282f2 SW |
131 | cpu_physical_memory_read(s->rom_state_paddr, &s->rom_state, |
132 | sizeof(GuestROMState)); | |
e5ad936b JK |
133 | } |
134 | ||
135 | static void write_guest_rom_state(VAPICROMState *s) | |
136 | { | |
eb6282f2 SW |
137 | cpu_physical_memory_write(s->rom_state_paddr, &s->rom_state, |
138 | sizeof(GuestROMState)); | |
e5ad936b JK |
139 | } |
140 | ||
141 | static void update_guest_rom_state(VAPICROMState *s) | |
142 | { | |
143 | read_guest_rom_state(s); | |
144 | ||
145 | s->rom_state.real_tpr_addr = cpu_to_le32(s->real_tpr_addr); | |
146 | s->rom_state.vcpu_shift = cpu_to_le32(VAPIC_CPU_SHIFT); | |
147 | ||
148 | write_guest_rom_state(s); | |
149 | } | |
150 | ||
4a8fa5dc | 151 | static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env) |
e5ad936b | 152 | { |
00b941e5 | 153 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
a8170e5e | 154 | hwaddr paddr; |
e5ad936b JK |
155 | target_ulong addr; |
156 | ||
157 | if (s->state == VAPIC_ACTIVE) { | |
158 | return 0; | |
159 | } | |
160 | /* | |
161 | * If there is no prior TPR access instruction we could analyze (which is | |
162 | * the case after resume from hibernation), we need to scan the possible | |
163 | * virtual address space for the APIC mapping. | |
164 | */ | |
165 | for (addr = 0xfffff000; addr >= 0x80000000; addr -= TARGET_PAGE_SIZE) { | |
00b941e5 | 166 | paddr = cpu_get_phys_page_debug(cs, addr); |
e5ad936b JK |
167 | if (paddr != APIC_DEFAULT_ADDRESS) { |
168 | continue; | |
169 | } | |
170 | s->real_tpr_addr = addr + 0x80; | |
171 | update_guest_rom_state(s); | |
172 | return 0; | |
173 | } | |
174 | return -1; | |
175 | } | |
176 | ||
177 | static uint8_t modrm_reg(uint8_t modrm) | |
178 | { | |
179 | return (modrm >> 3) & 7; | |
180 | } | |
181 | ||
182 | static bool is_abs_modrm(uint8_t modrm) | |
183 | { | |
184 | return (modrm & 0xc7) == 0x05; | |
185 | } | |
186 | ||
187 | static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr) | |
188 | { | |
189 | return opcode[0] == instr->opcode && | |
190 | (!(instr->flags & TPR_INSTR_ABS_MODRM) || is_abs_modrm(opcode[1])) && | |
191 | (!(instr->flags & TPR_INSTR_MATCH_MODRM_REG) || | |
192 | modrm_reg(opcode[1]) == instr->modrm_reg); | |
193 | } | |
194 | ||
f17ec444 | 195 | static int evaluate_tpr_instruction(VAPICROMState *s, X86CPU *cpu, |
e5ad936b JK |
196 | target_ulong *pip, TPRAccess access) |
197 | { | |
f17ec444 | 198 | CPUState *cs = CPU(cpu); |
e5ad936b JK |
199 | const TPRInstruction *instr; |
200 | target_ulong ip = *pip; | |
201 | uint8_t opcode[2]; | |
202 | uint32_t real_tpr_addr; | |
203 | int i; | |
204 | ||
205 | if ((ip & 0xf0000000ULL) != 0x80000000ULL && | |
206 | (ip & 0xf0000000ULL) != 0xe0000000ULL) { | |
207 | return -1; | |
208 | } | |
209 | ||
210 | /* | |
211 | * Early Windows 2003 SMP initialization contains a | |
212 | * | |
213 | * mov imm32, r/m32 | |
214 | * | |
215 | * instruction that is patched by TPR optimization. The problem is that | |
216 | * RSP, used by the patched instruction, is zero, so the guest gets a | |
217 | * double fault and dies. | |
218 | */ | |
f17ec444 | 219 | if (cpu->env.regs[R_ESP] == 0) { |
e5ad936b JK |
220 | return -1; |
221 | } | |
222 | ||
223 | if (kvm_enabled() && !kvm_irqchip_in_kernel()) { | |
224 | /* | |
225 | * KVM without kernel-based TPR access reporting will pass an IP that | |
226 | * points after the accessing instruction. So we need to look backward | |
227 | * to find the reason. | |
228 | */ | |
229 | for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) { | |
230 | instr = &tpr_instr[i]; | |
231 | if (instr->access != access) { | |
232 | continue; | |
233 | } | |
f17ec444 | 234 | if (cpu_memory_rw_debug(cs, ip - instr->length, opcode, |
e5ad936b JK |
235 | sizeof(opcode), 0) < 0) { |
236 | return -1; | |
237 | } | |
238 | if (opcode_matches(opcode, instr)) { | |
239 | ip -= instr->length; | |
240 | goto instruction_ok; | |
241 | } | |
242 | } | |
243 | return -1; | |
244 | } else { | |
f17ec444 | 245 | if (cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0) < 0) { |
e5ad936b JK |
246 | return -1; |
247 | } | |
248 | for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) { | |
249 | instr = &tpr_instr[i]; | |
250 | if (opcode_matches(opcode, instr)) { | |
251 | goto instruction_ok; | |
252 | } | |
253 | } | |
254 | return -1; | |
255 | } | |
256 | ||
257 | instruction_ok: | |
258 | /* | |
259 | * Grab the virtual TPR address from the instruction | |
260 | * and update the cached values. | |
261 | */ | |
f17ec444 | 262 | if (cpu_memory_rw_debug(cs, ip + instr->addr_offset, |
e5ad936b JK |
263 | (void *)&real_tpr_addr, |
264 | sizeof(real_tpr_addr), 0) < 0) { | |
265 | return -1; | |
266 | } | |
267 | real_tpr_addr = le32_to_cpu(real_tpr_addr); | |
268 | if ((real_tpr_addr & 0xfff) != 0x80) { | |
269 | return -1; | |
270 | } | |
271 | s->real_tpr_addr = real_tpr_addr; | |
272 | update_guest_rom_state(s); | |
273 | ||
274 | *pip = ip; | |
275 | return 0; | |
276 | } | |
277 | ||
4a8fa5dc | 278 | static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip) |
e5ad936b | 279 | { |
00b941e5 | 280 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
a8170e5e | 281 | hwaddr paddr; |
e5ad936b JK |
282 | uint32_t rom_state_vaddr; |
283 | uint32_t pos, patch, offset; | |
284 | ||
285 | /* nothing to do if already activated */ | |
286 | if (s->state == VAPIC_ACTIVE) { | |
287 | return 0; | |
288 | } | |
289 | ||
290 | /* bail out if ROM init code was not executed (missing ROM?) */ | |
291 | if (s->state == VAPIC_INACTIVE) { | |
292 | return -1; | |
293 | } | |
294 | ||
295 | /* find out virtual address of the ROM */ | |
296 | rom_state_vaddr = s->rom_state_paddr + (ip & 0xf0000000); | |
00b941e5 | 297 | paddr = cpu_get_phys_page_debug(cs, rom_state_vaddr); |
e5ad936b JK |
298 | if (paddr == -1) { |
299 | return -1; | |
300 | } | |
301 | paddr += rom_state_vaddr & ~TARGET_PAGE_MASK; | |
302 | if (paddr != s->rom_state_paddr) { | |
303 | return -1; | |
304 | } | |
305 | read_guest_rom_state(s); | |
306 | if (memcmp(s->rom_state.signature, "kvm aPiC", 8) != 0) { | |
307 | return -1; | |
308 | } | |
309 | s->rom_state_vaddr = rom_state_vaddr; | |
310 | ||
311 | /* fixup addresses in ROM if needed */ | |
312 | if (rom_state_vaddr == le32_to_cpu(s->rom_state.vaddr)) { | |
313 | return 0; | |
314 | } | |
315 | for (pos = le32_to_cpu(s->rom_state.fixup_start); | |
316 | pos < le32_to_cpu(s->rom_state.fixup_end); | |
317 | pos += 4) { | |
eb6282f2 SW |
318 | cpu_physical_memory_read(paddr + pos - s->rom_state.vaddr, |
319 | &offset, sizeof(offset)); | |
e5ad936b | 320 | offset = le32_to_cpu(offset); |
eb6282f2 | 321 | cpu_physical_memory_read(paddr + offset, &patch, sizeof(patch)); |
e5ad936b JK |
322 | patch = le32_to_cpu(patch); |
323 | patch += rom_state_vaddr - le32_to_cpu(s->rom_state.vaddr); | |
324 | patch = cpu_to_le32(patch); | |
eb6282f2 | 325 | cpu_physical_memory_write(paddr + offset, &patch, sizeof(patch)); |
e5ad936b JK |
326 | } |
327 | read_guest_rom_state(s); | |
328 | s->vapic_paddr = paddr + le32_to_cpu(s->rom_state.vapic_vaddr) - | |
329 | le32_to_cpu(s->rom_state.vaddr); | |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
334 | /* | |
335 | * Tries to read the unique processor number from the Kernel Processor Control | |
336 | * Region (KPCR) of 32-bit Windows XP and Server 2003. Returns -1 if the KPCR | |
337 | * cannot be accessed or is considered invalid. This also ensures that we are | |
338 | * not patching the wrong guest. | |
339 | */ | |
f17ec444 | 340 | static int get_kpcr_number(X86CPU *cpu) |
e5ad936b | 341 | { |
f17ec444 | 342 | CPUX86State *env = &cpu->env; |
e5ad936b JK |
343 | struct kpcr { |
344 | uint8_t fill1[0x1c]; | |
345 | uint32_t self; | |
346 | uint8_t fill2[0x31]; | |
347 | uint8_t number; | |
348 | } QEMU_PACKED kpcr; | |
349 | ||
f17ec444 | 350 | if (cpu_memory_rw_debug(CPU(cpu), env->segs[R_FS].base, |
e5ad936b JK |
351 | (void *)&kpcr, sizeof(kpcr), 0) < 0 || |
352 | kpcr.self != env->segs[R_FS].base) { | |
353 | return -1; | |
354 | } | |
355 | return kpcr.number; | |
356 | } | |
357 | ||
f17ec444 | 358 | static int vapic_enable(VAPICROMState *s, X86CPU *cpu) |
e5ad936b | 359 | { |
f17ec444 | 360 | int cpu_number = get_kpcr_number(cpu); |
a8170e5e | 361 | hwaddr vapic_paddr; |
e5ad936b JK |
362 | static const uint8_t enabled = 1; |
363 | ||
364 | if (cpu_number < 0) { | |
365 | return -1; | |
366 | } | |
367 | vapic_paddr = s->vapic_paddr + | |
a8170e5e | 368 | (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT); |
eb6282f2 SW |
369 | cpu_physical_memory_write(vapic_paddr + offsetof(VAPICState, enabled), |
370 | &enabled, sizeof(enabled)); | |
02e51483 | 371 | apic_enable_vapic(cpu->apic_state, vapic_paddr); |
e5ad936b JK |
372 | |
373 | s->state = VAPIC_ACTIVE; | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
f17ec444 | 378 | static void patch_byte(X86CPU *cpu, target_ulong addr, uint8_t byte) |
e5ad936b | 379 | { |
f17ec444 | 380 | cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, 1); |
e5ad936b JK |
381 | } |
382 | ||
f17ec444 | 383 | static void patch_call(VAPICROMState *s, X86CPU *cpu, target_ulong ip, |
e5ad936b JK |
384 | uint32_t target) |
385 | { | |
386 | uint32_t offset; | |
387 | ||
388 | offset = cpu_to_le32(target - ip - 5); | |
f17ec444 AF |
389 | patch_byte(cpu, ip, 0xe8); /* call near */ |
390 | cpu_memory_rw_debug(CPU(cpu), ip + 1, (void *)&offset, sizeof(offset), 1); | |
e5ad936b JK |
391 | } |
392 | ||
d77953b9 | 393 | static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) |
e5ad936b | 394 | { |
d77953b9 AF |
395 | CPUState *cs = CPU(cpu); |
396 | CPUX86State *env = &cpu->env; | |
e5ad936b JK |
397 | VAPICHandlers *handlers; |
398 | uint8_t opcode[2]; | |
399 | uint32_t imm32; | |
5c61afec JK |
400 | target_ulong current_pc = 0; |
401 | target_ulong current_cs_base = 0; | |
89fee74a | 402 | uint32_t current_flags = 0; |
e5ad936b JK |
403 | |
404 | if (smp_cpus == 1) { | |
405 | handlers = &s->rom_state.up; | |
406 | } else { | |
407 | handlers = &s->rom_state.mp; | |
408 | } | |
409 | ||
5c61afec | 410 | if (!kvm_enabled()) { |
5c61afec JK |
411 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
412 | ¤t_flags); | |
413 | } | |
414 | ||
e5ad936b JK |
415 | pause_all_vcpus(); |
416 | ||
f17ec444 | 417 | cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0); |
e5ad936b JK |
418 | |
419 | switch (opcode[0]) { | |
420 | case 0x89: /* mov r32 to r/m32 */ | |
f17ec444 AF |
421 | patch_byte(cpu, ip, 0x50 + modrm_reg(opcode[1])); /* push reg */ |
422 | patch_call(s, cpu, ip + 1, handlers->set_tpr); | |
e5ad936b JK |
423 | break; |
424 | case 0x8b: /* mov r/m32 to r32 */ | |
f17ec444 AF |
425 | patch_byte(cpu, ip, 0x90); |
426 | patch_call(s, cpu, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]); | |
e5ad936b JK |
427 | break; |
428 | case 0xa1: /* mov abs to eax */ | |
f17ec444 | 429 | patch_call(s, cpu, ip, handlers->get_tpr[0]); |
e5ad936b JK |
430 | break; |
431 | case 0xa3: /* mov eax to abs */ | |
f17ec444 | 432 | patch_call(s, cpu, ip, handlers->set_tpr_eax); |
e5ad936b JK |
433 | break; |
434 | case 0xc7: /* mov imm32, r/m32 (c7/0) */ | |
f17ec444 AF |
435 | patch_byte(cpu, ip, 0x68); /* push imm32 */ |
436 | cpu_memory_rw_debug(cs, ip + 6, (void *)&imm32, sizeof(imm32), 0); | |
437 | cpu_memory_rw_debug(cs, ip + 1, (void *)&imm32, sizeof(imm32), 1); | |
438 | patch_call(s, cpu, ip + 5, handlers->set_tpr); | |
e5ad936b JK |
439 | break; |
440 | case 0xff: /* push r/m32 */ | |
f17ec444 AF |
441 | patch_byte(cpu, ip, 0x50); /* push eax */ |
442 | patch_call(s, cpu, ip + 1, handlers->get_tpr_stack); | |
e5ad936b JK |
443 | break; |
444 | default: | |
445 | abort(); | |
446 | } | |
447 | ||
448 | resume_all_vcpus(); | |
449 | ||
5c61afec | 450 | if (!kvm_enabled()) { |
648f034c | 451 | tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1); |
0ea8cb88 | 452 | cpu_resume_from_signal(cs, NULL); |
5c61afec | 453 | } |
e5ad936b JK |
454 | } |
455 | ||
d77953b9 | 456 | void vapic_report_tpr_access(DeviceState *dev, CPUState *cs, target_ulong ip, |
e5ad936b JK |
457 | TPRAccess access) |
458 | { | |
253eacc2 | 459 | VAPICROMState *s = VAPIC(dev); |
d77953b9 AF |
460 | X86CPU *cpu = X86_CPU(cs); |
461 | CPUX86State *env = &cpu->env; | |
e5ad936b | 462 | |
cb446eca | 463 | cpu_synchronize_state(cs); |
e5ad936b | 464 | |
f17ec444 | 465 | if (evaluate_tpr_instruction(s, cpu, &ip, access) < 0) { |
e5ad936b | 466 | if (s->state == VAPIC_ACTIVE) { |
f17ec444 | 467 | vapic_enable(s, cpu); |
e5ad936b JK |
468 | } |
469 | return; | |
470 | } | |
471 | if (update_rom_mapping(s, env, ip) < 0) { | |
472 | return; | |
473 | } | |
f17ec444 | 474 | if (vapic_enable(s, cpu) < 0) { |
e5ad936b JK |
475 | return; |
476 | } | |
d77953b9 | 477 | patch_instruction(s, cpu, ip); |
e5ad936b JK |
478 | } |
479 | ||
480 | typedef struct VAPICEnableTPRReporting { | |
481 | DeviceState *apic; | |
482 | bool enable; | |
483 | } VAPICEnableTPRReporting; | |
484 | ||
485 | static void vapic_do_enable_tpr_reporting(void *data) | |
486 | { | |
487 | VAPICEnableTPRReporting *info = data; | |
488 | ||
489 | apic_enable_tpr_access_reporting(info->apic, info->enable); | |
490 | } | |
491 | ||
492 | static void vapic_enable_tpr_reporting(bool enable) | |
493 | { | |
494 | VAPICEnableTPRReporting info = { | |
495 | .enable = enable, | |
496 | }; | |
182735ef | 497 | CPUState *cs; |
f100f0b3 | 498 | X86CPU *cpu; |
e5ad936b | 499 | |
bdc44640 | 500 | CPU_FOREACH(cs) { |
182735ef | 501 | cpu = X86_CPU(cs); |
02e51483 | 502 | info.apic = cpu->apic_state; |
182735ef | 503 | run_on_cpu(cs, vapic_do_enable_tpr_reporting, &info); |
e5ad936b JK |
504 | } |
505 | } | |
506 | ||
507 | static void vapic_reset(DeviceState *dev) | |
508 | { | |
253eacc2 | 509 | VAPICROMState *s = VAPIC(dev); |
e5ad936b | 510 | |
c056bc3f | 511 | s->state = VAPIC_INACTIVE; |
4357930b | 512 | s->rom_state_paddr = 0; |
e5ad936b JK |
513 | vapic_enable_tpr_reporting(false); |
514 | } | |
515 | ||
516 | /* | |
517 | * Set the IRQ polling hypercalls to the supported variant: | |
518 | * - vmcall if using KVM in-kernel irqchip | |
519 | * - 32-bit VAPIC port write otherwise | |
520 | */ | |
521 | static int patch_hypercalls(VAPICROMState *s) | |
522 | { | |
a8170e5e | 523 | hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK; |
e5ad936b JK |
524 | static const uint8_t vmcall_pattern[] = { /* vmcall */ |
525 | 0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1 | |
526 | }; | |
527 | static const uint8_t outl_pattern[] = { /* nop; outl %eax,0x7e */ | |
528 | 0xb8, 0x1, 0, 0, 0, 0x90, 0xe7, 0x7e | |
529 | }; | |
530 | uint8_t alternates[2]; | |
531 | const uint8_t *pattern; | |
532 | const uint8_t *patch; | |
533 | int patches = 0; | |
534 | off_t pos; | |
535 | uint8_t *rom; | |
536 | ||
537 | rom = g_malloc(s->rom_size); | |
eb6282f2 | 538 | cpu_physical_memory_read(rom_paddr, rom, s->rom_size); |
e5ad936b JK |
539 | |
540 | for (pos = 0; pos < s->rom_size - sizeof(vmcall_pattern); pos++) { | |
541 | if (kvm_irqchip_in_kernel()) { | |
542 | pattern = outl_pattern; | |
543 | alternates[0] = outl_pattern[7]; | |
544 | alternates[1] = outl_pattern[7]; | |
545 | patch = &vmcall_pattern[5]; | |
546 | } else { | |
547 | pattern = vmcall_pattern; | |
548 | alternates[0] = vmcall_pattern[7]; | |
549 | alternates[1] = 0xd9; /* AMD's VMMCALL */ | |
550 | patch = &outl_pattern[5]; | |
551 | } | |
552 | if (memcmp(rom + pos, pattern, 7) == 0 && | |
553 | (rom[pos + 7] == alternates[0] || rom[pos + 7] == alternates[1])) { | |
eb6282f2 | 554 | cpu_physical_memory_write(rom_paddr + pos + 5, patch, 3); |
e5ad936b JK |
555 | /* |
556 | * Don't flush the tb here. Under ordinary conditions, the patched | |
557 | * calls are miles away from the current IP. Under malicious | |
558 | * conditions, the guest could trick us to crash. | |
559 | */ | |
560 | } | |
561 | } | |
562 | ||
563 | g_free(rom); | |
564 | ||
565 | if (patches != 0 && patches != 2) { | |
566 | return -1; | |
567 | } | |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
572 | /* | |
573 | * For TCG mode or the time KVM honors read-only memory regions, we need to | |
574 | * enable write access to the option ROM so that variables can be updated by | |
575 | * the guest. | |
576 | */ | |
18e5eec4 | 577 | static int vapic_map_rom_writable(VAPICROMState *s) |
e5ad936b | 578 | { |
a8170e5e | 579 | hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK; |
e5ad936b JK |
580 | MemoryRegionSection section; |
581 | MemoryRegion *as; | |
582 | size_t rom_size; | |
583 | uint8_t *ram; | |
584 | ||
585 | as = sysbus_address_space(&s->busdev); | |
586 | ||
587 | if (s->rom_mapped_writable) { | |
588 | memory_region_del_subregion(as, &s->rom); | |
d8d95814 | 589 | object_unparent(OBJECT(&s->rom)); |
e5ad936b JK |
590 | } |
591 | ||
592 | /* grab RAM memory region (region @rom_paddr may still be pc.rom) */ | |
593 | section = memory_region_find(as, 0, 1); | |
594 | ||
595 | /* read ROM size from RAM region */ | |
7174e54c JK |
596 | if (rom_paddr + 2 >= memory_region_size(section.mr)) { |
597 | return -1; | |
598 | } | |
e5ad936b JK |
599 | ram = memory_region_get_ram_ptr(section.mr); |
600 | rom_size = ram[rom_paddr + 2] * ROM_BLOCK_SIZE; | |
18e5eec4 JK |
601 | if (rom_size == 0) { |
602 | return -1; | |
603 | } | |
e5ad936b JK |
604 | s->rom_size = rom_size; |
605 | ||
9512e4a9 | 606 | /* We need to round to avoid creating subpages |
e5ad936b | 607 | * from which we cannot run code. */ |
9512e4a9 AK |
608 | rom_size += rom_paddr & ~TARGET_PAGE_MASK; |
609 | rom_paddr &= TARGET_PAGE_MASK; | |
e5ad936b JK |
610 | rom_size = TARGET_PAGE_ALIGN(rom_size); |
611 | ||
1437c94b PB |
612 | memory_region_init_alias(&s->rom, OBJECT(s), "kvmvapic-rom", section.mr, |
613 | rom_paddr, rom_size); | |
e5ad936b JK |
614 | memory_region_add_subregion_overlap(as, rom_paddr, &s->rom, 1000); |
615 | s->rom_mapped_writable = true; | |
dfde4e6e | 616 | memory_region_unref(section.mr); |
18e5eec4 JK |
617 | |
618 | return 0; | |
e5ad936b JK |
619 | } |
620 | ||
621 | static int vapic_prepare(VAPICROMState *s) | |
622 | { | |
18e5eec4 JK |
623 | if (vapic_map_rom_writable(s) < 0) { |
624 | return -1; | |
625 | } | |
e5ad936b JK |
626 | |
627 | if (patch_hypercalls(s) < 0) { | |
628 | return -1; | |
629 | } | |
630 | ||
631 | vapic_enable_tpr_reporting(true); | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
a8170e5e | 636 | static void vapic_write(void *opaque, hwaddr addr, uint64_t data, |
e5ad936b JK |
637 | unsigned int size) |
638 | { | |
e5ad936b | 639 | VAPICROMState *s = opaque; |
4c1396cb PP |
640 | X86CPU *cpu; |
641 | CPUX86State *env; | |
642 | hwaddr rom_paddr; | |
e5ad936b | 643 | |
4c1396cb PP |
644 | if (!current_cpu) { |
645 | return; | |
646 | } | |
647 | ||
648 | cpu_synchronize_state(current_cpu); | |
649 | cpu = X86_CPU(current_cpu); | |
650 | env = &cpu->env; | |
e5ad936b JK |
651 | |
652 | /* | |
653 | * The VAPIC supports two PIO-based hypercalls, both via port 0x7E. | |
654 | * o 16-bit write access: | |
655 | * Reports the option ROM initialization to the hypervisor. Written | |
656 | * value is the offset of the state structure in the ROM. | |
657 | * o 8-bit write access: | |
658 | * Reactivates the VAPIC after a guest hibernation, i.e. after the | |
659 | * option ROM content has been re-initialized by a guest power cycle. | |
660 | * o 32-bit write access: | |
661 | * Poll for pending IRQs, considering the current VAPIC state. | |
662 | */ | |
663 | switch (size) { | |
664 | case 2: | |
665 | if (s->state == VAPIC_INACTIVE) { | |
666 | rom_paddr = (env->segs[R_CS].base + env->eip) & ROM_BLOCK_MASK; | |
667 | s->rom_state_paddr = rom_paddr + data; | |
668 | ||
669 | s->state = VAPIC_STANDBY; | |
670 | } | |
671 | if (vapic_prepare(s) < 0) { | |
672 | s->state = VAPIC_INACTIVE; | |
4357930b | 673 | s->rom_state_paddr = 0; |
e5ad936b JK |
674 | break; |
675 | } | |
676 | break; | |
677 | case 1: | |
678 | if (kvm_enabled()) { | |
679 | /* | |
680 | * Disable triggering instruction in ROM by writing a NOP. | |
681 | * | |
682 | * We cannot do this in TCG mode as the reported IP is not | |
683 | * accurate. | |
684 | */ | |
685 | pause_all_vcpus(); | |
f17ec444 AF |
686 | patch_byte(cpu, env->eip - 2, 0x66); |
687 | patch_byte(cpu, env->eip - 1, 0x90); | |
e5ad936b JK |
688 | resume_all_vcpus(); |
689 | } | |
690 | ||
691 | if (s->state == VAPIC_ACTIVE) { | |
692 | break; | |
693 | } | |
694 | if (update_rom_mapping(s, env, env->eip) < 0) { | |
695 | break; | |
696 | } | |
697 | if (find_real_tpr_addr(s, env) < 0) { | |
698 | break; | |
699 | } | |
f17ec444 | 700 | vapic_enable(s, cpu); |
e5ad936b JK |
701 | break; |
702 | default: | |
703 | case 4: | |
704 | if (!kvm_irqchip_in_kernel()) { | |
02e51483 | 705 | apic_poll_irq(cpu->apic_state); |
e5ad936b JK |
706 | } |
707 | break; | |
708 | } | |
709 | } | |
710 | ||
0c1cd0ae MT |
711 | static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size) |
712 | { | |
713 | return 0xffffffff; | |
714 | } | |
715 | ||
e5ad936b JK |
716 | static const MemoryRegionOps vapic_ops = { |
717 | .write = vapic_write, | |
0c1cd0ae | 718 | .read = vapic_read, |
e5ad936b JK |
719 | .endianness = DEVICE_NATIVE_ENDIAN, |
720 | }; | |
721 | ||
c118d44b | 722 | static void vapic_realize(DeviceState *dev, Error **errp) |
e5ad936b | 723 | { |
c118d44b | 724 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
f1fc3e66 | 725 | VAPICROMState *s = VAPIC(dev); |
e5ad936b | 726 | |
1437c94b | 727 | memory_region_init_io(&s->io, OBJECT(s), &vapic_ops, s, "kvmvapic", 2); |
c118d44b HT |
728 | sysbus_add_io(sbd, VAPIC_IO_PORT, &s->io); |
729 | sysbus_init_ioports(sbd, VAPIC_IO_PORT, 2); | |
e5ad936b JK |
730 | |
731 | option_rom[nb_option_roms].name = "kvmvapic.bin"; | |
732 | option_rom[nb_option_roms].bootindex = -1; | |
733 | nb_option_roms++; | |
e5ad936b JK |
734 | } |
735 | ||
736 | static void do_vapic_enable(void *data) | |
737 | { | |
738 | VAPICROMState *s = data; | |
182735ef | 739 | X86CPU *cpu = X86_CPU(first_cpu); |
e5ad936b | 740 | |
5a6e8ba6 PD |
741 | static const uint8_t enabled = 1; |
742 | cpu_physical_memory_write(s->vapic_paddr + offsetof(VAPICState, enabled), | |
743 | &enabled, sizeof(enabled)); | |
744 | apic_enable_vapic(cpu->apic_state, s->vapic_paddr); | |
745 | s->state = VAPIC_ACTIVE; | |
e5ad936b JK |
746 | } |
747 | ||
a6dead43 PD |
748 | static void kvmvapic_vm_state_change(void *opaque, int running, |
749 | RunState state) | |
e5ad936b JK |
750 | { |
751 | VAPICROMState *s = opaque; | |
752 | uint8_t *zero; | |
753 | ||
a6dead43 PD |
754 | if (!running) { |
755 | return; | |
756 | } | |
757 | ||
758 | if (s->state == VAPIC_ACTIVE) { | |
759 | if (smp_cpus == 1) { | |
760 | run_on_cpu(first_cpu, do_vapic_enable, s); | |
761 | } else { | |
762 | zero = g_malloc0(s->rom_state.vapic_size); | |
763 | cpu_physical_memory_write(s->vapic_paddr, zero, | |
764 | s->rom_state.vapic_size); | |
765 | g_free(zero); | |
766 | } | |
767 | } | |
768 | ||
769 | qemu_del_vm_change_state_handler(s->vmsentry); | |
770 | } | |
771 | ||
772 | static int vapic_post_load(void *opaque, int version_id) | |
773 | { | |
774 | VAPICROMState *s = opaque; | |
775 | ||
e5ad936b JK |
776 | /* |
777 | * The old implementation of qemu-kvm did not provide the state | |
778 | * VAPIC_STANDBY. Reconstruct it. | |
779 | */ | |
780 | if (s->state == VAPIC_INACTIVE && s->rom_state_paddr != 0) { | |
781 | s->state = VAPIC_STANDBY; | |
782 | } | |
783 | ||
784 | if (s->state != VAPIC_INACTIVE) { | |
785 | if (vapic_prepare(s) < 0) { | |
786 | return -1; | |
787 | } | |
788 | } | |
e5ad936b | 789 | |
5a6e8ba6 PD |
790 | if (!s->vmsentry) { |
791 | s->vmsentry = | |
792 | qemu_add_vm_change_state_handler(kvmvapic_vm_state_change, s); | |
793 | } | |
e5ad936b JK |
794 | return 0; |
795 | } | |
796 | ||
797 | static const VMStateDescription vmstate_handlers = { | |
798 | .name = "kvmvapic-handlers", | |
799 | .version_id = 1, | |
800 | .minimum_version_id = 1, | |
e5ad936b JK |
801 | .fields = (VMStateField[]) { |
802 | VMSTATE_UINT32(set_tpr, VAPICHandlers), | |
803 | VMSTATE_UINT32(set_tpr_eax, VAPICHandlers), | |
804 | VMSTATE_UINT32_ARRAY(get_tpr, VAPICHandlers, 8), | |
805 | VMSTATE_UINT32(get_tpr_stack, VAPICHandlers), | |
806 | VMSTATE_END_OF_LIST() | |
807 | } | |
808 | }; | |
809 | ||
810 | static const VMStateDescription vmstate_guest_rom = { | |
811 | .name = "kvmvapic-guest-rom", | |
812 | .version_id = 1, | |
813 | .minimum_version_id = 1, | |
e5ad936b JK |
814 | .fields = (VMStateField[]) { |
815 | VMSTATE_UNUSED(8), /* signature */ | |
816 | VMSTATE_UINT32(vaddr, GuestROMState), | |
817 | VMSTATE_UINT32(fixup_start, GuestROMState), | |
818 | VMSTATE_UINT32(fixup_end, GuestROMState), | |
819 | VMSTATE_UINT32(vapic_vaddr, GuestROMState), | |
820 | VMSTATE_UINT32(vapic_size, GuestROMState), | |
821 | VMSTATE_UINT32(vcpu_shift, GuestROMState), | |
822 | VMSTATE_UINT32(real_tpr_addr, GuestROMState), | |
823 | VMSTATE_STRUCT(up, GuestROMState, 0, vmstate_handlers, VAPICHandlers), | |
824 | VMSTATE_STRUCT(mp, GuestROMState, 0, vmstate_handlers, VAPICHandlers), | |
825 | VMSTATE_END_OF_LIST() | |
826 | } | |
827 | }; | |
828 | ||
829 | static const VMStateDescription vmstate_vapic = { | |
830 | .name = "kvm-tpr-opt", /* compatible with qemu-kvm VAPIC */ | |
831 | .version_id = 1, | |
832 | .minimum_version_id = 1, | |
e5ad936b JK |
833 | .post_load = vapic_post_load, |
834 | .fields = (VMStateField[]) { | |
835 | VMSTATE_STRUCT(rom_state, VAPICROMState, 0, vmstate_guest_rom, | |
836 | GuestROMState), | |
837 | VMSTATE_UINT32(state, VAPICROMState), | |
838 | VMSTATE_UINT32(real_tpr_addr, VAPICROMState), | |
839 | VMSTATE_UINT32(rom_state_vaddr, VAPICROMState), | |
840 | VMSTATE_UINT32(vapic_paddr, VAPICROMState), | |
841 | VMSTATE_UINT32(rom_state_paddr, VAPICROMState), | |
842 | VMSTATE_END_OF_LIST() | |
843 | } | |
844 | }; | |
845 | ||
846 | static void vapic_class_init(ObjectClass *klass, void *data) | |
847 | { | |
e5ad936b JK |
848 | DeviceClass *dc = DEVICE_CLASS(klass); |
849 | ||
e5ad936b JK |
850 | dc->reset = vapic_reset; |
851 | dc->vmsd = &vmstate_vapic; | |
c118d44b | 852 | dc->realize = vapic_realize; |
e5ad936b JK |
853 | } |
854 | ||
8c43a6f0 | 855 | static const TypeInfo vapic_type = { |
f1fc3e66 | 856 | .name = TYPE_VAPIC, |
e5ad936b JK |
857 | .parent = TYPE_SYS_BUS_DEVICE, |
858 | .instance_size = sizeof(VAPICROMState), | |
859 | .class_init = vapic_class_init, | |
860 | }; | |
861 | ||
862 | static void vapic_register(void) | |
863 | { | |
864 | type_register_static(&vapic_type); | |
865 | } | |
866 | ||
867 | type_init(vapic_register); |