]>
Commit | Line | Data |
---|---|---|
80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
83c9f4ca | 24 | #include "hw/hw.h" |
0d09e41a PB |
25 | #include "hw/i386/pc.h" |
26 | #include "hw/char/serial.h" | |
27 | #include "hw/i386/apic.h" | |
28 | #include "hw/block/fdc.h" | |
83c9f4ca PB |
29 | #include "hw/ide.h" |
30 | #include "hw/pci/pci.h" | |
83c9089e | 31 | #include "monitor/monitor.h" |
0d09e41a PB |
32 | #include "hw/nvram/fw_cfg.h" |
33 | #include "hw/timer/hpet.h" | |
34 | #include "hw/i386/smbios.h" | |
83c9f4ca | 35 | #include "hw/loader.h" |
ca20cf32 | 36 | #include "elf.h" |
47b43a1f | 37 | #include "multiboot.h" |
0d09e41a PB |
38 | #include "hw/timer/mc146818rtc.h" |
39 | #include "hw/timer/i8254.h" | |
40 | #include "hw/audio/pcspk.h" | |
83c9f4ca PB |
41 | #include "hw/pci/msi.h" |
42 | #include "hw/sysbus.h" | |
9c17d615 PB |
43 | #include "sysemu/sysemu.h" |
44 | #include "sysemu/kvm.h" | |
1d31f66b | 45 | #include "kvm_i386.h" |
0d09e41a | 46 | #include "hw/xen/xen.h" |
4be74634 | 47 | #include "sysemu/block-backend.h" |
0d09e41a | 48 | #include "hw/block/block.h" |
a19cbfb3 | 49 | #include "ui/qemu-spice.h" |
022c62cb PB |
50 | #include "exec/memory.h" |
51 | #include "exec/address-spaces.h" | |
9c17d615 | 52 | #include "sysemu/arch_init.h" |
1de7afc9 | 53 | #include "qemu/bitmap.h" |
0c764a9d | 54 | #include "qemu/config-file.h" |
0445259b | 55 | #include "hw/acpi/acpi.h" |
5ff020b7 | 56 | #include "hw/acpi/cpu_hotplug.h" |
53a89e26 | 57 | #include "hw/cpu/icc_bus.h" |
c649983b | 58 | #include "hw/boards.h" |
39848901 | 59 | #include "hw/pci/pci_host.h" |
72c194f7 | 60 | #include "acpi-build.h" |
95bee274 | 61 | #include "hw/mem/pc-dimm.h" |
2e1ac493 | 62 | #include "trace.h" |
bf1e8939 | 63 | #include "qapi/visitor.h" |
80cabfad | 64 | |
471fd342 BS |
65 | /* debug PC/ISA interrupts */ |
66 | //#define DEBUG_IRQ | |
67 | ||
68 | #ifdef DEBUG_IRQ | |
69 | #define DPRINTF(fmt, ...) \ | |
70 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
71 | #else | |
72 | #define DPRINTF(fmt, ...) | |
73 | #endif | |
74 | ||
438f92ee MT |
75 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables |
76 | * (128K) and other BIOS datastructures (less than 4K reported to be used at | |
77 | * the moment, 32K should be enough for a while). */ | |
e0bcc42e | 78 | static unsigned acpi_data_size = 0x20000 + 0x8000; |
927766c7 MT |
79 | void pc_set_legacy_acpi_data_size(void) |
80 | { | |
81 | acpi_data_size = 0x10000; | |
82 | } | |
83 | ||
3cce6243 | 84 | #define BIOS_CFG_IOPORT 0x510 |
8a92ea2f | 85 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 86 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 87 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 88 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 89 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 90 | |
4c5b10b7 JS |
91 | #define E820_NR_ENTRIES 16 |
92 | ||
93 | struct e820_entry { | |
94 | uint64_t address; | |
95 | uint64_t length; | |
96 | uint32_t type; | |
541dc0d4 | 97 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
98 | |
99 | struct e820_table { | |
100 | uint32_t count; | |
101 | struct e820_entry entry[E820_NR_ENTRIES]; | |
541dc0d4 | 102 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 | 103 | |
7d67110f GH |
104 | static struct e820_table e820_reserve; |
105 | static struct e820_entry *e820_table; | |
106 | static unsigned e820_entries; | |
dd703b99 | 107 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 108 | |
b881fbe9 | 109 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 110 | { |
b881fbe9 | 111 | GSIState *s = opaque; |
1452411b | 112 | |
b881fbe9 JK |
113 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
114 | if (n < ISA_NUM_IRQS) { | |
115 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 116 | } |
b881fbe9 | 117 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 118 | } |
1452411b | 119 | |
258711c6 JG |
120 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
121 | unsigned size) | |
80cabfad FB |
122 | { |
123 | } | |
124 | ||
c02e1eac JG |
125 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
126 | { | |
a6fc23e5 | 127 | return 0xffffffffffffffffULL; |
c02e1eac JG |
128 | } |
129 | ||
f929aad6 | 130 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 131 | static qemu_irq ferr_irq; |
8e78eb28 IY |
132 | |
133 | void pc_register_ferr_irq(qemu_irq irq) | |
134 | { | |
135 | ferr_irq = irq; | |
136 | } | |
137 | ||
f929aad6 FB |
138 | /* XXX: add IGNNE support */ |
139 | void cpu_set_ferr(CPUX86State *s) | |
140 | { | |
d537cf6c | 141 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
142 | } |
143 | ||
258711c6 JG |
144 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
145 | unsigned size) | |
f929aad6 | 146 | { |
d537cf6c | 147 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
148 | } |
149 | ||
c02e1eac JG |
150 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
151 | { | |
a6fc23e5 | 152 | return 0xffffffffffffffffULL; |
c02e1eac JG |
153 | } |
154 | ||
28ab0e2e | 155 | /* TSC handling */ |
28ab0e2e FB |
156 | uint64_t cpu_get_tsc(CPUX86State *env) |
157 | { | |
4a1418e0 | 158 | return cpu_get_ticks(); |
28ab0e2e FB |
159 | } |
160 | ||
a5954d5c | 161 | /* SMM support */ |
f885f1ea IY |
162 | |
163 | static cpu_set_smm_t smm_set; | |
164 | static void *smm_arg; | |
165 | ||
166 | void cpu_smm_register(cpu_set_smm_t callback, void *arg) | |
167 | { | |
168 | assert(smm_set == NULL); | |
169 | assert(smm_arg == NULL); | |
170 | smm_set = callback; | |
171 | smm_arg = arg; | |
172 | } | |
173 | ||
4a8fa5dc | 174 | void cpu_smm_update(CPUX86State *env) |
a5954d5c | 175 | { |
182735ef | 176 | if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { |
f885f1ea | 177 | smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); |
182735ef | 178 | } |
a5954d5c FB |
179 | } |
180 | ||
181 | ||
3de388f6 | 182 | /* IRQ handling */ |
4a8fa5dc | 183 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 | 184 | { |
02e51483 | 185 | X86CPU *cpu = x86_env_get_cpu(env); |
3de388f6 FB |
186 | int intno; |
187 | ||
02e51483 | 188 | intno = apic_get_interrupt(cpu->apic_state); |
3de388f6 | 189 | if (intno >= 0) { |
3de388f6 FB |
190 | return intno; |
191 | } | |
3de388f6 | 192 | /* read the irq from the PIC */ |
02e51483 | 193 | if (!apic_accept_pic_intr(cpu->apic_state)) { |
0e21e12b | 194 | return -1; |
cf6d64bf | 195 | } |
0e21e12b | 196 | |
3de388f6 FB |
197 | intno = pic_read_irq(isa_pic); |
198 | return intno; | |
199 | } | |
200 | ||
d537cf6c | 201 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 202 | { |
182735ef AF |
203 | CPUState *cs = first_cpu; |
204 | X86CPU *cpu = X86_CPU(cs); | |
a5b38b51 | 205 | |
471fd342 | 206 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
02e51483 | 207 | if (cpu->apic_state) { |
bdc44640 | 208 | CPU_FOREACH(cs) { |
182735ef | 209 | cpu = X86_CPU(cs); |
02e51483 CF |
210 | if (apic_accept_pic_intr(cpu->apic_state)) { |
211 | apic_deliver_pic_intr(cpu->apic_state, level); | |
cf6d64bf | 212 | } |
d5529471 AJ |
213 | } |
214 | } else { | |
d8ed887b | 215 | if (level) { |
c3affe56 | 216 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
d8ed887b AF |
217 | } else { |
218 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
219 | } | |
a5b38b51 | 220 | } |
3de388f6 FB |
221 | } |
222 | ||
b0a21b53 FB |
223 | /* PC cmos mappings */ |
224 | ||
80cabfad FB |
225 | #define REG_EQUIPMENT_BYTE 0x14 |
226 | ||
d288c7ba | 227 | static int cmos_get_fd_drive_type(FDriveType fd0) |
777428f2 FB |
228 | { |
229 | int val; | |
230 | ||
231 | switch (fd0) { | |
d288c7ba | 232 | case FDRIVE_DRV_144: |
777428f2 FB |
233 | /* 1.44 Mb 3"5 drive */ |
234 | val = 4; | |
235 | break; | |
d288c7ba | 236 | case FDRIVE_DRV_288: |
777428f2 FB |
237 | /* 2.88 Mb 3"5 drive */ |
238 | val = 5; | |
239 | break; | |
d288c7ba | 240 | case FDRIVE_DRV_120: |
777428f2 FB |
241 | /* 1.2 Mb 5"5 drive */ |
242 | val = 2; | |
243 | break; | |
d288c7ba | 244 | case FDRIVE_DRV_NONE: |
777428f2 FB |
245 | default: |
246 | val = 0; | |
247 | break; | |
248 | } | |
249 | return val; | |
250 | } | |
251 | ||
9139046c MA |
252 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
253 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 254 | { |
ba6c2377 FB |
255 | rtc_set_memory(s, type_ofs, 47); |
256 | rtc_set_memory(s, info_ofs, cylinders); | |
257 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
258 | rtc_set_memory(s, info_ofs + 2, heads); | |
259 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
260 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
261 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
262 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
263 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
264 | rtc_set_memory(s, info_ofs + 8, sectors); | |
265 | } | |
266 | ||
6ac0e82d AZ |
267 | /* convert boot_device letter to something recognizable by the bios */ |
268 | static int boot_device2nibble(char boot_device) | |
269 | { | |
270 | switch(boot_device) { | |
271 | case 'a': | |
272 | case 'b': | |
273 | return 0x01; /* floppy boot */ | |
274 | case 'c': | |
275 | return 0x02; /* hard drive boot */ | |
276 | case 'd': | |
277 | return 0x03; /* CD-ROM boot */ | |
278 | case 'n': | |
279 | return 0x04; /* Network boot */ | |
280 | } | |
281 | return 0; | |
282 | } | |
283 | ||
e1123015 | 284 | static int set_boot_dev(ISADevice *s, const char *boot_device) |
0ecdffbb AJ |
285 | { |
286 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
287 | int nbds, bds[3] = { 0, }; |
288 | int i; | |
289 | ||
290 | nbds = strlen(boot_device); | |
291 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
1ecda02b | 292 | error_report("Too many boot devices for PC"); |
0ecdffbb AJ |
293 | return(1); |
294 | } | |
295 | for (i = 0; i < nbds; i++) { | |
296 | bds[i] = boot_device2nibble(boot_device[i]); | |
297 | if (bds[i] == 0) { | |
1ecda02b MA |
298 | error_report("Invalid boot device for PC: '%c'", |
299 | boot_device[i]); | |
0ecdffbb AJ |
300 | return(1); |
301 | } | |
302 | } | |
303 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 304 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
305 | return(0); |
306 | } | |
307 | ||
d9346e81 MA |
308 | static int pc_boot_set(void *opaque, const char *boot_device) |
309 | { | |
e1123015 | 310 | return set_boot_dev(opaque, boot_device); |
d9346e81 MA |
311 | } |
312 | ||
c0897e0c MA |
313 | typedef struct pc_cmos_init_late_arg { |
314 | ISADevice *rtc_state; | |
9139046c | 315 | BusState *idebus[2]; |
c0897e0c MA |
316 | } pc_cmos_init_late_arg; |
317 | ||
318 | static void pc_cmos_init_late(void *opaque) | |
319 | { | |
320 | pc_cmos_init_late_arg *arg = opaque; | |
321 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
322 | int16_t cylinders; |
323 | int8_t heads, sectors; | |
c0897e0c | 324 | int val; |
2adc99b2 | 325 | int i, trans; |
c0897e0c | 326 | |
9139046c MA |
327 | val = 0; |
328 | if (ide_get_geometry(arg->idebus[0], 0, | |
329 | &cylinders, &heads, §ors) >= 0) { | |
330 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); | |
331 | val |= 0xf0; | |
332 | } | |
333 | if (ide_get_geometry(arg->idebus[0], 1, | |
334 | &cylinders, &heads, §ors) >= 0) { | |
335 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); | |
336 | val |= 0x0f; | |
337 | } | |
338 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
339 | |
340 | val = 0; | |
341 | for (i = 0; i < 4; i++) { | |
9139046c MA |
342 | /* NOTE: ide_get_geometry() returns the physical |
343 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
344 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
345 | geometry can be different if a translation is done. */ | |
346 | if (ide_get_geometry(arg->idebus[i / 2], i % 2, | |
347 | &cylinders, &heads, §ors) >= 0) { | |
2adc99b2 MA |
348 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
349 | assert((trans & ~3) == 0); | |
350 | val |= trans << (i * 2); | |
c0897e0c MA |
351 | } |
352 | } | |
353 | rtc_set_memory(s, 0x39, val); | |
354 | ||
355 | qemu_unregister_reset(pc_cmos_init_late, opaque); | |
356 | } | |
357 | ||
b8b7456d IM |
358 | typedef struct RTCCPUHotplugArg { |
359 | Notifier cpu_added_notifier; | |
360 | ISADevice *rtc_state; | |
361 | } RTCCPUHotplugArg; | |
362 | ||
363 | static void rtc_notify_cpu_added(Notifier *notifier, void *data) | |
364 | { | |
365 | RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg, | |
366 | cpu_added_notifier); | |
367 | ISADevice *s = arg->rtc_state; | |
368 | ||
369 | /* increment the number of CPUs */ | |
370 | rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1); | |
371 | } | |
372 | ||
845773ab | 373 | void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
c0897e0c | 374 | const char *boot_device, |
34d4260e | 375 | ISADevice *floppy, BusState *idebus0, BusState *idebus1, |
63ffb564 | 376 | ISADevice *s) |
80cabfad | 377 | { |
61a8d649 | 378 | int val, nb, i; |
980bda8b | 379 | FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; |
c0897e0c | 380 | static pc_cmos_init_late_arg arg; |
b8b7456d | 381 | static RTCCPUHotplugArg cpu_hotplug_cb; |
b0a21b53 | 382 | |
b0a21b53 | 383 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
384 | |
385 | /* memory size */ | |
e89001f7 MA |
386 | /* base memory (first MiB) */ |
387 | val = MIN(ram_size / 1024, 640); | |
333190eb FB |
388 | rtc_set_memory(s, 0x15, val); |
389 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 MA |
390 | /* extended memory (next 64MiB) */ |
391 | if (ram_size > 1024 * 1024) { | |
392 | val = (ram_size - 1024 * 1024) / 1024; | |
393 | } else { | |
394 | val = 0; | |
395 | } | |
80cabfad FB |
396 | if (val > 65535) |
397 | val = 65535; | |
b0a21b53 FB |
398 | rtc_set_memory(s, 0x17, val); |
399 | rtc_set_memory(s, 0x18, val >> 8); | |
400 | rtc_set_memory(s, 0x30, val); | |
401 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 MA |
402 | /* memory between 16MiB and 4GiB */ |
403 | if (ram_size > 16 * 1024 * 1024) { | |
404 | val = (ram_size - 16 * 1024 * 1024) / 65536; | |
405 | } else { | |
9da98861 | 406 | val = 0; |
e89001f7 | 407 | } |
80cabfad FB |
408 | if (val > 65535) |
409 | val = 65535; | |
b0a21b53 FB |
410 | rtc_set_memory(s, 0x34, val); |
411 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 MA |
412 | /* memory above 4GiB */ |
413 | val = above_4g_mem_size / 65536; | |
414 | rtc_set_memory(s, 0x5b, val); | |
415 | rtc_set_memory(s, 0x5c, val >> 8); | |
416 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 417 | |
298e01b6 AJ |
418 | /* set the number of CPU */ |
419 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
b8b7456d IM |
420 | /* init CPU hotplug notifier */ |
421 | cpu_hotplug_cb.rtc_state = s; | |
422 | cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added; | |
423 | qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier); | |
298e01b6 | 424 | |
e1123015 | 425 | if (set_boot_dev(s, boot_device)) { |
28c5af54 JM |
426 | exit(1); |
427 | } | |
80cabfad | 428 | |
b41a2cd1 | 429 | /* floppy type */ |
34d4260e | 430 | if (floppy) { |
34d4260e | 431 | for (i = 0; i < 2; i++) { |
61a8d649 | 432 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); |
63ffb564 BS |
433 | } |
434 | } | |
435 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
436 | cmos_get_fd_drive_type(fd_type[1]); | |
b0a21b53 | 437 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 438 | |
b0a21b53 | 439 | val = 0; |
b41a2cd1 | 440 | nb = 0; |
63ffb564 | 441 | if (fd_type[0] < FDRIVE_DRV_NONE) { |
80cabfad | 442 | nb++; |
d288c7ba | 443 | } |
63ffb564 | 444 | if (fd_type[1] < FDRIVE_DRV_NONE) { |
80cabfad | 445 | nb++; |
d288c7ba | 446 | } |
80cabfad FB |
447 | switch (nb) { |
448 | case 0: | |
449 | break; | |
450 | case 1: | |
b0a21b53 | 451 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
452 | break; |
453 | case 2: | |
b0a21b53 | 454 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
455 | break; |
456 | } | |
b0a21b53 FB |
457 | val |= 0x02; /* FPU is there */ |
458 | val |= 0x04; /* PS/2 mouse installed */ | |
459 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
460 | ||
ba6c2377 | 461 | /* hard drives */ |
c0897e0c | 462 | arg.rtc_state = s; |
9139046c MA |
463 | arg.idebus[0] = idebus0; |
464 | arg.idebus[1] = idebus1; | |
c0897e0c | 465 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
466 | } |
467 | ||
a0881c64 AF |
468 | #define TYPE_PORT92 "port92" |
469 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
470 | ||
4b78a802 BS |
471 | /* port 92 stuff: could be split off */ |
472 | typedef struct Port92State { | |
a0881c64 AF |
473 | ISADevice parent_obj; |
474 | ||
23af670e | 475 | MemoryRegion io; |
4b78a802 BS |
476 | uint8_t outport; |
477 | qemu_irq *a20_out; | |
478 | } Port92State; | |
479 | ||
93ef4192 AG |
480 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, |
481 | unsigned size) | |
4b78a802 BS |
482 | { |
483 | Port92State *s = opaque; | |
4700a316 | 484 | int oldval = s->outport; |
4b78a802 | 485 | |
c5539cb4 | 486 | DPRINTF("port92: write 0x%02" PRIx64 "\n", val); |
4b78a802 BS |
487 | s->outport = val; |
488 | qemu_set_irq(*s->a20_out, (val >> 1) & 1); | |
4700a316 | 489 | if ((val & 1) && !(oldval & 1)) { |
4b78a802 BS |
490 | qemu_system_reset_request(); |
491 | } | |
492 | } | |
493 | ||
93ef4192 AG |
494 | static uint64_t port92_read(void *opaque, hwaddr addr, |
495 | unsigned size) | |
4b78a802 BS |
496 | { |
497 | Port92State *s = opaque; | |
498 | uint32_t ret; | |
499 | ||
500 | ret = s->outport; | |
501 | DPRINTF("port92: read 0x%02x\n", ret); | |
502 | return ret; | |
503 | } | |
504 | ||
505 | static void port92_init(ISADevice *dev, qemu_irq *a20_out) | |
506 | { | |
a0881c64 | 507 | Port92State *s = PORT92(dev); |
4b78a802 BS |
508 | |
509 | s->a20_out = a20_out; | |
510 | } | |
511 | ||
512 | static const VMStateDescription vmstate_port92_isa = { | |
513 | .name = "port92", | |
514 | .version_id = 1, | |
515 | .minimum_version_id = 1, | |
d49805ae | 516 | .fields = (VMStateField[]) { |
4b78a802 BS |
517 | VMSTATE_UINT8(outport, Port92State), |
518 | VMSTATE_END_OF_LIST() | |
519 | } | |
520 | }; | |
521 | ||
522 | static void port92_reset(DeviceState *d) | |
523 | { | |
a0881c64 | 524 | Port92State *s = PORT92(d); |
4b78a802 BS |
525 | |
526 | s->outport &= ~1; | |
527 | } | |
528 | ||
23af670e | 529 | static const MemoryRegionOps port92_ops = { |
93ef4192 AG |
530 | .read = port92_read, |
531 | .write = port92_write, | |
532 | .impl = { | |
533 | .min_access_size = 1, | |
534 | .max_access_size = 1, | |
535 | }, | |
536 | .endianness = DEVICE_LITTLE_ENDIAN, | |
23af670e RH |
537 | }; |
538 | ||
db895a1e | 539 | static void port92_initfn(Object *obj) |
4b78a802 | 540 | { |
db895a1e | 541 | Port92State *s = PORT92(obj); |
4b78a802 | 542 | |
1437c94b | 543 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); |
23af670e | 544 | |
4b78a802 | 545 | s->outport = 0; |
db895a1e AF |
546 | } |
547 | ||
548 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
549 | { | |
550 | ISADevice *isadev = ISA_DEVICE(dev); | |
551 | Port92State *s = PORT92(dev); | |
552 | ||
553 | isa_register_ioport(isadev, &s->io, 0x92); | |
4b78a802 BS |
554 | } |
555 | ||
8f04ee08 AL |
556 | static void port92_class_initfn(ObjectClass *klass, void *data) |
557 | { | |
39bffca2 | 558 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e | 559 | |
db895a1e | 560 | dc->realize = port92_realizefn; |
39bffca2 AL |
561 | dc->reset = port92_reset; |
562 | dc->vmsd = &vmstate_port92_isa; | |
f3b17640 MA |
563 | /* |
564 | * Reason: unlike ordinary ISA devices, this one needs additional | |
565 | * wiring: its A20 output line needs to be wired up by | |
566 | * port92_init(). | |
567 | */ | |
568 | dc->cannot_instantiate_with_device_add_yet = true; | |
8f04ee08 AL |
569 | } |
570 | ||
8c43a6f0 | 571 | static const TypeInfo port92_info = { |
a0881c64 | 572 | .name = TYPE_PORT92, |
39bffca2 AL |
573 | .parent = TYPE_ISA_DEVICE, |
574 | .instance_size = sizeof(Port92State), | |
db895a1e | 575 | .instance_init = port92_initfn, |
39bffca2 | 576 | .class_init = port92_class_initfn, |
4b78a802 BS |
577 | }; |
578 | ||
83f7d43a | 579 | static void port92_register_types(void) |
4b78a802 | 580 | { |
39bffca2 | 581 | type_register_static(&port92_info); |
4b78a802 | 582 | } |
83f7d43a AF |
583 | |
584 | type_init(port92_register_types) | |
4b78a802 | 585 | |
956a3e6b | 586 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 587 | { |
cc36a7a2 | 588 | X86CPU *cpu = opaque; |
e1a23744 | 589 | |
956a3e6b | 590 | /* XXX: send to all CPUs ? */ |
4b78a802 | 591 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 592 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
593 | } |
594 | ||
4c5b10b7 JS |
595 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
596 | { | |
7d67110f | 597 | int index = le32_to_cpu(e820_reserve.count); |
4c5b10b7 JS |
598 | struct e820_entry *entry; |
599 | ||
7d67110f GH |
600 | if (type != E820_RAM) { |
601 | /* old FW_CFG_E820_TABLE entry -- reservations only */ | |
602 | if (index >= E820_NR_ENTRIES) { | |
603 | return -EBUSY; | |
604 | } | |
605 | entry = &e820_reserve.entry[index++]; | |
606 | ||
607 | entry->address = cpu_to_le64(address); | |
608 | entry->length = cpu_to_le64(length); | |
609 | entry->type = cpu_to_le32(type); | |
610 | ||
611 | e820_reserve.count = cpu_to_le32(index); | |
612 | } | |
4c5b10b7 | 613 | |
7d67110f GH |
614 | /* new "etc/e820" file -- include ram too */ |
615 | e820_table = g_realloc(e820_table, | |
616 | sizeof(struct e820_entry) * (e820_entries+1)); | |
617 | e820_table[e820_entries].address = cpu_to_le64(address); | |
618 | e820_table[e820_entries].length = cpu_to_le64(length); | |
619 | e820_table[e820_entries].type = cpu_to_le32(type); | |
620 | e820_entries++; | |
4c5b10b7 | 621 | |
7d67110f | 622 | return e820_entries; |
4c5b10b7 JS |
623 | } |
624 | ||
7bf8ef19 GS |
625 | int e820_get_num_entries(void) |
626 | { | |
627 | return e820_entries; | |
628 | } | |
629 | ||
630 | bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) | |
631 | { | |
632 | if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { | |
633 | *address = le64_to_cpu(e820_table[idx].address); | |
634 | *length = le64_to_cpu(e820_table[idx].length); | |
635 | return true; | |
636 | } | |
637 | return false; | |
638 | } | |
639 | ||
1d934e89 EH |
640 | /* Calculates the limit to CPU APIC ID values |
641 | * | |
642 | * This function returns the limit for the APIC ID value, so that all | |
643 | * CPU APIC IDs are < pc_apic_id_limit(). | |
644 | * | |
645 | * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). | |
646 | */ | |
647 | static unsigned int pc_apic_id_limit(unsigned int max_cpus) | |
648 | { | |
649 | return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; | |
650 | } | |
651 | ||
a88b362c | 652 | static FWCfgState *bochs_bios_init(void) |
80cabfad | 653 | { |
a88b362c | 654 | FWCfgState *fw_cfg; |
c97294ec GS |
655 | uint8_t *smbios_tables, *smbios_anchor; |
656 | size_t smbios_tables_len, smbios_anchor_len; | |
11c2fd3e AL |
657 | uint64_t *numa_fw_cfg; |
658 | int i, j; | |
1d934e89 | 659 | unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); |
3cce6243 BS |
660 | |
661 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
1d934e89 EH |
662 | /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: |
663 | * | |
664 | * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug | |
665 | * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC | |
666 | * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the | |
667 | * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS | |
668 | * may see". | |
669 | * | |
670 | * So, this means we must not use max_cpus, here, but the maximum possible | |
671 | * APIC ID value, plus one. | |
672 | * | |
673 | * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is | |
674 | * the APIC ID, not the "CPU index" | |
675 | */ | |
676 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); | |
3cce6243 | 677 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); |
905fdcb5 | 678 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
089da572 MA |
679 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, |
680 | acpi_tables, acpi_tables_len); | |
9b5b76d4 | 681 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
b6f6e3d3 | 682 | |
c97294ec GS |
683 | smbios_tables = smbios_get_table_legacy(&smbios_tables_len); |
684 | if (smbios_tables) { | |
b6f6e3d3 | 685 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
c97294ec GS |
686 | smbios_tables, smbios_tables_len); |
687 | } | |
688 | ||
689 | smbios_get_tables(&smbios_tables, &smbios_tables_len, | |
690 | &smbios_anchor, &smbios_anchor_len); | |
691 | if (smbios_anchor) { | |
692 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", | |
693 | smbios_tables, smbios_tables_len); | |
694 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", | |
695 | smbios_anchor, smbios_anchor_len); | |
696 | } | |
697 | ||
089da572 | 698 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, |
7d67110f GH |
699 | &e820_reserve, sizeof(e820_reserve)); |
700 | fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, | |
701 | sizeof(struct e820_entry) * e820_entries); | |
11c2fd3e | 702 | |
089da572 | 703 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); |
11c2fd3e AL |
704 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
705 | * of nodes, one word for each VCPU->node and one word for each node to | |
706 | * hold the amount of memory. | |
707 | */ | |
1d934e89 | 708 | numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); |
11c2fd3e | 709 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
991dfefd | 710 | for (i = 0; i < max_cpus; i++) { |
1d934e89 EH |
711 | unsigned int apic_id = x86_cpu_apic_id_from_index(i); |
712 | assert(apic_id < apic_id_limit); | |
11c2fd3e | 713 | for (j = 0; j < nb_numa_nodes; j++) { |
8c85901e | 714 | if (test_bit(i, numa_info[j].node_cpu)) { |
1d934e89 | 715 | numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); |
11c2fd3e AL |
716 | break; |
717 | } | |
718 | } | |
719 | } | |
720 | for (i = 0; i < nb_numa_nodes; i++) { | |
8c85901e | 721 | numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); |
11c2fd3e | 722 | } |
089da572 | 723 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, |
1d934e89 EH |
724 | (1 + apic_id_limit + nb_numa_nodes) * |
725 | sizeof(*numa_fw_cfg)); | |
bf483392 AG |
726 | |
727 | return fw_cfg; | |
80cabfad FB |
728 | } |
729 | ||
642a4f96 TS |
730 | static long get_file_size(FILE *f) |
731 | { | |
732 | long where, size; | |
733 | ||
734 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
735 | ||
736 | where = ftell(f); | |
737 | fseek(f, 0, SEEK_END); | |
738 | size = ftell(f); | |
739 | fseek(f, where, SEEK_SET); | |
740 | ||
741 | return size; | |
742 | } | |
743 | ||
a88b362c | 744 | static void load_linux(FWCfgState *fw_cfg, |
4fc9af53 | 745 | const char *kernel_filename, |
0f9d76e5 LG |
746 | const char *initrd_filename, |
747 | const char *kernel_cmdline, | |
a8170e5e | 748 | hwaddr max_ram_size) |
642a4f96 TS |
749 | { |
750 | uint16_t protocol; | |
5cea8590 | 751 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
642a4f96 | 752 | uint32_t initrd_max; |
57a46d05 | 753 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
a8170e5e | 754 | hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 755 | FILE *f; |
bf4e5d92 | 756 | char *vmode; |
642a4f96 TS |
757 | |
758 | /* Align to 16 bytes as a paranoia measure */ | |
759 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
760 | ||
761 | /* load the kernel header */ | |
762 | f = fopen(kernel_filename, "rb"); | |
763 | if (!f || !(kernel_size = get_file_size(f)) || | |
0f9d76e5 LG |
764 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
765 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
766 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
767 | kernel_filename, strerror(errno)); | |
768 | exit(1); | |
642a4f96 TS |
769 | } |
770 | ||
771 | /* kernel protocol version */ | |
bc4edd79 | 772 | #if 0 |
642a4f96 | 773 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 774 | #endif |
0f9d76e5 LG |
775 | if (ldl_p(header+0x202) == 0x53726448) { |
776 | protocol = lduw_p(header+0x206); | |
777 | } else { | |
778 | /* This looks like a multiboot kernel. If it is, let's stop | |
779 | treating it like a Linux kernel. */ | |
52001445 | 780 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
0f9d76e5 | 781 | kernel_cmdline, kernel_size, header)) { |
82663ee2 | 782 | return; |
0f9d76e5 LG |
783 | } |
784 | protocol = 0; | |
f16408df | 785 | } |
642a4f96 TS |
786 | |
787 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
0f9d76e5 LG |
788 | /* Low kernel */ |
789 | real_addr = 0x90000; | |
790 | cmdline_addr = 0x9a000 - cmdline_size; | |
791 | prot_addr = 0x10000; | |
642a4f96 | 792 | } else if (protocol < 0x202) { |
0f9d76e5 LG |
793 | /* High but ancient kernel */ |
794 | real_addr = 0x90000; | |
795 | cmdline_addr = 0x9a000 - cmdline_size; | |
796 | prot_addr = 0x100000; | |
642a4f96 | 797 | } else { |
0f9d76e5 LG |
798 | /* High and recent kernel */ |
799 | real_addr = 0x10000; | |
800 | cmdline_addr = 0x20000; | |
801 | prot_addr = 0x100000; | |
642a4f96 TS |
802 | } |
803 | ||
bc4edd79 | 804 | #if 0 |
642a4f96 | 805 | fprintf(stderr, |
0f9d76e5 LG |
806 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
807 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
808 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
809 | real_addr, | |
810 | cmdline_addr, | |
811 | prot_addr); | |
bc4edd79 | 812 | #endif |
642a4f96 TS |
813 | |
814 | /* highest address for loading the initrd */ | |
0f9d76e5 LG |
815 | if (protocol >= 0x203) { |
816 | initrd_max = ldl_p(header+0x22c); | |
817 | } else { | |
818 | initrd_max = 0x37ffffff; | |
819 | } | |
642a4f96 | 820 | |
927766c7 MT |
821 | if (initrd_max >= max_ram_size - acpi_data_size) { |
822 | initrd_max = max_ram_size - acpi_data_size - 1; | |
823 | } | |
642a4f96 | 824 | |
57a46d05 AG |
825 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
826 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
96f80586 | 827 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
642a4f96 TS |
828 | |
829 | if (protocol >= 0x202) { | |
0f9d76e5 | 830 | stl_p(header+0x228, cmdline_addr); |
642a4f96 | 831 | } else { |
0f9d76e5 LG |
832 | stw_p(header+0x20, 0xA33F); |
833 | stw_p(header+0x22, cmdline_addr-real_addr); | |
642a4f96 TS |
834 | } |
835 | ||
bf4e5d92 PT |
836 | /* handle vga= parameter */ |
837 | vmode = strstr(kernel_cmdline, "vga="); | |
838 | if (vmode) { | |
839 | unsigned int video_mode; | |
840 | /* skip "vga=" */ | |
841 | vmode += 4; | |
842 | if (!strncmp(vmode, "normal", 6)) { | |
843 | video_mode = 0xffff; | |
844 | } else if (!strncmp(vmode, "ext", 3)) { | |
845 | video_mode = 0xfffe; | |
846 | } else if (!strncmp(vmode, "ask", 3)) { | |
847 | video_mode = 0xfffd; | |
848 | } else { | |
849 | video_mode = strtol(vmode, NULL, 0); | |
850 | } | |
851 | stw_p(header+0x1fa, video_mode); | |
852 | } | |
853 | ||
642a4f96 | 854 | /* loader type */ |
5cbdb3a3 | 855 | /* High nybble = B reserved for QEMU; low nybble is revision number. |
642a4f96 TS |
856 | If this code is substantially changed, you may want to consider |
857 | incrementing the revision. */ | |
0f9d76e5 LG |
858 | if (protocol >= 0x200) { |
859 | header[0x210] = 0xB0; | |
860 | } | |
642a4f96 TS |
861 | /* heap */ |
862 | if (protocol >= 0x201) { | |
0f9d76e5 LG |
863 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
864 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
642a4f96 TS |
865 | } |
866 | ||
867 | /* load initrd */ | |
868 | if (initrd_filename) { | |
0f9d76e5 LG |
869 | if (protocol < 0x200) { |
870 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
871 | exit(1); | |
872 | } | |
642a4f96 | 873 | |
0f9d76e5 | 874 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 | 875 | if (initrd_size < 0) { |
7454e51d MT |
876 | fprintf(stderr, "qemu: error reading initrd %s: %s\n", |
877 | initrd_filename, strerror(errno)); | |
d6fa4b77 MK |
878 | exit(1); |
879 | } | |
880 | ||
45a50b16 | 881 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 | 882 | |
7267c094 | 883 | initrd_data = g_malloc(initrd_size); |
57a46d05 AG |
884 | load_image(initrd_filename, initrd_data); |
885 | ||
886 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
887 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
888 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 889 | |
0f9d76e5 LG |
890 | stl_p(header+0x218, initrd_addr); |
891 | stl_p(header+0x21c, initrd_size); | |
642a4f96 TS |
892 | } |
893 | ||
45a50b16 | 894 | /* load kernel and setup */ |
642a4f96 | 895 | setup_size = header[0x1f1]; |
0f9d76e5 LG |
896 | if (setup_size == 0) { |
897 | setup_size = 4; | |
898 | } | |
642a4f96 | 899 | setup_size = (setup_size+1)*512; |
45a50b16 | 900 | kernel_size -= setup_size; |
642a4f96 | 901 | |
7267c094 AL |
902 | setup = g_malloc(setup_size); |
903 | kernel = g_malloc(kernel_size); | |
45a50b16 | 904 | fseek(f, 0, SEEK_SET); |
5a41ecc5 KS |
905 | if (fread(setup, 1, setup_size, f) != setup_size) { |
906 | fprintf(stderr, "fread() failed\n"); | |
907 | exit(1); | |
908 | } | |
909 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
910 | fprintf(stderr, "fread() failed\n"); | |
911 | exit(1); | |
912 | } | |
642a4f96 | 913 | fclose(f); |
45a50b16 | 914 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
915 | |
916 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
917 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
918 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
919 | ||
920 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
921 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
922 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
923 | ||
2e55e842 GN |
924 | option_rom[nb_option_roms].name = "linuxboot.bin"; |
925 | option_rom[nb_option_roms].bootindex = 0; | |
57a46d05 | 926 | nb_option_roms++; |
642a4f96 TS |
927 | } |
928 | ||
b41a2cd1 FB |
929 | #define NE2000_NB_MAX 6 |
930 | ||
675d6f82 BS |
931 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
932 | 0x280, 0x380 }; | |
933 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 934 | |
48a18b3c | 935 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
936 | { |
937 | static int nb_ne2k = 0; | |
938 | ||
939 | if (nb_ne2k == NE2000_NB_MAX) | |
940 | return; | |
48a18b3c | 941 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 942 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
943 | nb_ne2k++; |
944 | } | |
945 | ||
92a16d7a | 946 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 | 947 | { |
4917cf44 AF |
948 | if (current_cpu) { |
949 | X86CPU *cpu = X86_CPU(current_cpu); | |
02e51483 | 950 | return cpu->apic_state; |
0e26b7b8 BS |
951 | } else { |
952 | return NULL; | |
953 | } | |
954 | } | |
955 | ||
845773ab | 956 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 957 | { |
c3affe56 | 958 | X86CPU *cpu = opaque; |
53b67b30 BS |
959 | |
960 | if (level) { | |
c3affe56 | 961 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
962 | } |
963 | } | |
964 | ||
62fc403f IM |
965 | static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, |
966 | DeviceState *icc_bridge, Error **errp) | |
31050930 IM |
967 | { |
968 | X86CPU *cpu; | |
969 | Error *local_err = NULL; | |
970 | ||
cd7b87ff AF |
971 | cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err); |
972 | if (local_err != NULL) { | |
973 | error_propagate(errp, local_err); | |
974 | return NULL; | |
31050930 IM |
975 | } |
976 | ||
977 | object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); | |
978 | object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); | |
979 | ||
980 | if (local_err) { | |
31050930 | 981 | error_propagate(errp, local_err); |
cd7b87ff AF |
982 | object_unref(OBJECT(cpu)); |
983 | cpu = NULL; | |
31050930 IM |
984 | } |
985 | return cpu; | |
986 | } | |
987 | ||
c649983b IM |
988 | static const char *current_cpu_model; |
989 | ||
990 | void pc_hot_add_cpu(const int64_t id, Error **errp) | |
991 | { | |
992 | DeviceState *icc_bridge; | |
993 | int64_t apic_id = x86_cpu_apic_id_from_index(id); | |
994 | ||
8de433cb IM |
995 | if (id < 0) { |
996 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
997 | return; | |
998 | } | |
999 | ||
c649983b IM |
1000 | if (cpu_exists(apic_id)) { |
1001 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1002 | ", it already exists", id); | |
1003 | return; | |
1004 | } | |
1005 | ||
1006 | if (id >= max_cpus) { | |
1007 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1008 | ", max allowed: %d", id, max_cpus - 1); | |
1009 | return; | |
1010 | } | |
1011 | ||
5ff020b7 EH |
1012 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { |
1013 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1014 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
1015 | id, apic_id); | |
1016 | return; | |
1017 | } | |
1018 | ||
c649983b IM |
1019 | icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", |
1020 | TYPE_ICC_BRIDGE, NULL)); | |
1021 | pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); | |
1022 | } | |
1023 | ||
62fc403f | 1024 | void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) |
70166477 IY |
1025 | { |
1026 | int i; | |
53a89e26 | 1027 | X86CPU *cpu = NULL; |
31050930 | 1028 | Error *error = NULL; |
f03bd716 | 1029 | unsigned long apic_id_limit; |
70166477 IY |
1030 | |
1031 | /* init CPUs */ | |
1032 | if (cpu_model == NULL) { | |
1033 | #ifdef TARGET_X86_64 | |
1034 | cpu_model = "qemu64"; | |
1035 | #else | |
1036 | cpu_model = "qemu32"; | |
1037 | #endif | |
1038 | } | |
c649983b | 1039 | current_cpu_model = cpu_model; |
70166477 | 1040 | |
f03bd716 EH |
1041 | apic_id_limit = pc_apic_id_limit(max_cpus); |
1042 | if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { | |
1043 | error_report("max_cpus is too large. APIC ID of last CPU is %lu", | |
1044 | apic_id_limit - 1); | |
1045 | exit(1); | |
1046 | } | |
1047 | ||
bdeec802 | 1048 | for (i = 0; i < smp_cpus; i++) { |
53a89e26 IM |
1049 | cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), |
1050 | icc_bridge, &error); | |
31050930 | 1051 | if (error) { |
4a44d85e | 1052 | error_report("%s", error_get_pretty(error)); |
31050930 | 1053 | error_free(error); |
bdeec802 IM |
1054 | exit(1); |
1055 | } | |
70166477 | 1056 | } |
53a89e26 IM |
1057 | |
1058 | /* map APIC MMIO area if CPU has APIC */ | |
02e51483 | 1059 | if (cpu && cpu->apic_state) { |
53a89e26 IM |
1060 | /* XXX: what if the base changes? */ |
1061 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, | |
1062 | APIC_DEFAULT_ADDRESS, 0x1000); | |
1063 | } | |
c97294ec GS |
1064 | |
1065 | /* tell smbios about cpuid version and features */ | |
1066 | smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); | |
70166477 IY |
1067 | } |
1068 | ||
f8c457b8 MT |
1069 | /* pci-info ROM file. Little endian format */ |
1070 | typedef struct PcRomPciInfo { | |
1071 | uint64_t w32_min; | |
1072 | uint64_t w32_max; | |
1073 | uint64_t w64_min; | |
1074 | uint64_t w64_max; | |
1075 | } PcRomPciInfo; | |
1076 | ||
3459a625 MT |
1077 | typedef struct PcGuestInfoState { |
1078 | PcGuestInfo info; | |
1079 | Notifier machine_done; | |
1080 | } PcGuestInfoState; | |
1081 | ||
1082 | static | |
1083 | void pc_guest_info_machine_done(Notifier *notifier, void *data) | |
1084 | { | |
1085 | PcGuestInfoState *guest_info_state = container_of(notifier, | |
1086 | PcGuestInfoState, | |
1087 | machine_done); | |
72c194f7 | 1088 | acpi_setup(&guest_info_state->info); |
3459a625 MT |
1089 | } |
1090 | ||
1091 | PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, | |
1092 | ram_addr_t above_4g_mem_size) | |
1093 | { | |
1094 | PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); | |
1095 | PcGuestInfo *guest_info = &guest_info_state->info; | |
b20c9bd5 MT |
1096 | int i, j; |
1097 | ||
f30ee8a9 | 1098 | guest_info->ram_size_below_4g = below_4g_mem_size; |
b20c9bd5 MT |
1099 | guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; |
1100 | guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); | |
1101 | guest_info->apic_xrupt_override = kvm_allows_irq0_override(); | |
1102 | guest_info->numa_nodes = nb_numa_nodes; | |
8c85901e | 1103 | guest_info->node_mem = g_malloc0(guest_info->numa_nodes * |
b20c9bd5 | 1104 | sizeof *guest_info->node_mem); |
8c85901e WG |
1105 | for (i = 0; i < nb_numa_nodes; i++) { |
1106 | guest_info->node_mem[i] = numa_info[i].node_mem; | |
1107 | } | |
1108 | ||
b20c9bd5 MT |
1109 | guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * |
1110 | sizeof *guest_info->node_cpu); | |
1111 | ||
1112 | for (i = 0; i < max_cpus; i++) { | |
1113 | unsigned int apic_id = x86_cpu_apic_id_from_index(i); | |
1114 | assert(apic_id < guest_info->apic_id_limit); | |
1115 | for (j = 0; j < nb_numa_nodes; j++) { | |
8c85901e | 1116 | if (test_bit(i, numa_info[j].node_cpu)) { |
b20c9bd5 MT |
1117 | guest_info->node_cpu[apic_id] = j; |
1118 | break; | |
1119 | } | |
1120 | } | |
1121 | } | |
3459a625 | 1122 | |
3459a625 MT |
1123 | guest_info_state->machine_done.notify = pc_guest_info_machine_done; |
1124 | qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); | |
1125 | return guest_info; | |
1126 | } | |
1127 | ||
83d08f26 MT |
1128 | /* setup pci memory address space mapping into system address space */ |
1129 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1130 | MemoryRegion *pci_address_space) | |
39848901 | 1131 | { |
83d08f26 MT |
1132 | /* Set to lower priority than RAM */ |
1133 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1134 | pci_address_space, -1); | |
39848901 IM |
1135 | } |
1136 | ||
f7e4dd6c GH |
1137 | void pc_acpi_init(const char *default_dsdt) |
1138 | { | |
c5a98cf3 | 1139 | char *filename; |
f7e4dd6c GH |
1140 | |
1141 | if (acpi_tables != NULL) { | |
1142 | /* manually set via -acpitable, leave it alone */ | |
1143 | return; | |
1144 | } | |
1145 | ||
1146 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); | |
1147 | if (filename == NULL) { | |
1148 | fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); | |
c5a98cf3 LE |
1149 | } else { |
1150 | char *arg; | |
1151 | QemuOpts *opts; | |
1152 | Error *err = NULL; | |
f7e4dd6c | 1153 | |
c5a98cf3 | 1154 | arg = g_strdup_printf("file=%s", filename); |
0c764a9d | 1155 | |
c5a98cf3 LE |
1156 | /* creates a deep copy of "arg" */ |
1157 | opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0); | |
1158 | g_assert(opts != NULL); | |
0c764a9d | 1159 | |
1a4b2666 | 1160 | acpi_table_add_builtin(opts, &err); |
c5a98cf3 | 1161 | if (err) { |
4a44d85e SA |
1162 | error_report("WARNING: failed to load %s: %s", filename, |
1163 | error_get_pretty(err)); | |
c5a98cf3 LE |
1164 | error_free(err); |
1165 | } | |
1166 | g_free(arg); | |
1167 | g_free(filename); | |
f7e4dd6c | 1168 | } |
f7e4dd6c GH |
1169 | } |
1170 | ||
b33a5bbf CL |
1171 | FWCfgState *xen_load_linux(const char *kernel_filename, |
1172 | const char *kernel_cmdline, | |
1173 | const char *initrd_filename, | |
1174 | ram_addr_t below_4g_mem_size, | |
1175 | PcGuestInfo *guest_info) | |
1176 | { | |
1177 | int i; | |
1178 | FWCfgState *fw_cfg; | |
1179 | ||
1180 | assert(kernel_filename != NULL); | |
1181 | ||
1182 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
1183 | rom_set_fw(fw_cfg); | |
1184 | ||
1185 | load_linux(fw_cfg, kernel_filename, initrd_filename, | |
1186 | kernel_cmdline, below_4g_mem_size); | |
1187 | for (i = 0; i < nb_option_roms; i++) { | |
1188 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
1189 | !strcmp(option_rom[i].name, "multiboot.bin")); | |
1190 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1191 | } | |
1192 | guest_info->fw_cfg = fw_cfg; | |
1193 | return fw_cfg; | |
1194 | } | |
1195 | ||
9521d42b PB |
1196 | FWCfgState *pc_memory_init(MachineState *machine, |
1197 | MemoryRegion *system_memory, | |
a88b362c LE |
1198 | ram_addr_t below_4g_mem_size, |
1199 | ram_addr_t above_4g_mem_size, | |
1200 | MemoryRegion *rom_memory, | |
3459a625 MT |
1201 | MemoryRegion **ram_memory, |
1202 | PcGuestInfo *guest_info) | |
80cabfad | 1203 | { |
cbc5b5f3 JJ |
1204 | int linux_boot, i; |
1205 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 1206 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 1207 | FWCfgState *fw_cfg; |
619d11e4 | 1208 | PCMachineState *pcms = PC_MACHINE(machine); |
d592d303 | 1209 | |
9521d42b PB |
1210 | assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size); |
1211 | ||
1212 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 1213 | |
00cb2a99 | 1214 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 1215 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
1216 | * with older qemus that used qemu_ram_alloc(). |
1217 | */ | |
7267c094 | 1218 | ram = g_malloc(sizeof(*ram)); |
9521d42b PB |
1219 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", |
1220 | machine->ram_size); | |
ae0a5466 | 1221 | *ram_memory = ram; |
7267c094 | 1222 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
2c9b15ca | 1223 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, |
00cb2a99 AK |
1224 | 0, below_4g_mem_size); |
1225 | memory_region_add_subregion(system_memory, 0, ram_below_4g); | |
7db16f24 | 1226 | e820_add_entry(0, below_4g_mem_size, E820_RAM); |
bbe80adf | 1227 | if (above_4g_mem_size > 0) { |
7267c094 | 1228 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
2c9b15ca | 1229 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, |
00cb2a99 AK |
1230 | below_4g_mem_size, above_4g_mem_size); |
1231 | memory_region_add_subregion(system_memory, 0x100000000ULL, | |
1232 | ram_above_4g); | |
0624c7f9 | 1233 | e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); |
bbe80adf | 1234 | } |
82b36dc3 | 1235 | |
ca8336f3 IM |
1236 | if (!guest_info->has_reserved_memory && |
1237 | (machine->ram_slots || | |
9521d42b | 1238 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
1239 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
1240 | ||
1241 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1242 | mc->name); | |
1243 | exit(EXIT_FAILURE); | |
1244 | } | |
1245 | ||
619d11e4 | 1246 | /* initialize hotplug memory address space */ |
de268e13 | 1247 | if (guest_info->has_reserved_memory && |
9521d42b | 1248 | (machine->ram_size < machine->maxram_size)) { |
619d11e4 | 1249 | ram_addr_t hotplug_mem_size = |
9521d42b | 1250 | machine->maxram_size - machine->ram_size; |
619d11e4 | 1251 | |
a0cc8856 IM |
1252 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
1253 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1254 | machine->ram_slots); | |
1255 | exit(EXIT_FAILURE); | |
1256 | } | |
1257 | ||
619d11e4 IM |
1258 | pcms->hotplug_memory_base = |
1259 | ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30); | |
1260 | ||
1261 | if ((pcms->hotplug_memory_base + hotplug_mem_size) < | |
1262 | hotplug_mem_size) { | |
1263 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, | |
1264 | machine->maxram_size); | |
1265 | exit(EXIT_FAILURE); | |
1266 | } | |
1267 | ||
1268 | memory_region_init(&pcms->hotplug_memory, OBJECT(pcms), | |
1269 | "hotplug-memory", hotplug_mem_size); | |
1270 | memory_region_add_subregion(system_memory, pcms->hotplug_memory_base, | |
1271 | &pcms->hotplug_memory); | |
1272 | } | |
cbc5b5f3 JJ |
1273 | |
1274 | /* Initialize PC system firmware */ | |
6dd2a5c9 | 1275 | pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); |
00cb2a99 | 1276 | |
7267c094 | 1277 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
49946538 HT |
1278 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
1279 | &error_abort); | |
c5705a77 | 1280 | vmstate_register_ram_global(option_rom_mr); |
4463aee6 | 1281 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1282 | PC_ROM_MIN_VGA, |
1283 | option_rom_mr, | |
1284 | 1); | |
f753ff16 | 1285 | |
bf483392 | 1286 | fw_cfg = bochs_bios_init(); |
8832cb80 | 1287 | rom_set_fw(fw_cfg); |
1d108d97 | 1288 | |
de268e13 IM |
1289 | if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) { |
1290 | uint64_t *val = g_malloc(sizeof(*val)); | |
1291 | *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30)); | |
1292 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); | |
1293 | } | |
1294 | ||
f753ff16 | 1295 | if (linux_boot) { |
9521d42b PB |
1296 | load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename, |
1297 | machine->kernel_cmdline, below_4g_mem_size); | |
f753ff16 PB |
1298 | } |
1299 | ||
1300 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1301 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1302 | } |
3459a625 | 1303 | guest_info->fw_cfg = fw_cfg; |
459ae5ea | 1304 | return fw_cfg; |
3d53f5c3 IY |
1305 | } |
1306 | ||
845773ab IY |
1307 | qemu_irq *pc_allocate_cpu_irq(void) |
1308 | { | |
1309 | return qemu_allocate_irqs(pic_irq_request, NULL, 1); | |
1310 | } | |
1311 | ||
48a18b3c | 1312 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1313 | { |
ad6d45fa AL |
1314 | DeviceState *dev = NULL; |
1315 | ||
16094b75 AJ |
1316 | if (pci_bus) { |
1317 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1318 | dev = pcidev ? &pcidev->qdev : NULL; | |
1319 | } else if (isa_bus) { | |
1320 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 1321 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 1322 | } |
ad6d45fa | 1323 | return dev; |
765d7908 IY |
1324 | } |
1325 | ||
4556bd8b BS |
1326 | static void cpu_request_exit(void *opaque, int irq, int level) |
1327 | { | |
4917cf44 | 1328 | CPUState *cpu = current_cpu; |
4556bd8b | 1329 | |
4917cf44 AF |
1330 | if (cpu && level) { |
1331 | cpu_exit(cpu); | |
4556bd8b BS |
1332 | } |
1333 | } | |
1334 | ||
258711c6 JG |
1335 | static const MemoryRegionOps ioport80_io_ops = { |
1336 | .write = ioport80_write, | |
c02e1eac | 1337 | .read = ioport80_read, |
258711c6 JG |
1338 | .endianness = DEVICE_NATIVE_ENDIAN, |
1339 | .impl = { | |
1340 | .min_access_size = 1, | |
1341 | .max_access_size = 1, | |
1342 | }, | |
1343 | }; | |
1344 | ||
1345 | static const MemoryRegionOps ioportF0_io_ops = { | |
1346 | .write = ioportF0_write, | |
c02e1eac | 1347 | .read = ioportF0_read, |
258711c6 JG |
1348 | .endianness = DEVICE_NATIVE_ENDIAN, |
1349 | .impl = { | |
1350 | .min_access_size = 1, | |
1351 | .max_access_size = 1, | |
1352 | }, | |
1353 | }; | |
1354 | ||
48a18b3c | 1355 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1356 | ISADevice **rtc_state, |
34d4260e | 1357 | ISADevice **floppy, |
7a10ef51 LPF |
1358 | bool no_vmport, |
1359 | uint32 hpet_irqs) | |
ffe513da IY |
1360 | { |
1361 | int i; | |
1362 | DriveInfo *fd[MAX_FD]; | |
ce967e2f JK |
1363 | DeviceState *hpet = NULL; |
1364 | int pit_isa_irq = 0; | |
1365 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1366 | qemu_irq rtc_irq = NULL; |
956a3e6b | 1367 | qemu_irq *a20_line; |
c2d8d311 | 1368 | ISADevice *i8042, *port92, *vmmouse, *pit = NULL; |
4556bd8b | 1369 | qemu_irq *cpu_exit_irq; |
258711c6 JG |
1370 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1371 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1372 | |
2c9b15ca | 1373 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1374 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1375 | |
2c9b15ca | 1376 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1377 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1378 | |
5d17c0d2 JK |
1379 | /* |
1380 | * Check if an HPET shall be created. | |
1381 | * | |
1382 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1383 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1384 | */ | |
1385 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
7a10ef51 | 1386 | /* In order to set property, here not using sysbus_try_create_simple */ |
51116102 | 1387 | hpet = qdev_try_create(NULL, TYPE_HPET); |
dd703b99 | 1388 | if (hpet) { |
7a10ef51 LPF |
1389 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 |
1390 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1391 | * IRQ8 and IRQ2. | |
1392 | */ | |
1393 | uint8_t compat = object_property_get_int(OBJECT(hpet), | |
1394 | HPET_INTCAP, NULL); | |
1395 | if (!compat) { | |
1396 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1397 | } | |
1398 | qdev_init_nofail(hpet); | |
1399 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1400 | ||
b881fbe9 | 1401 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1356b98d | 1402 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
dd703b99 | 1403 | } |
ce967e2f JK |
1404 | pit_isa_irq = -1; |
1405 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1406 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1407 | } |
ffe513da | 1408 | } |
48a18b3c | 1409 | *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1410 | |
1411 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1412 | ||
c2d8d311 SS |
1413 | if (!xen_enabled()) { |
1414 | if (kvm_irqchip_in_kernel()) { | |
1415 | pit = kvm_pit_init(isa_bus, 0x40); | |
1416 | } else { | |
1417 | pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); | |
1418 | } | |
1419 | if (hpet) { | |
1420 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1421 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 SS |
1422 | } |
1423 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1424 | } |
ffe513da IY |
1425 | |
1426 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
1427 | if (serial_hds[i]) { | |
48a18b3c | 1428 | serial_isa_init(isa_bus, i, serial_hds[i]); |
ffe513da IY |
1429 | } |
1430 | } | |
1431 | ||
1432 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
1433 | if (parallel_hds[i]) { | |
48a18b3c | 1434 | parallel_init(isa_bus, i, parallel_hds[i]); |
ffe513da IY |
1435 | } |
1436 | } | |
1437 | ||
182735ef | 1438 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); |
48a18b3c | 1439 | i8042 = isa_create_simple(isa_bus, "i8042"); |
4b78a802 | 1440 | i8042_setup_a20_line(i8042, &a20_line[0]); |
1611977c | 1441 | if (!no_vmport) { |
48a18b3c HP |
1442 | vmport_init(isa_bus); |
1443 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1611977c AP |
1444 | } else { |
1445 | vmmouse = NULL; | |
1446 | } | |
86d86414 | 1447 | if (vmmouse) { |
4a17cc4f AF |
1448 | DeviceState *dev = DEVICE(vmmouse); |
1449 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1450 | qdev_init_nofail(dev); | |
86d86414 | 1451 | } |
48a18b3c | 1452 | port92 = isa_create_simple(isa_bus, "port92"); |
4b78a802 | 1453 | port92_init(port92, &a20_line[1]); |
956a3e6b | 1454 | |
4556bd8b BS |
1455 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
1456 | DMA_init(0, cpu_exit_irq); | |
ffe513da IY |
1457 | |
1458 | for(i = 0; i < MAX_FD; i++) { | |
1459 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1460 | } | |
48a18b3c | 1461 | *floppy = fdctrl_init_isa(isa_bus, fd); |
ffe513da IY |
1462 | } |
1463 | ||
9011a1a7 IY |
1464 | void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) |
1465 | { | |
1466 | int i; | |
1467 | ||
1468 | for (i = 0; i < nb_nics; i++) { | |
1469 | NICInfo *nd = &nd_table[i]; | |
1470 | ||
1471 | if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { | |
1472 | pc_init_ne2k_isa(isa_bus, nd); | |
1473 | } else { | |
29b358f9 | 1474 | pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); |
9011a1a7 IY |
1475 | } |
1476 | } | |
1477 | } | |
1478 | ||
845773ab | 1479 | void pc_pci_device_init(PCIBus *pci_bus) |
e3a5cf42 IY |
1480 | { |
1481 | int max_bus; | |
1482 | int bus; | |
1483 | ||
1484 | max_bus = drive_get_max_bus(IF_SCSI); | |
1485 | for (bus = 0; bus <= max_bus; bus++) { | |
1486 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
1487 | } | |
1488 | } | |
a39e3564 JB |
1489 | |
1490 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) | |
1491 | { | |
1492 | DeviceState *dev; | |
1493 | SysBusDevice *d; | |
1494 | unsigned int i; | |
1495 | ||
1496 | if (kvm_irqchip_in_kernel()) { | |
1497 | dev = qdev_create(NULL, "kvm-ioapic"); | |
1498 | } else { | |
1499 | dev = qdev_create(NULL, "ioapic"); | |
1500 | } | |
1501 | if (parent_name) { | |
1502 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1503 | "ioapic", OBJECT(dev), NULL); | |
1504 | } | |
1505 | qdev_init_nofail(dev); | |
1356b98d | 1506 | d = SYS_BUS_DEVICE(dev); |
3a4a4697 | 1507 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); |
a39e3564 JB |
1508 | |
1509 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1510 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1511 | } | |
1512 | } | |
d5747cac IM |
1513 | |
1514 | static void pc_generic_machine_class_init(ObjectClass *oc, void *data) | |
1515 | { | |
1516 | MachineClass *mc = MACHINE_CLASS(oc); | |
1517 | QEMUMachine *qm = data; | |
1518 | ||
2709f263 | 1519 | mc->family = qm->family; |
d5747cac IM |
1520 | mc->name = qm->name; |
1521 | mc->alias = qm->alias; | |
1522 | mc->desc = qm->desc; | |
1523 | mc->init = qm->init; | |
1524 | mc->reset = qm->reset; | |
1525 | mc->hot_add_cpu = qm->hot_add_cpu; | |
1526 | mc->kvm_type = qm->kvm_type; | |
1527 | mc->block_default_type = qm->block_default_type; | |
16026518 | 1528 | mc->units_per_default_bus = qm->units_per_default_bus; |
d5747cac IM |
1529 | mc->max_cpus = qm->max_cpus; |
1530 | mc->no_serial = qm->no_serial; | |
1531 | mc->no_parallel = qm->no_parallel; | |
1532 | mc->use_virtcon = qm->use_virtcon; | |
1533 | mc->use_sclp = qm->use_sclp; | |
1534 | mc->no_floppy = qm->no_floppy; | |
1535 | mc->no_cdrom = qm->no_cdrom; | |
1536 | mc->no_sdcard = qm->no_sdcard; | |
1537 | mc->is_default = qm->is_default; | |
1538 | mc->default_machine_opts = qm->default_machine_opts; | |
1539 | mc->default_boot_order = qm->default_boot_order; | |
1540 | mc->compat_props = qm->compat_props; | |
1541 | mc->hw_version = qm->hw_version; | |
1542 | } | |
1543 | ||
1544 | void qemu_register_pc_machine(QEMUMachine *m) | |
1545 | { | |
1546 | char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL); | |
1547 | TypeInfo ti = { | |
1548 | .name = name, | |
1549 | .parent = TYPE_PC_MACHINE, | |
1550 | .class_init = pc_generic_machine_class_init, | |
1551 | .class_data = (void *)m, | |
1552 | }; | |
1553 | ||
1554 | type_register(&ti); | |
1555 | g_free(name); | |
1556 | } | |
1557 | ||
95bee274 IM |
1558 | static void pc_dimm_plug(HotplugHandler *hotplug_dev, |
1559 | DeviceState *dev, Error **errp) | |
1560 | { | |
0cd03d89 | 1561 | int slot; |
3fbcdc27 | 1562 | HotplugHandlerClass *hhc; |
95bee274 IM |
1563 | Error *local_err = NULL; |
1564 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
0cd03d89 | 1565 | MachineState *machine = MACHINE(hotplug_dev); |
95bee274 IM |
1566 | PCDIMMDevice *dimm = PC_DIMM(dev); |
1567 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
1568 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
1569 | uint64_t addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, | |
1570 | &local_err); | |
1571 | if (local_err) { | |
1572 | goto out; | |
1573 | } | |
1574 | ||
0b312571 IM |
1575 | addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base, |
1576 | memory_region_size(&pcms->hotplug_memory), | |
1577 | !addr ? NULL : &addr, | |
1578 | memory_region_size(mr), &local_err); | |
1579 | if (local_err) { | |
1580 | goto out; | |
1581 | } | |
0cd03d89 | 1582 | |
0b312571 | 1583 | object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err); |
0cd03d89 IM |
1584 | if (local_err) { |
1585 | goto out; | |
1586 | } | |
2e1ac493 | 1587 | trace_mhp_pc_dimm_assigned_address(addr); |
0cd03d89 IM |
1588 | |
1589 | slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err); | |
1590 | if (local_err) { | |
1591 | goto out; | |
1592 | } | |
1593 | ||
1594 | slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, | |
1595 | machine->ram_slots, &local_err); | |
1596 | if (local_err) { | |
1597 | goto out; | |
1598 | } | |
1599 | object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err); | |
1600 | if (local_err) { | |
1601 | goto out; | |
1602 | } | |
2e1ac493 | 1603 | trace_mhp_pc_dimm_assigned_slot(slot); |
0b312571 | 1604 | |
3fbcdc27 IM |
1605 | if (!pcms->acpi_dev) { |
1606 | error_setg(&local_err, | |
1607 | "memory hotplug is not enabled: missing acpi device"); | |
1608 | goto out; | |
1609 | } | |
1610 | ||
95bee274 IM |
1611 | memory_region_add_subregion(&pcms->hotplug_memory, |
1612 | addr - pcms->hotplug_memory_base, mr); | |
1613 | vmstate_register_ram(mr, dev); | |
3fbcdc27 IM |
1614 | |
1615 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1616 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
95bee274 IM |
1617 | out: |
1618 | error_propagate(errp, local_err); | |
1619 | } | |
1620 | ||
1621 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, | |
1622 | DeviceState *dev, Error **errp) | |
1623 | { | |
1624 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
1625 | pc_dimm_plug(hotplug_dev, dev, errp); | |
1626 | } | |
1627 | } | |
1628 | ||
1629 | static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, | |
1630 | DeviceState *dev) | |
1631 | { | |
1632 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); | |
1633 | ||
1634 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
1635 | return HOTPLUG_HANDLER(machine); | |
1636 | } | |
1637 | ||
1638 | return pcmc->get_hotplug_handler ? | |
1639 | pcmc->get_hotplug_handler(machine, dev) : NULL; | |
1640 | } | |
1641 | ||
bf1e8939 IM |
1642 | static void |
1643 | pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, | |
1644 | const char *name, Error **errp) | |
1645 | { | |
1646 | PCMachineState *pcms = PC_MACHINE(obj); | |
1647 | int64_t value = memory_region_size(&pcms->hotplug_memory); | |
1648 | ||
1649 | visit_type_int(v, &value, name, errp); | |
1650 | } | |
1651 | ||
c87b1520 DS |
1652 | static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, |
1653 | void *opaque, const char *name, | |
1654 | Error **errp) | |
1655 | { | |
1656 | PCMachineState *pcms = PC_MACHINE(obj); | |
1657 | uint64_t value = pcms->max_ram_below_4g; | |
1658 | ||
1659 | visit_type_size(v, &value, name, errp); | |
1660 | } | |
1661 | ||
1662 | static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, | |
1663 | void *opaque, const char *name, | |
1664 | Error **errp) | |
1665 | { | |
1666 | PCMachineState *pcms = PC_MACHINE(obj); | |
1667 | Error *error = NULL; | |
1668 | uint64_t value; | |
1669 | ||
1670 | visit_type_size(v, &value, name, &error); | |
1671 | if (error) { | |
1672 | error_propagate(errp, error); | |
1673 | return; | |
1674 | } | |
1675 | if (value > (1ULL << 32)) { | |
1676 | error_set(&error, ERROR_CLASS_GENERIC_ERROR, | |
1677 | "Machine option 'max-ram-below-4g=%"PRIu64 | |
1678 | "' expects size less than or equal to 4G", value); | |
1679 | error_propagate(errp, error); | |
1680 | return; | |
1681 | } | |
1682 | ||
1683 | if (value < (1ULL << 20)) { | |
1684 | error_report("Warning: small max_ram_below_4g(%"PRIu64 | |
1685 | ") less than 1M. BIOS may not work..", | |
1686 | value); | |
1687 | } | |
1688 | ||
1689 | pcms->max_ram_below_4g = value; | |
1690 | } | |
1691 | ||
bf1e8939 IM |
1692 | static void pc_machine_initfn(Object *obj) |
1693 | { | |
c87b1520 DS |
1694 | PCMachineState *pcms = PC_MACHINE(obj); |
1695 | ||
bf1e8939 IM |
1696 | object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", |
1697 | pc_machine_get_hotplug_memory_region_size, | |
1698 | NULL, NULL, NULL, NULL); | |
c87b1520 DS |
1699 | pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ |
1700 | object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", | |
1701 | pc_machine_get_max_ram_below_4g, | |
1702 | pc_machine_set_max_ram_below_4g, | |
1703 | NULL, NULL, NULL); | |
bf1e8939 IM |
1704 | } |
1705 | ||
95bee274 IM |
1706 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
1707 | { | |
1708 | MachineClass *mc = MACHINE_CLASS(oc); | |
1709 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
1710 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
1711 | ||
1712 | pcmc->get_hotplug_handler = mc->get_hotplug_handler; | |
1713 | mc->get_hotplug_handler = pc_get_hotpug_handler; | |
1714 | hc->plug = pc_machine_device_plug_cb; | |
1715 | } | |
1716 | ||
d5747cac IM |
1717 | static const TypeInfo pc_machine_info = { |
1718 | .name = TYPE_PC_MACHINE, | |
1719 | .parent = TYPE_MACHINE, | |
1720 | .abstract = true, | |
1721 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 1722 | .instance_init = pc_machine_initfn, |
d5747cac | 1723 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
1724 | .class_init = pc_machine_class_init, |
1725 | .interfaces = (InterfaceInfo[]) { | |
1726 | { TYPE_HOTPLUG_HANDLER }, | |
1727 | { } | |
1728 | }, | |
d5747cac IM |
1729 | }; |
1730 | ||
1731 | static void pc_machine_register_types(void) | |
1732 | { | |
1733 | type_register_static(&pc_machine_info); | |
1734 | } | |
1735 | ||
1736 | type_init(pc_machine_register_types) |