]>
Commit | Line | Data |
---|---|---|
80cabfad FB |
1 | /* |
2 | * QEMU 8259 interrupt controller emulation | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
80cabfad FB |
24 | #include "vl.h" |
25 | ||
26 | /* debug PIC */ | |
27 | //#define DEBUG_PIC | |
28 | ||
b41a2cd1 | 29 | //#define DEBUG_IRQ_LATENCY |
4a0fb71e | 30 | //#define DEBUG_IRQ_COUNT |
b41a2cd1 | 31 | |
80cabfad FB |
32 | typedef struct PicState { |
33 | uint8_t last_irr; /* edge detection */ | |
34 | uint8_t irr; /* interrupt request register */ | |
35 | uint8_t imr; /* interrupt mask register */ | |
36 | uint8_t isr; /* interrupt service register */ | |
37 | uint8_t priority_add; /* highest irq priority */ | |
38 | uint8_t irq_base; | |
39 | uint8_t read_reg_select; | |
40 | uint8_t poll; | |
41 | uint8_t special_mask; | |
42 | uint8_t init_state; | |
43 | uint8_t auto_eoi; | |
44 | uint8_t rotate_on_auto_eoi; | |
45 | uint8_t special_fully_nested_mode; | |
46 | uint8_t init4; /* true if 4 byte init */ | |
660de336 FB |
47 | uint8_t elcr; /* PIIX edge/trigger selection*/ |
48 | uint8_t elcr_mask; | |
80cabfad FB |
49 | } PicState; |
50 | ||
51 | /* 0 is master pic, 1 is slave pic */ | |
ba91cd80 | 52 | static PicState pics[2]; |
80cabfad | 53 | |
4a0fb71e FB |
54 | #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT) |
55 | static int irq_level[16]; | |
56 | #endif | |
57 | #ifdef DEBUG_IRQ_COUNT | |
58 | static uint64_t irq_count[16]; | |
59 | #endif | |
60 | ||
80cabfad FB |
61 | /* set irq level. If an edge is detected, then the IRR is set to 1 */ |
62 | static inline void pic_set_irq1(PicState *s, int irq, int level) | |
63 | { | |
64 | int mask; | |
65 | mask = 1 << irq; | |
660de336 FB |
66 | if (s->elcr & mask) { |
67 | /* level triggered */ | |
68 | if (level) { | |
80cabfad | 69 | s->irr |= mask; |
660de336 FB |
70 | s->last_irr |= mask; |
71 | } else { | |
72 | s->irr &= ~mask; | |
73 | s->last_irr &= ~mask; | |
74 | } | |
80cabfad | 75 | } else { |
660de336 FB |
76 | /* edge triggered */ |
77 | if (level) { | |
78 | if ((s->last_irr & mask) == 0) | |
79 | s->irr |= mask; | |
80 | s->last_irr |= mask; | |
81 | } else { | |
82 | s->last_irr &= ~mask; | |
83 | } | |
80cabfad FB |
84 | } |
85 | } | |
86 | ||
87 | /* return the highest priority found in mask (highest = smallest | |
88 | number). Return 8 if no irq */ | |
89 | static inline int get_priority(PicState *s, int mask) | |
90 | { | |
91 | int priority; | |
92 | if (mask == 0) | |
93 | return 8; | |
94 | priority = 0; | |
95 | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) | |
96 | priority++; | |
97 | return priority; | |
98 | } | |
99 | ||
100 | /* return the pic wanted interrupt. return -1 if none */ | |
101 | static int pic_get_irq(PicState *s) | |
102 | { | |
103 | int mask, cur_priority, priority; | |
104 | ||
105 | mask = s->irr & ~s->imr; | |
106 | priority = get_priority(s, mask); | |
107 | if (priority == 8) | |
108 | return -1; | |
109 | /* compute current priority. If special fully nested mode on the | |
110 | master, the IRQ coming from the slave is not taken into account | |
111 | for the priority computation. */ | |
112 | mask = s->isr; | |
113 | if (s->special_fully_nested_mode && s == &pics[0]) | |
114 | mask &= ~(1 << 2); | |
115 | cur_priority = get_priority(s, mask); | |
116 | if (priority < cur_priority) { | |
117 | /* higher priority found: an irq should be generated */ | |
118 | return (priority + s->priority_add) & 7; | |
119 | } else { | |
120 | return -1; | |
121 | } | |
122 | } | |
123 | ||
124 | /* raise irq to CPU if necessary. must be called every time the active | |
125 | irq may change */ | |
b0a21b53 | 126 | static void pic_update_irq(void) |
80cabfad FB |
127 | { |
128 | int irq2, irq; | |
129 | ||
130 | /* first look at slave pic */ | |
131 | irq2 = pic_get_irq(&pics[1]); | |
132 | if (irq2 >= 0) { | |
133 | /* if irq request by slave pic, signal master PIC */ | |
134 | pic_set_irq1(&pics[0], 2, 1); | |
135 | pic_set_irq1(&pics[0], 2, 0); | |
136 | } | |
137 | /* look at requested irq */ | |
138 | irq = pic_get_irq(&pics[0]); | |
139 | if (irq >= 0) { | |
80cabfad FB |
140 | #if defined(DEBUG_PIC) |
141 | { | |
142 | int i; | |
143 | for(i = 0; i < 2; i++) { | |
144 | printf("pic%d: imr=%x irr=%x padd=%d\n", | |
145 | i, pics[i].imr, pics[i].irr, pics[i].priority_add); | |
146 | ||
147 | } | |
148 | } | |
2444ca41 | 149 | printf("pic: cpu_interrupt\n"); |
80cabfad FB |
150 | #endif |
151 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); | |
152 | } | |
153 | } | |
154 | ||
155 | #ifdef DEBUG_IRQ_LATENCY | |
156 | int64_t irq_time[16]; | |
80cabfad | 157 | #endif |
80cabfad FB |
158 | |
159 | void pic_set_irq(int irq, int level) | |
160 | { | |
4a0fb71e | 161 | #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) |
80cabfad | 162 | if (level != irq_level[irq]) { |
4a0fb71e | 163 | #if defined(DEBUG_PIC) |
80cabfad | 164 | printf("pic_set_irq: irq=%d level=%d\n", irq, level); |
4a0fb71e | 165 | #endif |
80cabfad | 166 | irq_level[irq] = level; |
4a0fb71e FB |
167 | #ifdef DEBUG_IRQ_COUNT |
168 | if (level == 1) | |
169 | irq_count[irq]++; | |
170 | #endif | |
80cabfad FB |
171 | } |
172 | #endif | |
173 | #ifdef DEBUG_IRQ_LATENCY | |
174 | if (level) { | |
2444ca41 | 175 | irq_time[irq] = qemu_get_clock(vm_clock); |
80cabfad FB |
176 | } |
177 | #endif | |
178 | pic_set_irq1(&pics[irq >> 3], irq & 7, level); | |
179 | pic_update_irq(); | |
180 | } | |
181 | ||
182 | /* acknowledge interrupt 'irq' */ | |
183 | static inline void pic_intack(PicState *s, int irq) | |
184 | { | |
185 | if (s->auto_eoi) { | |
186 | if (s->rotate_on_auto_eoi) | |
187 | s->priority_add = (irq + 1) & 7; | |
188 | } else { | |
189 | s->isr |= (1 << irq); | |
190 | } | |
191 | s->irr &= ~(1 << irq); | |
192 | } | |
193 | ||
a541f297 | 194 | int cpu_get_pic_interrupt(CPUState *env) |
80cabfad FB |
195 | { |
196 | int irq, irq2, intno; | |
197 | ||
15aeac38 FB |
198 | /* read the irq from the PIC */ |
199 | ||
200 | irq = pic_get_irq(&pics[0]); | |
201 | if (irq >= 0) { | |
202 | pic_intack(&pics[0], irq); | |
203 | if (irq == 2) { | |
204 | irq2 = pic_get_irq(&pics[1]); | |
205 | if (irq2 >= 0) { | |
206 | pic_intack(&pics[1], irq2); | |
207 | } else { | |
208 | /* spurious IRQ on slave controller */ | |
209 | irq2 = 7; | |
210 | } | |
211 | intno = pics[1].irq_base + irq2; | |
212 | irq = irq2 + 8; | |
213 | } else { | |
214 | intno = pics[0].irq_base + irq; | |
215 | } | |
216 | } else { | |
217 | /* spurious IRQ on host controller */ | |
218 | irq = 7; | |
219 | intno = pics[0].irq_base + irq; | |
220 | } | |
221 | pic_update_irq(); | |
222 | ||
80cabfad FB |
223 | #ifdef DEBUG_IRQ_LATENCY |
224 | printf("IRQ%d latency=%0.3fus\n", | |
225 | irq, | |
2444ca41 | 226 | (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec); |
80cabfad FB |
227 | #endif |
228 | #if defined(DEBUG_PIC) | |
229 | printf("pic_interrupt: irq=%d\n", irq); | |
230 | #endif | |
80cabfad FB |
231 | return intno; |
232 | } | |
233 | ||
b41a2cd1 | 234 | static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 235 | { |
b41a2cd1 | 236 | PicState *s = opaque; |
660de336 | 237 | int priority, cmd, irq, tmp; |
80cabfad FB |
238 | |
239 | #ifdef DEBUG_PIC | |
240 | printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val); | |
241 | #endif | |
80cabfad FB |
242 | addr &= 1; |
243 | if (addr == 0) { | |
244 | if (val & 0x10) { | |
245 | /* init */ | |
660de336 | 246 | tmp = s->elcr_mask; |
80cabfad | 247 | memset(s, 0, sizeof(PicState)); |
660de336 | 248 | s->elcr_mask = tmp; |
b54ad049 FB |
249 | /* deassert a pending interrupt */ |
250 | cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); | |
660de336 | 251 | |
80cabfad FB |
252 | s->init_state = 1; |
253 | s->init4 = val & 1; | |
254 | if (val & 0x02) | |
255 | hw_error("single mode not supported"); | |
256 | if (val & 0x08) | |
257 | hw_error("level sensitive irq not supported"); | |
258 | } else if (val & 0x08) { | |
259 | if (val & 0x04) | |
260 | s->poll = 1; | |
261 | if (val & 0x02) | |
262 | s->read_reg_select = val & 1; | |
263 | if (val & 0x40) | |
264 | s->special_mask = (val >> 5) & 1; | |
265 | } else { | |
266 | cmd = val >> 5; | |
267 | switch(cmd) { | |
268 | case 0: | |
269 | case 4: | |
270 | s->rotate_on_auto_eoi = cmd >> 2; | |
271 | break; | |
272 | case 1: /* end of interrupt */ | |
273 | case 5: | |
274 | priority = get_priority(s, s->isr); | |
275 | if (priority != 8) { | |
276 | irq = (priority + s->priority_add) & 7; | |
277 | s->isr &= ~(1 << irq); | |
278 | if (cmd == 5) | |
279 | s->priority_add = (irq + 1) & 7; | |
280 | pic_update_irq(); | |
281 | } | |
282 | break; | |
283 | case 3: | |
284 | irq = val & 7; | |
285 | s->isr &= ~(1 << irq); | |
286 | pic_update_irq(); | |
287 | break; | |
288 | case 6: | |
289 | s->priority_add = (val + 1) & 7; | |
290 | pic_update_irq(); | |
291 | break; | |
292 | case 7: | |
293 | irq = val & 7; | |
294 | s->isr &= ~(1 << irq); | |
295 | s->priority_add = (irq + 1) & 7; | |
296 | pic_update_irq(); | |
297 | break; | |
298 | default: | |
299 | /* no operation */ | |
300 | break; | |
301 | } | |
302 | } | |
303 | } else { | |
304 | switch(s->init_state) { | |
305 | case 0: | |
306 | /* normal mode */ | |
307 | s->imr = val; | |
308 | pic_update_irq(); | |
309 | break; | |
310 | case 1: | |
311 | s->irq_base = val & 0xf8; | |
312 | s->init_state = 2; | |
313 | break; | |
314 | case 2: | |
315 | if (s->init4) { | |
316 | s->init_state = 3; | |
317 | } else { | |
318 | s->init_state = 0; | |
319 | } | |
320 | break; | |
321 | case 3: | |
322 | s->special_fully_nested_mode = (val >> 4) & 1; | |
323 | s->auto_eoi = (val >> 1) & 1; | |
324 | s->init_state = 0; | |
325 | break; | |
326 | } | |
327 | } | |
328 | } | |
329 | ||
330 | static uint32_t pic_poll_read (PicState *s, uint32_t addr1) | |
331 | { | |
332 | int ret; | |
333 | ||
334 | ret = pic_get_irq(s); | |
335 | if (ret >= 0) { | |
336 | if (addr1 >> 7) { | |
337 | pics[0].isr &= ~(1 << 2); | |
338 | pics[0].irr &= ~(1 << 2); | |
339 | } | |
340 | s->irr &= ~(1 << ret); | |
341 | s->isr &= ~(1 << ret); | |
342 | if (addr1 >> 7 || ret != 2) | |
343 | pic_update_irq(); | |
344 | } else { | |
345 | ret = 0x07; | |
346 | pic_update_irq(); | |
347 | } | |
348 | ||
349 | return ret; | |
350 | } | |
351 | ||
b41a2cd1 | 352 | static uint32_t pic_ioport_read(void *opaque, uint32_t addr1) |
80cabfad | 353 | { |
b41a2cd1 | 354 | PicState *s = opaque; |
80cabfad FB |
355 | unsigned int addr; |
356 | int ret; | |
357 | ||
358 | addr = addr1; | |
80cabfad FB |
359 | addr &= 1; |
360 | if (s->poll) { | |
361 | ret = pic_poll_read(s, addr1); | |
362 | s->poll = 0; | |
363 | } else { | |
364 | if (addr == 0) { | |
365 | if (s->read_reg_select) | |
366 | ret = s->isr; | |
367 | else | |
368 | ret = s->irr; | |
369 | } else { | |
370 | ret = s->imr; | |
371 | } | |
372 | } | |
373 | #ifdef DEBUG_PIC | |
374 | printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret); | |
375 | #endif | |
376 | return ret; | |
377 | } | |
378 | ||
379 | /* memory mapped interrupt status */ | |
380 | uint32_t pic_intack_read(CPUState *env) | |
381 | { | |
382 | int ret; | |
383 | ||
384 | ret = pic_poll_read(&pics[0], 0x00); | |
385 | if (ret == 2) | |
386 | ret = pic_poll_read(&pics[1], 0x80) + 8; | |
387 | /* Prepare for ISR read */ | |
388 | pics[0].read_reg_select = 1; | |
389 | ||
390 | return ret; | |
391 | } | |
392 | ||
660de336 FB |
393 | static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
394 | { | |
395 | PicState *s = opaque; | |
396 | s->elcr = val & s->elcr_mask; | |
397 | } | |
398 | ||
399 | static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1) | |
400 | { | |
401 | PicState *s = opaque; | |
402 | return s->elcr; | |
403 | } | |
404 | ||
b0a21b53 FB |
405 | static void pic_save(QEMUFile *f, void *opaque) |
406 | { | |
407 | PicState *s = opaque; | |
408 | ||
409 | qemu_put_8s(f, &s->last_irr); | |
410 | qemu_put_8s(f, &s->irr); | |
411 | qemu_put_8s(f, &s->imr); | |
412 | qemu_put_8s(f, &s->isr); | |
413 | qemu_put_8s(f, &s->priority_add); | |
414 | qemu_put_8s(f, &s->irq_base); | |
415 | qemu_put_8s(f, &s->read_reg_select); | |
416 | qemu_put_8s(f, &s->poll); | |
417 | qemu_put_8s(f, &s->special_mask); | |
418 | qemu_put_8s(f, &s->init_state); | |
419 | qemu_put_8s(f, &s->auto_eoi); | |
420 | qemu_put_8s(f, &s->rotate_on_auto_eoi); | |
421 | qemu_put_8s(f, &s->special_fully_nested_mode); | |
422 | qemu_put_8s(f, &s->init4); | |
660de336 | 423 | qemu_put_8s(f, &s->elcr); |
b0a21b53 FB |
424 | } |
425 | ||
426 | static int pic_load(QEMUFile *f, void *opaque, int version_id) | |
427 | { | |
428 | PicState *s = opaque; | |
429 | ||
430 | if (version_id != 1) | |
431 | return -EINVAL; | |
432 | ||
433 | qemu_get_8s(f, &s->last_irr); | |
434 | qemu_get_8s(f, &s->irr); | |
435 | qemu_get_8s(f, &s->imr); | |
436 | qemu_get_8s(f, &s->isr); | |
437 | qemu_get_8s(f, &s->priority_add); | |
438 | qemu_get_8s(f, &s->irq_base); | |
439 | qemu_get_8s(f, &s->read_reg_select); | |
440 | qemu_get_8s(f, &s->poll); | |
441 | qemu_get_8s(f, &s->special_mask); | |
442 | qemu_get_8s(f, &s->init_state); | |
443 | qemu_get_8s(f, &s->auto_eoi); | |
444 | qemu_get_8s(f, &s->rotate_on_auto_eoi); | |
445 | qemu_get_8s(f, &s->special_fully_nested_mode); | |
446 | qemu_get_8s(f, &s->init4); | |
660de336 | 447 | qemu_get_8s(f, &s->elcr); |
b0a21b53 FB |
448 | return 0; |
449 | } | |
450 | ||
451 | /* XXX: add generic master/slave system */ | |
660de336 | 452 | static void pic_init1(int io_addr, int elcr_addr, PicState *s) |
b0a21b53 FB |
453 | { |
454 | register_ioport_write(io_addr, 2, 1, pic_ioport_write, s); | |
455 | register_ioport_read(io_addr, 2, 1, pic_ioport_read, s); | |
660de336 FB |
456 | if (elcr_addr >= 0) { |
457 | register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s); | |
458 | register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s); | |
459 | } | |
b0a21b53 FB |
460 | register_savevm("i8259", io_addr, 1, pic_save, pic_load, s); |
461 | } | |
462 | ||
ba91cd80 FB |
463 | void pic_info(void) |
464 | { | |
465 | int i; | |
466 | PicState *s; | |
467 | ||
468 | for(i=0;i<2;i++) { | |
469 | s = &pics[i]; | |
15aeac38 | 470 | term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", |
660de336 | 471 | i, s->irr, s->imr, s->isr, s->priority_add, |
15aeac38 FB |
472 | s->irq_base, s->read_reg_select, s->elcr, |
473 | s->special_fully_nested_mode); | |
ba91cd80 FB |
474 | } |
475 | } | |
476 | ||
4a0fb71e FB |
477 | void irq_info(void) |
478 | { | |
479 | #ifndef DEBUG_IRQ_COUNT | |
480 | term_printf("irq statistic code not compiled.\n"); | |
481 | #else | |
482 | int i; | |
483 | int64_t count; | |
484 | ||
485 | term_printf("IRQ statistics:\n"); | |
486 | for (i = 0; i < 16; i++) { | |
487 | count = irq_count[i]; | |
488 | if (count > 0) | |
489 | term_printf("%2d: %lld\n", i, count); | |
490 | } | |
491 | #endif | |
492 | } | |
ba91cd80 | 493 | |
80cabfad FB |
494 | void pic_init(void) |
495 | { | |
660de336 FB |
496 | pic_init1(0x20, 0x4d0, &pics[0]); |
497 | pic_init1(0xa0, 0x4d1, &pics[1]); | |
498 | pics[0].elcr_mask = 0xf8; | |
499 | pics[1].elcr_mask = 0xde; | |
80cabfad FB |
500 | } |
501 |