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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU 8259 interrupt controller emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pc.h" | |
26 | #include "isa.h" | |
376253ec | 27 | #include "monitor.h" |
0bf9e31a | 28 | #include "qemu-timer.h" |
80cabfad FB |
29 | |
30 | /* debug PIC */ | |
31 | //#define DEBUG_PIC | |
32 | ||
8ac02ff8 BS |
33 | #ifdef DEBUG_PIC |
34 | #define DPRINTF(fmt, ...) \ | |
35 | do { printf("pic: " fmt , ## __VA_ARGS__); } while (0) | |
36 | #else | |
37 | #define DPRINTF(fmt, ...) | |
38 | #endif | |
39 | ||
b41a2cd1 | 40 | //#define DEBUG_IRQ_LATENCY |
4a0fb71e | 41 | //#define DEBUG_IRQ_COUNT |
b41a2cd1 | 42 | |
80cabfad FB |
43 | typedef struct PicState { |
44 | uint8_t last_irr; /* edge detection */ | |
45 | uint8_t irr; /* interrupt request register */ | |
46 | uint8_t imr; /* interrupt mask register */ | |
47 | uint8_t isr; /* interrupt service register */ | |
48 | uint8_t priority_add; /* highest irq priority */ | |
49 | uint8_t irq_base; | |
50 | uint8_t read_reg_select; | |
51 | uint8_t poll; | |
52 | uint8_t special_mask; | |
53 | uint8_t init_state; | |
54 | uint8_t auto_eoi; | |
55 | uint8_t rotate_on_auto_eoi; | |
56 | uint8_t special_fully_nested_mode; | |
57 | uint8_t init4; /* true if 4 byte init */ | |
2053152b | 58 | uint8_t single_mode; /* true if slave pic is not initialized */ |
660de336 FB |
59 | uint8_t elcr; /* PIIX edge/trigger selection*/ |
60 | uint8_t elcr_mask; | |
3de388f6 | 61 | PicState2 *pics_state; |
098d314a RH |
62 | MemoryRegion base_io; |
63 | MemoryRegion elcr_io; | |
80cabfad FB |
64 | } PicState; |
65 | ||
3de388f6 FB |
66 | struct PicState2 { |
67 | /* 0 is master pic, 1 is slave pic */ | |
68 | /* XXX: better separation between the two pics */ | |
69 | PicState pics[2]; | |
d537cf6c | 70 | qemu_irq parent_irq; |
3de388f6 FB |
71 | void *irq_request_opaque; |
72 | }; | |
80cabfad | 73 | |
4a0fb71e FB |
74 | #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT) |
75 | static int irq_level[16]; | |
76 | #endif | |
77 | #ifdef DEBUG_IRQ_COUNT | |
78 | static uint64_t irq_count[16]; | |
79 | #endif | |
fbe3288d | 80 | PicState2 *isa_pic; |
4a0fb71e | 81 | |
80cabfad | 82 | /* set irq level. If an edge is detected, then the IRR is set to 1 */ |
5dcd35e2 | 83 | static void pic_set_irq1(PicState *s, int irq, int level) |
80cabfad FB |
84 | { |
85 | int mask; | |
86 | mask = 1 << irq; | |
660de336 FB |
87 | if (s->elcr & mask) { |
88 | /* level triggered */ | |
89 | if (level) { | |
80cabfad | 90 | s->irr |= mask; |
660de336 FB |
91 | s->last_irr |= mask; |
92 | } else { | |
93 | s->irr &= ~mask; | |
94 | s->last_irr &= ~mask; | |
95 | } | |
80cabfad | 96 | } else { |
660de336 FB |
97 | /* edge triggered */ |
98 | if (level) { | |
99 | if ((s->last_irr & mask) == 0) | |
100 | s->irr |= mask; | |
101 | s->last_irr |= mask; | |
102 | } else { | |
103 | s->last_irr &= ~mask; | |
104 | } | |
80cabfad FB |
105 | } |
106 | } | |
107 | ||
108 | /* return the highest priority found in mask (highest = smallest | |
109 | number). Return 8 if no irq */ | |
5dcd35e2 | 110 | static int get_priority(PicState *s, int mask) |
80cabfad FB |
111 | { |
112 | int priority; | |
113 | if (mask == 0) | |
114 | return 8; | |
115 | priority = 0; | |
116 | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) | |
117 | priority++; | |
118 | return priority; | |
119 | } | |
120 | ||
121 | /* return the pic wanted interrupt. return -1 if none */ | |
122 | static int pic_get_irq(PicState *s) | |
123 | { | |
124 | int mask, cur_priority, priority; | |
125 | ||
126 | mask = s->irr & ~s->imr; | |
127 | priority = get_priority(s, mask); | |
128 | if (priority == 8) | |
129 | return -1; | |
130 | /* compute current priority. If special fully nested mode on the | |
131 | master, the IRQ coming from the slave is not taken into account | |
132 | for the priority computation. */ | |
133 | mask = s->isr; | |
84678711 AZ |
134 | if (s->special_mask) |
135 | mask &= ~s->imr; | |
3de388f6 | 136 | if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) |
80cabfad FB |
137 | mask &= ~(1 << 2); |
138 | cur_priority = get_priority(s, mask); | |
139 | if (priority < cur_priority) { | |
140 | /* higher priority found: an irq should be generated */ | |
141 | return (priority + s->priority_add) & 7; | |
142 | } else { | |
143 | return -1; | |
144 | } | |
145 | } | |
146 | ||
147 | /* raise irq to CPU if necessary. must be called every time the active | |
148 | irq may change */ | |
d96e1737 | 149 | static void pic_update_irq(PicState2 *s) |
80cabfad FB |
150 | { |
151 | int irq2, irq; | |
152 | ||
153 | /* first look at slave pic */ | |
3de388f6 | 154 | irq2 = pic_get_irq(&s->pics[1]); |
80cabfad FB |
155 | if (irq2 >= 0) { |
156 | /* if irq request by slave pic, signal master PIC */ | |
3de388f6 FB |
157 | pic_set_irq1(&s->pics[0], 2, 1); |
158 | pic_set_irq1(&s->pics[0], 2, 0); | |
80cabfad FB |
159 | } |
160 | /* look at requested irq */ | |
3de388f6 | 161 | irq = pic_get_irq(&s->pics[0]); |
80cabfad | 162 | if (irq >= 0) { |
80cabfad FB |
163 | #if defined(DEBUG_PIC) |
164 | { | |
165 | int i; | |
166 | for(i = 0; i < 2; i++) { | |
5fafdf24 TS |
167 | printf("pic%d: imr=%x irr=%x padd=%d\n", |
168 | i, s->pics[i].imr, s->pics[i].irr, | |
3de388f6 | 169 | s->pics[i].priority_add); |
3b46e624 | 170 | |
80cabfad FB |
171 | } |
172 | } | |
2444ca41 | 173 | printf("pic: cpu_interrupt\n"); |
80cabfad | 174 | #endif |
d537cf6c | 175 | qemu_irq_raise(s->parent_irq); |
d96e1737 | 176 | } else { |
d537cf6c | 177 | qemu_irq_lower(s->parent_irq); |
4de9b249 | 178 | } |
80cabfad FB |
179 | } |
180 | ||
181 | #ifdef DEBUG_IRQ_LATENCY | |
182 | int64_t irq_time[16]; | |
80cabfad | 183 | #endif |
80cabfad | 184 | |
9596ebb7 | 185 | static void i8259_set_irq(void *opaque, int irq, int level) |
80cabfad | 186 | { |
3de388f6 FB |
187 | PicState2 *s = opaque; |
188 | ||
4a0fb71e | 189 | #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) |
80cabfad | 190 | if (level != irq_level[irq]) { |
8ac02ff8 | 191 | DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level); |
80cabfad | 192 | irq_level[irq] = level; |
4a0fb71e FB |
193 | #ifdef DEBUG_IRQ_COUNT |
194 | if (level == 1) | |
195 | irq_count[irq]++; | |
196 | #endif | |
80cabfad FB |
197 | } |
198 | #endif | |
199 | #ifdef DEBUG_IRQ_LATENCY | |
200 | if (level) { | |
74475455 | 201 | irq_time[irq] = qemu_get_clock_ns(vm_clock); |
80cabfad FB |
202 | } |
203 | #endif | |
3de388f6 FB |
204 | pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); |
205 | pic_update_irq(s); | |
80cabfad FB |
206 | } |
207 | ||
208 | /* acknowledge interrupt 'irq' */ | |
5dcd35e2 | 209 | static void pic_intack(PicState *s, int irq) |
80cabfad FB |
210 | { |
211 | if (s->auto_eoi) { | |
212 | if (s->rotate_on_auto_eoi) | |
213 | s->priority_add = (irq + 1) & 7; | |
214 | } else { | |
215 | s->isr |= (1 << irq); | |
216 | } | |
0ecf89aa FB |
217 | /* We don't clear a level sensitive interrupt here */ |
218 | if (!(s->elcr & (1 << irq))) | |
219 | s->irr &= ~(1 << irq); | |
80cabfad FB |
220 | } |
221 | ||
3de388f6 | 222 | int pic_read_irq(PicState2 *s) |
80cabfad FB |
223 | { |
224 | int irq, irq2, intno; | |
225 | ||
3de388f6 | 226 | irq = pic_get_irq(&s->pics[0]); |
15aeac38 | 227 | if (irq >= 0) { |
3de388f6 | 228 | pic_intack(&s->pics[0], irq); |
15aeac38 | 229 | if (irq == 2) { |
3de388f6 | 230 | irq2 = pic_get_irq(&s->pics[1]); |
15aeac38 | 231 | if (irq2 >= 0) { |
3de388f6 | 232 | pic_intack(&s->pics[1], irq2); |
15aeac38 FB |
233 | } else { |
234 | /* spurious IRQ on slave controller */ | |
235 | irq2 = 7; | |
236 | } | |
3de388f6 | 237 | intno = s->pics[1].irq_base + irq2; |
7f5b7d3e | 238 | #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY) |
15aeac38 | 239 | irq = irq2 + 8; |
7f5b7d3e | 240 | #endif |
15aeac38 | 241 | } else { |
3de388f6 | 242 | intno = s->pics[0].irq_base + irq; |
15aeac38 FB |
243 | } |
244 | } else { | |
245 | /* spurious IRQ on host controller */ | |
246 | irq = 7; | |
3de388f6 | 247 | intno = s->pics[0].irq_base + irq; |
15aeac38 | 248 | } |
3de388f6 | 249 | pic_update_irq(s); |
3b46e624 | 250 | |
80cabfad | 251 | #ifdef DEBUG_IRQ_LATENCY |
5fafdf24 TS |
252 | printf("IRQ%d latency=%0.3fus\n", |
253 | irq, | |
74475455 | 254 | (double)(qemu_get_clock_ns(vm_clock) - |
6ee093c9 | 255 | irq_time[irq]) * 1000000.0 / get_ticks_per_sec()); |
80cabfad | 256 | #endif |
8ac02ff8 | 257 | DPRINTF("pic_interrupt: irq=%d\n", irq); |
80cabfad FB |
258 | return intno; |
259 | } | |
260 | ||
d7d02e3c FB |
261 | static void pic_reset(void *opaque) |
262 | { | |
263 | PicState *s = opaque; | |
d7d02e3c | 264 | |
3de388f6 FB |
265 | s->last_irr = 0; |
266 | s->irr = 0; | |
267 | s->imr = 0; | |
268 | s->isr = 0; | |
269 | s->priority_add = 0; | |
270 | s->irq_base = 0; | |
271 | s->read_reg_select = 0; | |
272 | s->poll = 0; | |
273 | s->special_mask = 0; | |
274 | s->init_state = 0; | |
275 | s->auto_eoi = 0; | |
276 | s->rotate_on_auto_eoi = 0; | |
277 | s->special_fully_nested_mode = 0; | |
278 | s->init4 = 0; | |
2053152b | 279 | s->single_mode = 0; |
4dbe19e1 | 280 | /* Note: ELCR is not reset */ |
d7d02e3c FB |
281 | } |
282 | ||
098d314a RH |
283 | static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, |
284 | uint64_t val64, unsigned size) | |
80cabfad | 285 | { |
b41a2cd1 | 286 | PicState *s = opaque; |
098d314a RH |
287 | uint32_t addr = addr64; |
288 | uint32_t val = val64; | |
d7d02e3c | 289 | int priority, cmd, irq; |
80cabfad | 290 | |
8ac02ff8 | 291 | DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val); |
80cabfad FB |
292 | if (addr == 0) { |
293 | if (val & 0x10) { | |
294 | /* init */ | |
d7d02e3c | 295 | pic_reset(s); |
b54ad049 | 296 | /* deassert a pending interrupt */ |
d537cf6c | 297 | qemu_irq_lower(s->pics_state->parent_irq); |
80cabfad FB |
298 | s->init_state = 1; |
299 | s->init4 = val & 1; | |
2053152b | 300 | s->single_mode = val & 2; |
80cabfad FB |
301 | if (val & 0x08) |
302 | hw_error("level sensitive irq not supported"); | |
303 | } else if (val & 0x08) { | |
304 | if (val & 0x04) | |
305 | s->poll = 1; | |
306 | if (val & 0x02) | |
307 | s->read_reg_select = val & 1; | |
308 | if (val & 0x40) | |
309 | s->special_mask = (val >> 5) & 1; | |
310 | } else { | |
311 | cmd = val >> 5; | |
312 | switch(cmd) { | |
313 | case 0: | |
314 | case 4: | |
315 | s->rotate_on_auto_eoi = cmd >> 2; | |
316 | break; | |
317 | case 1: /* end of interrupt */ | |
318 | case 5: | |
319 | priority = get_priority(s, s->isr); | |
320 | if (priority != 8) { | |
321 | irq = (priority + s->priority_add) & 7; | |
322 | s->isr &= ~(1 << irq); | |
323 | if (cmd == 5) | |
324 | s->priority_add = (irq + 1) & 7; | |
3de388f6 | 325 | pic_update_irq(s->pics_state); |
80cabfad FB |
326 | } |
327 | break; | |
328 | case 3: | |
329 | irq = val & 7; | |
330 | s->isr &= ~(1 << irq); | |
3de388f6 | 331 | pic_update_irq(s->pics_state); |
80cabfad FB |
332 | break; |
333 | case 6: | |
334 | s->priority_add = (val + 1) & 7; | |
3de388f6 | 335 | pic_update_irq(s->pics_state); |
80cabfad FB |
336 | break; |
337 | case 7: | |
338 | irq = val & 7; | |
339 | s->isr &= ~(1 << irq); | |
340 | s->priority_add = (irq + 1) & 7; | |
3de388f6 | 341 | pic_update_irq(s->pics_state); |
80cabfad FB |
342 | break; |
343 | default: | |
344 | /* no operation */ | |
345 | break; | |
346 | } | |
347 | } | |
348 | } else { | |
349 | switch(s->init_state) { | |
350 | case 0: | |
351 | /* normal mode */ | |
352 | s->imr = val; | |
3de388f6 | 353 | pic_update_irq(s->pics_state); |
80cabfad FB |
354 | break; |
355 | case 1: | |
356 | s->irq_base = val & 0xf8; | |
2bb081f7 | 357 | s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2; |
80cabfad FB |
358 | break; |
359 | case 2: | |
360 | if (s->init4) { | |
361 | s->init_state = 3; | |
362 | } else { | |
363 | s->init_state = 0; | |
364 | } | |
365 | break; | |
366 | case 3: | |
367 | s->special_fully_nested_mode = (val >> 4) & 1; | |
368 | s->auto_eoi = (val >> 1) & 1; | |
369 | s->init_state = 0; | |
370 | break; | |
371 | } | |
372 | } | |
373 | } | |
374 | ||
098d314a | 375 | static uint32_t pic_poll_read(PicState *s) |
80cabfad FB |
376 | { |
377 | int ret; | |
378 | ||
379 | ret = pic_get_irq(s); | |
380 | if (ret >= 0) { | |
098d314a RH |
381 | bool slave = (s == &isa_pic->pics[1]); |
382 | ||
383 | if (slave) { | |
3de388f6 FB |
384 | s->pics_state->pics[0].isr &= ~(1 << 2); |
385 | s->pics_state->pics[0].irr &= ~(1 << 2); | |
80cabfad FB |
386 | } |
387 | s->irr &= ~(1 << ret); | |
388 | s->isr &= ~(1 << ret); | |
098d314a | 389 | if (slave || ret != 2) |
3de388f6 | 390 | pic_update_irq(s->pics_state); |
80cabfad FB |
391 | } else { |
392 | ret = 0x07; | |
3de388f6 | 393 | pic_update_irq(s->pics_state); |
80cabfad FB |
394 | } |
395 | ||
396 | return ret; | |
397 | } | |
398 | ||
098d314a RH |
399 | static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr1, |
400 | unsigned size) | |
80cabfad | 401 | { |
b41a2cd1 | 402 | PicState *s = opaque; |
098d314a | 403 | unsigned int addr = addr1; |
80cabfad FB |
404 | int ret; |
405 | ||
80cabfad | 406 | if (s->poll) { |
098d314a | 407 | ret = pic_poll_read(s); |
80cabfad FB |
408 | s->poll = 0; |
409 | } else { | |
410 | if (addr == 0) { | |
411 | if (s->read_reg_select) | |
412 | ret = s->isr; | |
413 | else | |
414 | ret = s->irr; | |
415 | } else { | |
416 | ret = s->imr; | |
417 | } | |
418 | } | |
098d314a | 419 | DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret); |
80cabfad FB |
420 | return ret; |
421 | } | |
422 | ||
423 | /* memory mapped interrupt status */ | |
3de388f6 FB |
424 | /* XXX: may be the same than pic_read_irq() */ |
425 | uint32_t pic_intack_read(PicState2 *s) | |
80cabfad FB |
426 | { |
427 | int ret; | |
428 | ||
098d314a | 429 | ret = pic_poll_read(&s->pics[0]); |
80cabfad | 430 | if (ret == 2) |
098d314a | 431 | ret = pic_poll_read(&s->pics[1]) + 8; |
80cabfad | 432 | /* Prepare for ISR read */ |
3de388f6 | 433 | s->pics[0].read_reg_select = 1; |
3b46e624 | 434 | |
80cabfad FB |
435 | return ret; |
436 | } | |
437 | ||
d96e1737 JK |
438 | int pic_get_output(PicState2 *s) |
439 | { | |
440 | return (pic_get_irq(&s->pics[0]) >= 0); | |
441 | } | |
442 | ||
098d314a RH |
443 | static void elcr_ioport_write(void *opaque, target_phys_addr_t addr, |
444 | uint64_t val, unsigned size) | |
660de336 FB |
445 | { |
446 | PicState *s = opaque; | |
447 | s->elcr = val & s->elcr_mask; | |
448 | } | |
449 | ||
098d314a RH |
450 | static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr, |
451 | unsigned size) | |
660de336 FB |
452 | { |
453 | PicState *s = opaque; | |
454 | return s->elcr; | |
455 | } | |
456 | ||
77eea838 JQ |
457 | static const VMStateDescription vmstate_pic = { |
458 | .name = "i8259", | |
459 | .version_id = 1, | |
460 | .minimum_version_id = 1, | |
461 | .minimum_version_id_old = 1, | |
462 | .fields = (VMStateField []) { | |
463 | VMSTATE_UINT8(last_irr, PicState), | |
464 | VMSTATE_UINT8(irr, PicState), | |
465 | VMSTATE_UINT8(imr, PicState), | |
466 | VMSTATE_UINT8(isr, PicState), | |
467 | VMSTATE_UINT8(priority_add, PicState), | |
468 | VMSTATE_UINT8(irq_base, PicState), | |
469 | VMSTATE_UINT8(read_reg_select, PicState), | |
470 | VMSTATE_UINT8(poll, PicState), | |
471 | VMSTATE_UINT8(special_mask, PicState), | |
472 | VMSTATE_UINT8(init_state, PicState), | |
473 | VMSTATE_UINT8(auto_eoi, PicState), | |
474 | VMSTATE_UINT8(rotate_on_auto_eoi, PicState), | |
475 | VMSTATE_UINT8(special_fully_nested_mode, PicState), | |
476 | VMSTATE_UINT8(init4, PicState), | |
477 | VMSTATE_UINT8(single_mode, PicState), | |
478 | VMSTATE_UINT8(elcr, PicState), | |
479 | VMSTATE_END_OF_LIST() | |
480 | } | |
481 | }; | |
b0a21b53 | 482 | |
098d314a RH |
483 | static const MemoryRegionOps pic_base_ioport_ops = { |
484 | .read = pic_ioport_read, | |
485 | .write = pic_ioport_write, | |
486 | .impl = { | |
487 | .min_access_size = 1, | |
488 | .max_access_size = 1, | |
489 | }, | |
490 | }; | |
491 | ||
492 | static const MemoryRegionOps pic_elcr_ioport_ops = { | |
493 | .read = elcr_ioport_read, | |
494 | .write = elcr_ioport_write, | |
495 | .impl = { | |
496 | .min_access_size = 1, | |
497 | .max_access_size = 1, | |
498 | }, | |
499 | }; | |
500 | ||
b0a21b53 | 501 | /* XXX: add generic master/slave system */ |
660de336 | 502 | static void pic_init1(int io_addr, int elcr_addr, PicState *s) |
b0a21b53 | 503 | { |
098d314a RH |
504 | memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2); |
505 | memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1); | |
506 | ||
507 | isa_register_ioport(NULL, &s->base_io, io_addr); | |
660de336 | 508 | if (elcr_addr >= 0) { |
098d314a | 509 | isa_register_ioport(NULL, &s->elcr_io, elcr_addr); |
660de336 | 510 | } |
098d314a | 511 | |
0be71e32 | 512 | vmstate_register(NULL, io_addr, &vmstate_pic, s); |
a08d4367 | 513 | qemu_register_reset(pic_reset, s); |
b0a21b53 FB |
514 | } |
515 | ||
376253ec | 516 | void pic_info(Monitor *mon) |
ba91cd80 FB |
517 | { |
518 | int i; | |
519 | PicState *s; | |
3b46e624 | 520 | |
3de388f6 FB |
521 | if (!isa_pic) |
522 | return; | |
ba91cd80 FB |
523 | |
524 | for(i=0;i<2;i++) { | |
3de388f6 | 525 | s = &isa_pic->pics[i]; |
376253ec AL |
526 | monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d " |
527 | "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", | |
528 | i, s->irr, s->imr, s->isr, s->priority_add, | |
529 | s->irq_base, s->read_reg_select, s->elcr, | |
530 | s->special_fully_nested_mode); | |
ba91cd80 FB |
531 | } |
532 | } | |
533 | ||
376253ec | 534 | void irq_info(Monitor *mon) |
4a0fb71e FB |
535 | { |
536 | #ifndef DEBUG_IRQ_COUNT | |
376253ec | 537 | monitor_printf(mon, "irq statistic code not compiled.\n"); |
4a0fb71e FB |
538 | #else |
539 | int i; | |
540 | int64_t count; | |
541 | ||
376253ec | 542 | monitor_printf(mon, "IRQ statistics:\n"); |
4a0fb71e FB |
543 | for (i = 0; i < 16; i++) { |
544 | count = irq_count[i]; | |
545 | if (count > 0) | |
376253ec | 546 | monitor_printf(mon, "%2d: %" PRId64 "\n", i, count); |
4a0fb71e FB |
547 | } |
548 | #endif | |
549 | } | |
ba91cd80 | 550 | |
d537cf6c | 551 | qemu_irq *i8259_init(qemu_irq parent_irq) |
80cabfad | 552 | { |
3de388f6 | 553 | PicState2 *s; |
d537cf6c | 554 | |
7267c094 | 555 | s = g_malloc0(sizeof(PicState2)); |
3de388f6 FB |
556 | pic_init1(0x20, 0x4d0, &s->pics[0]); |
557 | pic_init1(0xa0, 0x4d1, &s->pics[1]); | |
558 | s->pics[0].elcr_mask = 0xf8; | |
559 | s->pics[1].elcr_mask = 0xde; | |
d537cf6c | 560 | s->parent_irq = parent_irq; |
3de388f6 FB |
561 | s->pics[0].pics_state = s; |
562 | s->pics[1].pics_state = s; | |
d537cf6c PB |
563 | isa_pic = s; |
564 | return qemu_allocate_irqs(i8259_set_irq, s, 16); | |
80cabfad | 565 | } |