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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU 8259 interrupt controller emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pc.h" | |
26 | #include "isa.h" | |
376253ec | 27 | #include "monitor.h" |
0bf9e31a | 28 | #include "qemu-timer.h" |
80cabfad FB |
29 | |
30 | /* debug PIC */ | |
31 | //#define DEBUG_PIC | |
32 | ||
b41a2cd1 | 33 | //#define DEBUG_IRQ_LATENCY |
4a0fb71e | 34 | //#define DEBUG_IRQ_COUNT |
b41a2cd1 | 35 | |
80cabfad FB |
36 | typedef struct PicState { |
37 | uint8_t last_irr; /* edge detection */ | |
38 | uint8_t irr; /* interrupt request register */ | |
39 | uint8_t imr; /* interrupt mask register */ | |
40 | uint8_t isr; /* interrupt service register */ | |
41 | uint8_t priority_add; /* highest irq priority */ | |
42 | uint8_t irq_base; | |
43 | uint8_t read_reg_select; | |
44 | uint8_t poll; | |
45 | uint8_t special_mask; | |
46 | uint8_t init_state; | |
47 | uint8_t auto_eoi; | |
48 | uint8_t rotate_on_auto_eoi; | |
49 | uint8_t special_fully_nested_mode; | |
50 | uint8_t init4; /* true if 4 byte init */ | |
2053152b | 51 | uint8_t single_mode; /* true if slave pic is not initialized */ |
660de336 FB |
52 | uint8_t elcr; /* PIIX edge/trigger selection*/ |
53 | uint8_t elcr_mask; | |
3de388f6 | 54 | PicState2 *pics_state; |
80cabfad FB |
55 | } PicState; |
56 | ||
3de388f6 FB |
57 | struct PicState2 { |
58 | /* 0 is master pic, 1 is slave pic */ | |
59 | /* XXX: better separation between the two pics */ | |
60 | PicState pics[2]; | |
d537cf6c | 61 | qemu_irq parent_irq; |
3de388f6 FB |
62 | void *irq_request_opaque; |
63 | }; | |
80cabfad | 64 | |
4a0fb71e FB |
65 | #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT) |
66 | static int irq_level[16]; | |
67 | #endif | |
68 | #ifdef DEBUG_IRQ_COUNT | |
69 | static uint64_t irq_count[16]; | |
70 | #endif | |
fbe3288d | 71 | PicState2 *isa_pic; |
4a0fb71e | 72 | |
80cabfad FB |
73 | /* set irq level. If an edge is detected, then the IRR is set to 1 */ |
74 | static inline void pic_set_irq1(PicState *s, int irq, int level) | |
75 | { | |
76 | int mask; | |
77 | mask = 1 << irq; | |
660de336 FB |
78 | if (s->elcr & mask) { |
79 | /* level triggered */ | |
80 | if (level) { | |
80cabfad | 81 | s->irr |= mask; |
660de336 FB |
82 | s->last_irr |= mask; |
83 | } else { | |
84 | s->irr &= ~mask; | |
85 | s->last_irr &= ~mask; | |
86 | } | |
80cabfad | 87 | } else { |
660de336 FB |
88 | /* edge triggered */ |
89 | if (level) { | |
90 | if ((s->last_irr & mask) == 0) | |
91 | s->irr |= mask; | |
92 | s->last_irr |= mask; | |
93 | } else { | |
94 | s->last_irr &= ~mask; | |
95 | } | |
80cabfad FB |
96 | } |
97 | } | |
98 | ||
99 | /* return the highest priority found in mask (highest = smallest | |
100 | number). Return 8 if no irq */ | |
101 | static inline int get_priority(PicState *s, int mask) | |
102 | { | |
103 | int priority; | |
104 | if (mask == 0) | |
105 | return 8; | |
106 | priority = 0; | |
107 | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) | |
108 | priority++; | |
109 | return priority; | |
110 | } | |
111 | ||
112 | /* return the pic wanted interrupt. return -1 if none */ | |
113 | static int pic_get_irq(PicState *s) | |
114 | { | |
115 | int mask, cur_priority, priority; | |
116 | ||
117 | mask = s->irr & ~s->imr; | |
118 | priority = get_priority(s, mask); | |
119 | if (priority == 8) | |
120 | return -1; | |
121 | /* compute current priority. If special fully nested mode on the | |
122 | master, the IRQ coming from the slave is not taken into account | |
123 | for the priority computation. */ | |
124 | mask = s->isr; | |
84678711 AZ |
125 | if (s->special_mask) |
126 | mask &= ~s->imr; | |
3de388f6 | 127 | if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) |
80cabfad FB |
128 | mask &= ~(1 << 2); |
129 | cur_priority = get_priority(s, mask); | |
130 | if (priority < cur_priority) { | |
131 | /* higher priority found: an irq should be generated */ | |
132 | return (priority + s->priority_add) & 7; | |
133 | } else { | |
134 | return -1; | |
135 | } | |
136 | } | |
137 | ||
138 | /* raise irq to CPU if necessary. must be called every time the active | |
139 | irq may change */ | |
3de388f6 FB |
140 | /* XXX: should not export it, but it is needed for an APIC kludge */ |
141 | void pic_update_irq(PicState2 *s) | |
80cabfad FB |
142 | { |
143 | int irq2, irq; | |
144 | ||
145 | /* first look at slave pic */ | |
3de388f6 | 146 | irq2 = pic_get_irq(&s->pics[1]); |
80cabfad FB |
147 | if (irq2 >= 0) { |
148 | /* if irq request by slave pic, signal master PIC */ | |
3de388f6 FB |
149 | pic_set_irq1(&s->pics[0], 2, 1); |
150 | pic_set_irq1(&s->pics[0], 2, 0); | |
80cabfad FB |
151 | } |
152 | /* look at requested irq */ | |
3de388f6 | 153 | irq = pic_get_irq(&s->pics[0]); |
80cabfad | 154 | if (irq >= 0) { |
80cabfad FB |
155 | #if defined(DEBUG_PIC) |
156 | { | |
157 | int i; | |
158 | for(i = 0; i < 2; i++) { | |
5fafdf24 TS |
159 | printf("pic%d: imr=%x irr=%x padd=%d\n", |
160 | i, s->pics[i].imr, s->pics[i].irr, | |
3de388f6 | 161 | s->pics[i].priority_add); |
3b46e624 | 162 | |
80cabfad FB |
163 | } |
164 | } | |
2444ca41 | 165 | printf("pic: cpu_interrupt\n"); |
80cabfad | 166 | #endif |
d537cf6c | 167 | qemu_irq_raise(s->parent_irq); |
80cabfad | 168 | } |
4de9b249 TS |
169 | |
170 | /* all targets should do this rather than acking the IRQ in the cpu */ | |
29463b24 | 171 | #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA) |
4de9b249 | 172 | else { |
d537cf6c | 173 | qemu_irq_lower(s->parent_irq); |
4de9b249 TS |
174 | } |
175 | #endif | |
80cabfad FB |
176 | } |
177 | ||
178 | #ifdef DEBUG_IRQ_LATENCY | |
179 | int64_t irq_time[16]; | |
80cabfad | 180 | #endif |
80cabfad | 181 | |
9596ebb7 | 182 | static void i8259_set_irq(void *opaque, int irq, int level) |
80cabfad | 183 | { |
3de388f6 FB |
184 | PicState2 *s = opaque; |
185 | ||
4a0fb71e | 186 | #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) |
80cabfad | 187 | if (level != irq_level[irq]) { |
4a0fb71e | 188 | #if defined(DEBUG_PIC) |
d537cf6c | 189 | printf("i8259_set_irq: irq=%d level=%d\n", irq, level); |
4a0fb71e | 190 | #endif |
80cabfad | 191 | irq_level[irq] = level; |
4a0fb71e FB |
192 | #ifdef DEBUG_IRQ_COUNT |
193 | if (level == 1) | |
194 | irq_count[irq]++; | |
195 | #endif | |
80cabfad FB |
196 | } |
197 | #endif | |
198 | #ifdef DEBUG_IRQ_LATENCY | |
199 | if (level) { | |
2444ca41 | 200 | irq_time[irq] = qemu_get_clock(vm_clock); |
80cabfad FB |
201 | } |
202 | #endif | |
3de388f6 FB |
203 | pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); |
204 | pic_update_irq(s); | |
80cabfad FB |
205 | } |
206 | ||
207 | /* acknowledge interrupt 'irq' */ | |
208 | static inline void pic_intack(PicState *s, int irq) | |
209 | { | |
210 | if (s->auto_eoi) { | |
211 | if (s->rotate_on_auto_eoi) | |
212 | s->priority_add = (irq + 1) & 7; | |
213 | } else { | |
214 | s->isr |= (1 << irq); | |
215 | } | |
0ecf89aa FB |
216 | /* We don't clear a level sensitive interrupt here */ |
217 | if (!(s->elcr & (1 << irq))) | |
218 | s->irr &= ~(1 << irq); | |
80cabfad FB |
219 | } |
220 | ||
3de388f6 | 221 | int pic_read_irq(PicState2 *s) |
80cabfad FB |
222 | { |
223 | int irq, irq2, intno; | |
224 | ||
3de388f6 | 225 | irq = pic_get_irq(&s->pics[0]); |
15aeac38 | 226 | if (irq >= 0) { |
3de388f6 | 227 | pic_intack(&s->pics[0], irq); |
15aeac38 | 228 | if (irq == 2) { |
3de388f6 | 229 | irq2 = pic_get_irq(&s->pics[1]); |
15aeac38 | 230 | if (irq2 >= 0) { |
3de388f6 | 231 | pic_intack(&s->pics[1], irq2); |
15aeac38 FB |
232 | } else { |
233 | /* spurious IRQ on slave controller */ | |
234 | irq2 = 7; | |
235 | } | |
3de388f6 | 236 | intno = s->pics[1].irq_base + irq2; |
15aeac38 FB |
237 | irq = irq2 + 8; |
238 | } else { | |
3de388f6 | 239 | intno = s->pics[0].irq_base + irq; |
15aeac38 FB |
240 | } |
241 | } else { | |
242 | /* spurious IRQ on host controller */ | |
243 | irq = 7; | |
3de388f6 | 244 | intno = s->pics[0].irq_base + irq; |
15aeac38 | 245 | } |
3de388f6 | 246 | pic_update_irq(s); |
3b46e624 | 247 | |
80cabfad | 248 | #ifdef DEBUG_IRQ_LATENCY |
5fafdf24 TS |
249 | printf("IRQ%d latency=%0.3fus\n", |
250 | irq, | |
6ee093c9 JQ |
251 | (double)(qemu_get_clock(vm_clock) - |
252 | irq_time[irq]) * 1000000.0 / get_ticks_per_sec()); | |
80cabfad FB |
253 | #endif |
254 | #if defined(DEBUG_PIC) | |
255 | printf("pic_interrupt: irq=%d\n", irq); | |
256 | #endif | |
80cabfad FB |
257 | return intno; |
258 | } | |
259 | ||
d7d02e3c FB |
260 | static void pic_reset(void *opaque) |
261 | { | |
262 | PicState *s = opaque; | |
d7d02e3c | 263 | |
3de388f6 FB |
264 | s->last_irr = 0; |
265 | s->irr = 0; | |
266 | s->imr = 0; | |
267 | s->isr = 0; | |
268 | s->priority_add = 0; | |
269 | s->irq_base = 0; | |
270 | s->read_reg_select = 0; | |
271 | s->poll = 0; | |
272 | s->special_mask = 0; | |
273 | s->init_state = 0; | |
274 | s->auto_eoi = 0; | |
275 | s->rotate_on_auto_eoi = 0; | |
276 | s->special_fully_nested_mode = 0; | |
277 | s->init4 = 0; | |
2053152b | 278 | s->single_mode = 0; |
4dbe19e1 | 279 | /* Note: ELCR is not reset */ |
d7d02e3c FB |
280 | } |
281 | ||
b41a2cd1 | 282 | static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 283 | { |
b41a2cd1 | 284 | PicState *s = opaque; |
d7d02e3c | 285 | int priority, cmd, irq; |
80cabfad FB |
286 | |
287 | #ifdef DEBUG_PIC | |
288 | printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val); | |
289 | #endif | |
80cabfad FB |
290 | addr &= 1; |
291 | if (addr == 0) { | |
292 | if (val & 0x10) { | |
293 | /* init */ | |
d7d02e3c | 294 | pic_reset(s); |
b54ad049 | 295 | /* deassert a pending interrupt */ |
d537cf6c | 296 | qemu_irq_lower(s->pics_state->parent_irq); |
80cabfad FB |
297 | s->init_state = 1; |
298 | s->init4 = val & 1; | |
2053152b | 299 | s->single_mode = val & 2; |
80cabfad FB |
300 | if (val & 0x08) |
301 | hw_error("level sensitive irq not supported"); | |
302 | } else if (val & 0x08) { | |
303 | if (val & 0x04) | |
304 | s->poll = 1; | |
305 | if (val & 0x02) | |
306 | s->read_reg_select = val & 1; | |
307 | if (val & 0x40) | |
308 | s->special_mask = (val >> 5) & 1; | |
309 | } else { | |
310 | cmd = val >> 5; | |
311 | switch(cmd) { | |
312 | case 0: | |
313 | case 4: | |
314 | s->rotate_on_auto_eoi = cmd >> 2; | |
315 | break; | |
316 | case 1: /* end of interrupt */ | |
317 | case 5: | |
318 | priority = get_priority(s, s->isr); | |
319 | if (priority != 8) { | |
320 | irq = (priority + s->priority_add) & 7; | |
321 | s->isr &= ~(1 << irq); | |
322 | if (cmd == 5) | |
323 | s->priority_add = (irq + 1) & 7; | |
3de388f6 | 324 | pic_update_irq(s->pics_state); |
80cabfad FB |
325 | } |
326 | break; | |
327 | case 3: | |
328 | irq = val & 7; | |
329 | s->isr &= ~(1 << irq); | |
3de388f6 | 330 | pic_update_irq(s->pics_state); |
80cabfad FB |
331 | break; |
332 | case 6: | |
333 | s->priority_add = (val + 1) & 7; | |
3de388f6 | 334 | pic_update_irq(s->pics_state); |
80cabfad FB |
335 | break; |
336 | case 7: | |
337 | irq = val & 7; | |
338 | s->isr &= ~(1 << irq); | |
339 | s->priority_add = (irq + 1) & 7; | |
3de388f6 | 340 | pic_update_irq(s->pics_state); |
80cabfad FB |
341 | break; |
342 | default: | |
343 | /* no operation */ | |
344 | break; | |
345 | } | |
346 | } | |
347 | } else { | |
348 | switch(s->init_state) { | |
349 | case 0: | |
350 | /* normal mode */ | |
351 | s->imr = val; | |
3de388f6 | 352 | pic_update_irq(s->pics_state); |
80cabfad FB |
353 | break; |
354 | case 1: | |
355 | s->irq_base = val & 0xf8; | |
2bb081f7 | 356 | s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2; |
80cabfad FB |
357 | break; |
358 | case 2: | |
359 | if (s->init4) { | |
360 | s->init_state = 3; | |
361 | } else { | |
362 | s->init_state = 0; | |
363 | } | |
364 | break; | |
365 | case 3: | |
366 | s->special_fully_nested_mode = (val >> 4) & 1; | |
367 | s->auto_eoi = (val >> 1) & 1; | |
368 | s->init_state = 0; | |
369 | break; | |
370 | } | |
371 | } | |
372 | } | |
373 | ||
374 | static uint32_t pic_poll_read (PicState *s, uint32_t addr1) | |
375 | { | |
376 | int ret; | |
377 | ||
378 | ret = pic_get_irq(s); | |
379 | if (ret >= 0) { | |
380 | if (addr1 >> 7) { | |
3de388f6 FB |
381 | s->pics_state->pics[0].isr &= ~(1 << 2); |
382 | s->pics_state->pics[0].irr &= ~(1 << 2); | |
80cabfad FB |
383 | } |
384 | s->irr &= ~(1 << ret); | |
385 | s->isr &= ~(1 << ret); | |
386 | if (addr1 >> 7 || ret != 2) | |
3de388f6 | 387 | pic_update_irq(s->pics_state); |
80cabfad FB |
388 | } else { |
389 | ret = 0x07; | |
3de388f6 | 390 | pic_update_irq(s->pics_state); |
80cabfad FB |
391 | } |
392 | ||
393 | return ret; | |
394 | } | |
395 | ||
b41a2cd1 | 396 | static uint32_t pic_ioport_read(void *opaque, uint32_t addr1) |
80cabfad | 397 | { |
b41a2cd1 | 398 | PicState *s = opaque; |
80cabfad FB |
399 | unsigned int addr; |
400 | int ret; | |
401 | ||
402 | addr = addr1; | |
80cabfad FB |
403 | addr &= 1; |
404 | if (s->poll) { | |
405 | ret = pic_poll_read(s, addr1); | |
406 | s->poll = 0; | |
407 | } else { | |
408 | if (addr == 0) { | |
409 | if (s->read_reg_select) | |
410 | ret = s->isr; | |
411 | else | |
412 | ret = s->irr; | |
413 | } else { | |
414 | ret = s->imr; | |
415 | } | |
416 | } | |
417 | #ifdef DEBUG_PIC | |
418 | printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret); | |
419 | #endif | |
420 | return ret; | |
421 | } | |
422 | ||
423 | /* memory mapped interrupt status */ | |
3de388f6 FB |
424 | /* XXX: may be the same than pic_read_irq() */ |
425 | uint32_t pic_intack_read(PicState2 *s) | |
80cabfad FB |
426 | { |
427 | int ret; | |
428 | ||
3de388f6 | 429 | ret = pic_poll_read(&s->pics[0], 0x00); |
80cabfad | 430 | if (ret == 2) |
3de388f6 | 431 | ret = pic_poll_read(&s->pics[1], 0x80) + 8; |
80cabfad | 432 | /* Prepare for ISR read */ |
3de388f6 | 433 | s->pics[0].read_reg_select = 1; |
3b46e624 | 434 | |
80cabfad FB |
435 | return ret; |
436 | } | |
437 | ||
660de336 FB |
438 | static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
439 | { | |
440 | PicState *s = opaque; | |
441 | s->elcr = val & s->elcr_mask; | |
442 | } | |
443 | ||
444 | static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1) | |
445 | { | |
446 | PicState *s = opaque; | |
447 | return s->elcr; | |
448 | } | |
449 | ||
77eea838 JQ |
450 | static const VMStateDescription vmstate_pic = { |
451 | .name = "i8259", | |
452 | .version_id = 1, | |
453 | .minimum_version_id = 1, | |
454 | .minimum_version_id_old = 1, | |
455 | .fields = (VMStateField []) { | |
456 | VMSTATE_UINT8(last_irr, PicState), | |
457 | VMSTATE_UINT8(irr, PicState), | |
458 | VMSTATE_UINT8(imr, PicState), | |
459 | VMSTATE_UINT8(isr, PicState), | |
460 | VMSTATE_UINT8(priority_add, PicState), | |
461 | VMSTATE_UINT8(irq_base, PicState), | |
462 | VMSTATE_UINT8(read_reg_select, PicState), | |
463 | VMSTATE_UINT8(poll, PicState), | |
464 | VMSTATE_UINT8(special_mask, PicState), | |
465 | VMSTATE_UINT8(init_state, PicState), | |
466 | VMSTATE_UINT8(auto_eoi, PicState), | |
467 | VMSTATE_UINT8(rotate_on_auto_eoi, PicState), | |
468 | VMSTATE_UINT8(special_fully_nested_mode, PicState), | |
469 | VMSTATE_UINT8(init4, PicState), | |
470 | VMSTATE_UINT8(single_mode, PicState), | |
471 | VMSTATE_UINT8(elcr, PicState), | |
472 | VMSTATE_END_OF_LIST() | |
473 | } | |
474 | }; | |
b0a21b53 FB |
475 | |
476 | /* XXX: add generic master/slave system */ | |
660de336 | 477 | static void pic_init1(int io_addr, int elcr_addr, PicState *s) |
b0a21b53 FB |
478 | { |
479 | register_ioport_write(io_addr, 2, 1, pic_ioport_write, s); | |
480 | register_ioport_read(io_addr, 2, 1, pic_ioport_read, s); | |
660de336 FB |
481 | if (elcr_addr >= 0) { |
482 | register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s); | |
483 | register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s); | |
484 | } | |
77eea838 | 485 | vmstate_register(io_addr, &vmstate_pic, s); |
a08d4367 | 486 | qemu_register_reset(pic_reset, s); |
b0a21b53 FB |
487 | } |
488 | ||
376253ec | 489 | void pic_info(Monitor *mon) |
ba91cd80 FB |
490 | { |
491 | int i; | |
492 | PicState *s; | |
3b46e624 | 493 | |
3de388f6 FB |
494 | if (!isa_pic) |
495 | return; | |
ba91cd80 FB |
496 | |
497 | for(i=0;i<2;i++) { | |
3de388f6 | 498 | s = &isa_pic->pics[i]; |
376253ec AL |
499 | monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d " |
500 | "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", | |
501 | i, s->irr, s->imr, s->isr, s->priority_add, | |
502 | s->irq_base, s->read_reg_select, s->elcr, | |
503 | s->special_fully_nested_mode); | |
ba91cd80 FB |
504 | } |
505 | } | |
506 | ||
376253ec | 507 | void irq_info(Monitor *mon) |
4a0fb71e FB |
508 | { |
509 | #ifndef DEBUG_IRQ_COUNT | |
376253ec | 510 | monitor_printf(mon, "irq statistic code not compiled.\n"); |
4a0fb71e FB |
511 | #else |
512 | int i; | |
513 | int64_t count; | |
514 | ||
376253ec | 515 | monitor_printf(mon, "IRQ statistics:\n"); |
4a0fb71e FB |
516 | for (i = 0; i < 16; i++) { |
517 | count = irq_count[i]; | |
518 | if (count > 0) | |
376253ec | 519 | monitor_printf(mon, "%2d: %" PRId64 "\n", i, count); |
4a0fb71e FB |
520 | } |
521 | #endif | |
522 | } | |
ba91cd80 | 523 | |
d537cf6c | 524 | qemu_irq *i8259_init(qemu_irq parent_irq) |
80cabfad | 525 | { |
3de388f6 | 526 | PicState2 *s; |
d537cf6c | 527 | |
3de388f6 | 528 | s = qemu_mallocz(sizeof(PicState2)); |
3de388f6 FB |
529 | pic_init1(0x20, 0x4d0, &s->pics[0]); |
530 | pic_init1(0xa0, 0x4d1, &s->pics[1]); | |
531 | s->pics[0].elcr_mask = 0xf8; | |
532 | s->pics[1].elcr_mask = 0xde; | |
d537cf6c | 533 | s->parent_irq = parent_irq; |
3de388f6 FB |
534 | s->pics[0].pics_state = s; |
535 | s->pics[1].pics_state = s; | |
d537cf6c PB |
536 | isa_pic = s; |
537 | return qemu_allocate_irqs(i8259_set_irq, s, 16); | |
80cabfad | 538 | } |