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f6ad2e32 AG |
1 | /* |
2 | * QEMU AHCI Emulation | |
3 | * | |
4 | * Copyright (c) 2010 qiaochong@loongson.cn | |
5 | * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> | |
6 | * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> | |
7 | * Copyright (c) 2010 Alexander Graf <agraf@suse.de> | |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
61f3c91a | 12 | * version 2.1 of the License, or (at your option) any later version. |
f6ad2e32 AG |
13 | * |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
21 | * | |
f6ad2e32 AG |
22 | */ |
23 | ||
53239262 | 24 | #include "qemu/osdep.h" |
a9c94277 | 25 | #include "hw/pci/msi.h" |
a9c94277 | 26 | #include "hw/pci/pci.h" |
a27bd6c7 | 27 | #include "hw/qdev-properties.h" |
d6454270 | 28 | #include "migration/vmstate.h" |
f6ad2e32 | 29 | |
d49b6836 | 30 | #include "qemu/error-report.h" |
06e35065 | 31 | #include "qemu/log.h" |
db725815 | 32 | #include "qemu/main-loop.h" |
0b8fa32f | 33 | #include "qemu/module.h" |
4be74634 | 34 | #include "sysemu/block-backend.h" |
9c17d615 | 35 | #include "sysemu/dma.h" |
a9c94277 MA |
36 | #include "hw/ide/internal.h" |
37 | #include "hw/ide/pci.h" | |
9314b859 | 38 | #include "ahci_internal.h" |
f6ad2e32 | 39 | |
e4baa9f0 | 40 | #include "trace.h" |
f6ad2e32 | 41 | |
f6ad2e32 | 42 | static void check_cmd(AHCIState *s, int port); |
9364384d | 43 | static int handle_cmd(AHCIState *s, int port, uint8_t slot); |
f6ad2e32 | 44 | static void ahci_reset_port(AHCIState *s, int port); |
e47f9eb1 | 45 | static bool ahci_write_fis_d2h(AHCIDevice *ad); |
87e62065 | 46 | static void ahci_init_d2h(AHCIDevice *ad); |
ae0cebd7 | 47 | static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit); |
a13ab5a3 JS |
48 | static bool ahci_map_clb_address(AHCIDevice *ad); |
49 | static bool ahci_map_fis_address(AHCIDevice *ad); | |
fc3d8e11 JS |
50 | static void ahci_unmap_clb_address(AHCIDevice *ad); |
51 | static void ahci_unmap_fis_address(AHCIDevice *ad); | |
659142ec | 52 | |
da868a46 JS |
53 | static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = { |
54 | [AHCI_HOST_REG_CAP] = "CAP", | |
55 | [AHCI_HOST_REG_CTL] = "GHC", | |
56 | [AHCI_HOST_REG_IRQ_STAT] = "IS", | |
57 | [AHCI_HOST_REG_PORTS_IMPL] = "PI", | |
58 | [AHCI_HOST_REG_VERSION] = "VS", | |
59 | [AHCI_HOST_REG_CCC_CTL] = "CCC_CTL", | |
60 | [AHCI_HOST_REG_CCC_PORTS] = "CCC_PORTS", | |
61 | [AHCI_HOST_REG_EM_LOC] = "EM_LOC", | |
62 | [AHCI_HOST_REG_EM_CTL] = "EM_CTL", | |
63 | [AHCI_HOST_REG_CAP2] = "CAP2", | |
64 | [AHCI_HOST_REG_BOHC] = "BOHC", | |
65 | }; | |
66 | ||
4e6e1de4 JS |
67 | static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] = { |
68 | [AHCI_PORT_REG_LST_ADDR] = "PxCLB", | |
69 | [AHCI_PORT_REG_LST_ADDR_HI] = "PxCLBU", | |
70 | [AHCI_PORT_REG_FIS_ADDR] = "PxFB", | |
71 | [AHCI_PORT_REG_FIS_ADDR_HI] = "PxFBU", | |
72 | [AHCI_PORT_REG_IRQ_STAT] = "PxIS", | |
73 | [AHCI_PORT_REG_IRQ_MASK] = "PXIE", | |
74 | [AHCI_PORT_REG_CMD] = "PxCMD", | |
75 | [7] = "Reserved", | |
76 | [AHCI_PORT_REG_TFDATA] = "PxTFD", | |
77 | [AHCI_PORT_REG_SIG] = "PxSIG", | |
78 | [AHCI_PORT_REG_SCR_STAT] = "PxSSTS", | |
79 | [AHCI_PORT_REG_SCR_CTL] = "PxSCTL", | |
80 | [AHCI_PORT_REG_SCR_ERR] = "PxSERR", | |
81 | [AHCI_PORT_REG_SCR_ACT] = "PxSACT", | |
82 | [AHCI_PORT_REG_CMD_ISSUE] = "PxCI", | |
83 | [AHCI_PORT_REG_SCR_NOTIF] = "PxSNTF", | |
84 | [AHCI_PORT_REG_FIS_CTL] = "PxFBS", | |
85 | [AHCI_PORT_REG_DEV_SLEEP] = "PxDEVSLP", | |
86 | [18 ... 27] = "Reserved", | |
87 | [AHCI_PORT_REG_VENDOR_1 ... | |
88 | AHCI_PORT_REG_VENDOR_4] = "PxVS", | |
89 | }; | |
90 | ||
5fa0feec JS |
91 | static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = { |
92 | [AHCI_PORT_IRQ_BIT_DHRS] = "DHRS", | |
93 | [AHCI_PORT_IRQ_BIT_PSS] = "PSS", | |
94 | [AHCI_PORT_IRQ_BIT_DSS] = "DSS", | |
95 | [AHCI_PORT_IRQ_BIT_SDBS] = "SDBS", | |
96 | [AHCI_PORT_IRQ_BIT_UFS] = "UFS", | |
97 | [AHCI_PORT_IRQ_BIT_DPS] = "DPS", | |
98 | [AHCI_PORT_IRQ_BIT_PCS] = "PCS", | |
99 | [AHCI_PORT_IRQ_BIT_DMPS] = "DMPS", | |
100 | [8 ... 21] = "RESERVED", | |
101 | [AHCI_PORT_IRQ_BIT_PRCS] = "PRCS", | |
102 | [AHCI_PORT_IRQ_BIT_IPMS] = "IPMS", | |
103 | [AHCI_PORT_IRQ_BIT_OFS] = "OFS", | |
104 | [25] = "RESERVED", | |
105 | [AHCI_PORT_IRQ_BIT_INFS] = "INFS", | |
106 | [AHCI_PORT_IRQ_BIT_IFS] = "IFS", | |
107 | [AHCI_PORT_IRQ_BIT_HBDS] = "HBDS", | |
108 | [AHCI_PORT_IRQ_BIT_HBFS] = "HBFS", | |
109 | [AHCI_PORT_IRQ_BIT_TFES] = "TFES", | |
110 | [AHCI_PORT_IRQ_BIT_CPDS] = "CPDS" | |
111 | }; | |
f6ad2e32 | 112 | |
536551d7 | 113 | static uint32_t ahci_port_read(AHCIState *s, int port, int offset) |
f6ad2e32 AG |
114 | { |
115 | uint32_t val; | |
536551d7 JS |
116 | AHCIPortRegs *pr = &s->dev[port].port_regs; |
117 | enum AHCIPortReg regnum = offset / sizeof(uint32_t); | |
118 | assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); | |
f6ad2e32 | 119 | |
536551d7 JS |
120 | switch (regnum) { |
121 | case AHCI_PORT_REG_LST_ADDR: | |
f6ad2e32 AG |
122 | val = pr->lst_addr; |
123 | break; | |
536551d7 | 124 | case AHCI_PORT_REG_LST_ADDR_HI: |
f6ad2e32 AG |
125 | val = pr->lst_addr_hi; |
126 | break; | |
536551d7 | 127 | case AHCI_PORT_REG_FIS_ADDR: |
f6ad2e32 AG |
128 | val = pr->fis_addr; |
129 | break; | |
536551d7 | 130 | case AHCI_PORT_REG_FIS_ADDR_HI: |
f6ad2e32 AG |
131 | val = pr->fis_addr_hi; |
132 | break; | |
536551d7 | 133 | case AHCI_PORT_REG_IRQ_STAT: |
f6ad2e32 AG |
134 | val = pr->irq_stat; |
135 | break; | |
536551d7 | 136 | case AHCI_PORT_REG_IRQ_MASK: |
f6ad2e32 AG |
137 | val = pr->irq_mask; |
138 | break; | |
536551d7 | 139 | case AHCI_PORT_REG_CMD: |
f6ad2e32 AG |
140 | val = pr->cmd; |
141 | break; | |
536551d7 | 142 | case AHCI_PORT_REG_TFDATA: |
fac7aa7f | 143 | val = pr->tfdata; |
f6ad2e32 | 144 | break; |
536551d7 | 145 | case AHCI_PORT_REG_SIG: |
f6ad2e32 AG |
146 | val = pr->sig; |
147 | break; | |
536551d7 | 148 | case AHCI_PORT_REG_SCR_STAT: |
4be74634 | 149 | if (s->dev[port].port.ifs[0].blk) { |
f6ad2e32 AG |
150 | val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | |
151 | SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; | |
152 | } else { | |
153 | val = SATA_SCR_SSTATUS_DET_NODEV; | |
154 | } | |
155 | break; | |
536551d7 | 156 | case AHCI_PORT_REG_SCR_CTL: |
f6ad2e32 AG |
157 | val = pr->scr_ctl; |
158 | break; | |
536551d7 | 159 | case AHCI_PORT_REG_SCR_ERR: |
f6ad2e32 AG |
160 | val = pr->scr_err; |
161 | break; | |
536551d7 | 162 | case AHCI_PORT_REG_SCR_ACT: |
f6ad2e32 AG |
163 | val = pr->scr_act; |
164 | break; | |
536551d7 | 165 | case AHCI_PORT_REG_CMD_ISSUE: |
f6ad2e32 AG |
166 | val = pr->cmd_issue; |
167 | break; | |
f6ad2e32 | 168 | default: |
e5389163 JS |
169 | trace_ahci_port_read_default(s, port, AHCIPortReg_lookup[regnum], |
170 | offset); | |
f6ad2e32 AG |
171 | val = 0; |
172 | } | |
f6ad2e32 | 173 | |
e5389163 | 174 | trace_ahci_port_read(s, port, AHCIPortReg_lookup[regnum], offset, val); |
e4baa9f0 | 175 | return val; |
f6ad2e32 AG |
176 | } |
177 | ||
dc5a43ed | 178 | static void ahci_irq_raise(AHCIState *s) |
f6ad2e32 | 179 | { |
bb639f82 AF |
180 | DeviceState *dev_state = s->container; |
181 | PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state), | |
182 | TYPE_PCI_DEVICE); | |
f6ad2e32 | 183 | |
e4baa9f0 | 184 | trace_ahci_irq_raise(s); |
f6ad2e32 | 185 | |
bd164307 | 186 | if (pci_dev && msi_enabled(pci_dev)) { |
0d3aea56 | 187 | msi_notify(pci_dev, 0); |
f6ad2e32 AG |
188 | } else { |
189 | qemu_irq_raise(s->irq); | |
190 | } | |
191 | } | |
192 | ||
dc5a43ed | 193 | static void ahci_irq_lower(AHCIState *s) |
f6ad2e32 | 194 | { |
bb639f82 AF |
195 | DeviceState *dev_state = s->container; |
196 | PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state), | |
197 | TYPE_PCI_DEVICE); | |
f6ad2e32 | 198 | |
e4baa9f0 | 199 | trace_ahci_irq_lower(s); |
f6ad2e32 | 200 | |
bd164307 | 201 | if (!pci_dev || !msi_enabled(pci_dev)) { |
f6ad2e32 AG |
202 | qemu_irq_lower(s->irq); |
203 | } | |
204 | } | |
205 | ||
206 | static void ahci_check_irq(AHCIState *s) | |
207 | { | |
208 | int i; | |
e4baa9f0 | 209 | uint32_t old_irq = s->control_regs.irqstatus; |
f6ad2e32 | 210 | |
b8676728 | 211 | s->control_regs.irqstatus = 0; |
2c4b9d0e | 212 | for (i = 0; i < s->ports; i++) { |
f6ad2e32 AG |
213 | AHCIPortRegs *pr = &s->dev[i].port_regs; |
214 | if (pr->irq_stat & pr->irq_mask) { | |
215 | s->control_regs.irqstatus |= (1 << i); | |
216 | } | |
217 | } | |
e4baa9f0 | 218 | trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus); |
f6ad2e32 AG |
219 | if (s->control_regs.irqstatus && |
220 | (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { | |
dc5a43ed | 221 | ahci_irq_raise(s); |
f6ad2e32 | 222 | } else { |
dc5a43ed | 223 | ahci_irq_lower(s); |
f6ad2e32 AG |
224 | } |
225 | } | |
226 | ||
227 | static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, | |
5fa0feec | 228 | enum AHCIPortIRQ irqbit) |
f6ad2e32 | 229 | { |
159a9df0 | 230 | g_assert((unsigned)irqbit < 32); |
5fa0feec JS |
231 | uint32_t irq = 1U << irqbit; |
232 | uint32_t irqstat = d->port_regs.irq_stat | irq; | |
233 | ||
234 | trace_ahci_trigger_irq(s, d->port_no, | |
235 | AHCIPortIRQ_lookup[irqbit], irq, | |
236 | d->port_regs.irq_stat, irqstat, | |
237 | irqstat & d->port_regs.irq_mask); | |
f6ad2e32 | 238 | |
5fa0feec | 239 | d->port_regs.irq_stat = irqstat; |
f6ad2e32 AG |
240 | ahci_check_irq(s); |
241 | } | |
242 | ||
5a18e67d LT |
243 | static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr, |
244 | uint32_t wanted) | |
f6ad2e32 | 245 | { |
a8170e5e | 246 | hwaddr len = wanted; |
f6ad2e32 AG |
247 | |
248 | if (*ptr) { | |
5a18e67d | 249 | dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); |
f6ad2e32 AG |
250 | } |
251 | ||
5a18e67d | 252 | *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE); |
1d1c4bdb | 253 | if (len < wanted && *ptr) { |
5a18e67d | 254 | dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); |
f6ad2e32 AG |
255 | *ptr = NULL; |
256 | } | |
257 | } | |
258 | ||
cd6cb73b JS |
259 | /** |
260 | * Check the cmd register to see if we should start or stop | |
261 | * the DMA or FIS RX engines. | |
262 | * | |
d5904749 | 263 | * @ad: Device to dis/engage. |
cd6cb73b JS |
264 | * |
265 | * @return 0 on success, -1 on error. | |
266 | */ | |
d5904749 | 267 | static int ahci_cond_start_engines(AHCIDevice *ad) |
cd6cb73b JS |
268 | { |
269 | AHCIPortRegs *pr = &ad->port_regs; | |
d5904749 JS |
270 | bool cmd_start = pr->cmd & PORT_CMD_START; |
271 | bool cmd_on = pr->cmd & PORT_CMD_LIST_ON; | |
272 | bool fis_start = pr->cmd & PORT_CMD_FIS_RX; | |
273 | bool fis_on = pr->cmd & PORT_CMD_FIS_ON; | |
cd6cb73b | 274 | |
d5904749 | 275 | if (cmd_start && !cmd_on) { |
f32a2f33 | 276 | if (!ahci_map_clb_address(ad)) { |
d5904749 | 277 | pr->cmd &= ~PORT_CMD_START; |
cd6cb73b JS |
278 | error_report("AHCI: Failed to start DMA engine: " |
279 | "bad command list buffer address"); | |
280 | return -1; | |
281 | } | |
d5904749 JS |
282 | } else if (!cmd_start && cmd_on) { |
283 | ahci_unmap_clb_address(ad); | |
cd6cb73b JS |
284 | } |
285 | ||
d5904749 | 286 | if (fis_start && !fis_on) { |
f32a2f33 | 287 | if (!ahci_map_fis_address(ad)) { |
d5904749 | 288 | pr->cmd &= ~PORT_CMD_FIS_RX; |
cd6cb73b JS |
289 | error_report("AHCI: Failed to start FIS receive engine: " |
290 | "bad FIS receive buffer address"); | |
291 | return -1; | |
292 | } | |
d5904749 JS |
293 | } else if (!fis_start && fis_on) { |
294 | ahci_unmap_fis_address(ad); | |
cd6cb73b JS |
295 | } |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
f1123e4b | 300 | static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) |
f6ad2e32 AG |
301 | { |
302 | AHCIPortRegs *pr = &s->dev[port].port_regs; | |
f647f458 JS |
303 | enum AHCIPortReg regnum = offset / sizeof(uint32_t); |
304 | assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); | |
06e35065 | 305 | trace_ahci_port_write(s, port, AHCIPortReg_lookup[regnum], offset, val); |
f6ad2e32 | 306 | |
f647f458 JS |
307 | switch (regnum) { |
308 | case AHCI_PORT_REG_LST_ADDR: | |
f1123e4b JS |
309 | pr->lst_addr = val; |
310 | break; | |
f647f458 | 311 | case AHCI_PORT_REG_LST_ADDR_HI: |
f1123e4b JS |
312 | pr->lst_addr_hi = val; |
313 | break; | |
f647f458 | 314 | case AHCI_PORT_REG_FIS_ADDR: |
f1123e4b JS |
315 | pr->fis_addr = val; |
316 | break; | |
f647f458 | 317 | case AHCI_PORT_REG_FIS_ADDR_HI: |
f1123e4b JS |
318 | pr->fis_addr_hi = val; |
319 | break; | |
f647f458 | 320 | case AHCI_PORT_REG_IRQ_STAT: |
f1123e4b JS |
321 | pr->irq_stat &= ~val; |
322 | ahci_check_irq(s); | |
323 | break; | |
f647f458 | 324 | case AHCI_PORT_REG_IRQ_MASK: |
f1123e4b JS |
325 | pr->irq_mask = val & 0xfdc000ff; |
326 | ahci_check_irq(s); | |
327 | break; | |
f647f458 | 328 | case AHCI_PORT_REG_CMD: |
f1123e4b JS |
329 | /* Block any Read-only fields from being set; |
330 | * including LIST_ON and FIS_ON. | |
331 | * The spec requires to set ICC bits to zero after the ICC change | |
332 | * is done. We don't support ICC state changes, therefore always | |
333 | * force the ICC bits to zero. | |
334 | */ | |
335 | pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) | | |
336 | (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK)); | |
337 | ||
338 | /* Check FIS RX and CLB engines */ | |
339 | ahci_cond_start_engines(&s->dev[port]); | |
340 | ||
341 | /* XXX usually the FIS would be pending on the bus here and | |
342 | issuing deferred until the OS enables FIS receival. | |
343 | Instead, we only submit it once - which works in most | |
344 | cases, but is a hack. */ | |
345 | if ((pr->cmd & PORT_CMD_FIS_ON) && | |
346 | !s->dev[port].init_d2h_sent) { | |
347 | ahci_init_d2h(&s->dev[port]); | |
348 | } | |
349 | ||
350 | check_cmd(s, port); | |
351 | break; | |
f647f458 JS |
352 | case AHCI_PORT_REG_TFDATA: |
353 | case AHCI_PORT_REG_SIG: | |
354 | case AHCI_PORT_REG_SCR_STAT: | |
f1123e4b JS |
355 | /* Read Only */ |
356 | break; | |
f647f458 | 357 | case AHCI_PORT_REG_SCR_CTL: |
f1123e4b JS |
358 | if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && |
359 | ((val & AHCI_SCR_SCTL_DET) == 0)) { | |
360 | ahci_reset_port(s, port); | |
361 | } | |
362 | pr->scr_ctl = val; | |
363 | break; | |
f647f458 | 364 | case AHCI_PORT_REG_SCR_ERR: |
f1123e4b JS |
365 | pr->scr_err &= ~val; |
366 | break; | |
f647f458 | 367 | case AHCI_PORT_REG_SCR_ACT: |
f1123e4b JS |
368 | /* RW1 */ |
369 | pr->scr_act |= val; | |
370 | break; | |
f647f458 | 371 | case AHCI_PORT_REG_CMD_ISSUE: |
f1123e4b JS |
372 | pr->cmd_issue |= val; |
373 | check_cmd(s, port); | |
374 | break; | |
375 | default: | |
06e35065 JS |
376 | trace_ahci_port_write_unimpl(s, port, AHCIPortReg_lookup[regnum], |
377 | offset, val); | |
378 | qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " | |
379 | "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32, | |
380 | port, AHCIPortReg_lookup[regnum], offset, val); | |
f1123e4b | 381 | break; |
f6ad2e32 AG |
382 | } |
383 | } | |
384 | ||
e9ebb2f7 | 385 | static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr) |
f6ad2e32 | 386 | { |
67e576c2 | 387 | AHCIState *s = opaque; |
f6ad2e32 AG |
388 | uint32_t val = 0; |
389 | ||
f6ad2e32 | 390 | if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { |
215c41aa JS |
391 | enum AHCIHostReg regnum = addr / 4; |
392 | assert(regnum < AHCI_HOST_REG__COUNT); | |
393 | ||
394 | switch (regnum) { | |
395 | case AHCI_HOST_REG_CAP: | |
f6ad2e32 AG |
396 | val = s->control_regs.cap; |
397 | break; | |
215c41aa | 398 | case AHCI_HOST_REG_CTL: |
f6ad2e32 AG |
399 | val = s->control_regs.ghc; |
400 | break; | |
215c41aa | 401 | case AHCI_HOST_REG_IRQ_STAT: |
f6ad2e32 AG |
402 | val = s->control_regs.irqstatus; |
403 | break; | |
215c41aa | 404 | case AHCI_HOST_REG_PORTS_IMPL: |
f6ad2e32 AG |
405 | val = s->control_regs.impl; |
406 | break; | |
215c41aa | 407 | case AHCI_HOST_REG_VERSION: |
f6ad2e32 AG |
408 | val = s->control_regs.version; |
409 | break; | |
215c41aa | 410 | default: |
9da8ac32 JS |
411 | trace_ahci_mem_read_32_host_default(s, AHCIHostReg_lookup[regnum], |
412 | addr); | |
f6ad2e32 | 413 | } |
9da8ac32 | 414 | trace_ahci_mem_read_32_host(s, AHCIHostReg_lookup[regnum], addr, val); |
f6ad2e32 | 415 | } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && |
2c4b9d0e AG |
416 | (addr < (AHCI_PORT_REGS_START_ADDR + |
417 | (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { | |
f6ad2e32 AG |
418 | val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, |
419 | addr & AHCI_PORT_ADDR_OFFSET_MASK); | |
9da8ac32 JS |
420 | } else { |
421 | trace_ahci_mem_read_32_default(s, addr, val); | |
f6ad2e32 AG |
422 | } |
423 | ||
e4baa9f0 | 424 | trace_ahci_mem_read_32(s, addr, val); |
f6ad2e32 AG |
425 | return val; |
426 | } | |
427 | ||
428 | ||
e9ebb2f7 JS |
429 | /** |
430 | * AHCI 1.3 section 3 ("HBA Memory Registers") | |
431 | * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads. | |
432 | * Caller is responsible for masking unwanted higher order bytes. | |
433 | */ | |
434 | static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size) | |
435 | { | |
436 | hwaddr aligned = addr & ~0x3; | |
437 | int ofst = addr - aligned; | |
438 | uint64_t lo = ahci_mem_read_32(opaque, aligned); | |
439 | uint64_t hi; | |
80274267 | 440 | uint64_t val; |
e9ebb2f7 JS |
441 | |
442 | /* if < 8 byte read does not cross 4 byte boundary */ | |
443 | if (ofst + size <= 4) { | |
80274267 PC |
444 | val = lo >> (ofst * 8); |
445 | } else { | |
719a3077 | 446 | g_assert(size > 1); |
80274267 PC |
447 | |
448 | /* If the 64bit read is unaligned, we will produce undefined | |
449 | * results. AHCI does not support unaligned 64bit reads. */ | |
450 | hi = ahci_mem_read_32(opaque, aligned + 4); | |
451 | val = (hi << 32 | lo) >> (ofst * 8); | |
e9ebb2f7 | 452 | } |
e9ebb2f7 | 453 | |
e4baa9f0 | 454 | trace_ahci_mem_read(opaque, size, addr, val); |
80274267 | 455 | return val; |
e9ebb2f7 JS |
456 | } |
457 | ||
f6ad2e32 | 458 | |
a8170e5e | 459 | static void ahci_mem_write(void *opaque, hwaddr addr, |
67e576c2 | 460 | uint64_t val, unsigned size) |
f6ad2e32 | 461 | { |
67e576c2 | 462 | AHCIState *s = opaque; |
f6ad2e32 | 463 | |
e4baa9f0 | 464 | trace_ahci_mem_write(s, size, addr, val); |
80274267 | 465 | |
f6ad2e32 AG |
466 | /* Only aligned reads are allowed on AHCI */ |
467 | if (addr & 3) { | |
580e7333 PMD |
468 | qemu_log_mask(LOG_GUEST_ERROR, |
469 | "ahci: Mis-aligned write to addr 0x%03" HWADDR_PRIX "\n", | |
470 | addr); | |
f6ad2e32 AG |
471 | return; |
472 | } | |
473 | ||
474 | if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { | |
d566811a JS |
475 | enum AHCIHostReg regnum = addr / 4; |
476 | assert(regnum < AHCI_HOST_REG__COUNT); | |
477 | ||
478 | switch (regnum) { | |
479 | case AHCI_HOST_REG_CAP: /* R/WO, RO */ | |
467378ba JS |
480 | /* FIXME handle R/WO */ |
481 | break; | |
d566811a | 482 | case AHCI_HOST_REG_CTL: /* R/W */ |
467378ba JS |
483 | if (val & HOST_CTL_RESET) { |
484 | ahci_reset(s); | |
485 | } else { | |
486 | s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; | |
f6ad2e32 | 487 | ahci_check_irq(s); |
467378ba JS |
488 | } |
489 | break; | |
d566811a | 490 | case AHCI_HOST_REG_IRQ_STAT: /* R/WC, RO */ |
467378ba JS |
491 | s->control_regs.irqstatus &= ~val; |
492 | ahci_check_irq(s); | |
493 | break; | |
d566811a | 494 | case AHCI_HOST_REG_PORTS_IMPL: /* R/WO, RO */ |
467378ba JS |
495 | /* FIXME handle R/WO */ |
496 | break; | |
d566811a | 497 | case AHCI_HOST_REG_VERSION: /* RO */ |
467378ba JS |
498 | /* FIXME report write? */ |
499 | break; | |
500 | default: | |
01796126 JS |
501 | qemu_log_mask(LOG_UNIMP, |
502 | "Attempted write to unimplemented register: " | |
503 | "AHCI host register %s, " | |
504 | "offset 0x%"PRIx64": 0x%"PRIx64, | |
505 | AHCIHostReg_lookup[regnum], addr, val); | |
506 | trace_ahci_mem_write_host_unimpl(s, size, | |
507 | AHCIHostReg_lookup[regnum], addr); | |
f6ad2e32 | 508 | } |
01796126 JS |
509 | trace_ahci_mem_write_host(s, size, AHCIHostReg_lookup[regnum], |
510 | addr, val); | |
f6ad2e32 | 511 | } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && |
2c4b9d0e | 512 | (addr < (AHCI_PORT_REGS_START_ADDR + |
467378ba | 513 | (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { |
f6ad2e32 AG |
514 | ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, |
515 | addr & AHCI_PORT_ADDR_OFFSET_MASK, val); | |
01796126 JS |
516 | } else { |
517 | qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " | |
518 | "AHCI global register at offset 0x%"PRIx64": 0x%"PRIx64, | |
519 | addr, val); | |
520 | trace_ahci_mem_write_unimpl(s, size, addr, val); | |
f6ad2e32 | 521 | } |
f6ad2e32 AG |
522 | } |
523 | ||
a348f108 | 524 | static const MemoryRegionOps ahci_mem_ops = { |
67e576c2 AK |
525 | .read = ahci_mem_read, |
526 | .write = ahci_mem_write, | |
527 | .endianness = DEVICE_LITTLE_ENDIAN, | |
f6ad2e32 AG |
528 | }; |
529 | ||
a8170e5e | 530 | static uint64_t ahci_idp_read(void *opaque, hwaddr addr, |
465f1ab1 DV |
531 | unsigned size) |
532 | { | |
533 | AHCIState *s = opaque; | |
534 | ||
535 | if (addr == s->idp_offset) { | |
536 | /* index register */ | |
537 | return s->idp_index; | |
538 | } else if (addr == s->idp_offset + 4) { | |
539 | /* data register - do memory read at location selected by index */ | |
540 | return ahci_mem_read(opaque, s->idp_index, size); | |
541 | } else { | |
542 | return 0; | |
543 | } | |
544 | } | |
545 | ||
a8170e5e | 546 | static void ahci_idp_write(void *opaque, hwaddr addr, |
465f1ab1 DV |
547 | uint64_t val, unsigned size) |
548 | { | |
549 | AHCIState *s = opaque; | |
550 | ||
551 | if (addr == s->idp_offset) { | |
552 | /* index register - mask off reserved bits */ | |
553 | s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); | |
554 | } else if (addr == s->idp_offset + 4) { | |
555 | /* data register - do memory write at location selected by index */ | |
556 | ahci_mem_write(opaque, s->idp_index, val, size); | |
557 | } | |
558 | } | |
559 | ||
a348f108 | 560 | static const MemoryRegionOps ahci_idp_ops = { |
465f1ab1 DV |
561 | .read = ahci_idp_read, |
562 | .write = ahci_idp_write, | |
563 | .endianness = DEVICE_LITTLE_ENDIAN, | |
564 | }; | |
565 | ||
566 | ||
f6ad2e32 AG |
567 | static void ahci_reg_init(AHCIState *s) |
568 | { | |
569 | int i; | |
570 | ||
2c4b9d0e | 571 | s->control_regs.cap = (s->ports - 1) | |
f6ad2e32 AG |
572 | (AHCI_NUM_COMMAND_SLOTS << 8) | |
573 | (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | | |
98cb5dcc | 574 | HOST_CAP_NCQ | HOST_CAP_AHCI | HOST_CAP_64; |
f6ad2e32 | 575 | |
2c4b9d0e | 576 | s->control_regs.impl = (1 << s->ports) - 1; |
f6ad2e32 AG |
577 | |
578 | s->control_regs.version = AHCI_VERSION_1_0; | |
579 | ||
2c4b9d0e | 580 | for (i = 0; i < s->ports; i++) { |
f6ad2e32 AG |
581 | s->dev[i].port_state = STATE_RUN; |
582 | } | |
583 | } | |
584 | ||
f6ad2e32 AG |
585 | static void check_cmd(AHCIState *s, int port) |
586 | { | |
587 | AHCIPortRegs *pr = &s->dev[port].port_regs; | |
9364384d | 588 | uint8_t slot; |
f6ad2e32 AG |
589 | |
590 | if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { | |
591 | for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { | |
ee25595f | 592 | if ((pr->cmd_issue & (1U << slot)) && |
f6ad2e32 | 593 | !handle_cmd(s, port, slot)) { |
ee25595f | 594 | pr->cmd_issue &= ~(1U << slot); |
f6ad2e32 AG |
595 | } |
596 | } | |
597 | } | |
598 | } | |
599 | ||
600 | static void ahci_check_cmd_bh(void *opaque) | |
601 | { | |
602 | AHCIDevice *ad = opaque; | |
603 | ||
604 | qemu_bh_delete(ad->check_bh); | |
605 | ad->check_bh = NULL; | |
606 | ||
f6ad2e32 AG |
607 | check_cmd(ad->hba, ad->port_no); |
608 | } | |
609 | ||
87e62065 AG |
610 | static void ahci_init_d2h(AHCIDevice *ad) |
611 | { | |
87e62065 | 612 | IDEState *ide_state = &ad->port.ifs[0]; |
33a983cb | 613 | AHCIPortRegs *pr = &ad->port_regs; |
87e62065 | 614 | |
e47f9eb1 JS |
615 | if (ad->init_d2h_sent) { |
616 | return; | |
617 | } | |
87e62065 | 618 | |
e47f9eb1 JS |
619 | if (ahci_write_fis_d2h(ad)) { |
620 | ad->init_d2h_sent = true; | |
621 | /* We're emulating receiving the first Reg H2D Fis from the device; | |
622 | * Update the SIG register, but otherwise proceed as normal. */ | |
40fe17be | 623 | pr->sig = ((uint32_t)ide_state->hcyl << 24) | |
e47f9eb1 JS |
624 | (ide_state->lcyl << 16) | |
625 | (ide_state->sector << 8) | | |
626 | (ide_state->nsector & 0xFF); | |
627 | } | |
87e62065 AG |
628 | } |
629 | ||
33a983cb JS |
630 | static void ahci_set_signature(AHCIDevice *ad, uint32_t sig) |
631 | { | |
632 | IDEState *s = &ad->port.ifs[0]; | |
633 | s->hcyl = sig >> 24 & 0xFF; | |
634 | s->lcyl = sig >> 16 & 0xFF; | |
635 | s->sector = sig >> 8 & 0xFF; | |
636 | s->nsector = sig & 0xFF; | |
637 | ||
e4baa9f0 JS |
638 | trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector, |
639 | s->lcyl, s->hcyl, sig); | |
33a983cb JS |
640 | } |
641 | ||
f6ad2e32 AG |
642 | static void ahci_reset_port(AHCIState *s, int port) |
643 | { | |
644 | AHCIDevice *d = &s->dev[port]; | |
645 | AHCIPortRegs *pr = &d->port_regs; | |
646 | IDEState *ide_state = &d->port.ifs[0]; | |
f6ad2e32 AG |
647 | int i; |
648 | ||
e4baa9f0 | 649 | trace_ahci_reset_port(s, port); |
f6ad2e32 AG |
650 | |
651 | ide_bus_reset(&d->port); | |
652 | ide_state->ncq_queues = AHCI_MAX_CMDS; | |
653 | ||
f6ad2e32 | 654 | pr->scr_stat = 0; |
f6ad2e32 AG |
655 | pr->scr_err = 0; |
656 | pr->scr_act = 0; | |
fac7aa7f JS |
657 | pr->tfdata = 0x7F; |
658 | pr->sig = 0xFFFFFFFF; | |
f6ad2e32 | 659 | d->busy_slot = -1; |
4ac557c8 | 660 | d->init_d2h_sent = false; |
f6ad2e32 AG |
661 | |
662 | ide_state = &s->dev[port].port.ifs[0]; | |
4be74634 | 663 | if (!ide_state->blk) { |
f6ad2e32 AG |
664 | return; |
665 | } | |
666 | ||
667 | /* reset ncq queue */ | |
668 | for (i = 0; i < AHCI_MAX_CMDS; i++) { | |
669 | NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; | |
7c03a691 | 670 | ncq_tfs->halt = false; |
f6ad2e32 AG |
671 | if (!ncq_tfs->used) { |
672 | continue; | |
673 | } | |
674 | ||
675 | if (ncq_tfs->aiocb) { | |
4be74634 | 676 | blk_aio_cancel(ncq_tfs->aiocb); |
f6ad2e32 AG |
677 | ncq_tfs->aiocb = NULL; |
678 | } | |
679 | ||
4be74634 | 680 | /* Maybe we just finished the request thanks to blk_aio_cancel() */ |
c9b308d2 AG |
681 | if (!ncq_tfs->used) { |
682 | continue; | |
683 | } | |
684 | ||
f6ad2e32 AG |
685 | qemu_sglist_destroy(&ncq_tfs->sglist); |
686 | ncq_tfs->used = 0; | |
687 | } | |
688 | ||
f6ad2e32 | 689 | s->dev[port].port_state = STATE_RUN; |
f91a0aa3 | 690 | if (ide_state->drive_kind == IDE_CD) { |
33a983cb | 691 | ahci_set_signature(d, SATA_SIGNATURE_CDROM);\ |
f6ad2e32 AG |
692 | ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; |
693 | } else { | |
33a983cb | 694 | ahci_set_signature(d, SATA_SIGNATURE_DISK); |
f6ad2e32 AG |
695 | ide_state->status = SEEK_STAT | WRERR_STAT; |
696 | } | |
697 | ||
698 | ide_state->error = 1; | |
87e62065 | 699 | ahci_init_d2h(d); |
f6ad2e32 AG |
700 | } |
701 | ||
797285c8 | 702 | /* Buffer pretty output based on a raw FIS structure. */ |
26941eb4 | 703 | static char *ahci_pretty_buffer_fis(const uint8_t *fis, int cmd_len) |
f6ad2e32 | 704 | { |
f6ad2e32 | 705 | int i; |
797285c8 | 706 | GString *s = g_string_new("FIS:"); |
f6ad2e32 | 707 | |
f6ad2e32 AG |
708 | for (i = 0; i < cmd_len; i++) { |
709 | if ((i & 0xf) == 0) { | |
797285c8 | 710 | g_string_append_printf(s, "\n0x%02x: ", i); |
f6ad2e32 | 711 | } |
797285c8 | 712 | g_string_append_printf(s, "%02x ", fis[i]); |
f6ad2e32 | 713 | } |
797285c8 JS |
714 | g_string_append_c(s, '\n'); |
715 | ||
716 | return g_string_free(s, FALSE); | |
f6ad2e32 AG |
717 | } |
718 | ||
a13ab5a3 JS |
719 | static bool ahci_map_fis_address(AHCIDevice *ad) |
720 | { | |
721 | AHCIPortRegs *pr = &ad->port_regs; | |
722 | map_page(ad->hba->as, &ad->res_fis, | |
723 | ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); | |
f32a2f33 JS |
724 | if (ad->res_fis != NULL) { |
725 | pr->cmd |= PORT_CMD_FIS_ON; | |
726 | return true; | |
727 | } | |
728 | ||
729 | pr->cmd &= ~PORT_CMD_FIS_ON; | |
730 | return false; | |
a13ab5a3 JS |
731 | } |
732 | ||
fc3d8e11 JS |
733 | static void ahci_unmap_fis_address(AHCIDevice *ad) |
734 | { | |
99b4cb71 | 735 | if (ad->res_fis == NULL) { |
e4baa9f0 | 736 | trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no); |
99b4cb71 JS |
737 | return; |
738 | } | |
f32a2f33 | 739 | ad->port_regs.cmd &= ~PORT_CMD_FIS_ON; |
fc3d8e11 JS |
740 | dma_memory_unmap(ad->hba->as, ad->res_fis, 256, |
741 | DMA_DIRECTION_FROM_DEVICE, 256); | |
742 | ad->res_fis = NULL; | |
743 | } | |
744 | ||
a13ab5a3 JS |
745 | static bool ahci_map_clb_address(AHCIDevice *ad) |
746 | { | |
747 | AHCIPortRegs *pr = &ad->port_regs; | |
748 | ad->cur_cmd = NULL; | |
749 | map_page(ad->hba->as, &ad->lst, | |
750 | ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); | |
f32a2f33 JS |
751 | if (ad->lst != NULL) { |
752 | pr->cmd |= PORT_CMD_LIST_ON; | |
753 | return true; | |
754 | } | |
755 | ||
756 | pr->cmd &= ~PORT_CMD_LIST_ON; | |
757 | return false; | |
a13ab5a3 JS |
758 | } |
759 | ||
fc3d8e11 JS |
760 | static void ahci_unmap_clb_address(AHCIDevice *ad) |
761 | { | |
99b4cb71 | 762 | if (ad->lst == NULL) { |
e4baa9f0 | 763 | trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no); |
99b4cb71 JS |
764 | return; |
765 | } | |
f32a2f33 | 766 | ad->port_regs.cmd &= ~PORT_CMD_LIST_ON; |
fc3d8e11 JS |
767 | dma_memory_unmap(ad->hba->as, ad->lst, 1024, |
768 | DMA_DIRECTION_FROM_DEVICE, 1024); | |
769 | ad->lst = NULL; | |
770 | } | |
771 | ||
7c649ac5 | 772 | static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs) |
f6ad2e32 | 773 | { |
7c649ac5 | 774 | AHCIDevice *ad = ncq_tfs->drive; |
fac7aa7f | 775 | AHCIPortRegs *pr = &ad->port_regs; |
f6ad2e32 | 776 | IDEState *ide_state; |
54a7f8f3 | 777 | SDBFIS *sdb_fis; |
f6ad2e32 | 778 | |
7c649ac5 | 779 | if (!ad->res_fis || |
f6ad2e32 AG |
780 | !(pr->cmd & PORT_CMD_FIS_RX)) { |
781 | return; | |
782 | } | |
783 | ||
54a7f8f3 | 784 | sdb_fis = (SDBFIS *)&ad->res_fis[RES_FIS_SDBFIS]; |
fac7aa7f | 785 | ide_state = &ad->port.ifs[0]; |
f6ad2e32 | 786 | |
17fcb74a | 787 | sdb_fis->type = SATA_FIS_TYPE_SDB; |
54a7f8f3 | 788 | /* Interrupt pending & Notification bit */ |
7c649ac5 | 789 | sdb_fis->flags = 0x40; /* Interrupt bit, always 1 for NCQ */ |
54a7f8f3 JS |
790 | sdb_fis->status = ide_state->status & 0x77; |
791 | sdb_fis->error = ide_state->error; | |
792 | /* update SAct field in SDB_FIS */ | |
54a7f8f3 | 793 | sdb_fis->payload = cpu_to_le32(ad->finished); |
f6ad2e32 | 794 | |
fac7aa7f JS |
795 | /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */ |
796 | pr->tfdata = (ad->port.ifs[0].error << 8) | | |
797 | (ad->port.ifs[0].status & 0x77) | | |
798 | (pr->tfdata & 0x88); | |
7c649ac5 JS |
799 | pr->scr_act &= ~ad->finished; |
800 | ad->finished = 0; | |
fac7aa7f | 801 | |
7c649ac5 JS |
802 | /* Trigger IRQ if interrupt bit is set (which currently, it always is) */ |
803 | if (sdb_fis->flags & 0x40) { | |
5fa0feec | 804 | ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS); |
7c649ac5 | 805 | } |
f6ad2e32 AG |
806 | } |
807 | ||
ae79c2db | 808 | static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len, bool pio_fis_i) |
08841520 PB |
809 | { |
810 | AHCIPortRegs *pr = &ad->port_regs; | |
dd628221 | 811 | uint8_t *pio_fis; |
7b8bad1b | 812 | IDEState *s = &ad->port.ifs[0]; |
08841520 PB |
813 | |
814 | if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { | |
815 | return; | |
816 | } | |
817 | ||
08841520 PB |
818 | pio_fis = &ad->res_fis[RES_FIS_PSFIS]; |
819 | ||
17fcb74a | 820 | pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP; |
ae79c2db | 821 | pio_fis[1] = (pio_fis_i ? (1 << 6) : 0); |
7b8bad1b JS |
822 | pio_fis[2] = s->status; |
823 | pio_fis[3] = s->error; | |
824 | ||
825 | pio_fis[4] = s->sector; | |
826 | pio_fis[5] = s->lcyl; | |
827 | pio_fis[6] = s->hcyl; | |
828 | pio_fis[7] = s->select; | |
829 | pio_fis[8] = s->hob_sector; | |
830 | pio_fis[9] = s->hob_lcyl; | |
831 | pio_fis[10] = s->hob_hcyl; | |
832 | pio_fis[11] = 0; | |
dd628221 JS |
833 | pio_fis[12] = s->nsector & 0xFF; |
834 | pio_fis[13] = (s->nsector >> 8) & 0xFF; | |
08841520 | 835 | pio_fis[14] = 0; |
7b8bad1b | 836 | pio_fis[15] = s->status; |
08841520 PB |
837 | pio_fis[16] = len & 255; |
838 | pio_fis[17] = len >> 8; | |
839 | pio_fis[18] = 0; | |
840 | pio_fis[19] = 0; | |
841 | ||
fac7aa7f JS |
842 | /* Update shadow registers: */ |
843 | pr->tfdata = (ad->port.ifs[0].error << 8) | | |
844 | ad->port.ifs[0].status; | |
845 | ||
08841520 | 846 | if (pio_fis[2] & ERR_STAT) { |
5fa0feec | 847 | ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); |
08841520 | 848 | } |
08841520 PB |
849 | } |
850 | ||
e47f9eb1 | 851 | static bool ahci_write_fis_d2h(AHCIDevice *ad) |
f6ad2e32 AG |
852 | { |
853 | AHCIPortRegs *pr = &ad->port_regs; | |
854 | uint8_t *d2h_fis; | |
855 | int i; | |
7b8bad1b | 856 | IDEState *s = &ad->port.ifs[0]; |
f6ad2e32 AG |
857 | |
858 | if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { | |
e47f9eb1 | 859 | return false; |
f6ad2e32 AG |
860 | } |
861 | ||
f6ad2e32 AG |
862 | d2h_fis = &ad->res_fis[RES_FIS_RFIS]; |
863 | ||
17fcb74a | 864 | d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H; |
ae79c2db | 865 | d2h_fis[1] = (1 << 6); /* interrupt bit */ |
7b8bad1b JS |
866 | d2h_fis[2] = s->status; |
867 | d2h_fis[3] = s->error; | |
868 | ||
869 | d2h_fis[4] = s->sector; | |
870 | d2h_fis[5] = s->lcyl; | |
871 | d2h_fis[6] = s->hcyl; | |
872 | d2h_fis[7] = s->select; | |
873 | d2h_fis[8] = s->hob_sector; | |
874 | d2h_fis[9] = s->hob_lcyl; | |
875 | d2h_fis[10] = s->hob_hcyl; | |
876 | d2h_fis[11] = 0; | |
dd628221 JS |
877 | d2h_fis[12] = s->nsector & 0xFF; |
878 | d2h_fis[13] = (s->nsector >> 8) & 0xFF; | |
4bb9c939 | 879 | for (i = 14; i < 20; i++) { |
f6ad2e32 AG |
880 | d2h_fis[i] = 0; |
881 | } | |
882 | ||
fac7aa7f JS |
883 | /* Update shadow registers: */ |
884 | pr->tfdata = (ad->port.ifs[0].error << 8) | | |
885 | ad->port.ifs[0].status; | |
886 | ||
f6ad2e32 | 887 | if (d2h_fis[2] & ERR_STAT) { |
5fa0feec | 888 | ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); |
f6ad2e32 AG |
889 | } |
890 | ||
5fa0feec | 891 | ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS); |
e47f9eb1 | 892 | return true; |
f6ad2e32 AG |
893 | } |
894 | ||
d02f8adc RJ |
895 | static int prdt_tbl_entry_size(const AHCI_SG *tbl) |
896 | { | |
a718978e | 897 | /* flags_size is zero-based */ |
d02f8adc RJ |
898 | return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1; |
899 | } | |
900 | ||
9fbf0fa8 JS |
901 | /** |
902 | * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist. | |
903 | * @ad: The AHCIDevice for whom we are building the SGList. | |
904 | * @sglist: The SGList target to add PRD entries to. | |
905 | * @cmd: The AHCI Command Header that describes where the PRDT is. | |
906 | * @limit: The remaining size of the S/ATA transaction, in bytes. | |
907 | * @offset: The number of bytes already transferred, in bytes. | |
908 | * | |
909 | * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of | |
910 | * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop | |
911 | * building the sglist from the PRDT as soon as we hit @limit bytes, | |
912 | * which is <= INT32_MAX/2GiB. | |
913 | */ | |
3251bdcf | 914 | static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, |
9fbf0fa8 | 915 | AHCICmdHdr *cmd, int64_t limit, uint64_t offset) |
f6ad2e32 | 916 | { |
d56f4d69 JS |
917 | uint16_t opts = le16_to_cpu(cmd->opts); |
918 | uint16_t prdtl = le16_to_cpu(cmd->prdtl); | |
919 | uint64_t cfis_addr = le64_to_cpu(cmd->tbl_addr); | |
920 | uint64_t prdt_addr = cfis_addr + 0x80; | |
921 | dma_addr_t prdt_len = (prdtl * sizeof(AHCI_SG)); | |
10ca2943 | 922 | dma_addr_t real_prdt_len = prdt_len; |
f6ad2e32 AG |
923 | uint8_t *prdt; |
924 | int i; | |
925 | int r = 0; | |
3251bdcf | 926 | uint64_t sum = 0; |
61f52e06 | 927 | int off_idx = -1; |
3251bdcf | 928 | int64_t off_pos = -1; |
61f52e06 | 929 | int tbl_entry_size; |
f487b677 PB |
930 | IDEBus *bus = &ad->port; |
931 | BusState *qbus = BUS(bus); | |
f6ad2e32 | 932 | |
e4baa9f0 JS |
933 | trace_ahci_populate_sglist(ad->hba, ad->port_no); |
934 | ||
d56f4d69 | 935 | if (!prdtl) { |
e4baa9f0 | 936 | trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts); |
f6ad2e32 AG |
937 | return -1; |
938 | } | |
939 | ||
940 | /* map PRDT */ | |
df32fd1c | 941 | if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, |
10ca2943 | 942 | DMA_DIRECTION_TO_DEVICE))){ |
e4baa9f0 | 943 | trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no); |
f6ad2e32 AG |
944 | return -1; |
945 | } | |
946 | ||
947 | if (prdt_len < real_prdt_len) { | |
e4baa9f0 | 948 | trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no); |
f6ad2e32 AG |
949 | r = -1; |
950 | goto out; | |
951 | } | |
952 | ||
953 | /* Get entries in the PRDT, init a qemu sglist accordingly */ | |
d56f4d69 | 954 | if (prdtl > 0) { |
f6ad2e32 | 955 | AHCI_SG *tbl = (AHCI_SG *)prdt; |
61f52e06 | 956 | sum = 0; |
d56f4d69 | 957 | for (i = 0; i < prdtl; i++) { |
d02f8adc | 958 | tbl_entry_size = prdt_tbl_entry_size(&tbl[i]); |
a718978e | 959 | if (offset < (sum + tbl_entry_size)) { |
61f52e06 JB |
960 | off_idx = i; |
961 | off_pos = offset - sum; | |
962 | break; | |
963 | } | |
964 | sum += tbl_entry_size; | |
965 | } | |
966 | if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { | |
e4baa9f0 JS |
967 | trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no, |
968 | off_idx, off_pos); | |
61f52e06 JB |
969 | r = -1; |
970 | goto out; | |
971 | } | |
972 | ||
d56f4d69 | 973 | qemu_sglist_init(sglist, qbus->parent, (prdtl - off_idx), |
f487b677 | 974 | ad->hba->as); |
ac381236 | 975 | qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos, |
a718978e JS |
976 | MIN(prdt_tbl_entry_size(&tbl[off_idx]) - off_pos, |
977 | limit)); | |
61f52e06 | 978 | |
a718978e | 979 | for (i = off_idx + 1; i < prdtl && sglist->size < limit; i++) { |
f6ad2e32 | 980 | qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), |
a718978e JS |
981 | MIN(prdt_tbl_entry_size(&tbl[i]), |
982 | limit - sglist->size)); | |
f6ad2e32 AG |
983 | } |
984 | } | |
985 | ||
986 | out: | |
df32fd1c | 987 | dma_memory_unmap(ad->hba->as, prdt, prdt_len, |
10ca2943 | 988 | DMA_DIRECTION_TO_DEVICE, prdt_len); |
f6ad2e32 AG |
989 | return r; |
990 | } | |
991 | ||
a55c8231 JS |
992 | static void ncq_err(NCQTransferState *ncq_tfs) |
993 | { | |
994 | IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; | |
995 | ||
996 | ide_state->error = ABRT_ERR; | |
997 | ide_state->status = READY_STAT | ERR_STAT; | |
998 | ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag); | |
5839df7b | 999 | qemu_sglist_destroy(&ncq_tfs->sglist); |
4ab0359a | 1000 | ncq_tfs->used = 0; |
a55c8231 JS |
1001 | } |
1002 | ||
54f32237 JS |
1003 | static void ncq_finish(NCQTransferState *ncq_tfs) |
1004 | { | |
7c649ac5 JS |
1005 | /* If we didn't error out, set our finished bit. Errored commands |
1006 | * do not get a bit set for the SDB FIS ACT register, nor do they | |
1007 | * clear the outstanding bit in scr_act (PxSACT). */ | |
1008 | if (!(ncq_tfs->drive->port_regs.scr_err & (1 << ncq_tfs->tag))) { | |
1009 | ncq_tfs->drive->finished |= (1 << ncq_tfs->tag); | |
1010 | } | |
54f32237 | 1011 | |
7c649ac5 | 1012 | ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs); |
54f32237 | 1013 | |
e4baa9f0 JS |
1014 | trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, |
1015 | ncq_tfs->tag); | |
54f32237 JS |
1016 | |
1017 | block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk), | |
1018 | &ncq_tfs->acct); | |
1019 | qemu_sglist_destroy(&ncq_tfs->sglist); | |
1020 | ncq_tfs->used = 0; | |
1021 | } | |
1022 | ||
f6ad2e32 AG |
1023 | static void ncq_cb(void *opaque, int ret) |
1024 | { | |
1025 | NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; | |
1026 | IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; | |
1027 | ||
df403bc5 | 1028 | ncq_tfs->aiocb = NULL; |
f6ad2e32 AG |
1029 | |
1030 | if (ret < 0) { | |
7c03a691 JS |
1031 | bool is_read = ncq_tfs->cmd == READ_FPDMA_QUEUED; |
1032 | BlockErrorAction action = blk_get_error_action(ide_state->blk, | |
1033 | is_read, -ret); | |
1034 | if (action == BLOCK_ERROR_ACTION_STOP) { | |
1035 | ncq_tfs->halt = true; | |
1036 | ide_state->bus->error_status = IDE_RETRY_HBA; | |
1037 | } else if (action == BLOCK_ERROR_ACTION_REPORT) { | |
1038 | ncq_err(ncq_tfs); | |
1039 | } | |
1040 | blk_error_action(ide_state->blk, action, is_read, -ret); | |
f6ad2e32 AG |
1041 | } else { |
1042 | ide_state->status = READY_STAT | SEEK_STAT; | |
1043 | } | |
1044 | ||
7c03a691 JS |
1045 | if (!ncq_tfs->halt) { |
1046 | ncq_finish(ncq_tfs); | |
1047 | } | |
f6ad2e32 AG |
1048 | } |
1049 | ||
72a065db JS |
1050 | static int is_ncq(uint8_t ata_cmd) |
1051 | { | |
1052 | /* Based on SATA 3.2 section 13.6.3.2 */ | |
1053 | switch (ata_cmd) { | |
1054 | case READ_FPDMA_QUEUED: | |
1055 | case WRITE_FPDMA_QUEUED: | |
1056 | case NCQ_NON_DATA: | |
1057 | case RECEIVE_FPDMA_QUEUED: | |
1058 | case SEND_FPDMA_QUEUED: | |
1059 | return 1; | |
1060 | default: | |
1061 | return 0; | |
1062 | } | |
1063 | } | |
1064 | ||
631ddc22 JS |
1065 | static void execute_ncq_command(NCQTransferState *ncq_tfs) |
1066 | { | |
1067 | AHCIDevice *ad = ncq_tfs->drive; | |
1068 | IDEState *ide_state = &ad->port.ifs[0]; | |
1069 | int port = ad->port_no; | |
7c03a691 | 1070 | |
631ddc22 | 1071 | g_assert(is_ncq(ncq_tfs->cmd)); |
7c03a691 | 1072 | ncq_tfs->halt = false; |
631ddc22 JS |
1073 | |
1074 | switch (ncq_tfs->cmd) { | |
1075 | case READ_FPDMA_QUEUED: | |
e4baa9f0 JS |
1076 | trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag, |
1077 | ncq_tfs->sector_count, ncq_tfs->lba); | |
631ddc22 JS |
1078 | dma_acct_start(ide_state->blk, &ncq_tfs->acct, |
1079 | &ncq_tfs->sglist, BLOCK_ACCT_READ); | |
1080 | ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist, | |
cbe0ed62 | 1081 | ncq_tfs->lba << BDRV_SECTOR_BITS, |
99868af3 | 1082 | BDRV_SECTOR_SIZE, |
cbe0ed62 | 1083 | ncq_cb, ncq_tfs); |
631ddc22 JS |
1084 | break; |
1085 | case WRITE_FPDMA_QUEUED: | |
e4baa9f0 JS |
1086 | trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag, |
1087 | ncq_tfs->sector_count, ncq_tfs->lba); | |
631ddc22 JS |
1088 | dma_acct_start(ide_state->blk, &ncq_tfs->acct, |
1089 | &ncq_tfs->sglist, BLOCK_ACCT_WRITE); | |
1090 | ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist, | |
cbe0ed62 | 1091 | ncq_tfs->lba << BDRV_SECTOR_BITS, |
99868af3 | 1092 | BDRV_SECTOR_SIZE, |
cbe0ed62 | 1093 | ncq_cb, ncq_tfs); |
631ddc22 JS |
1094 | break; |
1095 | default: | |
e4baa9f0 JS |
1096 | trace_execute_ncq_command_unsup(ad->hba, port, |
1097 | ncq_tfs->tag, ncq_tfs->cmd); | |
631ddc22 JS |
1098 | ncq_err(ncq_tfs); |
1099 | } | |
1100 | } | |
1101 | ||
1102 | ||
26941eb4 | 1103 | static void process_ncq_command(AHCIState *s, int port, const uint8_t *cmd_fis, |
9364384d | 1104 | uint8_t slot) |
f6ad2e32 | 1105 | { |
b6fe41fa | 1106 | AHCIDevice *ad = &s->dev[port]; |
26941eb4 | 1107 | const NCQFrame *ncq_fis = (NCQFrame *)cmd_fis; |
f6ad2e32 | 1108 | uint8_t tag = ncq_fis->tag >> 3; |
b6fe41fa | 1109 | NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag]; |
3bcbe4aa | 1110 | size_t size; |
f6ad2e32 | 1111 | |
922f893e | 1112 | g_assert(is_ncq(ncq_fis->command)); |
f6ad2e32 AG |
1113 | if (ncq_tfs->used) { |
1114 | /* error - already in use */ | |
580e7333 PMD |
1115 | qemu_log_mask(LOG_GUEST_ERROR, "%s: tag %d already used\n", |
1116 | __func__, tag); | |
f6ad2e32 AG |
1117 | return; |
1118 | } | |
1119 | ||
1120 | ncq_tfs->used = 1; | |
b6fe41fa | 1121 | ncq_tfs->drive = ad; |
f6ad2e32 | 1122 | ncq_tfs->slot = slot; |
c82bd3c8 | 1123 | ncq_tfs->cmdh = &((AHCICmdHdr *)ad->lst)[slot]; |
4614619e | 1124 | ncq_tfs->cmd = ncq_fis->command; |
f6ad2e32 AG |
1125 | ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | |
1126 | ((uint64_t)ncq_fis->lba4 << 32) | | |
1127 | ((uint64_t)ncq_fis->lba3 << 24) | | |
1128 | ((uint64_t)ncq_fis->lba2 << 16) | | |
1129 | ((uint64_t)ncq_fis->lba1 << 8) | | |
1130 | (uint64_t)ncq_fis->lba0; | |
3bcbe4aa | 1131 | ncq_tfs->tag = tag; |
f6ad2e32 | 1132 | |
5d5f8921 JS |
1133 | /* Sanity-check the NCQ packet */ |
1134 | if (tag != slot) { | |
e4baa9f0 | 1135 | trace_process_ncq_command_mismatch(s, port, tag, slot); |
5d5f8921 JS |
1136 | } |
1137 | ||
1138 | if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) { | |
e4baa9f0 | 1139 | trace_process_ncq_command_aux(s, port, tag); |
5d5f8921 JS |
1140 | } |
1141 | if (ncq_fis->prio || ncq_fis->icc) { | |
e4baa9f0 | 1142 | trace_process_ncq_command_prioicc(s, port, tag); |
5d5f8921 JS |
1143 | } |
1144 | if (ncq_fis->fua & NCQ_FIS_FUA_MASK) { | |
e4baa9f0 | 1145 | trace_process_ncq_command_fua(s, port, tag); |
5d5f8921 JS |
1146 | } |
1147 | if (ncq_fis->tag & NCQ_FIS_RARC_MASK) { | |
e4baa9f0 | 1148 | trace_process_ncq_command_rarc(s, port, tag); |
5d5f8921 JS |
1149 | } |
1150 | ||
e08a9835 JS |
1151 | ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) | |
1152 | ncq_fis->sector_count_low); | |
1153 | if (!ncq_tfs->sector_count) { | |
1154 | ncq_tfs->sector_count = 0x10000; | |
1155 | } | |
075f32d3 | 1156 | size = ncq_tfs->sector_count * BDRV_SECTOR_SIZE; |
c82bd3c8 | 1157 | ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0); |
3bcbe4aa JS |
1158 | |
1159 | if (ncq_tfs->sglist.size < size) { | |
1160 | error_report("ahci: PRDT length for NCQ command (0x%zx) " | |
1161 | "is smaller than the requested size (0x%zx)", | |
1162 | ncq_tfs->sglist.size, size); | |
3bcbe4aa | 1163 | ncq_err(ncq_tfs); |
5fa0feec | 1164 | ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS); |
3bcbe4aa | 1165 | return; |
5d5f8921 | 1166 | } else if (ncq_tfs->sglist.size != size) { |
e4baa9f0 JS |
1167 | trace_process_ncq_command_large(s, port, tag, |
1168 | ncq_tfs->sglist.size, size); | |
3bcbe4aa | 1169 | } |
f6ad2e32 | 1170 | |
e4baa9f0 JS |
1171 | trace_process_ncq_command(s, port, tag, |
1172 | ncq_fis->command, | |
1173 | ncq_tfs->lba, | |
1174 | ncq_tfs->lba + ncq_tfs->sector_count - 1); | |
631ddc22 | 1175 | execute_ncq_command(ncq_tfs); |
f6ad2e32 AG |
1176 | } |
1177 | ||
ee364416 JS |
1178 | static AHCICmdHdr *get_cmd_header(AHCIState *s, uint8_t port, uint8_t slot) |
1179 | { | |
1180 | if (port >= s->ports || slot >= AHCI_MAX_CMDS) { | |
1181 | return NULL; | |
1182 | } | |
1183 | ||
1184 | return s->dev[port].lst ? &((AHCICmdHdr *)s->dev[port].lst)[slot] : NULL; | |
1185 | } | |
1186 | ||
107f0d46 | 1187 | static void handle_reg_h2d_fis(AHCIState *s, int port, |
26941eb4 | 1188 | uint8_t slot, const uint8_t *cmd_fis) |
107f0d46 JS |
1189 | { |
1190 | IDEState *ide_state = &s->dev[port].port.ifs[0]; | |
ee364416 | 1191 | AHCICmdHdr *cmd = get_cmd_header(s, port, slot); |
d56f4d69 | 1192 | uint16_t opts = le16_to_cpu(cmd->opts); |
107f0d46 JS |
1193 | |
1194 | if (cmd_fis[1] & 0x0F) { | |
e4baa9f0 JS |
1195 | trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1], |
1196 | cmd_fis[2], cmd_fis[3]); | |
107f0d46 JS |
1197 | return; |
1198 | } | |
1199 | ||
1200 | if (cmd_fis[1] & 0x70) { | |
e4baa9f0 JS |
1201 | trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1], |
1202 | cmd_fis[2], cmd_fis[3]); | |
107f0d46 JS |
1203 | return; |
1204 | } | |
1205 | ||
1206 | if (!(cmd_fis[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER)) { | |
1207 | switch (s->dev[port].port_state) { | |
1208 | case STATE_RUN: | |
1209 | if (cmd_fis[15] & ATA_SRST) { | |
1210 | s->dev[port].port_state = STATE_RESET; | |
1211 | } | |
1212 | break; | |
1213 | case STATE_RESET: | |
1214 | if (!(cmd_fis[15] & ATA_SRST)) { | |
1215 | ahci_reset_port(s, port); | |
1216 | } | |
1217 | break; | |
1218 | } | |
1219 | return; | |
1220 | } | |
1221 | ||
1222 | /* Check for NCQ command */ | |
1223 | if (is_ncq(cmd_fis[2])) { | |
1224 | process_ncq_command(s, port, cmd_fis, slot); | |
1225 | return; | |
1226 | } | |
1227 | ||
1228 | /* Decompose the FIS: | |
1229 | * AHCI does not interpret FIS packets, it only forwards them. | |
1230 | * SATA 1.0 describes how to decode LBA28 and CHS FIS packets. | |
1231 | * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets. | |
1232 | * | |
1233 | * ATA4 describes sector number for LBA28/CHS commands. | |
1234 | * ATA6 describes sector number for LBA48 commands. | |
1235 | * ATA8 deprecates CHS fully, describing only LBA28/48. | |
1236 | * | |
1237 | * We dutifully convert the FIS into IDE registers, and allow the | |
1238 | * core layer to interpret them as needed. */ | |
1239 | ide_state->feature = cmd_fis[3]; | |
1240 | ide_state->sector = cmd_fis[4]; /* LBA 7:0 */ | |
1241 | ide_state->lcyl = cmd_fis[5]; /* LBA 15:8 */ | |
1242 | ide_state->hcyl = cmd_fis[6]; /* LBA 23:16 */ | |
1243 | ide_state->select = cmd_fis[7]; /* LBA 27:24 (LBA28) */ | |
1244 | ide_state->hob_sector = cmd_fis[8]; /* LBA 31:24 */ | |
1245 | ide_state->hob_lcyl = cmd_fis[9]; /* LBA 39:32 */ | |
1246 | ide_state->hob_hcyl = cmd_fis[10]; /* LBA 47:40 */ | |
1247 | ide_state->hob_feature = cmd_fis[11]; | |
1248 | ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); | |
1249 | /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */ | |
1250 | /* 15: Only valid when UPDATE_COMMAND not set. */ | |
1251 | ||
1252 | /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command | |
1253 | * table to ide_state->io_buffer */ | |
1254 | if (opts & AHCI_CMD_ATAPI) { | |
1255 | memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); | |
797285c8 JS |
1256 | if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP)) { |
1257 | char *pretty_fis = ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10); | |
1258 | trace_handle_reg_h2d_fis_dump(s, port, pretty_fis); | |
1259 | g_free(pretty_fis); | |
1260 | } | |
107f0d46 JS |
1261 | } |
1262 | ||
1263 | ide_state->error = 0; | |
ae79c2db | 1264 | s->dev[port].done_first_drq = false; |
107f0d46 JS |
1265 | /* Reset transferred byte counter */ |
1266 | cmd->status = 0; | |
1267 | ||
1268 | /* We're ready to process the command in FIS byte 2. */ | |
1269 | ide_exec_cmd(&s->dev[port].port, cmd_fis[2]); | |
1270 | } | |
1271 | ||
9364384d | 1272 | static int handle_cmd(AHCIState *s, int port, uint8_t slot) |
f6ad2e32 AG |
1273 | { |
1274 | IDEState *ide_state; | |
f6ad2e32 AG |
1275 | uint64_t tbl_addr; |
1276 | AHCICmdHdr *cmd; | |
1277 | uint8_t *cmd_fis; | |
10ca2943 | 1278 | dma_addr_t cmd_len; |
f6ad2e32 AG |
1279 | |
1280 | if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { | |
1281 | /* Engine currently busy, try again later */ | |
e4baa9f0 | 1282 | trace_handle_cmd_busy(s, port); |
f6ad2e32 AG |
1283 | return -1; |
1284 | } | |
1285 | ||
f6ad2e32 | 1286 | if (!s->dev[port].lst) { |
e4baa9f0 | 1287 | trace_handle_cmd_nolist(s, port); |
f6ad2e32 AG |
1288 | return -1; |
1289 | } | |
ee364416 | 1290 | cmd = get_cmd_header(s, port, slot); |
f6ad2e32 AG |
1291 | /* remember current slot handle for later */ |
1292 | s->dev[port].cur_cmd = cmd; | |
1293 | ||
36ab3c34 JS |
1294 | /* The device we are working for */ |
1295 | ide_state = &s->dev[port].port.ifs[0]; | |
1296 | if (!ide_state->blk) { | |
e4baa9f0 | 1297 | trace_handle_cmd_badport(s, port); |
36ab3c34 JS |
1298 | return -1; |
1299 | } | |
1300 | ||
f6ad2e32 | 1301 | tbl_addr = le64_to_cpu(cmd->tbl_addr); |
f6ad2e32 | 1302 | cmd_len = 0x80; |
df32fd1c | 1303 | cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, |
26941eb4 | 1304 | DMA_DIRECTION_TO_DEVICE); |
f6ad2e32 | 1305 | if (!cmd_fis) { |
e4baa9f0 | 1306 | trace_handle_cmd_badfis(s, port); |
f6ad2e32 | 1307 | return -1; |
36ab3c34 | 1308 | } else if (cmd_len != 0x80) { |
5fa0feec | 1309 | ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS); |
e4baa9f0 | 1310 | trace_handle_cmd_badmap(s, port, cmd_len); |
f6ad2e32 AG |
1311 | goto out; |
1312 | } | |
797285c8 JS |
1313 | if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP)) { |
1314 | char *pretty_fis = ahci_pretty_buffer_fis(cmd_fis, 0x80); | |
1315 | trace_handle_cmd_fis_dump(s, port, pretty_fis); | |
1316 | g_free(pretty_fis); | |
1317 | } | |
f6ad2e32 AG |
1318 | switch (cmd_fis[0]) { |
1319 | case SATA_FIS_TYPE_REGISTER_H2D: | |
107f0d46 | 1320 | handle_reg_h2d_fis(s, port, slot, cmd_fis); |
f6ad2e32 AG |
1321 | break; |
1322 | default: | |
e4baa9f0 JS |
1323 | trace_handle_cmd_unhandled_fis(s, port, |
1324 | cmd_fis[0], cmd_fis[1], cmd_fis[2]); | |
f6ad2e32 AG |
1325 | break; |
1326 | } | |
1327 | ||
f6ad2e32 | 1328 | out: |
26941eb4 | 1329 | dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_TO_DEVICE, |
10ca2943 | 1330 | cmd_len); |
f6ad2e32 AG |
1331 | |
1332 | if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { | |
1333 | /* async command, complete later */ | |
1334 | s->dev[port].busy_slot = slot; | |
1335 | return -1; | |
1336 | } | |
1337 | ||
1338 | /* done handling the command */ | |
1339 | return 0; | |
1340 | } | |
1341 | ||
bed9bcfa | 1342 | /* Transfer PIO data between RAM and device */ |
ae0cebd7 | 1343 | static void ahci_pio_transfer(const IDEDMA *dma) |
f6ad2e32 AG |
1344 | { |
1345 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
1346 | IDEState *s = &ad->port.ifs[0]; | |
1347 | uint32_t size = (uint32_t)(s->data_end - s->data_ptr); | |
1348 | /* write == ram -> device */ | |
d56f4d69 | 1349 | uint16_t opts = le16_to_cpu(ad->cur_cmd->opts); |
f6ad2e32 AG |
1350 | int is_write = opts & AHCI_CMD_WRITE; |
1351 | int is_atapi = opts & AHCI_CMD_ATAPI; | |
1352 | int has_sglist = 0; | |
ae79c2db | 1353 | bool pio_fis_i; |
f6ad2e32 | 1354 | |
ae79c2db PB |
1355 | /* The PIO Setup FIS is received prior to transfer, but the interrupt |
1356 | * is only triggered after data is received. | |
1357 | * | |
1358 | * The device only sets the 'I' bit in the PIO Setup FIS for device->host | |
1359 | * requests (see "DPIOI1" in the SATA spec), or for host->device DRQs after | |
1360 | * the first (see "DPIOO1"). The latter is consistent with the spec's | |
1361 | * description of the PACKET protocol, where the command part of ATAPI requests | |
1362 | * ("DPKT0") has the 'I' bit clear, while the data part of PIO ATAPI requests | |
1363 | * ("DPKT4a" and "DPKT7") has the 'I' bit set for both directions for all DRQs. | |
1364 | */ | |
1365 | pio_fis_i = ad->done_first_drq || (!is_atapi && !is_write); | |
1366 | ahci_write_fis_pio(ad, size, pio_fis_i); | |
956556e1 | 1367 | |
ae79c2db | 1368 | if (is_atapi && !ad->done_first_drq) { |
f6ad2e32 | 1369 | /* already prepopulated iobuffer */ |
f6ad2e32 AG |
1370 | goto out; |
1371 | } | |
1372 | ||
a718978e | 1373 | if (ahci_dma_prepare_buf(dma, size)) { |
f6ad2e32 AG |
1374 | has_sglist = 1; |
1375 | } | |
1376 | ||
bed9bcfa PB |
1377 | trace_ahci_pio_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read", |
1378 | size, is_atapi ? "atapi" : "ata", | |
1379 | has_sglist ? "" : "o"); | |
f6ad2e32 | 1380 | |
da221327 PB |
1381 | if (has_sglist && size) { |
1382 | if (is_write) { | |
1383 | dma_buf_write(s->data_ptr, size, &s->sg); | |
1384 | } else { | |
1385 | dma_buf_read(s->data_ptr, size, &s->sg); | |
1386 | } | |
f6ad2e32 AG |
1387 | } |
1388 | ||
956556e1 JS |
1389 | /* Update number of transferred bytes, destroy sglist */ |
1390 | dma_buf_commit(s, size); | |
ae79c2db | 1391 | |
f6ad2e32 AG |
1392 | out: |
1393 | /* declare that we processed everything */ | |
1394 | s->data_ptr = s->data_end; | |
ae79c2db PB |
1395 | |
1396 | ad->done_first_drq = true; | |
1397 | if (pio_fis_i) { | |
1398 | ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS); | |
1399 | } | |
f6ad2e32 AG |
1400 | } |
1401 | ||
ae0cebd7 | 1402 | static void ahci_start_dma(const IDEDMA *dma, IDEState *s, |
097310b5 | 1403 | BlockCompletionFunc *dma_cb) |
f6ad2e32 AG |
1404 | { |
1405 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
e4baa9f0 | 1406 | trace_ahci_start_dma(ad->hba, ad->port_no); |
61f52e06 | 1407 | s->io_buffer_offset = 0; |
f6ad2e32 AG |
1408 | dma_cb(s, 0); |
1409 | } | |
1410 | ||
ae0cebd7 | 1411 | static void ahci_restart_dma(const IDEDMA *dma) |
e8ef8743 PB |
1412 | { |
1413 | /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */ | |
1414 | } | |
1415 | ||
7c03a691 JS |
1416 | /** |
1417 | * IDE/PIO restarts are handled by the core layer, but NCQ commands | |
1418 | * need an extra kick from the AHCI HBA. | |
1419 | */ | |
ae0cebd7 | 1420 | static void ahci_restart(const IDEDMA *dma) |
7c03a691 JS |
1421 | { |
1422 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
1423 | int i; | |
1424 | ||
1425 | for (i = 0; i < AHCI_MAX_CMDS; i++) { | |
1426 | NCQTransferState *ncq_tfs = &ad->ncq_tfs[i]; | |
1427 | if (ncq_tfs->halt) { | |
1428 | execute_ncq_command(ncq_tfs); | |
1429 | } | |
1430 | } | |
1431 | } | |
1432 | ||
659142ec | 1433 | /** |
aaeda4a3 JS |
1434 | * Called in DMA and PIO R/W chains to read the PRDT. |
1435 | * Not shared with NCQ pathways. | |
659142ec | 1436 | */ |
ae0cebd7 | 1437 | static int32_t ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit) |
f6ad2e32 AG |
1438 | { |
1439 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
1440 | IDEState *s = &ad->port.ifs[0]; | |
f6ad2e32 | 1441 | |
c82bd3c8 JS |
1442 | if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, |
1443 | limit, s->io_buffer_offset) == -1) { | |
e4baa9f0 | 1444 | trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no); |
3251bdcf JS |
1445 | return -1; |
1446 | } | |
da221327 | 1447 | s->io_buffer_size = s->sg.size; |
f6ad2e32 | 1448 | |
e4baa9f0 | 1449 | trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_size); |
3251bdcf | 1450 | return s->io_buffer_size; |
f6ad2e32 AG |
1451 | } |
1452 | ||
659142ec | 1453 | /** |
aaeda4a3 JS |
1454 | * Updates the command header with a bytes-read value. |
1455 | * Called via dma_buf_commit, for both DMA and PIO paths. | |
1456 | * sglist destruction is handled within dma_buf_commit. | |
659142ec | 1457 | */ |
ae0cebd7 | 1458 | static void ahci_commit_buf(const IDEDMA *dma, uint32_t tx_bytes) |
659142ec JS |
1459 | { |
1460 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
659142ec JS |
1461 | |
1462 | tx_bytes += le32_to_cpu(ad->cur_cmd->status); | |
1463 | ad->cur_cmd->status = cpu_to_le32(tx_bytes); | |
659142ec JS |
1464 | } |
1465 | ||
ae0cebd7 | 1466 | static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write) |
f6ad2e32 AG |
1467 | { |
1468 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
1469 | IDEState *s = &ad->port.ifs[0]; | |
1470 | uint8_t *p = s->io_buffer + s->io_buffer_index; | |
1471 | int l = s->io_buffer_size - s->io_buffer_index; | |
1472 | ||
c82bd3c8 | 1473 | if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, l, s->io_buffer_offset)) { |
f6ad2e32 AG |
1474 | return 0; |
1475 | } | |
1476 | ||
1477 | if (is_write) { | |
da221327 | 1478 | dma_buf_read(p, l, &s->sg); |
f6ad2e32 | 1479 | } else { |
da221327 | 1480 | dma_buf_write(p, l, &s->sg); |
f6ad2e32 AG |
1481 | } |
1482 | ||
659142ec | 1483 | /* free sglist, update byte count */ |
aaeda4a3 | 1484 | dma_buf_commit(s, l); |
f6ad2e32 AG |
1485 | s->io_buffer_index += l; |
1486 | ||
e4baa9f0 | 1487 | trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l); |
f6ad2e32 AG |
1488 | return 1; |
1489 | } | |
1490 | ||
ae0cebd7 | 1491 | static void ahci_cmd_done(const IDEDMA *dma) |
f6ad2e32 AG |
1492 | { |
1493 | AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); | |
1494 | ||
e4baa9f0 | 1495 | trace_ahci_cmd_done(ad->hba, ad->port_no); |
f6ad2e32 | 1496 | |
5694c7ea JS |
1497 | /* no longer busy */ |
1498 | if (ad->busy_slot != -1) { | |
1499 | ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot); | |
1500 | ad->busy_slot = -1; | |
1501 | } | |
1502 | ||
f6ad2e32 | 1503 | /* update d2h status */ |
28ee8255 | 1504 | ahci_write_fis_d2h(ad); |
f6ad2e32 | 1505 | |
42af312a | 1506 | if (ad->port_regs.cmd_issue && !ad->check_bh) { |
4d29b50a JK |
1507 | ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad); |
1508 | qemu_bh_schedule(ad->check_bh); | |
1509 | } | |
f6ad2e32 AG |
1510 | } |
1511 | ||
1512 | static void ahci_irq_set(void *opaque, int n, int level) | |
1513 | { | |
c5f12a80 | 1514 | qemu_log_mask(LOG_UNIMP, "ahci: IRQ#%d level:%d\n", n, level); |
f6ad2e32 AG |
1515 | } |
1516 | ||
f6ad2e32 AG |
1517 | static const IDEDMAOps ahci_dma_ops = { |
1518 | .start_dma = ahci_start_dma, | |
7c03a691 | 1519 | .restart = ahci_restart, |
e8ef8743 | 1520 | .restart_dma = ahci_restart_dma, |
bed9bcfa | 1521 | .pio_transfer = ahci_pio_transfer, |
f6ad2e32 | 1522 | .prepare_buf = ahci_dma_prepare_buf, |
659142ec | 1523 | .commit_buf = ahci_commit_buf, |
f6ad2e32 | 1524 | .rw_buf = ahci_dma_rw_buf, |
c7e73adb | 1525 | .cmd_done = ahci_cmd_done, |
f6ad2e32 AG |
1526 | }; |
1527 | ||
0487eea4 | 1528 | void ahci_init(AHCIState *s, DeviceState *qdev) |
f6ad2e32 | 1529 | { |
bb639f82 | 1530 | s->container = qdev; |
67e576c2 | 1531 | /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ |
1437c94b PB |
1532 | memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, |
1533 | "ahci", AHCI_MEM_BAR_SIZE); | |
1534 | memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, | |
1535 | "ahci-idp", 32); | |
0487eea4 | 1536 | } |
465f1ab1 | 1537 | |
0487eea4 PC |
1538 | void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports) |
1539 | { | |
1540 | qemu_irq *irqs; | |
1541 | int i; | |
f6ad2e32 | 1542 | |
0487eea4 PC |
1543 | s->as = as; |
1544 | s->ports = ports; | |
1545 | s->dev = g_new0(AHCIDevice, ports); | |
1546 | ahci_reg_init(s); | |
1547 | irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); | |
2c4b9d0e | 1548 | for (i = 0; i < s->ports; i++) { |
f6ad2e32 AG |
1549 | AHCIDevice *ad = &s->dev[i]; |
1550 | ||
82c74ac4 | 1551 | ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1); |
f6ad2e32 AG |
1552 | ide_init2(&ad->port, irqs[i]); |
1553 | ||
1554 | ad->hba = s; | |
1555 | ad->port_no = i; | |
1556 | ad->port.dma = &ad->dma; | |
1557 | ad->port.dma->ops = &ahci_dma_ops; | |
e8ef8743 | 1558 | ide_register_restart_cb(&ad->port); |
f6ad2e32 | 1559 | } |
9d324b0e | 1560 | g_free(irqs); |
f6ad2e32 AG |
1561 | } |
1562 | ||
2c4b9d0e AG |
1563 | void ahci_uninit(AHCIState *s) |
1564 | { | |
d68f0f77 LQ |
1565 | int i, j; |
1566 | ||
1567 | for (i = 0; i < s->ports; i++) { | |
1568 | AHCIDevice *ad = &s->dev[i]; | |
1569 | ||
1570 | for (j = 0; j < 2; j++) { | |
1571 | IDEState *s = &ad->port.ifs[j]; | |
1572 | ||
1573 | ide_exit(s); | |
1574 | } | |
955f5c7b | 1575 | object_unparent(OBJECT(&ad->port)); |
d68f0f77 LQ |
1576 | } |
1577 | ||
7267c094 | 1578 | g_free(s->dev); |
2c4b9d0e AG |
1579 | } |
1580 | ||
8ab60a07 | 1581 | void ahci_reset(AHCIState *s) |
f6ad2e32 | 1582 | { |
a26a13da | 1583 | AHCIPortRegs *pr; |
f6ad2e32 AG |
1584 | int i; |
1585 | ||
e4baa9f0 JS |
1586 | trace_ahci_reset(s); |
1587 | ||
8ab60a07 | 1588 | s->control_regs.irqstatus = 0; |
13164591 MT |
1589 | /* AHCI Enable (AE) |
1590 | * The implementation of this bit is dependent upon the value of the | |
1591 | * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and | |
1592 | * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be | |
1593 | * read-only and shall have a reset value of '1'. | |
1594 | * | |
1595 | * We set HOST_CAP_AHCI so we must enable AHCI at reset. | |
1596 | */ | |
1597 | s->control_regs.ghc = HOST_CTL_AHCI_EN; | |
760c3e44 | 1598 | |
8ab60a07 JK |
1599 | for (i = 0; i < s->ports; i++) { |
1600 | pr = &s->dev[i].port_regs; | |
a26a13da AM |
1601 | pr->irq_stat = 0; |
1602 | pr->irq_mask = 0; | |
1603 | pr->scr_ctl = 0; | |
2a4f4f34 | 1604 | pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; |
8ab60a07 | 1605 | ahci_reset_port(s, i); |
f6ad2e32 AG |
1606 | } |
1607 | } | |
d9fa31a3 | 1608 | |
684d5013 JS |
1609 | static const VMStateDescription vmstate_ncq_tfs = { |
1610 | .name = "ncq state", | |
1611 | .version_id = 1, | |
1612 | .fields = (VMStateField[]) { | |
1613 | VMSTATE_UINT32(sector_count, NCQTransferState), | |
1614 | VMSTATE_UINT64(lba, NCQTransferState), | |
1615 | VMSTATE_UINT8(tag, NCQTransferState), | |
1616 | VMSTATE_UINT8(cmd, NCQTransferState), | |
1617 | VMSTATE_UINT8(slot, NCQTransferState), | |
1618 | VMSTATE_BOOL(used, NCQTransferState), | |
1619 | VMSTATE_BOOL(halt, NCQTransferState), | |
1620 | VMSTATE_END_OF_LIST() | |
1621 | }, | |
1622 | }; | |
1623 | ||
a2623021 JB |
1624 | static const VMStateDescription vmstate_ahci_device = { |
1625 | .name = "ahci port", | |
1626 | .version_id = 1, | |
d49805ae | 1627 | .fields = (VMStateField[]) { |
a2623021 | 1628 | VMSTATE_IDE_BUS(port, AHCIDevice), |
bd664910 | 1629 | VMSTATE_IDE_DRIVE(port.ifs[0], AHCIDevice), |
a2623021 JB |
1630 | VMSTATE_UINT32(port_state, AHCIDevice), |
1631 | VMSTATE_UINT32(finished, AHCIDevice), | |
1632 | VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), | |
1633 | VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), | |
1634 | VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), | |
1635 | VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), | |
1636 | VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), | |
1637 | VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), | |
1638 | VMSTATE_UINT32(port_regs.cmd, AHCIDevice), | |
1639 | VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), | |
1640 | VMSTATE_UINT32(port_regs.sig, AHCIDevice), | |
1641 | VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), | |
1642 | VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), | |
1643 | VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), | |
1644 | VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), | |
1645 | VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), | |
ae79c2db | 1646 | VMSTATE_BOOL(done_first_drq, AHCIDevice), |
a2623021 JB |
1647 | VMSTATE_INT32(busy_slot, AHCIDevice), |
1648 | VMSTATE_BOOL(init_d2h_sent, AHCIDevice), | |
684d5013 JS |
1649 | VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS, |
1650 | 1, vmstate_ncq_tfs, NCQTransferState), | |
a2623021 JB |
1651 | VMSTATE_END_OF_LIST() |
1652 | }, | |
1653 | }; | |
1654 | ||
1655 | static int ahci_state_post_load(void *opaque, int version_id) | |
1656 | { | |
684d5013 | 1657 | int i, j; |
a2623021 | 1658 | struct AHCIDevice *ad; |
684d5013 | 1659 | NCQTransferState *ncq_tfs; |
f8a6c5f3 | 1660 | AHCIPortRegs *pr; |
a2623021 JB |
1661 | AHCIState *s = opaque; |
1662 | ||
1663 | for (i = 0; i < s->ports; i++) { | |
1664 | ad = &s->dev[i]; | |
f8a6c5f3 JS |
1665 | pr = &ad->port_regs; |
1666 | ||
1667 | if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) { | |
1668 | error_report("AHCI: DMA engine should be off, but status bit " | |
1669 | "indicates it is still running."); | |
1670 | return -1; | |
1671 | } | |
1672 | if (!(pr->cmd & PORT_CMD_FIS_RX) && (pr->cmd & PORT_CMD_FIS_ON)) { | |
1673 | error_report("AHCI: FIS RX engine should be off, but status bit " | |
1674 | "indicates it is still running."); | |
1675 | return -1; | |
1676 | } | |
a2623021 | 1677 | |
d5904749 JS |
1678 | /* After a migrate, the DMA/FIS engines are "off" and |
1679 | * need to be conditionally restarted */ | |
1680 | pr->cmd &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); | |
1681 | if (ahci_cond_start_engines(ad) != 0) { | |
cd6cb73b JS |
1682 | return -1; |
1683 | } | |
1684 | ||
684d5013 JS |
1685 | for (j = 0; j < AHCI_MAX_CMDS; j++) { |
1686 | ncq_tfs = &ad->ncq_tfs[j]; | |
1687 | ncq_tfs->drive = ad; | |
1688 | ||
1689 | if (ncq_tfs->used != ncq_tfs->halt) { | |
1690 | return -1; | |
1691 | } | |
1692 | if (!ncq_tfs->halt) { | |
1693 | continue; | |
1694 | } | |
1695 | if (!is_ncq(ncq_tfs->cmd)) { | |
1696 | return -1; | |
1697 | } | |
1698 | if (ncq_tfs->slot != ncq_tfs->tag) { | |
1699 | return -1; | |
1700 | } | |
1701 | /* If ncq_tfs->halt is justly set, the engine should be engaged, | |
1702 | * and the command list buffer should be mapped. */ | |
1703 | ncq_tfs->cmdh = get_cmd_header(s, i, ncq_tfs->slot); | |
1704 | if (!ncq_tfs->cmdh) { | |
1705 | return -1; | |
1706 | } | |
1707 | ahci_populate_sglist(ncq_tfs->drive, &ncq_tfs->sglist, | |
075f32d3 PMD |
1708 | ncq_tfs->cmdh, |
1709 | ncq_tfs->sector_count * BDRV_SECTOR_SIZE, | |
684d5013 JS |
1710 | 0); |
1711 | if (ncq_tfs->sector_count != ncq_tfs->sglist.size >> 9) { | |
1712 | return -1; | |
1713 | } | |
1714 | } | |
1715 | ||
1716 | ||
a2623021 | 1717 | /* |
e8ef8743 PB |
1718 | * If an error is present, ad->busy_slot will be valid and not -1. |
1719 | * In this case, an operation is waiting to resume and will re-check | |
1720 | * for additional AHCI commands to execute upon completion. | |
1721 | * | |
1722 | * In the case where no error was present, busy_slot will be -1, | |
1723 | * and we should check to see if there are additional commands waiting. | |
a2623021 | 1724 | */ |
e8ef8743 PB |
1725 | if (ad->busy_slot == -1) { |
1726 | check_cmd(s, i); | |
c27c73aa JS |
1727 | } else { |
1728 | /* We are in the middle of a command, and may need to access | |
1729 | * the command header in guest memory again. */ | |
1730 | if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) { | |
1731 | return -1; | |
1732 | } | |
ee364416 | 1733 | ad->cur_cmd = get_cmd_header(s, i, ad->busy_slot); |
a2623021 | 1734 | } |
a2623021 JB |
1735 | } |
1736 | ||
1737 | return 0; | |
1738 | } | |
1739 | ||
1740 | const VMStateDescription vmstate_ahci = { | |
1741 | .name = "ahci", | |
1742 | .version_id = 1, | |
1743 | .post_load = ahci_state_post_load, | |
d49805ae | 1744 | .fields = (VMStateField[]) { |
a2623021 JB |
1745 | VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports, |
1746 | vmstate_ahci_device, AHCIDevice), | |
1747 | VMSTATE_UINT32(control_regs.cap, AHCIState), | |
1748 | VMSTATE_UINT32(control_regs.ghc, AHCIState), | |
1749 | VMSTATE_UINT32(control_regs.irqstatus, AHCIState), | |
1750 | VMSTATE_UINT32(control_regs.impl, AHCIState), | |
1751 | VMSTATE_UINT32(control_regs.version, AHCIState), | |
1752 | VMSTATE_UINT32(idp_index, AHCIState), | |
d2164ad3 | 1753 | VMSTATE_INT32_EQUAL(ports, AHCIState, NULL), |
a2623021 JB |
1754 | VMSTATE_END_OF_LIST() |
1755 | }, | |
1756 | }; | |
1757 | ||
d9fa31a3 RH |
1758 | static const VMStateDescription vmstate_sysbus_ahci = { |
1759 | .name = "sysbus-ahci", | |
d49805ae | 1760 | .fields = (VMStateField[]) { |
bd164307 | 1761 | VMSTATE_AHCI(ahci, SysbusAHCIState), |
a2623021 JB |
1762 | VMSTATE_END_OF_LIST() |
1763 | }, | |
d9fa31a3 RH |
1764 | }; |
1765 | ||
8ab60a07 JK |
1766 | static void sysbus_ahci_reset(DeviceState *dev) |
1767 | { | |
b3b162c3 | 1768 | SysbusAHCIState *s = SYSBUS_AHCI(dev); |
8ab60a07 JK |
1769 | |
1770 | ahci_reset(&s->ahci); | |
1771 | } | |
1772 | ||
0487eea4 | 1773 | static void sysbus_ahci_init(Object *obj) |
d9fa31a3 | 1774 | { |
0487eea4 PC |
1775 | SysbusAHCIState *s = SYSBUS_AHCI(obj); |
1776 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
d9fa31a3 | 1777 | |
0487eea4 | 1778 | ahci_init(&s->ahci, DEVICE(obj)); |
7acb423f HT |
1779 | |
1780 | sysbus_init_mmio(sbd, &s->ahci.mem); | |
1781 | sysbus_init_irq(sbd, &s->ahci.irq); | |
d9fa31a3 RH |
1782 | } |
1783 | ||
0487eea4 PC |
1784 | static void sysbus_ahci_realize(DeviceState *dev, Error **errp) |
1785 | { | |
1786 | SysbusAHCIState *s = SYSBUS_AHCI(dev); | |
1787 | ||
1788 | ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports); | |
1789 | } | |
1790 | ||
39bffca2 AL |
1791 | static Property sysbus_ahci_properties[] = { |
1792 | DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1), | |
1793 | DEFINE_PROP_END_OF_LIST(), | |
1794 | }; | |
1795 | ||
999e12bb AL |
1796 | static void sysbus_ahci_class_init(ObjectClass *klass, void *data) |
1797 | { | |
39bffca2 | 1798 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1799 | |
7acb423f | 1800 | dc->realize = sysbus_ahci_realize; |
39bffca2 | 1801 | dc->vmsd = &vmstate_sysbus_ahci; |
4f67d30b | 1802 | device_class_set_props(dc, sysbus_ahci_properties); |
8ab60a07 | 1803 | dc->reset = sysbus_ahci_reset; |
125ee0ed | 1804 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
999e12bb AL |
1805 | } |
1806 | ||
8c43a6f0 | 1807 | static const TypeInfo sysbus_ahci_info = { |
b3b162c3 | 1808 | .name = TYPE_SYSBUS_AHCI, |
39bffca2 AL |
1809 | .parent = TYPE_SYS_BUS_DEVICE, |
1810 | .instance_size = sizeof(SysbusAHCIState), | |
0487eea4 | 1811 | .instance_init = sysbus_ahci_init, |
39bffca2 | 1812 | .class_init = sysbus_ahci_class_init, |
d9fa31a3 RH |
1813 | }; |
1814 | ||
83f7d43a | 1815 | static void sysbus_ahci_register_types(void) |
d9fa31a3 | 1816 | { |
39bffca2 | 1817 | type_register_static(&sysbus_ahci_info); |
d9fa31a3 RH |
1818 | } |
1819 | ||
83f7d43a | 1820 | type_init(sysbus_ahci_register_types) |
d93162e1 | 1821 | |
bbe3179a JS |
1822 | int32_t ahci_get_num_ports(PCIDevice *dev) |
1823 | { | |
aa3c41fb | 1824 | AHCIPCIState *d = ICH9_AHCI(dev); |
bbe3179a JS |
1825 | AHCIState *ahci = &d->ahci; |
1826 | ||
1827 | return ahci->ports; | |
1828 | } | |
1829 | ||
d93162e1 JS |
1830 | void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd) |
1831 | { | |
aa3c41fb | 1832 | AHCIPCIState *d = ICH9_AHCI(dev); |
d93162e1 JS |
1833 | AHCIState *ahci = &d->ahci; |
1834 | int i; | |
1835 | ||
1836 | for (i = 0; i < ahci->ports; i++) { | |
1837 | if (hd[i] == NULL) { | |
1838 | continue; | |
1839 | } | |
1840 | ide_create_drive(&ahci->dev[i].port, 0, hd[i]); | |
1841 | } | |
1842 | ||
1843 | } |