[mirror_qemu.git] / hw / ide / cmd646.c

/*
 * QEMU IDE Emulation: PCI cmd646 support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "hw/isa/isa.h"
#include "sysemu/sysemu.h"
#include "sysemu/dma.h"
#include "sysemu/reset.h"

#include "hw/ide/pci.h"
#include "trace.h"

/* CMD646 specific */
#define CFR		0x50
#define   CFR_INTR_CH0	0x04
#define CNTRL		0x51
#define   CNTRL_EN_CH0	0x04
#define   CNTRL_EN_CH1	0x08
#define ARTTIM23	0x57
#define    ARTTIM23_INTR_CH1	0x10
#define MRDMODE		0x71
#define   MRDMODE_INTR_CH0	0x04
#define   MRDMODE_INTR_CH1	0x08
#define   MRDMODE_BLK_CH0	0x10
#define   MRDMODE_BLK_CH1	0x20
#define UDIDETCR0	0x73
#define UDIDETCR1	0x7B

static void cmd646_update_irq(PCIDevice *pd);

static void cmd646_update_dma_interrupts(PCIDevice *pd)
{
    /* Sync DMA interrupt status from UDMA interrupt status */
    if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
        pd->config[CFR] |= CFR_INTR_CH0;
    } else {
        pd->config[CFR] &= ~CFR_INTR_CH0;
    }

    if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
        pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
    } else {
        pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
    }
}

static void cmd646_update_udma_interrupts(PCIDevice *pd)
{
    /* Sync UDMA interrupt status from DMA interrupt status */
    if (pd->config[CFR] & CFR_INTR_CH0) {
        pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
    } else {
        pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
    }

    if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
        pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
    } else {
        pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
    }
}

static uint64_t bmdma_read(void *opaque, hwaddr addr,
                           unsigned size)
{
    BMDMAState *bm = opaque;
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
    uint32_t val;

    if (size != 1) {
        return ((uint64_t)1 << (size * 8)) - 1;
    }

    switch(addr & 3) {
    case 0:
        val = bm->cmd;
        break;
    case 1:
        val = pci_dev->config[MRDMODE];
        break;
    case 2:
        val = bm->status;
        break;
    case 3:
        if (bm == &bm->pci_dev->bmdma[0]) {
            val = pci_dev->config[UDIDETCR0];
        } else {
            val = pci_dev->config[UDIDETCR1];
        }
        break;
    default:
        val = 0xff;
        break;
    }

    trace_bmdma_read_cmd646(addr, val);
    return val;
}

static void bmdma_write(void *opaque, hwaddr addr,
                        uint64_t val, unsigned size)
{
    BMDMAState *bm = opaque;
    PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);

    if (size != 1) {
        return;
    }

    trace_bmdma_write_cmd646(addr, val);
    switch(addr & 3) {
    case 0:
        bmdma_cmd_writeb(bm, val);
        break;
    case 1:
        pci_dev->config[MRDMODE] =
            (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
        cmd646_update_dma_interrupts(pci_dev);
        cmd646_update_irq(pci_dev);
        break;
    case 2:
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
        break;
    case 3:
        if (bm == &bm->pci_dev->bmdma[0]) {
            pci_dev->config[UDIDETCR0] = val;
        } else {
            pci_dev->config[UDIDETCR1] = val;
        }
        break;
    }
}

static const MemoryRegionOps cmd646_bmdma_ops = {
    .read = bmdma_read,
    .write = bmdma_write,
};

static void bmdma_setup_bar(PCIIDEState *d)
{
    BMDMAState *bm;
    int i;

    memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
    for(i = 0;i < 2; i++) {
        bm = &d->bmdma[i];
        memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
                              "cmd646-bmdma-bus", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
        memory_region_init_io(&bm->addr_ioport, OBJECT(d),
                              &bmdma_addr_ioport_ops, bm,
                              "cmd646-bmdma-ioport", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
    }
}

static void cmd646_update_irq(PCIDevice *pd)
{
    int pci_level;

    pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
                 !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
        ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
         !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
    pci_set_irq(pd, pci_level);
}

/* the PCI irq level is the logical OR of the two channels */
static void cmd646_set_irq(void *opaque, int channel, int level)
{
    PCIIDEState *d = opaque;
    PCIDevice *pd = PCI_DEVICE(d);
    int irq_mask;

    irq_mask = MRDMODE_INTR_CH0 << channel;
    if (level) {
        pd->config[MRDMODE] |= irq_mask;
    } else {
        pd->config[MRDMODE] &= ~irq_mask;
    }
    cmd646_update_dma_interrupts(pd);
    cmd646_update_irq(pd);
}

static void cmd646_reset(void *opaque)
{
    PCIIDEState *d = opaque;
    unsigned int i;

    for (i = 0; i < 2; i++) {
        ide_bus_reset(&d->bus[i]);
    }
}

static uint32_t cmd646_pci_config_read(PCIDevice *d,
                                       uint32_t address, int len)
{
    return pci_default_read_config(d, address, len);
}

static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
                                    int l)
{
    uint32_t i;

    pci_default_write_config(d, addr, val, l);

    for (i = addr; i < addr + l; i++) {
        switch (i) {
        case CFR:
        case ARTTIM23:
            cmd646_update_udma_interrupts(d);
            break;
        case MRDMODE:
            cmd646_update_dma_interrupts(d);
            break;
        }
    }

    cmd646_update_irq(d);
}

/* CMD646 PCI IDE controller */
static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
{
    PCIIDEState *d = PCI_IDE(dev);
    uint8_t *pci_conf = dev->config;
    qemu_irq *irq;
    int i;

    pci_conf[PCI_CLASS_PROG] = 0x8f;

    pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
    if (d->secondary) {
        /* XXX: if not enabled, really disable the seconday IDE controller */
        pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
    }

    /* Set write-to-clear interrupt bits */
    dev->wmask[CFR] = 0x0;
    dev->w1cmask[CFR] = CFR_INTR_CH0;
    dev->wmask[ARTTIM23] = 0x0;
    dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
    dev->wmask[MRDMODE] = 0x0;
    dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;

    memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
                          &d->bus[0], "cmd646-data0", 8);
    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);

    memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
                          &d->bus[0], "cmd646-cmd0", 4);
    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);

    memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
                          &d->bus[1], "cmd646-data1", 8);
    pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);

    memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
                          &d->bus[1], "cmd646-cmd1", 4);
    pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);

    bmdma_setup_bar(d);
    pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    /* TODO: RST# value should be 0 */
    pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1

    irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
        ide_init2(&d->bus[i], irq[i]);

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        ide_register_restart_cb(&d->bus[i]);
    }

    vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
    qemu_register_reset(cmd646_reset, d);
}

static void pci_cmd646_ide_exitfn(PCIDevice *dev)
{
    PCIIDEState *d = PCI_IDE(dev);
    unsigned i;

    for (i = 0; i < 2; ++i) {
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
    }
}

void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
                         int secondary_ide_enabled)
{
    PCIDevice *dev;

    dev = pci_create(bus, -1, "cmd646-ide");
    qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
    qdev_init_nofail(&dev->qdev);

    pci_ide_create_devs(dev, hd_table);
}

static Property cmd646_ide_properties[] = {
    DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void cmd646_ide_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_cmd646_ide_realize;
    k->exit = pci_cmd646_ide_exitfn;
    k->vendor_id = PCI_VENDOR_ID_CMD;
    k->device_id = PCI_DEVICE_ID_CMD_646;
    k->revision = 0x07;
    k->class_id = PCI_CLASS_STORAGE_IDE;
    k->config_read = cmd646_pci_config_read;
    k->config_write = cmd646_pci_config_write;
    dc->props = cmd646_ide_properties;
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}

static const TypeInfo cmd646_ide_info = {
    .name          = "cmd646-ide",
    .parent        = TYPE_PCI_IDE,
    .class_init    = cmd646_ide_class_init,
};

static void cmd646_ide_register_types(void)
{
    type_register_static(&cmd646_ide_info);
}

type_init(cmd646_ide_register_types)
Commit	Line	Data
4c3df0ec JQ	1	/*
	2	* QEMU IDE Emulation: PCI cmd646 support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
0b8fa32f	25
53239262	26	#include "qemu/osdep.h"
a9c94277	27	#include "hw/hw.h"
a9c94277	28	#include "hw/pci/pci.h"
d6454270	29	#include "migration/vmstate.h"
0b8fa32f	30	#include "qemu/module.h"
a9c94277	31	#include "hw/isa/isa.h"
9c17d615 PB	32	#include "sysemu/sysemu.h"
9c17d615 PB	33	#include "sysemu/dma.h"
71e8a915	34	#include "sysemu/reset.h"
4c3df0ec	35
a9c94277	36	#include "hw/ide/pci.h"
3eee2611	37	#include "trace.h"
4c3df0ec JQ	38
4c3df0ec JQ	39	/* CMD646 specific */
5bbc0a70 MCA	40	#define CFR 0x50
5bbc0a70 MCA	41	#define CFR_INTR_CH0 0x04
58f16a7b MCA	42	#define CNTRL 0x51
	43	#define CNTRL_EN_CH0 0x04
	44	#define CNTRL_EN_CH1 0x08
5bbc0a70 MCA	45	#define ARTTIM23 0x57
5bbc0a70 MCA	46	#define ARTTIM23_INTR_CH1 0x10
4c3df0ec JQ	47	#define MRDMODE 0x71
	48	#define MRDMODE_INTR_CH0 0x04
	49	#define MRDMODE_INTR_CH1 0x08
	50	#define MRDMODE_BLK_CH0 0x10
	51	#define MRDMODE_BLK_CH1 0x20
	52	#define UDIDETCR0 0x73
	53	#define UDIDETCR1 0x7B
	54
dab91a1e	55	static void cmd646_update_irq(PCIDevice *pd);
4c3df0ec	56
5bbc0a70 MCA	57	static void cmd646_update_dma_interrupts(PCIDevice *pd)
	58	{
	59	/* Sync DMA interrupt status from UDMA interrupt status */
	60	if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
	61	pd->config[CFR] \|= CFR_INTR_CH0;
	62	} else {
	63	pd->config[CFR] &= ~CFR_INTR_CH0;
	64	}
	65
	66	if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
	67	pd->config[ARTTIM23] \|= ARTTIM23_INTR_CH1;
	68	} else {
	69	pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
	70	}
	71	}
	72
271dddd1 MCA	73	static void cmd646_update_udma_interrupts(PCIDevice *pd)
	74	{
	75	/* Sync UDMA interrupt status from DMA interrupt status */
	76	if (pd->config[CFR] & CFR_INTR_CH0) {
	77	pd->config[MRDMODE] \|= MRDMODE_INTR_CH0;
	78	} else {
	79	pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
	80	}
	81
	82	if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
	83	pd->config[MRDMODE] \|= MRDMODE_INTR_CH1;
	84	} else {
	85	pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
	86	}
	87	}
	88
a8170e5e	89	static uint64_t bmdma_read(void *opaque, hwaddr addr,
a9deb8c6 AK	90	unsigned size)
	91	{
	92	BMDMAState *bm = opaque;
f6c11d56	93	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
4c3df0ec JQ	94	uint32_t val;
4c3df0ec JQ	95
a9deb8c6 AK	96	if (size != 1) {
	97	return ((uint64_t)1 << (size * 8)) - 1;
	98	}
	99
4c3df0ec JQ	100	switch(addr & 3) {
	101	case 0:
	102	val = bm->cmd;
	103	break;
	104	case 1:
f6c11d56	105	val = pci_dev->config[MRDMODE];
4c3df0ec JQ	106	break;
	107	case 2:
	108	val = bm->status;
	109	break;
	110	case 3:
f6c11d56 AF	111	if (bm == &bm->pci_dev->bmdma[0]) {
f6c11d56 AF	112	val = pci_dev->config[UDIDETCR0];
4c3df0ec	113	} else {
f6c11d56	114	val = pci_dev->config[UDIDETCR1];
4c3df0ec JQ	115	}
	116	break;
	117	default:
	118	val = 0xff;
	119	break;
	120	}
3eee2611 JS	121
3eee2611 JS	122	trace_bmdma_read_cmd646(addr, val);
4c3df0ec JQ	123	return val;
	124	}
	125
a8170e5e	126	static void bmdma_write(void *opaque, hwaddr addr,
a9deb8c6	127	uint64_t val, unsigned size)
70ae65f5	128	{
a9deb8c6	129	BMDMAState *bm = opaque;
f6c11d56	130	PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
70ae65f5	131
a9deb8c6 AK	132	if (size != 1) {
	133	return;
	134	}
70ae65f5	135
3eee2611	136	trace_bmdma_write_cmd646(addr, val);
4c3df0ec	137	switch(addr & 3) {
50a48094	138	case 0:
a9deb8c6	139	bmdma_cmd_writeb(bm, val);
50a48094	140	break;
4c3df0ec	141	case 1:
f6c11d56 AF	142	pci_dev->config[MRDMODE] =
f6c11d56 AF	143	(pci_dev->config[MRDMODE] & ~0x30) \| (val & 0x30);
5bbc0a70	144	cmd646_update_dma_interrupts(pci_dev);
dab91a1e	145	cmd646_update_irq(pci_dev);
4c3df0ec JQ	146	break;
	147	case 2:
	148	bm->status = (val & 0x60) \| (bm->status & 1) \| (bm->status & ~val & 0x06);
	149	break;
	150	case 3:
f6c11d56 AF	151	if (bm == &bm->pci_dev->bmdma[0]) {
	152	pci_dev->config[UDIDETCR0] = val;
	153	} else {
	154	pci_dev->config[UDIDETCR1] = val;
	155	}
4c3df0ec JQ	156	break;
	157	}
	158	}
	159
a348f108	160	static const MemoryRegionOps cmd646_bmdma_ops = {
a9deb8c6 AK	161	.read = bmdma_read,
	162	.write = bmdma_write,
	163	};
70ae65f5	164
a9deb8c6	165	static void bmdma_setup_bar(PCIIDEState *d)
4c3df0ec	166	{
a9deb8c6	167	BMDMAState *bm;
4c3df0ec JQ	168	int i;
4c3df0ec JQ	169
1437c94b	170	memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
4c3df0ec	171	for(i = 0;i < 2; i++) {
a9deb8c6	172	bm = &d->bmdma[i];
1437c94b	173	memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
a9deb8c6 AK	174	"cmd646-bmdma-bus", 4);
a9deb8c6 AK	175	memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
1437c94b PB	176	memory_region_init_io(&bm->addr_ioport, OBJECT(d),
1437c94b PB	177	&bmdma_addr_ioport_ops, bm,
a9deb8c6 AK	178	"cmd646-bmdma-ioport", 4);
a9deb8c6 AK	179	memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
4c3df0ec JQ	180	}
	181	}
	182
dab91a1e	183	static void cmd646_update_irq(PCIDevice *pd)
4c3df0ec JQ	184	{
4c3df0ec JQ	185	int pci_level;
f6c11d56 AF	186
	187	pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
	188	!(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) \|\|
	189	((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
	190	!(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
9e64f8a3	191	pci_set_irq(pd, pci_level);
4c3df0ec JQ	192	}
	193
	194	/* the PCI irq level is the logical OR of the two channels */
	195	static void cmd646_set_irq(void *opaque, int channel, int level)
	196	{
	197	PCIIDEState *d = opaque;
f6c11d56	198	PCIDevice *pd = PCI_DEVICE(d);
4c3df0ec JQ	199	int irq_mask;
	200
	201	irq_mask = MRDMODE_INTR_CH0 << channel;
f6c11d56 AF	202	if (level) {
	203	pd->config[MRDMODE] \|= irq_mask;
	204	} else {
	205	pd->config[MRDMODE] &= ~irq_mask;
	206	}
5bbc0a70	207	cmd646_update_dma_interrupts(pd);
dab91a1e	208	cmd646_update_irq(pd);
4c3df0ec JQ	209	}
	210
	211	static void cmd646_reset(void *opaque)
	212	{
	213	PCIIDEState *d = opaque;
	214	unsigned int i;
	215
4a643563 BS	216	for (i = 0; i < 2; i++) {
4a643563 BS	217	ide_bus_reset(&d->bus[i]);
4a643563	218	}
4c3df0ec JQ	219	}
4c3df0ec JQ	220
1d113ef8 MCA	221	static uint32_t cmd646_pci_config_read(PCIDevice *d,
	222	uint32_t address, int len)
	223	{
	224	return pci_default_read_config(d, address, len);
	225	}
	226
	227	static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
	228	int l)
	229	{
	230	uint32_t i;
	231
	232	pci_default_write_config(d, addr, val, l);
	233
	234	for (i = addr; i < addr + l; i++) {
	235	switch (i) {
271dddd1 MCA	236	case CFR:
	237	case ARTTIM23:
	238	cmd646_update_udma_interrupts(d);
	239	break;
1d113ef8 MCA	240	case MRDMODE:
	241	cmd646_update_dma_interrupts(d);
	242	break;
	243	}
	244	}
	245
	246	cmd646_update_irq(d);
	247	}
	248
4c3df0ec	249	/* CMD646 PCI IDE controller */
9af21dbe	250	static void pci_cmd646_ide_realize(PCIDevice dev, Error *errp)
4c3df0ec	251	{
f6c11d56 AF	252	PCIIDEState *d = PCI_IDE(dev);
f6c11d56 AF	253	uint8_t *pci_conf = dev->config;
4c3df0ec	254	qemu_irq *irq;
61d9d6b0	255	int i;
4c3df0ec	256
409570a7	257	pci_conf[PCI_CLASS_PROG] = 0x8f;
4c3df0ec	258
58f16a7b	259	pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
4c3df0ec JQ	260	if (d->secondary) {
4c3df0ec JQ	261	/* XXX: if not enabled, really disable the seconday IDE controller */
58f16a7b	262	pci_conf[CNTRL] \|= CNTRL_EN_CH1; /* enable IDE1 */
4c3df0ec JQ	263	}
4c3df0ec JQ	264
1d113ef8	265	/* Set write-to-clear interrupt bits */
271dddd1 MCA	266	dev->wmask[CFR] = 0x0;
	267	dev->w1cmask[CFR] = CFR_INTR_CH0;
	268	dev->wmask[ARTTIM23] = 0x0;
	269	dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
1d113ef8 MCA	270	dev->wmask[MRDMODE] = 0x0;
	271	dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 \| MRDMODE_INTR_CH1;
	272
8ac98d1a BZ	273	memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
	274	&d->bus[0], "cmd646-data0", 8);
	275	pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);
	276
	277	memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
	278	&d->bus[0], "cmd646-cmd0", 4);
	279	pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);
	280
	281	memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
	282	&d->bus[1], "cmd646-data1", 8);
	283	pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);
	284
	285	memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
	286	&d->bus[1], "cmd646-cmd1", 4);
	287	pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);
	288
a9deb8c6	289	bmdma_setup_bar(d);
e824b2cc	290	pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
4c3df0ec	291
409570a7 MT	292	/* TODO: RST# value should be 0 */
409570a7 MT	293	pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
4c3df0ec JQ	294
4c3df0ec JQ	295	irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
61d9d6b0	296	for (i = 0; i < 2; i++) {
c6baf942	297	ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
61d9d6b0 SH	298	ide_init2(&d->bus[i], irq[i]);
61d9d6b0 SH	299
a9deb8c6	300	bmdma_init(&d->bus[i], &d->bmdma[i], d);
f56b18c0	301	d->bmdma[i].bus = &d->bus[i];
f878c916	302	ide_register_restart_cb(&d->bus[i]);
61d9d6b0	303	}
4c3df0ec	304
f6c11d56	305	vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
4c3df0ec	306	qemu_register_reset(cmd646_reset, d);
4c3df0ec JQ	307	}
4c3df0ec JQ	308
f90c2bcd	309	static void pci_cmd646_ide_exitfn(PCIDevice *dev)
a9deb8c6	310	{
f6c11d56	311	PCIIDEState *d = PCI_IDE(dev);
a9deb8c6 AK	312	unsigned i;
	313
	314	for (i = 0; i < 2; ++i) {
	315	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
a9deb8c6	316	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
a9deb8c6	317	}
a9deb8c6 AK	318	}
a9deb8c6 AK	319
4c3df0ec JQ	320	void pci_cmd646_ide_init(PCIBus bus, DriveInfo *hd_table,
	321	int secondary_ide_enabled)
	322	{
	323	PCIDevice *dev;
	324
556cd098	325	dev = pci_create(bus, -1, "cmd646-ide");
4c3df0ec JQ	326	qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
	327	qdev_init_nofail(&dev->qdev);
	328
	329	pci_ide_create_devs(dev, hd_table);
	330	}
	331
40021f08 AL	332	static Property cmd646_ide_properties[] = {
	333	DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
	334	DEFINE_PROP_END_OF_LIST(),
	335	};
	336
	337	static void cmd646_ide_class_init(ObjectClass klass, void data)
	338	{
39bffca2	339	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	340	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	341
9af21dbe	342	k->realize = pci_cmd646_ide_realize;
40021f08 AL	343	k->exit = pci_cmd646_ide_exitfn;
	344	k->vendor_id = PCI_VENDOR_ID_CMD;
	345	k->device_id = PCI_DEVICE_ID_CMD_646;
	346	k->revision = 0x07;
	347	k->class_id = PCI_CLASS_STORAGE_IDE;
1d113ef8 MCA	348	k->config_read = cmd646_pci_config_read;
1d113ef8 MCA	349	k->config_write = cmd646_pci_config_write;
39bffca2	350	dc->props = cmd646_ide_properties;
74623e73	351	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
40021f08 AL	352	}
40021f08 AL	353
8c43a6f0	354	static const TypeInfo cmd646_ide_info = {
39bffca2	355	.name = "cmd646-ide",
f6c11d56	356	.parent = TYPE_PCI_IDE,
39bffca2	357	.class_init = cmd646_ide_class_init,
4c3df0ec JQ	358	};
4c3df0ec JQ	359
83f7d43a	360	static void cmd646_ide_register_types(void)
4c3df0ec	361	{
39bffca2	362	type_register_static(&cmd646_ide_info);
4c3df0ec	363	}
83f7d43a AF	364
83f7d43a AF	365	type_init(cmd646_ide_register_types)