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Replaced get_tick_per_sec() by NANOSECONDS_PER_SECOND
[mirror_qemu.git] / hw / ide / core.c
CommitLineData
5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
53239262 25#include "qemu/osdep.h"
59f2a787 26#include <hw/hw.h>
0d09e41a 27#include <hw/i386/pc.h>
a2cb15b0 28#include <hw/pci/pci.h>
0d09e41a 29#include <hw/isa/isa.h>
1de7afc9
PB		 30#include "qemu/error-report.h"
31#include "qemu/timer.h"
9c17d615
PB		 32#include "sysemu/sysemu.h"
33#include "sysemu/dma.h"
0d09e41a 34#include "hw/block/block.h"
4be74634 35#include "sysemu/block-backend.h"
59f2a787
GH		 36
37#include <hw/ide/internal.h>
e8b54394 38
b93af93d
BW		 39/* These values were based on a Seagate ST3500418AS but have been modified
40 to make more sense in QEMU */
41static const int smart_attributes[][12] = {
42 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
43 /* raw read error rate*/
44 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
45 /* spin up */
46 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
47 /* start stop count */
48 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
49 /* remapped sectors */
50 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
51 /* power on hours */
52 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
53 /* power cycle count */
54 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
55 /* airflow-temperature-celsius */
56 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
e8b54394
BW		 57};
58
ce4b6522 59static int ide_handle_rw_error(IDEState *s, int error, int op);
40c4ed3f 60static void ide_dummy_transfer_stop(IDEState *s);
98087450 61
5391d806
FB		 62static void padstr(char *str, const char *src, int len)
63{
64 int i, v;
65 for(i = 0; i < len; i++) {
66 if (*src)
67 v = *src++;
68 else
69 v = ' ';
69b34976 70 str[i^1] = v;
5391d806
FB		 71 }
72}
73
67b915a5
FB		 74static void put_le16(uint16_t *p, unsigned int v)
75{
0c4ad8dc 76 *p = cpu_to_le16(v);
67b915a5
FB		 77}
78
01ce352e
JS		 79static void ide_identify_size(IDEState *s)
80{
81 uint16_t *p = (uint16_t *)s->identify_data;
82 put_le16(p + 60, s->nb_sectors);
83 put_le16(p + 61, s->nb_sectors >> 16);
84 put_le16(p + 100, s->nb_sectors);
85 put_le16(p + 101, s->nb_sectors >> 16);
86 put_le16(p + 102, s->nb_sectors >> 32);
87 put_le16(p + 103, s->nb_sectors >> 48);
88}
89
5391d806
FB		 90static void ide_identify(IDEState *s)
91{
92 uint16_t *p;
93 unsigned int oldsize;
d353fb72 94 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 95
4bf6637d 96 p = (uint16_t *)s->identify_data;
94458802 97 if (s->identify_set) {
4bf6637d 98 goto fill_buffer;
94458802 99 }
4bf6637d 100 memset(p, 0, sizeof(s->identify_data));
94458802 101
67b915a5 102 put_le16(p + 0, 0x0040);
5fafdf24 103 put_le16(p + 1, s->cylinders);
67b915a5
FB		 104 put_le16(p + 3, s->heads);
105 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
106 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 107 put_le16(p + 6, s->sectors);
fa879c64 108 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 109 put_le16(p + 20, 3); /* XXX: retired, remove ? */
110 put_le16(p + 21, 512); /* cache size in sectors */
111 put_le16(p + 22, 4); /* ecc bytes */
47c06340 112 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 113 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
3b46e624 114#if MAX_MULT_SECTORS > 1
67b915a5 115 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 116#endif
67b915a5 117 put_le16(p + 48, 1); /* dword I/O */
94458802 118 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 119 put_le16(p + 51, 0x200); /* PIO transfer cycle */
120 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 121 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 122 put_le16(p + 54, s->cylinders);
123 put_le16(p + 55, s->heads);
124 put_le16(p + 56, s->sectors);
5391d806 125 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 126 put_le16(p + 57, oldsize);
127 put_le16(p + 58, oldsize >> 16);
5391d806 128 if (s->mult_sectors)
67b915a5 129 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 130 /* *(p + 60) := nb_sectors -- see ide_identify_size */
131 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
d1b5c20d 132 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 133 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 134 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 135 put_le16(p + 65, 120);
136 put_le16(p + 66, 120);
137 put_le16(p + 67, 120);
138 put_le16(p + 68, 120);
d353fb72
CH		 139 if (dev && dev->conf.discard_granularity) {
140 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
141 }
ccf0fd8b
RE		 142
143 if (s->ncq_queues) {
144 put_le16(p + 75, s->ncq_queues - 1);
145 /* NCQ supported */
146 put_le16(p + 76, (1 << 8));
147 }
148
94458802
FB		 149 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
150 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 151 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
152 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 153 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
154 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 155 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
156 if (s->wwn) {
157 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
158 } else {
159 put_le16(p + 84, (1 << 14) | 0);
160 }
e900a7b7 161 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
4be74634
MA		 162 if (blk_enable_write_cache(s->blk)) {
163 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
164 } else {
165 put_le16(p + 85, (1 << 14) | 1);
166 }
c2ff060f 167 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
2844bdd9 168 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 169 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
170 if (s->wwn) {
171 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
172 } else {
173 put_le16(p + 87, (1 << 14) | 0);
174 }
94458802
FB		 175 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
176 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
01ce352e
JS		 177 /* *(p + 100) := nb_sectors -- see ide_identify_size */
178 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
179 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
180 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
d353fb72 181
57dac7ef
MA		 182 if (dev && dev->conf.physical_block_size)
183 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
95ebda85
FB		 184 if (s->wwn) {
185 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
186 put_le16(p + 108, s->wwn >> 48);
187 put_le16(p + 109, s->wwn >> 32);
188 put_le16(p + 110, s->wwn >> 16);
189 put_le16(p + 111, s->wwn);
190 }
d353fb72
CH		 191 if (dev && dev->conf.discard_granularity) {
192 put_le16(p + 169, 1); /* TRIM support */
193 }
94458802 194
01ce352e 195 ide_identify_size(s);
94458802 196 s->identify_set = 1;
4bf6637d
JS		 197
198fill_buffer:
199 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 200}
201
202static void ide_atapi_identify(IDEState *s)
203{
204 uint16_t *p;
205
4bf6637d 206 p = (uint16_t *)s->identify_data;
94458802 207 if (s->identify_set) {
4bf6637d 208 goto fill_buffer;
94458802 209 }
4bf6637d 210 memset(p, 0, sizeof(s->identify_data));
94458802 211
5391d806 212 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 213 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 214 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 215 put_le16(p + 20, 3); /* buffer type */
216 put_le16(p + 21, 512); /* cache size in sectors */
217 put_le16(p + 22, 4); /* ecc bytes */
47c06340 218 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 219 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
67b915a5 220 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 221#ifdef USE_DMA_CDROM
222 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
223 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 224 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 225 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 226#else
67b915a5
FB		 227 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
228 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
229 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 230#endif
79d1d331 231 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 232 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
233 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
234 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
235 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 236
67b915a5
FB		 237 put_le16(p + 71, 30); /* in ns */
238 put_le16(p + 72, 30); /* in ns */
5391d806 239
1bdaa28d
AG		 240 if (s->ncq_queues) {
241 put_le16(p + 75, s->ncq_queues - 1);
242 /* NCQ supported */
243 put_le16(p + 76, (1 << 8));
244 }
245
67b915a5 246 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
c5fe97e3
JS		 247 if (s->wwn) {
248 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
249 put_le16(p + 87, (1 << 8)); /* WWN enabled */
250 }
251
8ccad811
FB		 252#ifdef USE_DMA_CDROM
253 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
254#endif
c5fe97e3
JS		 255
256 if (s->wwn) {
257 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
258 put_le16(p + 108, s->wwn >> 48);
259 put_le16(p + 109, s->wwn >> 32);
260 put_le16(p + 110, s->wwn >> 16);
261 put_le16(p + 111, s->wwn);
262 }
263
94458802 264 s->identify_set = 1;
4bf6637d
JS		 265
266fill_buffer:
267 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 268}
269
01ce352e
JS		 270static void ide_cfata_identify_size(IDEState *s)
271{
272 uint16_t *p = (uint16_t *)s->identify_data;
273 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
274 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
275 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
276 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
277}
278
201a51fc
AZ		 279static void ide_cfata_identify(IDEState *s)
280{
281 uint16_t *p;
282 uint32_t cur_sec;
201a51fc 283
4bf6637d
JS		 284 p = (uint16_t *)s->identify_data;
285 if (s->identify_set) {
201a51fc 286 goto fill_buffer;
4bf6637d 287 }
201a51fc
AZ		 288 memset(p, 0, sizeof(s->identify_data));
289
290 cur_sec = s->cylinders * s->heads * s->sectors;
291
292 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
293 put_le16(p + 1, s->cylinders); /* Default cylinders */
294 put_le16(p + 3, s->heads); /* Default heads */
295 put_le16(p + 6, s->sectors); /* Default sectors per track */
01ce352e
JS		 296 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
297 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
fa879c64 298 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 299 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 300 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
27e0c9a1 301 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
201a51fc
AZ		 302#if MAX_MULT_SECTORS > 1
303 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
304#else
305 put_le16(p + 47, 0x0000);
306#endif
307 put_le16(p + 49, 0x0f00); /* Capabilities */
308 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
309 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
310 put_le16(p + 53, 0x0003); /* Translation params valid */
311 put_le16(p + 54, s->cylinders); /* Current cylinders */
312 put_le16(p + 55, s->heads); /* Current heads */
313 put_le16(p + 56, s->sectors); /* Current sectors */
314 put_le16(p + 57, cur_sec); /* Current capacity */
315 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
316 if (s->mult_sectors) /* Multiple sector setting */
317 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 318 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
319 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
201a51fc
AZ		 320 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
321 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
322 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
323 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
324 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
325 put_le16(p + 82, 0x400c); /* Command Set supported */
326 put_le16(p + 83, 0x7068); /* Command Set supported */
327 put_le16(p + 84, 0x4000); /* Features supported */
328 put_le16(p + 85, 0x000c); /* Command Set enabled */
329 put_le16(p + 86, 0x7044); /* Command Set enabled */
330 put_le16(p + 87, 0x4000); /* Features enabled */
331 put_le16(p + 91, 0x4060); /* Current APM level */
332 put_le16(p + 129, 0x0002); /* Current features option */
333 put_le16(p + 130, 0x0005); /* Reassigned sectors */
334 put_le16(p + 131, 0x0001); /* Initial power mode */
335 put_le16(p + 132, 0x0000); /* User signature */
336 put_le16(p + 160, 0x8100); /* Power requirement */
337 put_le16(p + 161, 0x8001); /* CF command set */
338
01ce352e 339 ide_cfata_identify_size(s);
201a51fc
AZ		 340 s->identify_set = 1;
341
342fill_buffer:
343 memcpy(s->io_buffer, p, sizeof(s->identify_data));
344}
345
5391d806
FB		 346static void ide_set_signature(IDEState *s)
347{
348 s->select &= 0xf0; /* clear head */
349 /* put signature */
350 s->nsector = 1;
351 s->sector = 1;
cd8722bb 352 if (s->drive_kind == IDE_CD) {
5391d806
FB		 353 s->lcyl = 0x14;
354 s->hcyl = 0xeb;
4be74634 355 } else if (s->blk) {
5391d806
FB		 356 s->lcyl = 0;
357 s->hcyl = 0;
358 } else {
359 s->lcyl = 0xff;
360 s->hcyl = 0xff;
361 }
362}
363
d353fb72 364typedef struct TrimAIOCB {
7c84b1b8 365 BlockAIOCB common;
a987ee1f 366 BlockBackend *blk;
d353fb72
CH		 367 QEMUBH *bh;
368 int ret;
501378c3 369 QEMUIOVector *qiov;
7c84b1b8 370 BlockAIOCB *aiocb;
501378c3 371 int i, j;
d353fb72
CH		 372} TrimAIOCB;
373
7c84b1b8 374static void trim_aio_cancel(BlockAIOCB *acb)
d353fb72
CH		 375{
376 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
377
e551c999 378 /* Exit the loop so ide_issue_trim_cb will not continue */
501378c3
PB		 379 iocb->j = iocb->qiov->niov - 1;
380 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
381
e551c999 382 iocb->ret = -ECANCELED;
501378c3
PB		 383
384 if (iocb->aiocb) {
4be74634 385 blk_aio_cancel_async(iocb->aiocb);
e551c999 386 iocb->aiocb = NULL;
501378c3 387 }
d353fb72
CH		 388}
389
d7331bed 390static const AIOCBInfo trim_aiocb_info = {
d353fb72 391 .aiocb_size = sizeof(TrimAIOCB),
e551c999 392 .cancel_async = trim_aio_cancel,
d353fb72
CH		 393};
394
395static void ide_trim_bh_cb(void *opaque)
396{
397 TrimAIOCB *iocb = opaque;
398
399 iocb->common.cb(iocb->common.opaque, iocb->ret);
400
401 qemu_bh_delete(iocb->bh);
402 iocb->bh = NULL;
8007429a 403 qemu_aio_unref(iocb);
d353fb72
CH		 404}
405
501378c3
PB		 406static void ide_issue_trim_cb(void *opaque, int ret)
407{
408 TrimAIOCB *iocb = opaque;
409 if (ret >= 0) {
410 while (iocb->j < iocb->qiov->niov) {
411 int j = iocb->j;
412 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
413 int i = iocb->i;
414 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
415
416 /* 6-byte LBA + 2-byte range per entry */
417 uint64_t entry = le64_to_cpu(buffer[i]);
418 uint64_t sector = entry & 0x0000ffffffffffffULL;
419 uint16_t count = entry >> 48;
420
421 if (count == 0) {
422 continue;
423 }
424
425 /* Got an entry! Submit and exit. */
a987ee1f
MA		 426 iocb->aiocb = blk_aio_discard(iocb->blk, sector, count,
427 ide_issue_trim_cb, opaque);
501378c3
PB		 428 return;
429 }
430
431 iocb->j++;
432 iocb->i = -1;
433 }
434 } else {
435 iocb->ret = ret;
436 }
437
438 iocb->aiocb = NULL;
439 if (iocb->bh) {
440 qemu_bh_schedule(iocb->bh);
441 }
442}
443
4be74634 444BlockAIOCB *ide_issue_trim(BlockBackend *blk,
d353fb72 445 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
097310b5 446 BlockCompletionFunc *cb, void *opaque)
d353fb72
CH		 447{
448 TrimAIOCB *iocb;
d353fb72 449
4be74634 450 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, opaque);
a987ee1f 451 iocb->blk = blk;
d353fb72
CH		 452 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
453 iocb->ret = 0;
501378c3
PB		 454 iocb->qiov = qiov;
455 iocb->i = -1;
456 iocb->j = 0;
457 ide_issue_trim_cb(iocb, 0);
d353fb72
CH		 458 return &iocb->common;
459}
460
9ef2e93f 461void ide_abort_command(IDEState *s)
5391d806 462{
08ee9e33 463 ide_transfer_stop(s);
5391d806
FB		 464 s->status = READY_STAT | ERR_STAT;
465 s->error = ABRT_ERR;
466}
467
5391d806 468/* prepare data transfer and tell what to do after */
33231e0e
KW		 469void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
470 EndTransferFunc *end_transfer_func)
5391d806
FB		 471{
472 s->end_transfer_func = end_transfer_func;
473 s->data_ptr = buf;
474 s->data_end = buf + size;
40a6238a 475 if (!(s->status & ERR_STAT)) {
7603d156 476 s->status |= DRQ_STAT;
40a6238a 477 }
44635123
PB		 478 if (s->bus->dma->ops->start_transfer) {
479 s->bus->dma->ops->start_transfer(s->bus->dma);
480 }
5391d806
FB		 481}
482
c7e73adb
PB		 483static void ide_cmd_done(IDEState *s)
484{
485 if (s->bus->dma->ops->cmd_done) {
486 s->bus->dma->ops->cmd_done(s->bus->dma);
487 }
488}
489
e3044e23
JS		 490static void ide_transfer_halt(IDEState *s,
491 void(*end_transfer_func)(IDEState *),
492 bool notify)
5391d806 493{
e3044e23 494 s->end_transfer_func = end_transfer_func;
5391d806
FB		 495 s->data_ptr = s->io_buffer;
496 s->data_end = s->io_buffer;
497 s->status &= ~DRQ_STAT;
e3044e23
JS		 498 if (notify) {
499 ide_cmd_done(s);
500 }
501}
502
503void ide_transfer_stop(IDEState *s)
504{
505 ide_transfer_halt(s, ide_transfer_stop, true);
506}
507
e3044e23
JS		 508static void ide_transfer_cancel(IDEState *s)
509{
510 ide_transfer_halt(s, ide_transfer_cancel, false);
5391d806
FB		 511}
512
356721ae 513int64_t ide_get_sector(IDEState *s)
5391d806
FB		 514{
515 int64_t sector_num;
516 if (s->select & 0x40) {
517 /* lba */
c2ff060f
FB		 518 if (!s->lba48) {
519 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
520 (s->lcyl << 8) | s->sector;
521 } else {
522 sector_num = ((int64_t)s->hob_hcyl << 40) |
523 ((int64_t) s->hob_lcyl << 32) |
524 ((int64_t) s->hob_sector << 24) |
525 ((int64_t) s->hcyl << 16) |
526 ((int64_t) s->lcyl << 8) | s->sector;
527 }
5391d806
FB		 528 } else {
529 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 530 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 531 }
532 return sector_num;
533}
534
356721ae 535void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 536{
537 unsigned int cyl, r;
538 if (s->select & 0x40) {
c2ff060f
FB		 539 if (!s->lba48) {
540 s->select = (s->select & 0xf0) | (sector_num >> 24);
541 s->hcyl = (sector_num >> 16);
542 s->lcyl = (sector_num >> 8);
543 s->sector = (sector_num);
544 } else {
545 s->sector = sector_num;
546 s->lcyl = sector_num >> 8;
547 s->hcyl = sector_num >> 16;
548 s->hob_sector = sector_num >> 24;
549 s->hob_lcyl = sector_num >> 32;
550 s->hob_hcyl = sector_num >> 40;
551 }
5391d806
FB		 552 } else {
553 cyl = sector_num / (s->heads * s->sectors);
554 r = sector_num % (s->heads * s->sectors);
555 s->hcyl = cyl >> 8;
556 s->lcyl = cyl;
1b8eb456 557 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 558 s->sector = (r % s->sectors) + 1;
559 }
560}
561
e162cfb0
AZ		 562static void ide_rw_error(IDEState *s) {
563 ide_abort_command(s);
9cdd03a7 564 ide_set_irq(s->bus);
e162cfb0
AZ		 565}
566
58ac3211
MA		 567static bool ide_sect_range_ok(IDEState *s,
568 uint64_t sector, uint64_t nb_sectors)
569{
570 uint64_t total_sectors;
571
4be74634 572 blk_get_geometry(s->blk, &total_sectors);
58ac3211
MA		 573 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
574 return false;
575 }
576 return true;
577}
578
1d8c11d6
PL		 579static void ide_buffered_readv_cb(void *opaque, int ret)
580{
581 IDEBufferedRequest *req = opaque;
582 if (!req->orphaned) {
583 if (!ret) {
584 qemu_iovec_from_buf(req->original_qiov, 0, req->iov.iov_base,
585 req->original_qiov->size);
586 }
587 req->original_cb(req->original_opaque, ret);
588 }
589 QLIST_REMOVE(req, list);
590 qemu_vfree(req->iov.iov_base);
591 g_free(req);
592}
593
594#define MAX_BUFFERED_REQS 16
595
596BlockAIOCB *ide_buffered_readv(IDEState *s, int64_t sector_num,
597 QEMUIOVector *iov, int nb_sectors,
598 BlockCompletionFunc *cb, void *opaque)
599{
600 BlockAIOCB *aioreq;
601 IDEBufferedRequest *req;
602 int c = 0;
603
604 QLIST_FOREACH(req, &s->buffered_requests, list) {
605 c++;
606 }
607 if (c > MAX_BUFFERED_REQS) {
608 return blk_abort_aio_request(s->blk, cb, opaque, -EIO);
609 }
610
611 req = g_new0(IDEBufferedRequest, 1);
612 req->original_qiov = iov;
613 req->original_cb = cb;
614 req->original_opaque = opaque;
615 req->iov.iov_base = qemu_blockalign(blk_bs(s->blk), iov->size);
616 req->iov.iov_len = iov->size;
617 qemu_iovec_init_external(&req->qiov, &req->iov, 1);
618
619 aioreq = blk_aio_readv(s->blk, sector_num, &req->qiov, nb_sectors,
620 ide_buffered_readv_cb, req);
621
622 QLIST_INSERT_HEAD(&s->buffered_requests, req, list);
623 return aioreq;
624}
625
86698a12
JS		 626/**
627 * Cancel all pending DMA requests.
628 * Any buffered DMA requests are instantly canceled,
629 * but any pending unbuffered DMA requests must be waited on.
630 */
631void ide_cancel_dma_sync(IDEState *s)
632{
633 IDEBufferedRequest *req;
634
635 /* First invoke the callbacks of all buffered requests
636 * and flag those requests as orphaned. Ideally there
637 * are no unbuffered (Scatter Gather DMA Requests or
638 * write requests) pending and we can avoid to drain. */
639 QLIST_FOREACH(req, &s->buffered_requests, list) {
640 if (!req->orphaned) {
641#ifdef DEBUG_IDE
642 printf("%s: invoking cb %p of buffered request %p with"
643 " -ECANCELED\n", __func__, req->original_cb, req);
644#endif
645 req->original_cb(req->original_opaque, -ECANCELED);
646 }
647 req->orphaned = true;
648 }
649
650 /*
651 * We can't cancel Scatter Gather DMA in the middle of the
652 * operation or a partial (not full) DMA transfer would reach
653 * the storage so we wait for completion instead (we beahve
654 * like if the DMA was completed by the time the guest trying
655 * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
656 * set).
657 *
658 * In the future we'll be able to safely cancel the I/O if the
659 * whole DMA operation will be submitted to disk with a single
660 * aio operation with preadv/pwritev.
661 */
662 if (s->bus->dma->aiocb) {
663#ifdef DEBUG_IDE
664 printf("%s: draining all remaining requests", __func__);
665#endif
51f7b5b8 666 blk_drain(s->blk);
86698a12
JS		 667 assert(s->bus->dma->aiocb == NULL);
668 }
669}
670
4e2b8b4a
PB		 671static void ide_sector_read(IDEState *s);
672
bef0fd59
SH		 673static void ide_sector_read_cb(void *opaque, int ret)
674{
675 IDEState *s = opaque;
676 int n;
677
678 s->pio_aiocb = NULL;
679 s->status &= ~BUSY_STAT;
680
0d910cfe
FZ		 681 if (ret == -ECANCELED) {
682 return;
683 }
bef0fd59 684 if (ret != 0) {
fd648f10
PB		 685 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
686 IDE_RETRY_READ)) {
bef0fd59
SH		 687 return;
688 }
689 }
690
ecca3b39
AG		 691 block_acct_done(blk_get_stats(s->blk), &s->acct);
692
bef0fd59
SH		 693 n = s->nsector;
694 if (n > s->req_nb_sectors) {
695 n = s->req_nb_sectors;
696 }
697
bef0fd59
SH		 698 ide_set_sector(s, ide_get_sector(s) + n);
699 s->nsector -= n;
dd0bf7ba
JS		 700 /* Allow the guest to read the io_buffer */
701 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
dd0bf7ba 702 ide_set_irq(s->bus);
bef0fd59
SH		 703}
704
4e2b8b4a 705static void ide_sector_read(IDEState *s)
5391d806
FB		 706{
707 int64_t sector_num;
bef0fd59 708 int n;
5391d806
FB		 709
710 s->status = READY_STAT | SEEK_STAT;
a136e5a8 711 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 712 sector_num = ide_get_sector(s);
713 n = s->nsector;
bef0fd59 714
5391d806 715 if (n == 0) {
5391d806 716 ide_transfer_stop(s);
bef0fd59
SH		 717 return;
718 }
719
720 s->status |= BUSY_STAT;
721
722 if (n > s->req_nb_sectors) {
723 n = s->req_nb_sectors;
724 }
725
5391d806 726#if defined(DEBUG_IDE)
bef0fd59 727 printf("sector=%" PRId64 "\n", sector_num);
5391d806 728#endif
a597e79c 729
58ac3211
MA		 730 if (!ide_sect_range_ok(s, sector_num, n)) {
731 ide_rw_error(s);
ecca3b39 732 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_READ);
58ac3211
MA		 733 return;
734 }
735
bef0fd59
SH		 736 s->iov.iov_base = s->io_buffer;
737 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
738 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
739
4be74634 740 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 741 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
d66a8fa8
PL		 742 s->pio_aiocb = ide_buffered_readv(s, sector_num, &s->qiov, n,
743 ide_sector_read_cb, s);
5391d806
FB		 744}
745
aaeda4a3 746void dma_buf_commit(IDEState *s, uint32_t tx_bytes)
7aea4412 747{
659142ec
JS		 748 if (s->bus->dma->ops->commit_buf) {
749 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes);
750 }
aaeda4a3 751 s->io_buffer_offset += tx_bytes;
1fb8648d 752 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 753}
754
0e7ce54c 755void ide_set_inactive(IDEState *s, bool more)
8337606d 756{
40a6238a 757 s->bus->dma->aiocb = NULL;
a96cb236 758 s->bus->retry_unit = -1;
dc5d0af4
PB		 759 s->bus->retry_sector_num = 0;
760 s->bus->retry_nsector = 0;
829b933b 761 if (s->bus->dma->ops->set_inactive) {
0e7ce54c 762 s->bus->dma->ops->set_inactive(s->bus->dma, more);
829b933b 763 }
c7e73adb 764 ide_cmd_done(s);
8337606d
KW		 765}
766
356721ae 767void ide_dma_error(IDEState *s)
e162cfb0 768{
659142ec 769 dma_buf_commit(s, 0);
08ee9e33 770 ide_abort_command(s);
0e7ce54c 771 ide_set_inactive(s, false);
9cdd03a7 772 ide_set_irq(s->bus);
e162cfb0
AZ		 773}
774
ce4b6522 775static int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 776{
fd648f10 777 bool is_read = (op & IDE_RETRY_READ) != 0;
4be74634 778 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
428c5705 779
a589569f 780 if (action == BLOCK_ERROR_ACTION_STOP) {
a96cb236 781 assert(s->bus->retry_unit == s->unit);
def93791 782 s->bus->error_status = op;
a589569f 783 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
ecca3b39 784 block_acct_failed(blk_get_stats(s->blk), &s->acct);
fd648f10 785 if (op & IDE_RETRY_DMA) {
428c5705 786 ide_dma_error(s);
7aea4412 787 } else {
428c5705 788 ide_rw_error(s);
7aea4412 789 }
428c5705 790 }
4be74634 791 blk_error_action(s->blk, action, is_read, error);
a589569f 792 return action != BLOCK_ERROR_ACTION_IGNORE;
428c5705
AL		 793}
794
4e2b8b4a 795static void ide_dma_cb(void *opaque, int ret)
98087450 796{
40a6238a 797 IDEState *s = opaque;
8ccad811
FB		 798 int n;
799 int64_t sector_num;
038268e2 800 bool stay_active = false;
8ccad811 801
0d910cfe
FZ		 802 if (ret == -ECANCELED) {
803 return;
804 }
e162cfb0 805 if (ret < 0) {
fd648f10 806 int op = IDE_RETRY_DMA;
cd369c46 807
4e1e0051 808 if (s->dma_cmd == IDE_DMA_READ)
fd648f10 809 op |= IDE_RETRY_READ;
d353fb72 810 else if (s->dma_cmd == IDE_DMA_TRIM)
fd648f10 811 op |= IDE_RETRY_TRIM;
d353fb72 812
cd369c46 813 if (ide_handle_rw_error(s, -ret, op)) {
ce4b6522
KW		 814 return;
815 }
e162cfb0
AZ		 816 }
817
8ccad811 818 n = s->io_buffer_size >> 9;
038268e2
KW		 819 if (n > s->nsector) {
820 /* The PRDs were longer than needed for this request. Shorten them so
821 * we don't get a negative remainder. The Active bit must remain set
822 * after the request completes. */
823 n = s->nsector;
824 stay_active = true;
825 }
826
8ccad811
FB		 827 sector_num = ide_get_sector(s);
828 if (n > 0) {
a718978e
JS		 829 assert(n * 512 == s->sg.size);
830 dma_buf_commit(s, s->sg.size);
8ccad811
FB		 831 sector_num += n;
832 ide_set_sector(s, sector_num);
833 s->nsector -= n;
8ccad811
FB		 834 }
835
836 /* end of transfer ? */
837 if (s->nsector == 0) {
98087450 838 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 839 ide_set_irq(s->bus);
cd369c46 840 goto eot;
98087450 841 }
8ccad811
FB		 842
843 /* launch next transfer */
844 n = s->nsector;
596bb44d 845 s->io_buffer_index = 0;
8ccad811 846 s->io_buffer_size = n * 512;
a718978e 847 if (s->bus->dma->ops->prepare_buf(s->bus->dma, s->io_buffer_size) < 512) {
69c38b8f
KW		 848 /* The PRDs were too short. Reset the Active bit, but don't raise an
849 * interrupt. */
72bcca73 850 s->status = READY_STAT | SEEK_STAT;
3251bdcf 851 dma_buf_commit(s, 0);
7aea4412 852 goto eot;
69c38b8f 853 }
cd369c46 854
8ccad811 855#ifdef DEBUG_AIO
4e1e0051
CH		 856 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
857 sector_num, n, s->dma_cmd);
8ccad811 858#endif
cd369c46 859
d66168ed
MT		 860 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
861 !ide_sect_range_ok(s, sector_num, n)) {
58ac3211 862 ide_dma_error(s);
ecca3b39 863 block_acct_invalid(blk_get_stats(s->blk), s->acct.type);
58ac3211
MA		 864 return;
865 }
866
4e1e0051
CH		 867 switch (s->dma_cmd) {
868 case IDE_DMA_READ:
4be74634
MA		 869 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, sector_num,
870 ide_dma_cb, s);
4e1e0051
CH		 871 break;
872 case IDE_DMA_WRITE:
4be74634
MA		 873 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, sector_num,
874 ide_dma_cb, s);
4e1e0051 875 break;
d353fb72 876 case IDE_DMA_TRIM:
4be74634
MA		 877 s->bus->dma->aiocb = dma_blk_io(s->blk, &s->sg, sector_num,
878 ide_issue_trim, ide_dma_cb, s,
879 DMA_DIRECTION_TO_DEVICE);
d353fb72 880 break;
cd369c46 881 }
cd369c46
CH		 882 return;
883
884eot:
a597e79c 885 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
4be74634 886 block_acct_done(blk_get_stats(s->blk), &s->acct);
a597e79c 887 }
0e7ce54c 888 ide_set_inactive(s, stay_active);
98087450
FB		 889}
890
4e1e0051 891static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 892{
8ccad811 893 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
98087450 894 s->io_buffer_size = 0;
4e1e0051 895 s->dma_cmd = dma_cmd;
a597e79c
CH		 896
897 switch (dma_cmd) {
898 case IDE_DMA_READ:
4be74634 899 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 900 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
a597e79c
CH		 901 break;
902 case IDE_DMA_WRITE:
4be74634 903 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 904 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
a597e79c
CH		 905 break;
906 default:
907 break;
908 }
909
4855b576
PB		 910 ide_start_dma(s, ide_dma_cb);
911}
912
097310b5 913void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
4855b576 914{
c71c06d4 915 s->io_buffer_index = 0;
a96cb236 916 s->bus->retry_unit = s->unit;
dc5d0af4
PB		 917 s->bus->retry_sector_num = ide_get_sector(s);
918 s->bus->retry_nsector = s->nsector;
4855b576
PB		 919 if (s->bus->dma->ops->start_dma) {
920 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
921 }
98087450
FB		 922}
923
4e2b8b4a
PB		 924static void ide_sector_write(IDEState *s);
925
a09db21f
FB		 926static void ide_sector_write_timer_cb(void *opaque)
927{
928 IDEState *s = opaque;
9cdd03a7 929 ide_set_irq(s->bus);
a09db21f
FB		 930}
931
e82dabd8 932static void ide_sector_write_cb(void *opaque, int ret)
5391d806 933{
e82dabd8
SH		 934 IDEState *s = opaque;
935 int n;
a597e79c 936
0d910cfe
FZ		 937 if (ret == -ECANCELED) {
938 return;
939 }
428c5705 940
e82dabd8
SH		 941 s->pio_aiocb = NULL;
942 s->status &= ~BUSY_STAT;
943
e162cfb0 944 if (ret != 0) {
fd648f10 945 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
428c5705 946 return;
e82dabd8 947 }
e162cfb0
AZ		 948 }
949
ecca3b39
AG		 950 block_acct_done(blk_get_stats(s->blk), &s->acct);
951
e82dabd8
SH		 952 n = s->nsector;
953 if (n > s->req_nb_sectors) {
954 n = s->req_nb_sectors;
955 }
5391d806 956 s->nsector -= n;
36334faf 957
6aff22c0 958 ide_set_sector(s, ide_get_sector(s) + n);
5391d806 959 if (s->nsector == 0) {
292eef5a 960 /* no more sectors to write */
5391d806
FB		 961 ide_transfer_stop(s);
962 } else {
e82dabd8
SH		 963 int n1 = s->nsector;
964 if (n1 > s->req_nb_sectors) {
5391d806 965 n1 = s->req_nb_sectors;
e82dabd8
SH		 966 }
967 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
968 ide_sector_write);
5391d806 969 }
3b46e624 970
31c2a146
TS		 971 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
972 /* It seems there is a bug in the Windows 2000 installer HDD
973 IDE driver which fills the disk with empty logs when the
974 IDE write IRQ comes too early. This hack tries to correct
975 that at the expense of slower write performances. Use this
976 option _only_ to install Windows 2000. You must disable it
977 for normal use. */
73bcb24d
RS		 978 timer_mod(s->sector_write_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
979 (NANOSECONDS_PER_SECOND / 1000));
f7736b91 980 } else {
9cdd03a7 981 ide_set_irq(s->bus);
31c2a146 982 }
5391d806
FB		 983}
984
4e2b8b4a 985static void ide_sector_write(IDEState *s)
e82dabd8
SH		 986{
987 int64_t sector_num;
988 int n;
989
990 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
991 sector_num = ide_get_sector(s);
992#if defined(DEBUG_IDE)
993 printf("sector=%" PRId64 "\n", sector_num);
994#endif
995 n = s->nsector;
996 if (n > s->req_nb_sectors) {
997 n = s->req_nb_sectors;
998 }
999
58ac3211
MA		 1000 if (!ide_sect_range_ok(s, sector_num, n)) {
1001 ide_rw_error(s);
ecca3b39 1002 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE);
58ac3211
MA		 1003 return;
1004 }
1005
e82dabd8
SH		 1006 s->iov.iov_base = s->io_buffer;
1007 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
1008 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
1009
4be74634 1010 block_acct_start(blk_get_stats(s->blk), &s->acct,
c618f331 1011 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
4be74634
MA		 1012 s->pio_aiocb = blk_aio_writev(s->blk, sector_num, &s->qiov, n,
1013 ide_sector_write_cb, s);
e82dabd8
SH		 1014}
1015
b0484ae4
CH		 1016static void ide_flush_cb(void *opaque, int ret)
1017{
1018 IDEState *s = opaque;
1019
69f72a22
PB		 1020 s->pio_aiocb = NULL;
1021
0d910cfe
FZ		 1022 if (ret == -ECANCELED) {
1023 return;
1024 }
e2bcadad
KW		 1025 if (ret < 0) {
1026 /* XXX: What sector number to set here? */
fd648f10 1027 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
e2bcadad
KW		 1028 return;
1029 }
1030 }
b0484ae4 1031
4be74634
MA		 1032 if (s->blk) {
1033 block_acct_done(blk_get_stats(s->blk), &s->acct);
f7f3ff1d 1034 }
b0484ae4 1035 s->status = READY_STAT | SEEK_STAT;
c7e73adb 1036 ide_cmd_done(s);
b0484ae4
CH		 1037 ide_set_irq(s->bus);
1038}
1039
4e2b8b4a 1040static void ide_flush_cache(IDEState *s)
6bcb1a79 1041{
4be74634 1042 if (s->blk == NULL) {
6bcb1a79 1043 ide_flush_cb(s, 0);
b2df7531
KW		 1044 return;
1045 }
1046
f68ec837 1047 s->status |= BUSY_STAT;
4be74634
MA		 1048 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
1049 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
6bcb1a79
KW		 1050}
1051
201a51fc
AZ		 1052static void ide_cfata_metadata_inquiry(IDEState *s)
1053{
1054 uint16_t *p;
1055 uint32_t spd;
1056
1057 p = (uint16_t *) s->io_buffer;
1058 memset(p, 0, 0x200);
1059 spd = ((s->mdata_size - 1) >> 9) + 1;
1060
1061 put_le16(p + 0, 0x0001); /* Data format revision */
1062 put_le16(p + 1, 0x0000); /* Media property: silicon */
1063 put_le16(p + 2, s->media_changed); /* Media status */
1064 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
1065 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
1066 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
1067 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
1068}
1069
1070static void ide_cfata_metadata_read(IDEState *s)
1071{
1072 uint16_t *p;
1073
1074 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1075 s->status = ERR_STAT;
1076 s->error = ABRT_ERR;
1077 return;
1078 }
1079
1080 p = (uint16_t *) s->io_buffer;
1081 memset(p, 0, 0x200);
1082
1083 put_le16(p + 0, s->media_changed); /* Media status */
1084 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1085 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1086 s->nsector << 9), 0x200 - 2));
1087}
1088
1089static void ide_cfata_metadata_write(IDEState *s)
1090{
1091 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1092 s->status = ERR_STAT;
1093 s->error = ABRT_ERR;
1094 return;
1095 }
1096
1097 s->media_changed = 0;
1098
1099 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1100 s->io_buffer + 2,
1101 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1102 s->nsector << 9), 0x200 - 2));
1103}
1104
bd491d6a 1105/* called when the inserted state of the media has changed */
7d4b4ba5 1106static void ide_cd_change_cb(void *opaque, bool load)
bd491d6a
TS		 1107{
1108 IDEState *s = opaque;
96b8f136 1109 uint64_t nb_sectors;
bd491d6a 1110
25ad22bc 1111 s->tray_open = !load;
4be74634 1112 blk_get_geometry(s->blk, &nb_sectors);
bd491d6a 1113 s->nb_sectors = nb_sectors;
9118e7f0 1114
4b9b7092
AS		 1115 /*
1116 * First indicate to the guest that a CD has been removed. That's
1117 * done on the next command the guest sends us.
1118 *
67cc61e4 1119 * Then we set UNIT_ATTENTION, by which the guest will
4b9b7092
AS		 1120 * detect a new CD in the drive. See ide_atapi_cmd() for details.
1121 */
93c8cfd9 1122 s->cdrom_changed = 1;
996faf1a 1123 s->events.new_media = true;
2df0a3a3
PB		 1124 s->events.eject_request = false;
1125 ide_set_irq(s->bus);
1126}
1127
1128static void ide_cd_eject_request_cb(void *opaque, bool force)
1129{
1130 IDEState *s = opaque;
1131
1132 s->events.eject_request = true;
1133 if (force) {
1134 s->tray_locked = false;
1135 }
9cdd03a7 1136 ide_set_irq(s->bus);
bd491d6a
TS		 1137}
1138
c2ff060f
FB		 1139static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1140{
1141 s->lba48 = lba48;
1142
1143 /* handle the 'magic' 0 nsector count conversion here. to avoid
1144 * fiddling with the rest of the read logic, we just store the
1145 * full sector count in ->nsector and ignore ->hob_nsector from now
1146 */
1147 if (!s->lba48) {
1148 if (!s->nsector)
1149 s->nsector = 256;
1150 } else {
1151 if (!s->nsector && !s->hob_nsector)
1152 s->nsector = 65536;
1153 else {
1154 int lo = s->nsector;
1155 int hi = s->hob_nsector;
1156
1157 s->nsector = (hi << 8) | lo;
1158 }
1159 }
1160}
1161
bcbdc4d3 1162static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 1163{
1164 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 1165 bus->ifs[0].select &= ~(1 << 7);
1166 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 1167}
1168
356721ae 1169void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 1170{
bcbdc4d3 1171 IDEBus *bus = opaque;
5391d806
FB		 1172
1173#ifdef DEBUG_IDE
1174 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1175#endif
c2ff060f 1176
5391d806 1177 addr &= 7;
fcdd25ab
AL		 1178
1179 /* ignore writes to command block while busy with previous command */
bcbdc4d3 1180 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
fcdd25ab
AL		 1181 return;
1182
5391d806
FB		 1183 switch(addr) {
1184 case 0:
1185 break;
1186 case 1:
bcbdc4d3 1187 ide_clear_hob(bus);
c45c3d00 1188 /* NOTE: data is written to the two drives */
bcbdc4d3
GH		 1189 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1190 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1191 bus->ifs[0].feature = val;
1192 bus->ifs[1].feature = val;
5391d806
FB		 1193 break;
1194 case 2:
bcbdc4d3
GH		 1195 ide_clear_hob(bus);
1196 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1197 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1198 bus->ifs[0].nsector = val;
1199 bus->ifs[1].nsector = val;
5391d806
FB		 1200 break;
1201 case 3:
bcbdc4d3
GH		 1202 ide_clear_hob(bus);
1203 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1204 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1205 bus->ifs[0].sector = val;
1206 bus->ifs[1].sector = val;
5391d806
FB		 1207 break;
1208 case 4:
bcbdc4d3
GH		 1209 ide_clear_hob(bus);
1210 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1211 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1212 bus->ifs[0].lcyl = val;
1213 bus->ifs[1].lcyl = val;
5391d806
FB		 1214 break;
1215 case 5:
bcbdc4d3
GH		 1216 ide_clear_hob(bus);
1217 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1218 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1219 bus->ifs[0].hcyl = val;
1220 bus->ifs[1].hcyl = val;
5391d806
FB		 1221 break;
1222 case 6:
c2ff060f 1223 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 1224 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1225 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 1226 /* select drive */
bcbdc4d3 1227 bus->unit = (val >> 4) & 1;
5391d806
FB		 1228 break;
1229 default:
1230 case 7:
1231 /* command */
7cff87ff
AG		 1232 ide_exec_cmd(bus, val);
1233 break;
1234 }
1235}
1236
4590355b
JS		 1237static void ide_reset(IDEState *s)
1238{
1239#ifdef DEBUG_IDE
1240 printf("ide: reset\n");
1241#endif
1242
1243 if (s->pio_aiocb) {
1244 blk_aio_cancel(s->pio_aiocb);
1245 s->pio_aiocb = NULL;
1246 }
1247
1248 if (s->drive_kind == IDE_CFATA)
1249 s->mult_sectors = 0;
1250 else
1251 s->mult_sectors = MAX_MULT_SECTORS;
1252 /* ide regs */
1253 s->feature = 0;
1254 s->error = 0;
1255 s->nsector = 0;
1256 s->sector = 0;
1257 s->lcyl = 0;
1258 s->hcyl = 0;
1259
1260 /* lba48 */
1261 s->hob_feature = 0;
1262 s->hob_sector = 0;
1263 s->hob_nsector = 0;
1264 s->hob_lcyl = 0;
1265 s->hob_hcyl = 0;
1266
1267 s->select = 0xa0;
1268 s->status = READY_STAT | SEEK_STAT;
1269
1270 s->lba48 = 0;
1271
1272 /* ATAPI specific */
1273 s->sense_key = 0;
1274 s->asc = 0;
1275 s->cdrom_changed = 0;
1276 s->packet_transfer_size = 0;
1277 s->elementary_transfer_size = 0;
1278 s->io_buffer_index = 0;
1279 s->cd_sector_size = 0;
1280 s->atapi_dma = 0;
1281 s->tray_locked = 0;
1282 s->tray_open = 0;
1283 /* ATA DMA state */
1284 s->io_buffer_size = 0;
1285 s->req_nb_sectors = 0;
1286
1287 ide_set_signature(s);
1288 /* init the transfer handler so that 0xffff is returned on data
1289 accesses */
1290 s->end_transfer_func = ide_dummy_transfer_stop;
1291 ide_dummy_transfer_stop(s);
1292 s->media_changed = 0;
1293}
1294
b300337e
KW		 1295static bool cmd_nop(IDEState *s, uint8_t cmd)
1296{
1297 return true;
1298}
1299
f34ae00d
JS		 1300static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1301{
1302 /* Halt PIO (in the DRQ phase), then DMA */
1303 ide_transfer_cancel(s);
1304 ide_cancel_dma_sync(s);
1305
1306 /* Reset any PIO commands, reset signature, etc */
1307 ide_reset(s);
1308
1309 /* RESET: ATA8-ACS3 7.10.4 "Normal Outputs";
1310 * ATA8-ACS3 Table 184 "Device Signatures for Normal Output" */
1311 s->status = 0x00;
1312
1313 /* Do not overwrite status register */
1314 return false;
1315}
1316
4286434c
KW		 1317static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1318{
1319 switch (s->feature) {
1320 case DSM_TRIM:
4be74634 1321 if (s->blk) {
4286434c
KW		 1322 ide_sector_start_dma(s, IDE_DMA_TRIM);
1323 return false;
1324 }
1325 break;
1326 }
1327
1328 ide_abort_command(s);
1329 return true;
1330}
1331
1c66869a
KW		 1332static bool cmd_identify(IDEState *s, uint8_t cmd)
1333{
4be74634 1334 if (s->blk && s->drive_kind != IDE_CD) {
1c66869a
KW		 1335 if (s->drive_kind != IDE_CFATA) {
1336 ide_identify(s);
1337 } else {
1338 ide_cfata_identify(s);
1339 }
1340 s->status = READY_STAT | SEEK_STAT;
1341 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1342 ide_set_irq(s->bus);
1343 return false;
1344 } else {
1345 if (s->drive_kind == IDE_CD) {
1346 ide_set_signature(s);
1347 }
1348 ide_abort_command(s);
1349 }
1350
1351 return true;
1352}
1353
413860cf
KW		 1354static bool cmd_verify(IDEState *s, uint8_t cmd)
1355{
1356 bool lba48 = (cmd == WIN_VERIFY_EXT);
1357
1358 /* do sector number check ? */
1359 ide_cmd_lba48_transform(s, lba48);
1360
1361 return true;
1362}
1363
adf3a2c4
KW		 1364static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1365{
1366 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1367 /* Disable Read and Write Multiple */
1368 s->mult_sectors = 0;
1369 } else if ((s->nsector & 0xff) != 0 &&
1370 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1371 (s->nsector & (s->nsector - 1)) != 0)) {
1372 ide_abort_command(s);
1373 } else {
1374 s->mult_sectors = s->nsector & 0xff;
1375 }
1376
1377 return true;
1378}
1379
1380static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1381{
1382 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1383
4be74634 1384 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1385 ide_abort_command(s);
1386 return true;
1387 }
1388
1389 ide_cmd_lba48_transform(s, lba48);
1390 s->req_nb_sectors = s->mult_sectors;
1391 ide_sector_read(s);
1392 return false;
1393}
1394
1395static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1396{
1397 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1398 int n;
1399
4be74634 1400 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1401 ide_abort_command(s);
1402 return true;
1403 }
1404
1405 ide_cmd_lba48_transform(s, lba48);
1406
1407 s->req_nb_sectors = s->mult_sectors;
1408 n = MIN(s->nsector, s->req_nb_sectors);
1409
1410 s->status = SEEK_STAT | READY_STAT;
1411 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1412
1413 s->media_changed = 1;
1414
1415 return false;
1416}
1417
0e6498ed
KW		 1418static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1419{
1420 bool lba48 = (cmd == WIN_READ_EXT);
1421
1422 if (s->drive_kind == IDE_CD) {
1423 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1424 ide_abort_command(s);
1425 return true;
1426 }
1427
4be74634 1428 if (!s->blk) {
0e6498ed
KW		 1429 ide_abort_command(s);
1430 return true;
1431 }
1432
1433 ide_cmd_lba48_transform(s, lba48);
1434 s->req_nb_sectors = 1;
1435 ide_sector_read(s);
1436
1437 return false;
1438}
1439
1440static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1441{
1442 bool lba48 = (cmd == WIN_WRITE_EXT);
1443
4be74634 1444 if (!s->blk) {
0e6498ed
KW		 1445 ide_abort_command(s);
1446 return true;
1447 }
1448
1449 ide_cmd_lba48_transform(s, lba48);
1450
1451 s->req_nb_sectors = 1;
1452 s->status = SEEK_STAT | READY_STAT;
1453 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1454
1455 s->media_changed = 1;
1456
1457 return false;
1458}
1459
92a6a6f6
KW		 1460static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1461{
1462 bool lba48 = (cmd == WIN_READDMA_EXT);
1463
4be74634 1464 if (!s->blk) {
92a6a6f6
KW		 1465 ide_abort_command(s);
1466 return true;
1467 }
1468
1469 ide_cmd_lba48_transform(s, lba48);
1470 ide_sector_start_dma(s, IDE_DMA_READ);
1471
1472 return false;
1473}
1474
1475static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1476{
1477 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1478
4be74634 1479 if (!s->blk) {
92a6a6f6
KW		 1480 ide_abort_command(s);
1481 return true;
1482 }
1483
1484 ide_cmd_lba48_transform(s, lba48);
1485 ide_sector_start_dma(s, IDE_DMA_WRITE);
1486
1487 s->media_changed = 1;
1488
1489 return false;
1490}
1491
9afce429
KW		 1492static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1493{
1494 ide_flush_cache(s);
1495 return false;
1496}
1497
61fdda37
KW		 1498static bool cmd_seek(IDEState *s, uint8_t cmd)
1499{
1500 /* XXX: Check that seek is within bounds */
1501 return true;
1502}
1503
63a82e6a
KW		 1504static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1505{
1506 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1507
1508 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1509 if (s->nb_sectors == 0) {
1510 ide_abort_command(s);
1511 return true;
1512 }
1513
1514 ide_cmd_lba48_transform(s, lba48);
1515 ide_set_sector(s, s->nb_sectors - 1);
1516
1517 return true;
1518}
1519
785f6320
KW		 1520static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1521{
1522 s->nsector = 0xff; /* device active or idle */
1523 return true;
1524}
1525
ee03398c
KW		 1526static bool cmd_set_features(IDEState *s, uint8_t cmd)
1527{
1528 uint16_t *identify_data;
1529
4be74634 1530 if (!s->blk) {
ee03398c
KW		 1531 ide_abort_command(s);
1532 return true;
1533 }
1534
1535 /* XXX: valid for CDROM ? */
1536 switch (s->feature) {
1537 case 0x02: /* write cache enable */
4be74634 1538 blk_set_enable_write_cache(s->blk, true);
ee03398c
KW		 1539 identify_data = (uint16_t *)s->identify_data;
1540 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1541 return true;
1542 case 0x82: /* write cache disable */
4be74634 1543 blk_set_enable_write_cache(s->blk, false);
ee03398c
KW		 1544 identify_data = (uint16_t *)s->identify_data;
1545 put_le16(identify_data + 85, (1 << 14) | 1);
1546 ide_flush_cache(s);
1547 return false;
1548 case 0xcc: /* reverting to power-on defaults enable */
1549 case 0x66: /* reverting to power-on defaults disable */
1550 case 0xaa: /* read look-ahead enable */
1551 case 0x55: /* read look-ahead disable */
1552 case 0x05: /* set advanced power management mode */
1553 case 0x85: /* disable advanced power management mode */
1554 case 0x69: /* NOP */
1555 case 0x67: /* NOP */
1556 case 0x96: /* NOP */
1557 case 0x9a: /* NOP */
1558 case 0x42: /* enable Automatic Acoustic Mode */
1559 case 0xc2: /* disable Automatic Acoustic Mode */
1560 return true;
1561 case 0x03: /* set transfer mode */
1562 {
1563 uint8_t val = s->nsector & 0x07;
1564 identify_data = (uint16_t *)s->identify_data;
1565
1566 switch (s->nsector >> 3) {
1567 case 0x00: /* pio default */
1568 case 0x01: /* pio mode */
1569 put_le16(identify_data + 62, 0x07);
1570 put_le16(identify_data + 63, 0x07);
1571 put_le16(identify_data + 88, 0x3f);
1572 break;
1573 case 0x02: /* sigle word dma mode*/
1574 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1575 put_le16(identify_data + 63, 0x07);
1576 put_le16(identify_data + 88, 0x3f);
1577 break;
1578 case 0x04: /* mdma mode */
1579 put_le16(identify_data + 62, 0x07);
1580 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1581 put_le16(identify_data + 88, 0x3f);
1582 break;
1583 case 0x08: /* udma mode */
1584 put_le16(identify_data + 62, 0x07);
1585 put_le16(identify_data + 63, 0x07);
1586 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1587 break;
1588 default:
1589 goto abort_cmd;
1590 }
1591 return true;
1592 }
1593 }
1594
1595abort_cmd:
1596 ide_abort_command(s);
1597 return true;
1598}
1599
ee425c78
KW		 1600
1601/*** ATAPI commands ***/
1602
1603static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1604{
1605 ide_atapi_identify(s);
1606 s->status = READY_STAT | SEEK_STAT;
1607 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1608 ide_set_irq(s->bus);
1609 return false;
1610}
1611
1612static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1613{
1614 ide_set_signature(s);
1615
1616 if (s->drive_kind == IDE_CD) {
1617 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1618 * devices to return a clear status register
1619 * with READY_STAT *not* set. */
850484a2 1620 s->error = 0x01;
ee425c78
KW		 1621 } else {
1622 s->status = READY_STAT | SEEK_STAT;
1623 /* The bits of the error register are not as usual for this command!
1624 * They are part of the regular output (this is why ERR_STAT isn't set)
1625 * Device 0 passed, Device 1 passed or not present. */
1626 s->error = 0x01;
1627 ide_set_irq(s->bus);
1628 }
1629
1630 return false;
1631}
1632
ee425c78
KW		 1633static bool cmd_packet(IDEState *s, uint8_t cmd)
1634{
1635 /* overlapping commands not supported */
1636 if (s->feature & 0x02) {
1637 ide_abort_command(s);
1638 return true;
1639 }
1640
1641 s->status = READY_STAT | SEEK_STAT;
1642 s->atapi_dma = s->feature & 1;
1643 s->nsector = 1;
1644 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1645 ide_atapi_cmd);
1646 return false;
1647}
1648
6b1dd744
KW		 1649
1650/*** CF-ATA commands ***/
1651
1652static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1653{
1654 s->error = 0x09; /* miscellaneous error */
1655 s->status = READY_STAT | SEEK_STAT;
1656 ide_set_irq(s->bus);
1657
1658 return false;
1659}
1660
1661static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1662{
1663 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1664 * required for Windows 8 to work with AHCI */
1665
1666 if (cmd == CFA_WEAR_LEVEL) {
1667 s->nsector = 0;
1668 }
1669
1670 if (cmd == CFA_ERASE_SECTORS) {
1671 s->media_changed = 1;
1672 }
1673
1674 return true;
1675}
1676
1677static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1678{
1679 s->status = READY_STAT | SEEK_STAT;
1680
1681 memset(s->io_buffer, 0, 0x200);
1682 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1683 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1684 s->io_buffer[0x02] = s->select; /* Head */
1685 s->io_buffer[0x03] = s->sector; /* Sector */
1686 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1687 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1688 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1689 s->io_buffer[0x13] = 0x00; /* Erase flag */
1690 s->io_buffer[0x18] = 0x00; /* Hot count */
1691 s->io_buffer[0x19] = 0x00; /* Hot count */
1692 s->io_buffer[0x1a] = 0x01; /* Hot count */
1693
1694 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1695 ide_set_irq(s->bus);
1696
1697 return false;
1698}
1699
1700static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1701{
1702 switch (s->feature) {
1703 case 0x02: /* Inquiry Metadata Storage */
1704 ide_cfata_metadata_inquiry(s);
1705 break;
1706 case 0x03: /* Read Metadata Storage */
1707 ide_cfata_metadata_read(s);
1708 break;
1709 case 0x04: /* Write Metadata Storage */
1710 ide_cfata_metadata_write(s);
1711 break;
1712 default:
1713 ide_abort_command(s);
1714 return true;
1715 }
1716
1717 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1718 s->status = 0x00; /* NOTE: READY is _not_ set */
1719 ide_set_irq(s->bus);
1720
1721 return false;
1722}
1723
1724static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1725{
1726 switch (s->feature) {
1727 case 0x01: /* sense temperature in device */
1728 s->nsector = 0x50; /* +20 C */
1729 break;
1730 default:
1731 ide_abort_command(s);
1732 return true;
1733 }
1734
1735 return true;
1736}
1737
ff352677
KW		 1738
1739/*** SMART commands ***/
1740
1741static bool cmd_smart(IDEState *s, uint8_t cmd)
1742{
1743 int n;
1744
1745 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1746 goto abort_cmd;
1747 }
1748
1749 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1750 goto abort_cmd;
1751 }
1752
1753 switch (s->feature) {
1754 case SMART_DISABLE:
1755 s->smart_enabled = 0;
1756 return true;
1757
1758 case SMART_ENABLE:
1759 s->smart_enabled = 1;
1760 return true;
1761
1762 case SMART_ATTR_AUTOSAVE:
1763 switch (s->sector) {
1764 case 0x00:
1765 s->smart_autosave = 0;
1766 break;
1767 case 0xf1:
1768 s->smart_autosave = 1;
1769 break;
1770 default:
1771 goto abort_cmd;
1772 }
1773 return true;
1774
1775 case SMART_STATUS:
1776 if (!s->smart_errors) {
1777 s->hcyl = 0xc2;
1778 s->lcyl = 0x4f;
1779 } else {
1780 s->hcyl = 0x2c;
1781 s->lcyl = 0xf4;
1782 }
1783 return true;
1784
1785 case SMART_READ_THRESH:
1786 memset(s->io_buffer, 0, 0x200);
1787 s->io_buffer[0] = 0x01; /* smart struct version */
1788
1789 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1790 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1791 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1792 }
1793
1794 /* checksum */
1795 for (n = 0; n < 511; n++) {
1796 s->io_buffer[511] += s->io_buffer[n];
1797 }
1798 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1799
1800 s->status = READY_STAT | SEEK_STAT;
1801 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1802 ide_set_irq(s->bus);
1803 return false;
1804
1805 case SMART_READ_DATA:
1806 memset(s->io_buffer, 0, 0x200);
1807 s->io_buffer[0] = 0x01; /* smart struct version */
1808
1809 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1810 int i;
1811 for (i = 0; i < 11; i++) {
1812 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1813 }
1814 }
1815
1816 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1817 if (s->smart_selftest_count == 0) {
1818 s->io_buffer[363] = 0;
1819 } else {
1820 s->io_buffer[363] =
1821 s->smart_selftest_data[3 +
1822 (s->smart_selftest_count - 1) *
1823 24];
1824 }
1825 s->io_buffer[364] = 0x20;
1826 s->io_buffer[365] = 0x01;
1827 /* offline data collection capacity: execute + self-test*/
1828 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1829 s->io_buffer[368] = 0x03; /* smart capability (1) */
1830 s->io_buffer[369] = 0x00; /* smart capability (2) */
1831 s->io_buffer[370] = 0x01; /* error logging supported */
1832 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1833 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1834 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1835
1836 for (n = 0; n < 511; n++) {
1837 s->io_buffer[511] += s->io_buffer[n];
1838 }
1839 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1840
1841 s->status = READY_STAT | SEEK_STAT;
1842 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1843 ide_set_irq(s->bus);
1844 return false;
1845
1846 case SMART_READ_LOG:
1847 switch (s->sector) {
1848 case 0x01: /* summary smart error log */
1849 memset(s->io_buffer, 0, 0x200);
1850 s->io_buffer[0] = 0x01;
1851 s->io_buffer[1] = 0x00; /* no error entries */
1852 s->io_buffer[452] = s->smart_errors & 0xff;
1853 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1854
1855 for (n = 0; n < 511; n++) {
1856 s->io_buffer[511] += s->io_buffer[n];
1857 }
1858 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1859 break;
1860 case 0x06: /* smart self test log */
1861 memset(s->io_buffer, 0, 0x200);
1862 s->io_buffer[0] = 0x01;
1863 if (s->smart_selftest_count == 0) {
1864 s->io_buffer[508] = 0;
1865 } else {
1866 s->io_buffer[508] = s->smart_selftest_count;
1867 for (n = 2; n < 506; n++) {
1868 s->io_buffer[n] = s->smart_selftest_data[n];
1869 }
1870 }
1871
1872 for (n = 0; n < 511; n++) {
1873 s->io_buffer[511] += s->io_buffer[n];
1874 }
1875 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1876 break;
1877 default:
1878 goto abort_cmd;
1879 }
1880 s->status = READY_STAT | SEEK_STAT;
1881 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1882 ide_set_irq(s->bus);
1883 return false;
1884
1885 case SMART_EXECUTE_OFFLINE:
1886 switch (s->sector) {
1887 case 0: /* off-line routine */
1888 case 1: /* short self test */
1889 case 2: /* extended self test */
1890 s->smart_selftest_count++;
1891 if (s->smart_selftest_count > 21) {
940973ae 1892 s->smart_selftest_count = 1;
ff352677
KW		 1893 }
1894 n = 2 + (s->smart_selftest_count - 1) * 24;
1895 s->smart_selftest_data[n] = s->sector;
1896 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1897 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1898 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1899 break;
1900 default:
1901 goto abort_cmd;
1902 }
1903 return true;
1904 }
1905
1906abort_cmd:
1907 ide_abort_command(s);
1908 return true;
1909}
1910
844505b1
MA		 1911#define HD_OK (1u << IDE_HD)
1912#define CD_OK (1u << IDE_CD)
1913#define CFA_OK (1u << IDE_CFATA)
1914#define HD_CFA_OK (HD_OK | CFA_OK)
1915#define ALL_OK (HD_OK | CD_OK | CFA_OK)
1916
a0436e92
KW		 1917/* Set the Disk Seek Completed status bit during completion */
1918#define SET_DSC (1u << 8)
1919
844505b1 1920/* See ACS-2 T13/2015-D Table B.2 Command codes */
a0436e92
KW		 1921static const struct {
1922 /* Returns true if the completion code should be run */
1923 bool (*handler)(IDEState *s, uint8_t cmd);
1924 int flags;
1925} ide_cmd_table[0x100] = {
844505b1 1926 /* NOP not implemented, mandatory for CD */
6b1dd744 1927 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
d9033e1d 1928 [WIN_DSM] = { cmd_data_set_management, HD_CFA_OK },
ee425c78 1929 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
b300337e 1930 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
0e6498ed 1931 [WIN_READ] = { cmd_read_pio, ALL_OK },
d9033e1d 1932 [WIN_READ_ONCE] = { cmd_read_pio, HD_CFA_OK },
0e6498ed 1933 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
92a6a6f6 1934 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
63a82e6a 1935 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
adf3a2c4 1936 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
0e6498ed
KW		 1937 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1938 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1939 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
92a6a6f6 1940 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
0e6498ed 1941 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
adf3a2c4 1942 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
0e6498ed 1943 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
413860cf
KW		 1944 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1945 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1946 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
61fdda37 1947 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
6b1dd744 1948 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
ee425c78 1949 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
b300337e 1950 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
d9033e1d
JS		 1951 [WIN_STANDBYNOW2] = { cmd_nop, HD_CFA_OK },
1952 [WIN_IDLEIMMEDIATE2] = { cmd_nop, HD_CFA_OK },
1953 [WIN_STANDBY2] = { cmd_nop, HD_CFA_OK },
1954 [WIN_SETIDLE2] = { cmd_nop, HD_CFA_OK },
1955 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1956 [WIN_SLEEPNOW2] = { cmd_nop, HD_CFA_OK },
ee425c78
KW		 1957 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1958 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
ff352677 1959 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
6b1dd744
KW		 1960 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1961 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
adf3a2c4
KW		 1962 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1963 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1964 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
92a6a6f6
KW		 1965 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1966 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1967 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1968 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
adf3a2c4 1969 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
d9033e1d
JS		 1970 [WIN_STANDBYNOW1] = { cmd_nop, HD_CFA_OK },
1971 [WIN_IDLEIMMEDIATE] = { cmd_nop, HD_CFA_OK },
1972 [WIN_STANDBY] = { cmd_nop, HD_CFA_OK },
1973 [WIN_SETIDLE1] = { cmd_nop, HD_CFA_OK },
1974 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1975 [WIN_SLEEPNOW1] = { cmd_nop, HD_CFA_OK },
9afce429
KW		 1976 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1977 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1c66869a 1978 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
ee03398c 1979 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
6b1dd744
KW		 1980 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1981 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
d9033e1d 1982 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
844505b1
MA		 1983};
1984
1985static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1986{
1987 return cmd < ARRAY_SIZE(ide_cmd_table)
a0436e92 1988 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
844505b1 1989}
7cff87ff
AG		 1990
1991void ide_exec_cmd(IDEBus *bus, uint32_t val)
1992{
1993 IDEState *s;
dfe1ea8f 1994 bool complete;
7cff87ff 1995
5391d806 1996#if defined(DEBUG_IDE)
6ef2ba5e 1997 printf("ide: CMD=%02x\n", val);
5391d806 1998#endif
6ef2ba5e 1999 s = idebus_active_if(bus);
66a0a2cb 2000 /* ignore commands to non existent slave */
4be74634 2001 if (s != bus->ifs && !s->blk) {
6ef2ba5e 2002 return;
4be74634 2003 }
c2ff060f 2004
266e7781
JS		 2005 /* Only RESET is allowed while BSY and/or DRQ are set,
2006 * and only to ATAPI devices. */
2007 if (s->status & (BUSY_STAT|DRQ_STAT)) {
2008 if (val != WIN_DEVICE_RESET || s->drive_kind != IDE_CD) {
2009 return;
2010 }
2011 }
fcdd25ab 2012
844505b1 2013 if (!ide_cmd_permitted(s, val)) {
dfe1ea8f
KW		 2014 ide_abort_command(s);
2015 ide_set_irq(s->bus);
2016 return;
844505b1
MA		 2017 }
2018
dfe1ea8f
KW		 2019 s->status = READY_STAT | BUSY_STAT;
2020 s->error = 0;
36334faf 2021 s->io_buffer_offset = 0;
a0436e92 2022
dfe1ea8f
KW		 2023 complete = ide_cmd_table[val].handler(s, val);
2024 if (complete) {
2025 s->status &= ~BUSY_STAT;
2026 assert(!!s->error == !!(s->status & ERR_STAT));
a0436e92 2027
dfe1ea8f
KW		 2028 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
2029 s->status |= SEEK_STAT;
a0436e92
KW		 2030 }
2031
c7e73adb 2032 ide_cmd_done(s);
6ef2ba5e 2033 ide_set_irq(s->bus);
6ef2ba5e 2034 }
5391d806
FB		 2035}
2036
356721ae 2037uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
5391d806 2038{
bcbdc4d3
GH		 2039 IDEBus *bus = opaque;
2040 IDEState *s = idebus_active_if(bus);
5391d806 2041 uint32_t addr;
c2ff060f 2042 int ret, hob;
5391d806
FB		 2043
2044 addr = addr1 & 7;
c2ff060f
FB		 2045 /* FIXME: HOB readback uses bit 7, but it's always set right now */
2046 //hob = s->select & (1 << 7);
2047 hob = 0;
5391d806
FB		 2048 switch(addr) {
2049 case 0:
2050 ret = 0xff;
2051 break;
2052 case 1:
4be74634
MA		 2053 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2054 (s != bus->ifs && !s->blk)) {
c45c3d00 2055 ret = 0;
4be74634 2056 } else if (!hob) {
c45c3d00 2057 ret = s->error;
4be74634 2058 } else {
c2ff060f 2059 ret = s->hob_feature;
4be74634 2060 }
5391d806
FB		 2061 break;
2062 case 2:
4be74634 2063 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2064 ret = 0;
4be74634 2065 } else if (!hob) {
c45c3d00 2066 ret = s->nsector & 0xff;
4be74634 2067 } else {
c2ff060f 2068 ret = s->hob_nsector;
4be74634 2069 }
5391d806
FB		 2070 break;
2071 case 3:
4be74634 2072 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2073 ret = 0;
4be74634 2074 } else if (!hob) {
c45c3d00 2075 ret = s->sector;
4be74634 2076 } else {
c2ff060f 2077 ret = s->hob_sector;
4be74634 2078 }
5391d806
FB		 2079 break;
2080 case 4:
4be74634 2081 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2082 ret = 0;
4be74634 2083 } else if (!hob) {
c45c3d00 2084 ret = s->lcyl;
4be74634 2085 } else {
c2ff060f 2086 ret = s->hob_lcyl;
4be74634 2087 }
5391d806
FB		 2088 break;
2089 case 5:
4be74634 2090 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2091 ret = 0;
4be74634 2092 } else if (!hob) {
c45c3d00 2093 ret = s->hcyl;
4be74634 2094 } else {
c2ff060f 2095 ret = s->hob_hcyl;
4be74634 2096 }
5391d806
FB		 2097 break;
2098 case 6:
4be74634 2099 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 2100 ret = 0;
4be74634 2101 } else {
7ae98627 2102 ret = s->select;
4be74634 2103 }
5391d806
FB		 2104 break;
2105 default:
2106 case 7:
4be74634
MA		 2107 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2108 (s != bus->ifs && !s->blk)) {
c45c3d00 2109 ret = 0;
4be74634 2110 } else {
c45c3d00 2111 ret = s->status;
4be74634 2112 }
9cdd03a7 2113 qemu_irq_lower(bus->irq);
5391d806
FB		 2114 break;
2115 }
2116#ifdef DEBUG_IDE
2117 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
2118#endif
2119 return ret;
2120}
2121
356721ae 2122uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 2123{
bcbdc4d3
GH		 2124 IDEBus *bus = opaque;
2125 IDEState *s = idebus_active_if(bus);
5391d806 2126 int ret;
7ae98627 2127
4be74634
MA		 2128 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2129 (s != bus->ifs && !s->blk)) {
7ae98627 2130 ret = 0;
4be74634 2131 } else {
7ae98627 2132 ret = s->status;
4be74634 2133 }
5391d806
FB		 2134#ifdef DEBUG_IDE
2135 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
2136#endif
2137 return ret;
2138}
2139
356721ae 2140void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 2141{
bcbdc4d3 2142 IDEBus *bus = opaque;
5391d806
FB		 2143 IDEState *s;
2144 int i;
2145
2146#ifdef DEBUG_IDE
2147 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
2148#endif
2149 /* common for both drives */
9cdd03a7 2150 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 2151 (val & IDE_CMD_RESET)) {
2152 /* reset low to high */
2153 for(i = 0;i < 2; i++) {
bcbdc4d3 2154 s = &bus->ifs[i];
5391d806
FB		 2155 s->status = BUSY_STAT | SEEK_STAT;
2156 s->error = 0x01;
2157 }
9cdd03a7 2158 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 2159 !(val & IDE_CMD_RESET)) {
2160 /* high to low */
2161 for(i = 0;i < 2; i++) {
bcbdc4d3 2162 s = &bus->ifs[i];
cd8722bb 2163 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 2164 s->status = 0x00; /* NOTE: READY is _not_ set */
2165 else
56bf1d37 2166 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 2167 ide_set_signature(s);
2168 }
2169 }
2170
9cdd03a7 2171 bus->cmd = val;
5391d806
FB		 2172}
2173
40c4ed3f
KW		 2174/*
2175 * Returns true if the running PIO transfer is a PIO out (i.e. data is
2176 * transferred from the device to the guest), false if it's a PIO in
2177 */
2178static bool ide_is_pio_out(IDEState *s)
2179{
2180 if (s->end_transfer_func == ide_sector_write ||
2181 s->end_transfer_func == ide_atapi_cmd) {
2182 return false;
2183 } else if (s->end_transfer_func == ide_sector_read ||
2184 s->end_transfer_func == ide_transfer_stop ||
2185 s->end_transfer_func == ide_atapi_cmd_reply_end ||
2186 s->end_transfer_func == ide_dummy_transfer_stop) {
2187 return true;
2188 }
2189
2190 abort();
2191}
2192
356721ae 2193void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 2194{
bcbdc4d3
GH		 2195 IDEBus *bus = opaque;
2196 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2197 uint8_t *p;
2198
40c4ed3f
KW		 2199 /* PIO data access allowed only when DRQ bit is set. The result of a write
2200 * during PIO out is indeterminate, just ignore it. */
2201 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2202 return;
40c4ed3f 2203 }
fcdd25ab 2204
5391d806 2205 p = s->data_ptr;
d2ff8585
KW		 2206 if (p + 2 > s->data_end) {
2207 return;
2208 }
2209
0c4ad8dc 2210 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 2211 p += 2;
2212 s->data_ptr = p;
cb72cba8
KW		 2213 if (p >= s->data_end) {
2214 s->status &= ~DRQ_STAT;
5391d806 2215 s->end_transfer_func(s);
cb72cba8 2216 }
5391d806
FB		 2217}
2218
356721ae 2219uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 2220{
bcbdc4d3
GH		 2221 IDEBus *bus = opaque;
2222 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2223 uint8_t *p;
2224 int ret;
fcdd25ab 2225
40c4ed3f
KW		 2226 /* PIO data access allowed only when DRQ bit is set. The result of a read
2227 * during PIO in is indeterminate, return 0 and don't move forward. */
2228 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 2229 return 0;
40c4ed3f 2230 }
fcdd25ab 2231
5391d806 2232 p = s->data_ptr;
d2ff8585
KW		 2233 if (p + 2 > s->data_end) {
2234 return 0;
2235 }
2236
0c4ad8dc 2237 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 2238 p += 2;
2239 s->data_ptr = p;
cb72cba8
KW		 2240 if (p >= s->data_end) {
2241 s->status &= ~DRQ_STAT;
5391d806 2242 s->end_transfer_func(s);
cb72cba8 2243 }
5391d806
FB		 2244 return ret;
2245}
2246
356721ae 2247void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 2248{
bcbdc4d3
GH		 2249 IDEBus *bus = opaque;
2250 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2251 uint8_t *p;
2252
40c4ed3f
KW		 2253 /* PIO data access allowed only when DRQ bit is set. The result of a write
2254 * during PIO out is indeterminate, just ignore it. */
2255 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2256 return;
40c4ed3f 2257 }
fcdd25ab 2258
5391d806 2259 p = s->data_ptr;
d2ff8585
KW		 2260 if (p + 4 > s->data_end) {
2261 return;
2262 }
2263
0c4ad8dc 2264 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 2265 p += 4;
2266 s->data_ptr = p;
cb72cba8
KW		 2267 if (p >= s->data_end) {
2268 s->status &= ~DRQ_STAT;
5391d806 2269 s->end_transfer_func(s);
cb72cba8 2270 }
5391d806
FB		 2271}
2272
356721ae 2273uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 2274{
bcbdc4d3
GH		 2275 IDEBus *bus = opaque;
2276 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2277 uint8_t *p;
2278 int ret;
3b46e624 2279
40c4ed3f
KW		 2280 /* PIO data access allowed only when DRQ bit is set. The result of a read
2281 * during PIO in is indeterminate, return 0 and don't move forward. */
2282 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 2283 return 0;
40c4ed3f 2284 }
fcdd25ab 2285
5391d806 2286 p = s->data_ptr;
d2ff8585
KW		 2287 if (p + 4 > s->data_end) {
2288 return 0;
2289 }
2290
0c4ad8dc 2291 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 2292 p += 4;
2293 s->data_ptr = p;
cb72cba8
KW		 2294 if (p >= s->data_end) {
2295 s->status &= ~DRQ_STAT;
5391d806 2296 s->end_transfer_func(s);
cb72cba8 2297 }
5391d806
FB		 2298 return ret;
2299}
2300
a7dfe172
FB		 2301static void ide_dummy_transfer_stop(IDEState *s)
2302{
2303 s->data_ptr = s->io_buffer;
2304 s->data_end = s->io_buffer;
2305 s->io_buffer[0] = 0xff;
2306 s->io_buffer[1] = 0xff;
2307 s->io_buffer[2] = 0xff;
2308 s->io_buffer[3] = 0xff;
2309}
2310
4a643563
BS		 2311void ide_bus_reset(IDEBus *bus)
2312{
2313 bus->unit = 0;
2314 bus->cmd = 0;
2315 ide_reset(&bus->ifs[0]);
2316 ide_reset(&bus->ifs[1]);
2317 ide_clear_hob(bus);
40a6238a
AG		 2318
2319 /* pending async DMA */
2320 if (bus->dma->aiocb) {
2321#ifdef DEBUG_AIO
2322 printf("aio_cancel\n");
2323#endif
4be74634 2324 blk_aio_cancel(bus->dma->aiocb);
40a6238a
AG		 2325 bus->dma->aiocb = NULL;
2326 }
2327
2328 /* reset dma provider too */
1374bec0
PB		 2329 if (bus->dma->ops->reset) {
2330 bus->dma->ops->reset(bus->dma);
2331 }
4a643563
BS		 2332}
2333
e4def80b
MA		 2334static bool ide_cd_is_tray_open(void *opaque)
2335{
2336 return ((IDEState *)opaque)->tray_open;
2337}
2338
f107639a
MA		 2339static bool ide_cd_is_medium_locked(void *opaque)
2340{
2341 return ((IDEState *)opaque)->tray_locked;
2342}
2343
01ce352e
JS		 2344static void ide_resize_cb(void *opaque)
2345{
2346 IDEState *s = opaque;
2347 uint64_t nb_sectors;
2348
2349 if (!s->identify_set) {
2350 return;
2351 }
2352
4be74634 2353 blk_get_geometry(s->blk, &nb_sectors);
01ce352e
JS		 2354 s->nb_sectors = nb_sectors;
2355
2356 /* Update the identify data buffer. */
2357 if (s->drive_kind == IDE_CFATA) {
2358 ide_cfata_identify_size(s);
2359 } else {
2360 /* IDE_CD uses a different set of callbacks entirely. */
2361 assert(s->drive_kind != IDE_CD);
2362 ide_identify_size(s);
2363 }
2364}
2365
0e49de52 2366static const BlockDevOps ide_cd_block_ops = {
145feb17 2367 .change_media_cb = ide_cd_change_cb,
2df0a3a3 2368 .eject_request_cb = ide_cd_eject_request_cb,
e4def80b 2369 .is_tray_open = ide_cd_is_tray_open,
f107639a 2370 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 2371};
2372
01ce352e
JS		 2373static const BlockDevOps ide_hd_block_ops = {
2374 .resize_cb = ide_resize_cb,
2375};
2376
4be74634 2377int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
95ebda85 2378 const char *version, const char *serial, const char *model,
ba801960
MA		 2379 uint64_t wwn,
2380 uint32_t cylinders, uint32_t heads, uint32_t secs,
2381 int chs_trans)
88804180 2382{
88804180
GH		 2383 uint64_t nb_sectors;
2384
4be74634 2385 s->blk = blk;
1f56e32a
MA		 2386 s->drive_kind = kind;
2387
4be74634 2388 blk_get_geometry(blk, &nb_sectors);
870111c8
MA		 2389 s->cylinders = cylinders;
2390 s->heads = heads;
2391 s->sectors = secs;
ba801960 2392 s->chs_trans = chs_trans;
870111c8 2393 s->nb_sectors = nb_sectors;
95ebda85 2394 s->wwn = wwn;
870111c8
MA		 2395 /* The SMART values should be preserved across power cycles
2396 but they aren't. */
2397 s->smart_enabled = 1;
2398 s->smart_autosave = 1;
2399 s->smart_errors = 0;
2400 s->smart_selftest_count = 0;
1f56e32a 2401 if (kind == IDE_CD) {
4be74634
MA		 2402 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2403 blk_set_guest_block_size(blk, 2048);
7aa9c811 2404 } else {
4be74634 2405 if (!blk_is_inserted(s->blk)) {
98f28ad7
MA		 2406 error_report("Device needs media, but drive is empty");
2407 return -1;
2408 }
4be74634 2409 if (blk_is_read_only(blk)) {
7aa9c811
MA		 2410 error_report("Can't use a read-only drive");
2411 return -1;
2412 }
4be74634 2413 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
88804180 2414 }
f8b6cc00 2415 if (serial) {
aa2c91bd 2416 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
6ced55a5 2417 } else {
88804180
GH		 2418 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2419 "QM%05d", s->drive_serial);
870111c8 2420 }
27e0c9a1
FB		 2421 if (model) {
2422 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2423 } else {
2424 switch (kind) {
2425 case IDE_CD:
2426 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2427 break;
2428 case IDE_CFATA:
2429 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2430 break;
2431 default:
2432 strcpy(s->drive_model_str, "QEMU HARDDISK");
2433 break;
2434 }
2435 }
2436
47c06340
GH		 2437 if (version) {
2438 pstrcpy(s->version, sizeof(s->version), version);
2439 } else {
35c2c8dc 2440 pstrcpy(s->version, sizeof(s->version), qemu_hw_version());
47c06340 2441 }
40a6238a 2442
88804180 2443 ide_reset(s);
4be74634 2444 blk_iostatus_enable(blk);
c4d74df7 2445 return 0;
88804180
GH		 2446}
2447
57234ee4 2448static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 2449{
2450 static int drive_serial = 1;
2451 IDEState *s = &bus->ifs[unit];
2452
2453 s->bus = bus;
2454 s->unit = unit;
2455 s->drive_serial = drive_serial++;
1b2adf28 2456 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 2457 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 2458 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2459 memset(s->io_buffer, 0, s->io_buffer_total_len);
2460
4be74634 2461 s->smart_selftest_data = blk_blockalign(s->blk, 512);
c925400b
KW		 2462 memset(s->smart_selftest_data, 0, 512);
2463
bc72ad67 2464 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
d459da0e 2465 ide_sector_write_timer_cb, s);
57234ee4
MA		 2466}
2467
40a6238a
AG		 2468static int ide_nop_int(IDEDMA *dma, int x)
2469{
2470 return 0;
2471}
2472
9898586d
PB		 2473static void ide_nop(IDEDMA *dma)
2474{
2475}
2476
a718978e 2477static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
3251bdcf
JS		 2478{
2479 return 0;
2480}
2481
40a6238a 2482static const IDEDMAOps ide_dma_nop_ops = {
3251bdcf 2483 .prepare_buf = ide_nop_int32,
9898586d 2484 .restart_dma = ide_nop,
40a6238a 2485 .rw_buf = ide_nop_int,
40a6238a
AG		 2486};
2487
9898586d
PB		 2488static void ide_restart_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
2489{
a96cb236 2490 s->unit = s->bus->retry_unit;
dc5d0af4
PB		 2491 ide_set_sector(s, s->bus->retry_sector_num);
2492 s->nsector = s->bus->retry_nsector;
9898586d 2493 s->bus->dma->ops->restart_dma(s->bus->dma);
9898586d
PB		 2494 s->io_buffer_size = 0;
2495 s->dma_cmd = dma_cmd;
2496 ide_start_dma(s, ide_dma_cb);
2497}
2498
2499static void ide_restart_bh(void *opaque)
2500{
2501 IDEBus *bus = opaque;
2502 IDEState *s;
2503 bool is_read;
2504 int error_status;
2505
2506 qemu_bh_delete(bus->bh);
2507 bus->bh = NULL;
2508
2509 error_status = bus->error_status;
2510 if (bus->error_status == 0) {
2511 return;
2512 }
2513
2514 s = idebus_active_if(bus);
2515 is_read = (bus->error_status & IDE_RETRY_READ) != 0;
2516
2517 /* The error status must be cleared before resubmitting the request: The
2518 * request may fail again, and this case can only be distinguished if the
2519 * called function can set a new error status. */
2520 bus->error_status = 0;
2521
7c03a691
JS		 2522 /* The HBA has generically asked to be kicked on retry */
2523 if (error_status & IDE_RETRY_HBA) {
2524 if (s->bus->dma->ops->restart) {
2525 s->bus->dma->ops->restart(s->bus->dma);
2526 }
2527 }
2528
9898586d
PB		 2529 if (error_status & IDE_RETRY_DMA) {
2530 if (error_status & IDE_RETRY_TRIM) {
2531 ide_restart_dma(s, IDE_DMA_TRIM);
2532 } else {
2533 ide_restart_dma(s, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
2534 }
2535 } else if (error_status & IDE_RETRY_PIO) {
2536 if (is_read) {
2537 ide_sector_read(s);
2538 } else {
2539 ide_sector_write(s);
2540 }
2541 } else if (error_status & IDE_RETRY_FLUSH) {
2542 ide_flush_cache(s);
2543 } else {
2544 /*
2545 * We've not got any bits to tell us about ATAPI - but
2546 * we do have the end_transfer_func that tells us what
2547 * we're trying to do.
2548 */
2549 if (s->end_transfer_func == ide_atapi_cmd) {
2550 ide_atapi_dma_restart(s);
2551 }
2552 }
2553}
2554
2555static void ide_restart_cb(void *opaque, int running, RunState state)
2556{
2557 IDEBus *bus = opaque;
2558
2559 if (!running)
2560 return;
2561
2562 if (!bus->bh) {
2563 bus->bh = qemu_bh_new(ide_restart_bh, bus);
2564 qemu_bh_schedule(bus->bh);
2565 }
2566}
2567
f878c916
PB		 2568void ide_register_restart_cb(IDEBus *bus)
2569{
9898586d
PB		 2570 if (bus->dma->ops->restart_dma) {
2571 qemu_add_vm_change_state_handler(ide_restart_cb, bus);
2572 }
f878c916
PB		 2573}
2574
40a6238a
AG		 2575static IDEDMA ide_dma_nop = {
2576 .ops = &ide_dma_nop_ops,
2577 .aiocb = NULL,
2578};
2579
57234ee4
MA		 2580void ide_init2(IDEBus *bus, qemu_irq irq)
2581{
2582 int i;
2583
2584 for(i = 0; i < 2; i++) {
2585 ide_init1(bus, i);
2586 ide_reset(&bus->ifs[i]);
870111c8 2587 }
57234ee4 2588 bus->irq = irq;
40a6238a 2589 bus->dma = &ide_dma_nop;
d459da0e
MA		 2590}
2591
4a91d3b3
RH		 2592static const MemoryRegionPortio ide_portio_list[] = {
2593 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
e477317c
PB		 2594 { 0, 1, 2, .read = ide_data_readw, .write = ide_data_writew },
2595 { 0, 1, 4, .read = ide_data_readl, .write = ide_data_writel },
4a91d3b3
RH		 2596 PORTIO_END_OF_LIST(),
2597};
2598
2599static const MemoryRegionPortio ide_portio2_list[] = {
2600 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2601 PORTIO_END_OF_LIST(),
2602};
2603
2604void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
69b91039 2605{
4a91d3b3
RH		 2606 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2607 bridge has been setup properly to always register with ISA. */
2608 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2609
caed8802 2610 if (iobase2) {
4a91d3b3 2611 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
5391d806 2612 }
5391d806 2613}
69b91039 2614
37159f13 2615static bool is_identify_set(void *opaque, int version_id)
aa941b94 2616{
37159f13
JQ		 2617 IDEState *s = opaque;
2618
2619 return s->identify_set != 0;
2620}
2621
50641c5c
JQ		 2622static EndTransferFunc* transfer_end_table[] = {
2623 ide_sector_read,
2624 ide_sector_write,
2625 ide_transfer_stop,
2626 ide_atapi_cmd_reply_end,
2627 ide_atapi_cmd,
2628 ide_dummy_transfer_stop,
2629};
2630
2631static int transfer_end_table_idx(EndTransferFunc *fn)
2632{
2633 int i;
2634
2635 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2636 if (transfer_end_table[i] == fn)
2637 return i;
2638
2639 return -1;
2640}
2641
37159f13 2642static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2643{
37159f13
JQ		 2644 IDEState *s = opaque;
2645
6b896ab2 2646 if (s->blk && s->identify_set) {
4be74634 2647 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
7cdd481c 2648 }
37159f13 2649 return 0;
aa941b94
AZ		 2650}
2651
50641c5c
JQ		 2652static int ide_drive_pio_post_load(void *opaque, int version_id)
2653{
2654 IDEState *s = opaque;
2655
fb60105d 2656 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2657 return -EINVAL;
2658 }
2659 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2660 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2661 s->data_end = s->data_ptr + s->cur_io_buffer_len;
819fa276 2662 s->atapi_dma = s->feature & 1; /* as per cmd_packet */
50641c5c
JQ		 2663
2664 return 0;
2665}
2666
2667static void ide_drive_pio_pre_save(void *opaque)
2668{
2669 IDEState *s = opaque;
2670 int idx;
2671
2672 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2673 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2674
2675 idx = transfer_end_table_idx(s->end_transfer_func);
2676 if (idx == -1) {
2677 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2678 __func__);
2679 s->end_transfer_fn_idx = 2;
2680 } else {
2681 s->end_transfer_fn_idx = idx;
2682 }
2683}
2684
2685static bool ide_drive_pio_state_needed(void *opaque)
2686{
2687 IDEState *s = opaque;
2688
fdc650d7 2689 return ((s->status & DRQ_STAT) != 0)
fd648f10 2690 || (s->bus->error_status & IDE_RETRY_PIO);
50641c5c
JQ		 2691}
2692
db118fe7
MA		 2693static bool ide_tray_state_needed(void *opaque)
2694{
2695 IDEState *s = opaque;
2696
2697 return s->tray_open || s->tray_locked;
2698}
2699
996faf1a
AS		 2700static bool ide_atapi_gesn_needed(void *opaque)
2701{
2702 IDEState *s = opaque;
2703
2704 return s->events.new_media || s->events.eject_request;
2705}
2706
def93791
KW		 2707static bool ide_error_needed(void *opaque)
2708{
2709 IDEBus *bus = opaque;
2710
2711 return (bus->error_status != 0);
2712}
2713
996faf1a 2714/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2715static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2716 .name ="ide_drive/atapi/gesn_state",
2717 .version_id = 1,
2718 .minimum_version_id = 1,
5cd8cada 2719 .needed = ide_atapi_gesn_needed,
35d08458 2720 .fields = (VMStateField[]) {
996faf1a
AS		 2721 VMSTATE_BOOL(events.new_media, IDEState),
2722 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2723 VMSTATE_END_OF_LIST()
996faf1a
AS		 2724 }
2725};
2726
db118fe7
MA		 2727static const VMStateDescription vmstate_ide_tray_state = {
2728 .name = "ide_drive/tray_state",
2729 .version_id = 1,
2730 .minimum_version_id = 1,
5cd8cada 2731 .needed = ide_tray_state_needed,
db118fe7
MA		 2732 .fields = (VMStateField[]) {
2733 VMSTATE_BOOL(tray_open, IDEState),
2734 VMSTATE_BOOL(tray_locked, IDEState),
2735 VMSTATE_END_OF_LIST()
2736 }
2737};
2738
656fbeff 2739static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2740 .name = "ide_drive/pio_state",
2741 .version_id = 1,
2742 .minimum_version_id = 1,
50641c5c
JQ		 2743 .pre_save = ide_drive_pio_pre_save,
2744 .post_load = ide_drive_pio_post_load,
5cd8cada 2745 .needed = ide_drive_pio_state_needed,
35d08458 2746 .fields = (VMStateField[]) {
50641c5c
JQ		 2747 VMSTATE_INT32(req_nb_sectors, IDEState),
2748 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2749 vmstate_info_uint8, uint8_t),
2750 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2751 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2752 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2753 VMSTATE_INT32(elementary_transfer_size, IDEState),
2754 VMSTATE_INT32(packet_transfer_size, IDEState),
2755 VMSTATE_END_OF_LIST()
2756 }
2757};
2758
37159f13
JQ		 2759const VMStateDescription vmstate_ide_drive = {
2760 .name = "ide_drive",
3abb6260 2761 .version_id = 3,
37159f13 2762 .minimum_version_id = 0,
37159f13 2763 .post_load = ide_drive_post_load,
35d08458 2764 .fields = (VMStateField[]) {
37159f13
JQ		 2765 VMSTATE_INT32(mult_sectors, IDEState),
2766 VMSTATE_INT32(identify_set, IDEState),
2767 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2768 VMSTATE_UINT8(feature, IDEState),
2769 VMSTATE_UINT8(error, IDEState),
2770 VMSTATE_UINT32(nsector, IDEState),
2771 VMSTATE_UINT8(sector, IDEState),
2772 VMSTATE_UINT8(lcyl, IDEState),
2773 VMSTATE_UINT8(hcyl, IDEState),
2774 VMSTATE_UINT8(hob_feature, IDEState),
2775 VMSTATE_UINT8(hob_sector, IDEState),
2776 VMSTATE_UINT8(hob_nsector, IDEState),
2777 VMSTATE_UINT8(hob_lcyl, IDEState),
2778 VMSTATE_UINT8(hob_hcyl, IDEState),
2779 VMSTATE_UINT8(select, IDEState),
2780 VMSTATE_UINT8(status, IDEState),
2781 VMSTATE_UINT8(lba48, IDEState),
2782 VMSTATE_UINT8(sense_key, IDEState),
2783 VMSTATE_UINT8(asc, IDEState),
2784 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2785 VMSTATE_END_OF_LIST()
50641c5c 2786 },
5cd8cada
JQ		 2787 .subsections = (const VMStateDescription*[]) {
2788 &vmstate_ide_drive_pio_state,
2789 &vmstate_ide_tray_state,
2790 &vmstate_ide_atapi_gesn_state,
2791 NULL
37159f13
JQ		 2792 }
2793};
2794
656fbeff 2795static const VMStateDescription vmstate_ide_error_status = {
def93791 2796 .name ="ide_bus/error",
d12b9ff2 2797 .version_id = 2,
def93791 2798 .minimum_version_id = 1,
5cd8cada 2799 .needed = ide_error_needed,
35d08458 2800 .fields = (VMStateField[]) {
def93791 2801 VMSTATE_INT32(error_status, IDEBus),
d12b9ff2
PB		 2802 VMSTATE_INT64_V(retry_sector_num, IDEBus, 2),
2803 VMSTATE_UINT32_V(retry_nsector, IDEBus, 2),
2804 VMSTATE_UINT8_V(retry_unit, IDEBus, 2),
def93791
KW		 2805 VMSTATE_END_OF_LIST()
2806 }
2807};
2808
6521dc62
JQ		 2809const VMStateDescription vmstate_ide_bus = {
2810 .name = "ide_bus",
2811 .version_id = 1,
2812 .minimum_version_id = 1,
35d08458 2813 .fields = (VMStateField[]) {
6521dc62
JQ		 2814 VMSTATE_UINT8(cmd, IDEBus),
2815 VMSTATE_UINT8(unit, IDEBus),
2816 VMSTATE_END_OF_LIST()
def93791 2817 },
5cd8cada
JQ		 2818 .subsections = (const VMStateDescription*[]) {
2819 &vmstate_ide_error_status,
2820 NULL
6521dc62
JQ		 2821 }
2822};
75717903 2823
d8f94e1b 2824void ide_drive_get(DriveInfo **hd, int n)
75717903
IY		 2825{
2826 int i;
d8f94e1b
JS		 2827 int highest_bus = drive_get_max_bus(IF_IDE) + 1;
2828 int max_devs = drive_get_max_devs(IF_IDE);
2829 int n_buses = max_devs ? (n / max_devs) : n;
75717903 2830
d8f94e1b
JS		 2831 /*
2832 * Note: The number of actual buses available is not known.
2833 * We compute this based on the size of the DriveInfo* array, n.
2834 * If it is less than max_devs * <num_real_buses>,
2835 * We will stop looking for drives prematurely instead of overfilling
2836 * the array.
2837 */
2838
2839 if (highest_bus > n_buses) {
2840 error_report("Too many IDE buses defined (%d > %d)",
2841 highest_bus, n_buses);
75717903
IY		 2842 exit(1);
2843 }
2844
d8f94e1b
JS		 2845 for (i = 0; i < n; i++) {
2846 hd[i] = drive_get_by_index(IF_IDE, i);
75717903
IY		 2847 }
2848}
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