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5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
59f2a787 25#include <hw/hw.h>
0d09e41a 26#include <hw/i386/pc.h>
a2cb15b0 27#include <hw/pci/pci.h>
0d09e41a 28#include <hw/isa/isa.h>
1de7afc9
PB		 29#include "qemu/error-report.h"
30#include "qemu/timer.h"
9c17d615
PB		 31#include "sysemu/sysemu.h"
32#include "sysemu/dma.h"
0d09e41a 33#include "hw/block/block.h"
4be74634 34#include "sysemu/block-backend.h"
59f2a787
GH		 35
36#include <hw/ide/internal.h>
e8b54394 37
b93af93d
BW		 38/* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
e8b54394
BW		 56};
57
ce4b6522 58static int ide_handle_rw_error(IDEState *s, int error, int op);
40c4ed3f 59static void ide_dummy_transfer_stop(IDEState *s);
98087450 60
5391d806
FB		 61static void padstr(char *str, const char *src, int len)
62{
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69b34976 69 str[i^1] = v;
5391d806
FB		 70 }
71}
72
67b915a5
FB		 73static void put_le16(uint16_t *p, unsigned int v)
74{
0c4ad8dc 75 *p = cpu_to_le16(v);
67b915a5
FB		 76}
77
01ce352e
JS		 78static void ide_identify_size(IDEState *s)
79{
80 uint16_t *p = (uint16_t *)s->identify_data;
81 put_le16(p + 60, s->nb_sectors);
82 put_le16(p + 61, s->nb_sectors >> 16);
83 put_le16(p + 100, s->nb_sectors);
84 put_le16(p + 101, s->nb_sectors >> 16);
85 put_le16(p + 102, s->nb_sectors >> 32);
86 put_le16(p + 103, s->nb_sectors >> 48);
87}
88
5391d806
FB		 89static void ide_identify(IDEState *s)
90{
91 uint16_t *p;
92 unsigned int oldsize;
d353fb72 93 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 94
4bf6637d 95 p = (uint16_t *)s->identify_data;
94458802 96 if (s->identify_set) {
4bf6637d 97 goto fill_buffer;
94458802 98 }
4bf6637d 99 memset(p, 0, sizeof(s->identify_data));
94458802 100
67b915a5 101 put_le16(p + 0, 0x0040);
5fafdf24 102 put_le16(p + 1, s->cylinders);
67b915a5
FB		 103 put_le16(p + 3, s->heads);
104 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
105 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 106 put_le16(p + 6, s->sectors);
fa879c64 107 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 108 put_le16(p + 20, 3); /* XXX: retired, remove ? */
109 put_le16(p + 21, 512); /* cache size in sectors */
110 put_le16(p + 22, 4); /* ecc bytes */
47c06340 111 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 112 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
3b46e624 113#if MAX_MULT_SECTORS > 1
67b915a5 114 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 115#endif
67b915a5 116 put_le16(p + 48, 1); /* dword I/O */
94458802 117 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 118 put_le16(p + 51, 0x200); /* PIO transfer cycle */
119 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 120 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 121 put_le16(p + 54, s->cylinders);
122 put_le16(p + 55, s->heads);
123 put_le16(p + 56, s->sectors);
5391d806 124 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 125 put_le16(p + 57, oldsize);
126 put_le16(p + 58, oldsize >> 16);
5391d806 127 if (s->mult_sectors)
67b915a5 128 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 129 /* *(p + 60) := nb_sectors -- see ide_identify_size */
130 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
d1b5c20d 131 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 132 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 133 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 134 put_le16(p + 65, 120);
135 put_le16(p + 66, 120);
136 put_le16(p + 67, 120);
137 put_le16(p + 68, 120);
d353fb72
CH		 138 if (dev && dev->conf.discard_granularity) {
139 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
140 }
ccf0fd8b
RE		 141
142 if (s->ncq_queues) {
143 put_le16(p + 75, s->ncq_queues - 1);
144 /* NCQ supported */
145 put_le16(p + 76, (1 << 8));
146 }
147
94458802
FB		 148 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
149 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 150 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
151 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 152 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
153 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 154 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
155 if (s->wwn) {
156 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
157 } else {
158 put_le16(p + 84, (1 << 14) | 0);
159 }
e900a7b7 160 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
4be74634
MA		 161 if (blk_enable_write_cache(s->blk)) {
162 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
163 } else {
164 put_le16(p + 85, (1 << 14) | 1);
165 }
c2ff060f 166 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
2844bdd9 167 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 168 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
169 if (s->wwn) {
170 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
171 } else {
172 put_le16(p + 87, (1 << 14) | 0);
173 }
94458802
FB		 174 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
175 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
01ce352e
JS		 176 /* *(p + 100) := nb_sectors -- see ide_identify_size */
177 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
178 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
179 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
d353fb72 180
57dac7ef
MA		 181 if (dev && dev->conf.physical_block_size)
182 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
95ebda85
FB		 183 if (s->wwn) {
184 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
185 put_le16(p + 108, s->wwn >> 48);
186 put_le16(p + 109, s->wwn >> 32);
187 put_le16(p + 110, s->wwn >> 16);
188 put_le16(p + 111, s->wwn);
189 }
d353fb72
CH		 190 if (dev && dev->conf.discard_granularity) {
191 put_le16(p + 169, 1); /* TRIM support */
192 }
94458802 193
01ce352e 194 ide_identify_size(s);
94458802 195 s->identify_set = 1;
4bf6637d
JS		 196
197fill_buffer:
198 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 199}
200
201static void ide_atapi_identify(IDEState *s)
202{
203 uint16_t *p;
204
4bf6637d 205 p = (uint16_t *)s->identify_data;
94458802 206 if (s->identify_set) {
4bf6637d 207 goto fill_buffer;
94458802 208 }
4bf6637d 209 memset(p, 0, sizeof(s->identify_data));
94458802 210
5391d806 211 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 212 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 213 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 214 put_le16(p + 20, 3); /* buffer type */
215 put_le16(p + 21, 512); /* cache size in sectors */
216 put_le16(p + 22, 4); /* ecc bytes */
47c06340 217 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 218 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
67b915a5 219 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 220#ifdef USE_DMA_CDROM
221 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
222 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 223 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 224 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 225#else
67b915a5
FB		 226 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
227 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
228 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 229#endif
79d1d331 230 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 231 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
232 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
233 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
234 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 235
67b915a5
FB		 236 put_le16(p + 71, 30); /* in ns */
237 put_le16(p + 72, 30); /* in ns */
5391d806 238
1bdaa28d
AG		 239 if (s->ncq_queues) {
240 put_le16(p + 75, s->ncq_queues - 1);
241 /* NCQ supported */
242 put_le16(p + 76, (1 << 8));
243 }
244
67b915a5 245 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
c5fe97e3
JS		 246 if (s->wwn) {
247 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
248 put_le16(p + 87, (1 << 8)); /* WWN enabled */
249 }
250
8ccad811
FB		 251#ifdef USE_DMA_CDROM
252 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
253#endif
c5fe97e3
JS		 254
255 if (s->wwn) {
256 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
257 put_le16(p + 108, s->wwn >> 48);
258 put_le16(p + 109, s->wwn >> 32);
259 put_le16(p + 110, s->wwn >> 16);
260 put_le16(p + 111, s->wwn);
261 }
262
94458802 263 s->identify_set = 1;
4bf6637d
JS		 264
265fill_buffer:
266 memcpy(s->io_buffer, p, sizeof(s->identify_data));
5391d806
FB		 267}
268
01ce352e
JS		 269static void ide_cfata_identify_size(IDEState *s)
270{
271 uint16_t *p = (uint16_t *)s->identify_data;
272 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
273 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
274 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
275 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
276}
277
201a51fc
AZ		 278static void ide_cfata_identify(IDEState *s)
279{
280 uint16_t *p;
281 uint32_t cur_sec;
201a51fc 282
4bf6637d
JS		 283 p = (uint16_t *)s->identify_data;
284 if (s->identify_set) {
201a51fc 285 goto fill_buffer;
4bf6637d 286 }
201a51fc
AZ		 287 memset(p, 0, sizeof(s->identify_data));
288
289 cur_sec = s->cylinders * s->heads * s->sectors;
290
291 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
292 put_le16(p + 1, s->cylinders); /* Default cylinders */
293 put_le16(p + 3, s->heads); /* Default heads */
294 put_le16(p + 6, s->sectors); /* Default sectors per track */
01ce352e
JS		 295 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
296 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
fa879c64 297 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 298 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 299 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
27e0c9a1 300 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
201a51fc
AZ		 301#if MAX_MULT_SECTORS > 1
302 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
303#else
304 put_le16(p + 47, 0x0000);
305#endif
306 put_le16(p + 49, 0x0f00); /* Capabilities */
307 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
308 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
309 put_le16(p + 53, 0x0003); /* Translation params valid */
310 put_le16(p + 54, s->cylinders); /* Current cylinders */
311 put_le16(p + 55, s->heads); /* Current heads */
312 put_le16(p + 56, s->sectors); /* Current sectors */
313 put_le16(p + 57, cur_sec); /* Current capacity */
314 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
315 if (s->mult_sectors) /* Multiple sector setting */
316 put_le16(p + 59, 0x100 | s->mult_sectors);
01ce352e
JS		 317 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
318 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
201a51fc
AZ		 319 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
320 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
321 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
322 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
323 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
324 put_le16(p + 82, 0x400c); /* Command Set supported */
325 put_le16(p + 83, 0x7068); /* Command Set supported */
326 put_le16(p + 84, 0x4000); /* Features supported */
327 put_le16(p + 85, 0x000c); /* Command Set enabled */
328 put_le16(p + 86, 0x7044); /* Command Set enabled */
329 put_le16(p + 87, 0x4000); /* Features enabled */
330 put_le16(p + 91, 0x4060); /* Current APM level */
331 put_le16(p + 129, 0x0002); /* Current features option */
332 put_le16(p + 130, 0x0005); /* Reassigned sectors */
333 put_le16(p + 131, 0x0001); /* Initial power mode */
334 put_le16(p + 132, 0x0000); /* User signature */
335 put_le16(p + 160, 0x8100); /* Power requirement */
336 put_le16(p + 161, 0x8001); /* CF command set */
337
01ce352e 338 ide_cfata_identify_size(s);
201a51fc
AZ		 339 s->identify_set = 1;
340
341fill_buffer:
342 memcpy(s->io_buffer, p, sizeof(s->identify_data));
343}
344
5391d806
FB		 345static void ide_set_signature(IDEState *s)
346{
347 s->select &= 0xf0; /* clear head */
348 /* put signature */
349 s->nsector = 1;
350 s->sector = 1;
cd8722bb 351 if (s->drive_kind == IDE_CD) {
5391d806
FB		 352 s->lcyl = 0x14;
353 s->hcyl = 0xeb;
4be74634 354 } else if (s->blk) {
5391d806
FB		 355 s->lcyl = 0;
356 s->hcyl = 0;
357 } else {
358 s->lcyl = 0xff;
359 s->hcyl = 0xff;
360 }
361}
362
d353fb72 363typedef struct TrimAIOCB {
7c84b1b8 364 BlockAIOCB common;
a987ee1f 365 BlockBackend *blk;
d353fb72
CH		 366 QEMUBH *bh;
367 int ret;
501378c3 368 QEMUIOVector *qiov;
7c84b1b8 369 BlockAIOCB *aiocb;
501378c3 370 int i, j;
d353fb72
CH		 371} TrimAIOCB;
372
7c84b1b8 373static void trim_aio_cancel(BlockAIOCB *acb)
d353fb72
CH		 374{
375 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
376
e551c999 377 /* Exit the loop so ide_issue_trim_cb will not continue */
501378c3
PB		 378 iocb->j = iocb->qiov->niov - 1;
379 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
380
e551c999 381 iocb->ret = -ECANCELED;
501378c3
PB		 382
383 if (iocb->aiocb) {
4be74634 384 blk_aio_cancel_async(iocb->aiocb);
e551c999 385 iocb->aiocb = NULL;
501378c3 386 }
d353fb72
CH		 387}
388
d7331bed 389static const AIOCBInfo trim_aiocb_info = {
d353fb72 390 .aiocb_size = sizeof(TrimAIOCB),
e551c999 391 .cancel_async = trim_aio_cancel,
d353fb72
CH		 392};
393
394static void ide_trim_bh_cb(void *opaque)
395{
396 TrimAIOCB *iocb = opaque;
397
398 iocb->common.cb(iocb->common.opaque, iocb->ret);
399
400 qemu_bh_delete(iocb->bh);
401 iocb->bh = NULL;
8007429a 402 qemu_aio_unref(iocb);
d353fb72
CH		 403}
404
501378c3
PB		 405static void ide_issue_trim_cb(void *opaque, int ret)
406{
407 TrimAIOCB *iocb = opaque;
408 if (ret >= 0) {
409 while (iocb->j < iocb->qiov->niov) {
410 int j = iocb->j;
411 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
412 int i = iocb->i;
413 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
414
415 /* 6-byte LBA + 2-byte range per entry */
416 uint64_t entry = le64_to_cpu(buffer[i]);
417 uint64_t sector = entry & 0x0000ffffffffffffULL;
418 uint16_t count = entry >> 48;
419
420 if (count == 0) {
421 continue;
422 }
423
424 /* Got an entry! Submit and exit. */
a987ee1f
MA		 425 iocb->aiocb = blk_aio_discard(iocb->blk, sector, count,
426 ide_issue_trim_cb, opaque);
501378c3
PB		 427 return;
428 }
429
430 iocb->j++;
431 iocb->i = -1;
432 }
433 } else {
434 iocb->ret = ret;
435 }
436
437 iocb->aiocb = NULL;
438 if (iocb->bh) {
439 qemu_bh_schedule(iocb->bh);
440 }
441}
442
4be74634 443BlockAIOCB *ide_issue_trim(BlockBackend *blk,
d353fb72 444 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
097310b5 445 BlockCompletionFunc *cb, void *opaque)
d353fb72
CH		 446{
447 TrimAIOCB *iocb;
d353fb72 448
4be74634 449 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, opaque);
a987ee1f 450 iocb->blk = blk;
d353fb72
CH		 451 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
452 iocb->ret = 0;
501378c3
PB		 453 iocb->qiov = qiov;
454 iocb->i = -1;
455 iocb->j = 0;
456 ide_issue_trim_cb(iocb, 0);
d353fb72
CH		 457 return &iocb->common;
458}
459
5391d806
FB		 460static inline void ide_abort_command(IDEState *s)
461{
08ee9e33 462 ide_transfer_stop(s);
5391d806
FB		 463 s->status = READY_STAT | ERR_STAT;
464 s->error = ABRT_ERR;
465}
466
5391d806 467/* prepare data transfer and tell what to do after */
33231e0e
KW		 468void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
469 EndTransferFunc *end_transfer_func)
5391d806
FB		 470{
471 s->end_transfer_func = end_transfer_func;
472 s->data_ptr = buf;
473 s->data_end = buf + size;
40a6238a 474 if (!(s->status & ERR_STAT)) {
7603d156 475 s->status |= DRQ_STAT;
40a6238a 476 }
44635123
PB		 477 if (s->bus->dma->ops->start_transfer) {
478 s->bus->dma->ops->start_transfer(s->bus->dma);
479 }
5391d806
FB		 480}
481
c7e73adb
PB		 482static void ide_cmd_done(IDEState *s)
483{
484 if (s->bus->dma->ops->cmd_done) {
485 s->bus->dma->ops->cmd_done(s->bus->dma);
486 }
487}
488
33231e0e 489void ide_transfer_stop(IDEState *s)
5391d806
FB		 490{
491 s->end_transfer_func = ide_transfer_stop;
492 s->data_ptr = s->io_buffer;
493 s->data_end = s->io_buffer;
494 s->status &= ~DRQ_STAT;
c7e73adb 495 ide_cmd_done(s);
5391d806
FB		 496}
497
356721ae 498int64_t ide_get_sector(IDEState *s)
5391d806
FB		 499{
500 int64_t sector_num;
501 if (s->select & 0x40) {
502 /* lba */
c2ff060f
FB		 503 if (!s->lba48) {
504 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
505 (s->lcyl << 8) | s->sector;
506 } else {
507 sector_num = ((int64_t)s->hob_hcyl << 40) |
508 ((int64_t) s->hob_lcyl << 32) |
509 ((int64_t) s->hob_sector << 24) |
510 ((int64_t) s->hcyl << 16) |
511 ((int64_t) s->lcyl << 8) | s->sector;
512 }
5391d806
FB		 513 } else {
514 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 515 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 516 }
517 return sector_num;
518}
519
356721ae 520void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 521{
522 unsigned int cyl, r;
523 if (s->select & 0x40) {
c2ff060f
FB		 524 if (!s->lba48) {
525 s->select = (s->select & 0xf0) | (sector_num >> 24);
526 s->hcyl = (sector_num >> 16);
527 s->lcyl = (sector_num >> 8);
528 s->sector = (sector_num);
529 } else {
530 s->sector = sector_num;
531 s->lcyl = sector_num >> 8;
532 s->hcyl = sector_num >> 16;
533 s->hob_sector = sector_num >> 24;
534 s->hob_lcyl = sector_num >> 32;
535 s->hob_hcyl = sector_num >> 40;
536 }
5391d806
FB		 537 } else {
538 cyl = sector_num / (s->heads * s->sectors);
539 r = sector_num % (s->heads * s->sectors);
540 s->hcyl = cyl >> 8;
541 s->lcyl = cyl;
1b8eb456 542 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 543 s->sector = (r % s->sectors) + 1;
544 }
545}
546
e162cfb0
AZ		 547static void ide_rw_error(IDEState *s) {
548 ide_abort_command(s);
9cdd03a7 549 ide_set_irq(s->bus);
e162cfb0
AZ		 550}
551
58ac3211
MA		 552static bool ide_sect_range_ok(IDEState *s,
553 uint64_t sector, uint64_t nb_sectors)
554{
555 uint64_t total_sectors;
556
4be74634 557 blk_get_geometry(s->blk, &total_sectors);
58ac3211
MA		 558 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
559 return false;
560 }
561 return true;
562}
563
bef0fd59
SH		 564static void ide_sector_read_cb(void *opaque, int ret)
565{
566 IDEState *s = opaque;
567 int n;
568
569 s->pio_aiocb = NULL;
570 s->status &= ~BUSY_STAT;
571
0d910cfe
FZ		 572 if (ret == -ECANCELED) {
573 return;
574 }
4be74634 575 block_acct_done(blk_get_stats(s->blk), &s->acct);
bef0fd59 576 if (ret != 0) {
fd648f10
PB		 577 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
578 IDE_RETRY_READ)) {
bef0fd59
SH		 579 return;
580 }
581 }
582
583 n = s->nsector;
584 if (n > s->req_nb_sectors) {
585 n = s->req_nb_sectors;
586 }
587
588 /* Allow the guest to read the io_buffer */
589 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
590
591 ide_set_irq(s->bus);
592
593 ide_set_sector(s, ide_get_sector(s) + n);
594 s->nsector -= n;
36334faf 595 s->io_buffer_offset += 512 * n;
bef0fd59
SH		 596}
597
40a6238a 598void ide_sector_read(IDEState *s)
5391d806
FB		 599{
600 int64_t sector_num;
bef0fd59 601 int n;
5391d806
FB		 602
603 s->status = READY_STAT | SEEK_STAT;
a136e5a8 604 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 605 sector_num = ide_get_sector(s);
606 n = s->nsector;
bef0fd59 607
5391d806 608 if (n == 0) {
5391d806 609 ide_transfer_stop(s);
bef0fd59
SH		 610 return;
611 }
612
613 s->status |= BUSY_STAT;
614
615 if (n > s->req_nb_sectors) {
616 n = s->req_nb_sectors;
617 }
618
5391d806 619#if defined(DEBUG_IDE)
bef0fd59 620 printf("sector=%" PRId64 "\n", sector_num);
5391d806 621#endif
a597e79c 622
58ac3211
MA		 623 if (!ide_sect_range_ok(s, sector_num, n)) {
624 ide_rw_error(s);
625 return;
626 }
627
bef0fd59
SH		 628 s->iov.iov_base = s->io_buffer;
629 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
630 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
631
4be74634 632 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 633 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
4be74634
MA		 634 s->pio_aiocb = blk_aio_readv(s->blk, sector_num, &s->qiov, n,
635 ide_sector_read_cb, s);
5391d806
FB		 636}
637
659142ec 638static void dma_buf_commit(IDEState *s, uint32_t tx_bytes)
7aea4412 639{
659142ec
JS		 640 if (s->bus->dma->ops->commit_buf) {
641 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes);
642 }
1fb8648d 643 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 644}
645
0e7ce54c 646void ide_set_inactive(IDEState *s, bool more)
8337606d 647{
40a6238a 648 s->bus->dma->aiocb = NULL;
829b933b 649 if (s->bus->dma->ops->set_inactive) {
0e7ce54c 650 s->bus->dma->ops->set_inactive(s->bus->dma, more);
829b933b 651 }
c7e73adb 652 ide_cmd_done(s);
8337606d
KW		 653}
654
356721ae 655void ide_dma_error(IDEState *s)
e162cfb0 656{
659142ec 657 dma_buf_commit(s, 0);
08ee9e33 658 ide_abort_command(s);
0e7ce54c 659 ide_set_inactive(s, false);
9cdd03a7 660 ide_set_irq(s->bus);
e162cfb0
AZ		 661}
662
ce4b6522 663static int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 664{
fd648f10 665 bool is_read = (op & IDE_RETRY_READ) != 0;
4be74634 666 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
428c5705 667
a589569f 668 if (action == BLOCK_ERROR_ACTION_STOP) {
40a6238a 669 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
def93791 670 s->bus->error_status = op;
a589569f 671 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
fd648f10 672 if (op & IDE_RETRY_DMA) {
428c5705 673 ide_dma_error(s);
7aea4412 674 } else {
428c5705 675 ide_rw_error(s);
7aea4412 676 }
428c5705 677 }
4be74634 678 blk_error_action(s->blk, action, is_read, error);
a589569f 679 return action != BLOCK_ERROR_ACTION_IGNORE;
428c5705
AL		 680}
681
cd369c46 682void ide_dma_cb(void *opaque, int ret)
98087450 683{
40a6238a 684 IDEState *s = opaque;
8ccad811
FB		 685 int n;
686 int64_t sector_num;
038268e2 687 bool stay_active = false;
8ccad811 688
0d910cfe
FZ		 689 if (ret == -ECANCELED) {
690 return;
691 }
e162cfb0 692 if (ret < 0) {
fd648f10 693 int op = IDE_RETRY_DMA;
cd369c46 694
4e1e0051 695 if (s->dma_cmd == IDE_DMA_READ)
fd648f10 696 op |= IDE_RETRY_READ;
d353fb72 697 else if (s->dma_cmd == IDE_DMA_TRIM)
fd648f10 698 op |= IDE_RETRY_TRIM;
d353fb72 699
cd369c46 700 if (ide_handle_rw_error(s, -ret, op)) {
ce4b6522
KW		 701 return;
702 }
e162cfb0
AZ		 703 }
704
8ccad811 705 n = s->io_buffer_size >> 9;
038268e2
KW		 706 if (n > s->nsector) {
707 /* The PRDs were longer than needed for this request. Shorten them so
708 * we don't get a negative remainder. The Active bit must remain set
709 * after the request completes. */
710 n = s->nsector;
711 stay_active = true;
712 }
713
8ccad811
FB		 714 sector_num = ide_get_sector(s);
715 if (n > 0) {
659142ec
JS		 716 assert(s->io_buffer_size == s->sg.size);
717 dma_buf_commit(s, s->io_buffer_size);
8ccad811
FB		 718 sector_num += n;
719 ide_set_sector(s, sector_num);
720 s->nsector -= n;
8ccad811
FB		 721 }
722
723 /* end of transfer ? */
724 if (s->nsector == 0) {
98087450 725 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 726 ide_set_irq(s->bus);
cd369c46 727 goto eot;
98087450 728 }
8ccad811
FB		 729
730 /* launch next transfer */
731 n = s->nsector;
596bb44d 732 s->io_buffer_index = 0;
8ccad811 733 s->io_buffer_size = n * 512;
4e1e0051 734 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
69c38b8f
KW		 735 /* The PRDs were too short. Reset the Active bit, but don't raise an
736 * interrupt. */
72bcca73 737 s->status = READY_STAT | SEEK_STAT;
7aea4412 738 goto eot;
69c38b8f 739 }
cd369c46 740
8ccad811 741#ifdef DEBUG_AIO
4e1e0051
CH		 742 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
743 sector_num, n, s->dma_cmd);
8ccad811 744#endif
cd369c46 745
d66168ed
MT		 746 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
747 !ide_sect_range_ok(s, sector_num, n)) {
58ac3211
MA		 748 ide_dma_error(s);
749 return;
750 }
751
4e1e0051
CH		 752 switch (s->dma_cmd) {
753 case IDE_DMA_READ:
4be74634
MA		 754 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, sector_num,
755 ide_dma_cb, s);
4e1e0051
CH		 756 break;
757 case IDE_DMA_WRITE:
4be74634
MA		 758 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, sector_num,
759 ide_dma_cb, s);
4e1e0051 760 break;
d353fb72 761 case IDE_DMA_TRIM:
4be74634
MA		 762 s->bus->dma->aiocb = dma_blk_io(s->blk, &s->sg, sector_num,
763 ide_issue_trim, ide_dma_cb, s,
764 DMA_DIRECTION_TO_DEVICE);
d353fb72 765 break;
cd369c46 766 }
cd369c46
CH		 767 return;
768
769eot:
a597e79c 770 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
4be74634 771 block_acct_done(blk_get_stats(s->blk), &s->acct);
a597e79c 772 }
0e7ce54c 773 ide_set_inactive(s, stay_active);
98087450
FB		 774}
775
4e1e0051 776static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 777{
8ccad811 778 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
98087450
FB		 779 s->io_buffer_index = 0;
780 s->io_buffer_size = 0;
4e1e0051 781 s->dma_cmd = dma_cmd;
a597e79c
CH		 782
783 switch (dma_cmd) {
784 case IDE_DMA_READ:
4be74634 785 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 786 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
a597e79c
CH		 787 break;
788 case IDE_DMA_WRITE:
4be74634 789 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 790 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
a597e79c
CH		 791 break;
792 default:
793 break;
794 }
795
4855b576
PB		 796 ide_start_dma(s, ide_dma_cb);
797}
798
097310b5 799void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
4855b576
PB		 800{
801 if (s->bus->dma->ops->start_dma) {
802 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
803 }
98087450
FB		 804}
805
a09db21f
FB		 806static void ide_sector_write_timer_cb(void *opaque)
807{
808 IDEState *s = opaque;
9cdd03a7 809 ide_set_irq(s->bus);
a09db21f
FB		 810}
811
e82dabd8 812static void ide_sector_write_cb(void *opaque, int ret)
5391d806 813{
e82dabd8
SH		 814 IDEState *s = opaque;
815 int n;
a597e79c 816
0d910cfe
FZ		 817 if (ret == -ECANCELED) {
818 return;
819 }
4be74634 820 block_acct_done(blk_get_stats(s->blk), &s->acct);
428c5705 821
e82dabd8
SH		 822 s->pio_aiocb = NULL;
823 s->status &= ~BUSY_STAT;
824
e162cfb0 825 if (ret != 0) {
fd648f10 826 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
428c5705 827 return;
e82dabd8 828 }
e162cfb0
AZ		 829 }
830
e82dabd8
SH		 831 n = s->nsector;
832 if (n > s->req_nb_sectors) {
833 n = s->req_nb_sectors;
834 }
5391d806 835 s->nsector -= n;
36334faf
JS		 836 s->io_buffer_offset += 512 * n;
837
5391d806 838 if (s->nsector == 0) {
292eef5a 839 /* no more sectors to write */
5391d806
FB		 840 ide_transfer_stop(s);
841 } else {
e82dabd8
SH		 842 int n1 = s->nsector;
843 if (n1 > s->req_nb_sectors) {
5391d806 844 n1 = s->req_nb_sectors;
e82dabd8
SH		 845 }
846 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
847 ide_sector_write);
5391d806 848 }
e82dabd8 849 ide_set_sector(s, ide_get_sector(s) + n);
3b46e624 850
31c2a146
TS		 851 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
852 /* It seems there is a bug in the Windows 2000 installer HDD
853 IDE driver which fills the disk with empty logs when the
854 IDE write IRQ comes too early. This hack tries to correct
855 that at the expense of slower write performances. Use this
856 option _only_ to install Windows 2000. You must disable it
857 for normal use. */
bc72ad67
AB		 858 timer_mod(s->sector_write_timer,
859 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000));
f7736b91 860 } else {
9cdd03a7 861 ide_set_irq(s->bus);
31c2a146 862 }
5391d806
FB		 863}
864
e82dabd8
SH		 865void ide_sector_write(IDEState *s)
866{
867 int64_t sector_num;
868 int n;
869
870 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
871 sector_num = ide_get_sector(s);
872#if defined(DEBUG_IDE)
873 printf("sector=%" PRId64 "\n", sector_num);
874#endif
875 n = s->nsector;
876 if (n > s->req_nb_sectors) {
877 n = s->req_nb_sectors;
878 }
879
58ac3211
MA		 880 if (!ide_sect_range_ok(s, sector_num, n)) {
881 ide_rw_error(s);
882 return;
883 }
884
e82dabd8
SH		 885 s->iov.iov_base = s->io_buffer;
886 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
887 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
888
4be74634 889 block_acct_start(blk_get_stats(s->blk), &s->acct,
5366d0c8 890 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
4be74634
MA		 891 s->pio_aiocb = blk_aio_writev(s->blk, sector_num, &s->qiov, n,
892 ide_sector_write_cb, s);
e82dabd8
SH		 893}
894
b0484ae4
CH		 895static void ide_flush_cb(void *opaque, int ret)
896{
897 IDEState *s = opaque;
898
69f72a22
PB		 899 s->pio_aiocb = NULL;
900
0d910cfe
FZ		 901 if (ret == -ECANCELED) {
902 return;
903 }
e2bcadad
KW		 904 if (ret < 0) {
905 /* XXX: What sector number to set here? */
fd648f10 906 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
e2bcadad
KW		 907 return;
908 }
909 }
b0484ae4 910
4be74634
MA		 911 if (s->blk) {
912 block_acct_done(blk_get_stats(s->blk), &s->acct);
f7f3ff1d 913 }
b0484ae4 914 s->status = READY_STAT | SEEK_STAT;
c7e73adb 915 ide_cmd_done(s);
b0484ae4
CH		 916 ide_set_irq(s->bus);
917}
918
40a6238a 919void ide_flush_cache(IDEState *s)
6bcb1a79 920{
4be74634 921 if (s->blk == NULL) {
6bcb1a79 922 ide_flush_cb(s, 0);
b2df7531
KW		 923 return;
924 }
925
f68ec837 926 s->status |= BUSY_STAT;
4be74634
MA		 927 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
928 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
6bcb1a79
KW		 929}
930
201a51fc
AZ		 931static void ide_cfata_metadata_inquiry(IDEState *s)
932{
933 uint16_t *p;
934 uint32_t spd;
935
936 p = (uint16_t *) s->io_buffer;
937 memset(p, 0, 0x200);
938 spd = ((s->mdata_size - 1) >> 9) + 1;
939
940 put_le16(p + 0, 0x0001); /* Data format revision */
941 put_le16(p + 1, 0x0000); /* Media property: silicon */
942 put_le16(p + 2, s->media_changed); /* Media status */
943 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
944 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
945 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
946 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
947}
948
949static void ide_cfata_metadata_read(IDEState *s)
950{
951 uint16_t *p;
952
953 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
954 s->status = ERR_STAT;
955 s->error = ABRT_ERR;
956 return;
957 }
958
959 p = (uint16_t *) s->io_buffer;
960 memset(p, 0, 0x200);
961
962 put_le16(p + 0, s->media_changed); /* Media status */
963 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
964 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
965 s->nsector << 9), 0x200 - 2));
966}
967
968static void ide_cfata_metadata_write(IDEState *s)
969{
970 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
971 s->status = ERR_STAT;
972 s->error = ABRT_ERR;
973 return;
974 }
975
976 s->media_changed = 0;
977
978 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
979 s->io_buffer + 2,
980 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
981 s->nsector << 9), 0x200 - 2));
982}
983
bd491d6a 984/* called when the inserted state of the media has changed */
7d4b4ba5 985static void ide_cd_change_cb(void *opaque, bool load)
bd491d6a
TS		 986{
987 IDEState *s = opaque;
96b8f136 988 uint64_t nb_sectors;
bd491d6a 989
25ad22bc 990 s->tray_open = !load;
4be74634 991 blk_get_geometry(s->blk, &nb_sectors);
bd491d6a 992 s->nb_sectors = nb_sectors;
9118e7f0 993
4b9b7092
AS		 994 /*
995 * First indicate to the guest that a CD has been removed. That's
996 * done on the next command the guest sends us.
997 *
67cc61e4 998 * Then we set UNIT_ATTENTION, by which the guest will
4b9b7092
AS		 999 * detect a new CD in the drive. See ide_atapi_cmd() for details.
1000 */
93c8cfd9 1001 s->cdrom_changed = 1;
996faf1a 1002 s->events.new_media = true;
2df0a3a3
PB		 1003 s->events.eject_request = false;
1004 ide_set_irq(s->bus);
1005}
1006
1007static void ide_cd_eject_request_cb(void *opaque, bool force)
1008{
1009 IDEState *s = opaque;
1010
1011 s->events.eject_request = true;
1012 if (force) {
1013 s->tray_locked = false;
1014 }
9cdd03a7 1015 ide_set_irq(s->bus);
bd491d6a
TS		 1016}
1017
c2ff060f
FB		 1018static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1019{
1020 s->lba48 = lba48;
1021
1022 /* handle the 'magic' 0 nsector count conversion here. to avoid
1023 * fiddling with the rest of the read logic, we just store the
1024 * full sector count in ->nsector and ignore ->hob_nsector from now
1025 */
1026 if (!s->lba48) {
1027 if (!s->nsector)
1028 s->nsector = 256;
1029 } else {
1030 if (!s->nsector && !s->hob_nsector)
1031 s->nsector = 65536;
1032 else {
1033 int lo = s->nsector;
1034 int hi = s->hob_nsector;
1035
1036 s->nsector = (hi << 8) | lo;
1037 }
1038 }
1039}
1040
bcbdc4d3 1041static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 1042{
1043 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 1044 bus->ifs[0].select &= ~(1 << 7);
1045 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 1046}
1047
356721ae 1048void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 1049{
bcbdc4d3 1050 IDEBus *bus = opaque;
5391d806
FB		 1051
1052#ifdef DEBUG_IDE
1053 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1054#endif
c2ff060f 1055
5391d806 1056 addr &= 7;
fcdd25ab
AL		 1057
1058 /* ignore writes to command block while busy with previous command */
bcbdc4d3 1059 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
fcdd25ab
AL		 1060 return;
1061
5391d806
FB		 1062 switch(addr) {
1063 case 0:
1064 break;
1065 case 1:
bcbdc4d3 1066 ide_clear_hob(bus);
c45c3d00 1067 /* NOTE: data is written to the two drives */
bcbdc4d3
GH		 1068 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1069 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1070 bus->ifs[0].feature = val;
1071 bus->ifs[1].feature = val;
5391d806
FB		 1072 break;
1073 case 2:
bcbdc4d3
GH		 1074 ide_clear_hob(bus);
1075 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1076 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1077 bus->ifs[0].nsector = val;
1078 bus->ifs[1].nsector = val;
5391d806
FB		 1079 break;
1080 case 3:
bcbdc4d3
GH		 1081 ide_clear_hob(bus);
1082 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1083 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1084 bus->ifs[0].sector = val;
1085 bus->ifs[1].sector = val;
5391d806
FB		 1086 break;
1087 case 4:
bcbdc4d3
GH		 1088 ide_clear_hob(bus);
1089 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1090 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1091 bus->ifs[0].lcyl = val;
1092 bus->ifs[1].lcyl = val;
5391d806
FB		 1093 break;
1094 case 5:
bcbdc4d3
GH		 1095 ide_clear_hob(bus);
1096 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1097 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1098 bus->ifs[0].hcyl = val;
1099 bus->ifs[1].hcyl = val;
5391d806
FB		 1100 break;
1101 case 6:
c2ff060f 1102 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 1103 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1104 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 1105 /* select drive */
bcbdc4d3 1106 bus->unit = (val >> 4) & 1;
5391d806
FB		 1107 break;
1108 default:
1109 case 7:
1110 /* command */
7cff87ff
AG		 1111 ide_exec_cmd(bus, val);
1112 break;
1113 }
1114}
1115
b300337e
KW		 1116static bool cmd_nop(IDEState *s, uint8_t cmd)
1117{
1118 return true;
1119}
1120
4286434c
KW		 1121static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1122{
1123 switch (s->feature) {
1124 case DSM_TRIM:
4be74634 1125 if (s->blk) {
4286434c
KW		 1126 ide_sector_start_dma(s, IDE_DMA_TRIM);
1127 return false;
1128 }
1129 break;
1130 }
1131
1132 ide_abort_command(s);
1133 return true;
1134}
1135
1c66869a
KW		 1136static bool cmd_identify(IDEState *s, uint8_t cmd)
1137{
4be74634 1138 if (s->blk && s->drive_kind != IDE_CD) {
1c66869a
KW		 1139 if (s->drive_kind != IDE_CFATA) {
1140 ide_identify(s);
1141 } else {
1142 ide_cfata_identify(s);
1143 }
1144 s->status = READY_STAT | SEEK_STAT;
1145 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1146 ide_set_irq(s->bus);
1147 return false;
1148 } else {
1149 if (s->drive_kind == IDE_CD) {
1150 ide_set_signature(s);
1151 }
1152 ide_abort_command(s);
1153 }
1154
1155 return true;
1156}
1157
413860cf
KW		 1158static bool cmd_verify(IDEState *s, uint8_t cmd)
1159{
1160 bool lba48 = (cmd == WIN_VERIFY_EXT);
1161
1162 /* do sector number check ? */
1163 ide_cmd_lba48_transform(s, lba48);
1164
1165 return true;
1166}
1167
adf3a2c4
KW		 1168static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1169{
1170 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1171 /* Disable Read and Write Multiple */
1172 s->mult_sectors = 0;
1173 } else if ((s->nsector & 0xff) != 0 &&
1174 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1175 (s->nsector & (s->nsector - 1)) != 0)) {
1176 ide_abort_command(s);
1177 } else {
1178 s->mult_sectors = s->nsector & 0xff;
1179 }
1180
1181 return true;
1182}
1183
1184static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1185{
1186 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1187
4be74634 1188 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1189 ide_abort_command(s);
1190 return true;
1191 }
1192
1193 ide_cmd_lba48_transform(s, lba48);
1194 s->req_nb_sectors = s->mult_sectors;
1195 ide_sector_read(s);
1196 return false;
1197}
1198
1199static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1200{
1201 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1202 int n;
1203
4be74634 1204 if (!s->blk || !s->mult_sectors) {
adf3a2c4
KW		 1205 ide_abort_command(s);
1206 return true;
1207 }
1208
1209 ide_cmd_lba48_transform(s, lba48);
1210
1211 s->req_nb_sectors = s->mult_sectors;
1212 n = MIN(s->nsector, s->req_nb_sectors);
1213
1214 s->status = SEEK_STAT | READY_STAT;
1215 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1216
1217 s->media_changed = 1;
1218
1219 return false;
1220}
1221
0e6498ed
KW		 1222static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1223{
1224 bool lba48 = (cmd == WIN_READ_EXT);
1225
1226 if (s->drive_kind == IDE_CD) {
1227 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1228 ide_abort_command(s);
1229 return true;
1230 }
1231
4be74634 1232 if (!s->blk) {
0e6498ed
KW		 1233 ide_abort_command(s);
1234 return true;
1235 }
1236
1237 ide_cmd_lba48_transform(s, lba48);
1238 s->req_nb_sectors = 1;
1239 ide_sector_read(s);
1240
1241 return false;
1242}
1243
1244static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1245{
1246 bool lba48 = (cmd == WIN_WRITE_EXT);
1247
4be74634 1248 if (!s->blk) {
0e6498ed
KW		 1249 ide_abort_command(s);
1250 return true;
1251 }
1252
1253 ide_cmd_lba48_transform(s, lba48);
1254
1255 s->req_nb_sectors = 1;
1256 s->status = SEEK_STAT | READY_STAT;
1257 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1258
1259 s->media_changed = 1;
1260
1261 return false;
1262}
1263
92a6a6f6
KW		 1264static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1265{
1266 bool lba48 = (cmd == WIN_READDMA_EXT);
1267
4be74634 1268 if (!s->blk) {
92a6a6f6
KW		 1269 ide_abort_command(s);
1270 return true;
1271 }
1272
1273 ide_cmd_lba48_transform(s, lba48);
1274 ide_sector_start_dma(s, IDE_DMA_READ);
1275
1276 return false;
1277}
1278
1279static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1280{
1281 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1282
4be74634 1283 if (!s->blk) {
92a6a6f6
KW		 1284 ide_abort_command(s);
1285 return true;
1286 }
1287
1288 ide_cmd_lba48_transform(s, lba48);
1289 ide_sector_start_dma(s, IDE_DMA_WRITE);
1290
1291 s->media_changed = 1;
1292
1293 return false;
1294}
1295
9afce429
KW		 1296static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1297{
1298 ide_flush_cache(s);
1299 return false;
1300}
1301
61fdda37
KW		 1302static bool cmd_seek(IDEState *s, uint8_t cmd)
1303{
1304 /* XXX: Check that seek is within bounds */
1305 return true;
1306}
1307
63a82e6a
KW		 1308static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1309{
1310 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1311
1312 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1313 if (s->nb_sectors == 0) {
1314 ide_abort_command(s);
1315 return true;
1316 }
1317
1318 ide_cmd_lba48_transform(s, lba48);
1319 ide_set_sector(s, s->nb_sectors - 1);
1320
1321 return true;
1322}
1323
785f6320
KW		 1324static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1325{
1326 s->nsector = 0xff; /* device active or idle */
1327 return true;
1328}
1329
ee03398c
KW		 1330static bool cmd_set_features(IDEState *s, uint8_t cmd)
1331{
1332 uint16_t *identify_data;
1333
4be74634 1334 if (!s->blk) {
ee03398c
KW		 1335 ide_abort_command(s);
1336 return true;
1337 }
1338
1339 /* XXX: valid for CDROM ? */
1340 switch (s->feature) {
1341 case 0x02: /* write cache enable */
4be74634 1342 blk_set_enable_write_cache(s->blk, true);
ee03398c
KW		 1343 identify_data = (uint16_t *)s->identify_data;
1344 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1345 return true;
1346 case 0x82: /* write cache disable */
4be74634 1347 blk_set_enable_write_cache(s->blk, false);
ee03398c
KW		 1348 identify_data = (uint16_t *)s->identify_data;
1349 put_le16(identify_data + 85, (1 << 14) | 1);
1350 ide_flush_cache(s);
1351 return false;
1352 case 0xcc: /* reverting to power-on defaults enable */
1353 case 0x66: /* reverting to power-on defaults disable */
1354 case 0xaa: /* read look-ahead enable */
1355 case 0x55: /* read look-ahead disable */
1356 case 0x05: /* set advanced power management mode */
1357 case 0x85: /* disable advanced power management mode */
1358 case 0x69: /* NOP */
1359 case 0x67: /* NOP */
1360 case 0x96: /* NOP */
1361 case 0x9a: /* NOP */
1362 case 0x42: /* enable Automatic Acoustic Mode */
1363 case 0xc2: /* disable Automatic Acoustic Mode */
1364 return true;
1365 case 0x03: /* set transfer mode */
1366 {
1367 uint8_t val = s->nsector & 0x07;
1368 identify_data = (uint16_t *)s->identify_data;
1369
1370 switch (s->nsector >> 3) {
1371 case 0x00: /* pio default */
1372 case 0x01: /* pio mode */
1373 put_le16(identify_data + 62, 0x07);
1374 put_le16(identify_data + 63, 0x07);
1375 put_le16(identify_data + 88, 0x3f);
1376 break;
1377 case 0x02: /* sigle word dma mode*/
1378 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1379 put_le16(identify_data + 63, 0x07);
1380 put_le16(identify_data + 88, 0x3f);
1381 break;
1382 case 0x04: /* mdma mode */
1383 put_le16(identify_data + 62, 0x07);
1384 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1385 put_le16(identify_data + 88, 0x3f);
1386 break;
1387 case 0x08: /* udma mode */
1388 put_le16(identify_data + 62, 0x07);
1389 put_le16(identify_data + 63, 0x07);
1390 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1391 break;
1392 default:
1393 goto abort_cmd;
1394 }
1395 return true;
1396 }
1397 }
1398
1399abort_cmd:
1400 ide_abort_command(s);
1401 return true;
1402}
1403
ee425c78
KW		 1404
1405/*** ATAPI commands ***/
1406
1407static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1408{
1409 ide_atapi_identify(s);
1410 s->status = READY_STAT | SEEK_STAT;
1411 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1412 ide_set_irq(s->bus);
1413 return false;
1414}
1415
1416static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1417{
1418 ide_set_signature(s);
1419
1420 if (s->drive_kind == IDE_CD) {
1421 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1422 * devices to return a clear status register
1423 * with READY_STAT *not* set. */
850484a2 1424 s->error = 0x01;
ee425c78
KW		 1425 } else {
1426 s->status = READY_STAT | SEEK_STAT;
1427 /* The bits of the error register are not as usual for this command!
1428 * They are part of the regular output (this is why ERR_STAT isn't set)
1429 * Device 0 passed, Device 1 passed or not present. */
1430 s->error = 0x01;
1431 ide_set_irq(s->bus);
1432 }
1433
1434 return false;
1435}
1436
1437static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1438{
1439 ide_set_signature(s);
1440 s->status = 0x00; /* NOTE: READY is _not_ set */
1441 s->error = 0x01;
1442
1443 return false;
1444}
1445
1446static bool cmd_packet(IDEState *s, uint8_t cmd)
1447{
1448 /* overlapping commands not supported */
1449 if (s->feature & 0x02) {
1450 ide_abort_command(s);
1451 return true;
1452 }
1453
1454 s->status = READY_STAT | SEEK_STAT;
1455 s->atapi_dma = s->feature & 1;
1456 s->nsector = 1;
1457 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1458 ide_atapi_cmd);
1459 return false;
1460}
1461
6b1dd744
KW		 1462
1463/*** CF-ATA commands ***/
1464
1465static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1466{
1467 s->error = 0x09; /* miscellaneous error */
1468 s->status = READY_STAT | SEEK_STAT;
1469 ide_set_irq(s->bus);
1470
1471 return false;
1472}
1473
1474static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1475{
1476 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1477 * required for Windows 8 to work with AHCI */
1478
1479 if (cmd == CFA_WEAR_LEVEL) {
1480 s->nsector = 0;
1481 }
1482
1483 if (cmd == CFA_ERASE_SECTORS) {
1484 s->media_changed = 1;
1485 }
1486
1487 return true;
1488}
1489
1490static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1491{
1492 s->status = READY_STAT | SEEK_STAT;
1493
1494 memset(s->io_buffer, 0, 0x200);
1495 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1496 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1497 s->io_buffer[0x02] = s->select; /* Head */
1498 s->io_buffer[0x03] = s->sector; /* Sector */
1499 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1500 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1501 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1502 s->io_buffer[0x13] = 0x00; /* Erase flag */
1503 s->io_buffer[0x18] = 0x00; /* Hot count */
1504 s->io_buffer[0x19] = 0x00; /* Hot count */
1505 s->io_buffer[0x1a] = 0x01; /* Hot count */
1506
1507 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1508 ide_set_irq(s->bus);
1509
1510 return false;
1511}
1512
1513static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1514{
1515 switch (s->feature) {
1516 case 0x02: /* Inquiry Metadata Storage */
1517 ide_cfata_metadata_inquiry(s);
1518 break;
1519 case 0x03: /* Read Metadata Storage */
1520 ide_cfata_metadata_read(s);
1521 break;
1522 case 0x04: /* Write Metadata Storage */
1523 ide_cfata_metadata_write(s);
1524 break;
1525 default:
1526 ide_abort_command(s);
1527 return true;
1528 }
1529
1530 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1531 s->status = 0x00; /* NOTE: READY is _not_ set */
1532 ide_set_irq(s->bus);
1533
1534 return false;
1535}
1536
1537static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1538{
1539 switch (s->feature) {
1540 case 0x01: /* sense temperature in device */
1541 s->nsector = 0x50; /* +20 C */
1542 break;
1543 default:
1544 ide_abort_command(s);
1545 return true;
1546 }
1547
1548 return true;
1549}
1550
ff352677
KW		 1551
1552/*** SMART commands ***/
1553
1554static bool cmd_smart(IDEState *s, uint8_t cmd)
1555{
1556 int n;
1557
1558 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1559 goto abort_cmd;
1560 }
1561
1562 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1563 goto abort_cmd;
1564 }
1565
1566 switch (s->feature) {
1567 case SMART_DISABLE:
1568 s->smart_enabled = 0;
1569 return true;
1570
1571 case SMART_ENABLE:
1572 s->smart_enabled = 1;
1573 return true;
1574
1575 case SMART_ATTR_AUTOSAVE:
1576 switch (s->sector) {
1577 case 0x00:
1578 s->smart_autosave = 0;
1579 break;
1580 case 0xf1:
1581 s->smart_autosave = 1;
1582 break;
1583 default:
1584 goto abort_cmd;
1585 }
1586 return true;
1587
1588 case SMART_STATUS:
1589 if (!s->smart_errors) {
1590 s->hcyl = 0xc2;
1591 s->lcyl = 0x4f;
1592 } else {
1593 s->hcyl = 0x2c;
1594 s->lcyl = 0xf4;
1595 }
1596 return true;
1597
1598 case SMART_READ_THRESH:
1599 memset(s->io_buffer, 0, 0x200);
1600 s->io_buffer[0] = 0x01; /* smart struct version */
1601
1602 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1603 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1604 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1605 }
1606
1607 /* checksum */
1608 for (n = 0; n < 511; n++) {
1609 s->io_buffer[511] += s->io_buffer[n];
1610 }
1611 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1612
1613 s->status = READY_STAT | SEEK_STAT;
1614 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1615 ide_set_irq(s->bus);
1616 return false;
1617
1618 case SMART_READ_DATA:
1619 memset(s->io_buffer, 0, 0x200);
1620 s->io_buffer[0] = 0x01; /* smart struct version */
1621
1622 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1623 int i;
1624 for (i = 0; i < 11; i++) {
1625 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1626 }
1627 }
1628
1629 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1630 if (s->smart_selftest_count == 0) {
1631 s->io_buffer[363] = 0;
1632 } else {
1633 s->io_buffer[363] =
1634 s->smart_selftest_data[3 +
1635 (s->smart_selftest_count - 1) *
1636 24];
1637 }
1638 s->io_buffer[364] = 0x20;
1639 s->io_buffer[365] = 0x01;
1640 /* offline data collection capacity: execute + self-test*/
1641 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1642 s->io_buffer[368] = 0x03; /* smart capability (1) */
1643 s->io_buffer[369] = 0x00; /* smart capability (2) */
1644 s->io_buffer[370] = 0x01; /* error logging supported */
1645 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1646 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1647 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1648
1649 for (n = 0; n < 511; n++) {
1650 s->io_buffer[511] += s->io_buffer[n];
1651 }
1652 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1653
1654 s->status = READY_STAT | SEEK_STAT;
1655 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1656 ide_set_irq(s->bus);
1657 return false;
1658
1659 case SMART_READ_LOG:
1660 switch (s->sector) {
1661 case 0x01: /* summary smart error log */
1662 memset(s->io_buffer, 0, 0x200);
1663 s->io_buffer[0] = 0x01;
1664 s->io_buffer[1] = 0x00; /* no error entries */
1665 s->io_buffer[452] = s->smart_errors & 0xff;
1666 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1667
1668 for (n = 0; n < 511; n++) {
1669 s->io_buffer[511] += s->io_buffer[n];
1670 }
1671 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1672 break;
1673 case 0x06: /* smart self test log */
1674 memset(s->io_buffer, 0, 0x200);
1675 s->io_buffer[0] = 0x01;
1676 if (s->smart_selftest_count == 0) {
1677 s->io_buffer[508] = 0;
1678 } else {
1679 s->io_buffer[508] = s->smart_selftest_count;
1680 for (n = 2; n < 506; n++) {
1681 s->io_buffer[n] = s->smart_selftest_data[n];
1682 }
1683 }
1684
1685 for (n = 0; n < 511; n++) {
1686 s->io_buffer[511] += s->io_buffer[n];
1687 }
1688 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1689 break;
1690 default:
1691 goto abort_cmd;
1692 }
1693 s->status = READY_STAT | SEEK_STAT;
1694 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1695 ide_set_irq(s->bus);
1696 return false;
1697
1698 case SMART_EXECUTE_OFFLINE:
1699 switch (s->sector) {
1700 case 0: /* off-line routine */
1701 case 1: /* short self test */
1702 case 2: /* extended self test */
1703 s->smart_selftest_count++;
1704 if (s->smart_selftest_count > 21) {
940973ae 1705 s->smart_selftest_count = 1;
ff352677
KW		 1706 }
1707 n = 2 + (s->smart_selftest_count - 1) * 24;
1708 s->smart_selftest_data[n] = s->sector;
1709 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1710 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1711 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1712 break;
1713 default:
1714 goto abort_cmd;
1715 }
1716 return true;
1717 }
1718
1719abort_cmd:
1720 ide_abort_command(s);
1721 return true;
1722}
1723
844505b1
MA		 1724#define HD_OK (1u << IDE_HD)
1725#define CD_OK (1u << IDE_CD)
1726#define CFA_OK (1u << IDE_CFATA)
1727#define HD_CFA_OK (HD_OK | CFA_OK)
1728#define ALL_OK (HD_OK | CD_OK | CFA_OK)
1729
a0436e92
KW		 1730/* Set the Disk Seek Completed status bit during completion */
1731#define SET_DSC (1u << 8)
1732
844505b1 1733/* See ACS-2 T13/2015-D Table B.2 Command codes */
a0436e92
KW		 1734static const struct {
1735 /* Returns true if the completion code should be run */
1736 bool (*handler)(IDEState *s, uint8_t cmd);
1737 int flags;
1738} ide_cmd_table[0x100] = {
844505b1 1739 /* NOP not implemented, mandatory for CD */
6b1dd744 1740 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
4286434c 1741 [WIN_DSM] = { cmd_data_set_management, ALL_OK },
ee425c78 1742 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
b300337e 1743 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
0e6498ed
KW		 1744 [WIN_READ] = { cmd_read_pio, ALL_OK },
1745 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK },
1746 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
92a6a6f6 1747 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
63a82e6a 1748 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
adf3a2c4 1749 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
0e6498ed
KW		 1750 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1751 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1752 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
92a6a6f6 1753 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
0e6498ed 1754 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
adf3a2c4 1755 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
0e6498ed 1756 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
413860cf
KW		 1757 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1758 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1759 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
61fdda37 1760 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
6b1dd744 1761 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
ee425c78 1762 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
b300337e
KW		 1763 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1764 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK },
1765 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK },
1766 [WIN_STANDBY2] = { cmd_nop, ALL_OK },
1767 [WIN_SETIDLE2] = { cmd_nop, ALL_OK },
785f6320 1768 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC },
b300337e 1769 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK },
ee425c78
KW		 1770 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1771 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
ff352677 1772 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
6b1dd744
KW		 1773 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1774 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
adf3a2c4
KW		 1775 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1776 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1777 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
92a6a6f6
KW		 1778 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1779 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1780 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1781 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
adf3a2c4 1782 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
b300337e
KW		 1783 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK },
1784 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK },
1785 [WIN_STANDBY] = { cmd_nop, ALL_OK },
1786 [WIN_SETIDLE1] = { cmd_nop, ALL_OK },
785f6320 1787 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC },
b300337e 1788 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK },
9afce429
KW		 1789 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1790 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1c66869a 1791 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
ee03398c 1792 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
6b1dd744
KW		 1793 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1794 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
63a82e6a 1795 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC },
844505b1
MA		 1796};
1797
1798static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1799{
1800 return cmd < ARRAY_SIZE(ide_cmd_table)
a0436e92 1801 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
844505b1 1802}
7cff87ff
AG		 1803
1804void ide_exec_cmd(IDEBus *bus, uint32_t val)
1805{
1806 IDEState *s;
dfe1ea8f 1807 bool complete;
7cff87ff 1808
5391d806 1809#if defined(DEBUG_IDE)
6ef2ba5e 1810 printf("ide: CMD=%02x\n", val);
5391d806 1811#endif
6ef2ba5e 1812 s = idebus_active_if(bus);
66a0a2cb 1813 /* ignore commands to non existent slave */
4be74634 1814 if (s != bus->ifs && !s->blk) {
6ef2ba5e 1815 return;
4be74634 1816 }
c2ff060f 1817
6ef2ba5e
AG		 1818 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1819 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1820 return;
fcdd25ab 1821
844505b1 1822 if (!ide_cmd_permitted(s, val)) {
dfe1ea8f
KW		 1823 ide_abort_command(s);
1824 ide_set_irq(s->bus);
1825 return;
844505b1
MA		 1826 }
1827
dfe1ea8f
KW		 1828 s->status = READY_STAT | BUSY_STAT;
1829 s->error = 0;
36334faf 1830 s->io_buffer_offset = 0;
a0436e92 1831
dfe1ea8f
KW		 1832 complete = ide_cmd_table[val].handler(s, val);
1833 if (complete) {
1834 s->status &= ~BUSY_STAT;
1835 assert(!!s->error == !!(s->status & ERR_STAT));
a0436e92 1836
dfe1ea8f
KW		 1837 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
1838 s->status |= SEEK_STAT;
a0436e92
KW		 1839 }
1840
c7e73adb 1841 ide_cmd_done(s);
6ef2ba5e 1842 ide_set_irq(s->bus);
6ef2ba5e 1843 }
5391d806
FB		 1844}
1845
356721ae 1846uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
5391d806 1847{
bcbdc4d3
GH		 1848 IDEBus *bus = opaque;
1849 IDEState *s = idebus_active_if(bus);
5391d806 1850 uint32_t addr;
c2ff060f 1851 int ret, hob;
5391d806
FB		 1852
1853 addr = addr1 & 7;
c2ff060f
FB		 1854 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1855 //hob = s->select & (1 << 7);
1856 hob = 0;
5391d806
FB		 1857 switch(addr) {
1858 case 0:
1859 ret = 0xff;
1860 break;
1861 case 1:
4be74634
MA		 1862 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1863 (s != bus->ifs && !s->blk)) {
c45c3d00 1864 ret = 0;
4be74634 1865 } else if (!hob) {
c45c3d00 1866 ret = s->error;
4be74634 1867 } else {
c2ff060f 1868 ret = s->hob_feature;
4be74634 1869 }
5391d806
FB		 1870 break;
1871 case 2:
4be74634 1872 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 1873 ret = 0;
4be74634 1874 } else if (!hob) {
c45c3d00 1875 ret = s->nsector & 0xff;
4be74634 1876 } else {
c2ff060f 1877 ret = s->hob_nsector;
4be74634 1878 }
5391d806
FB		 1879 break;
1880 case 3:
4be74634 1881 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 1882 ret = 0;
4be74634 1883 } else if (!hob) {
c45c3d00 1884 ret = s->sector;
4be74634 1885 } else {
c2ff060f 1886 ret = s->hob_sector;
4be74634 1887 }
5391d806
FB		 1888 break;
1889 case 4:
4be74634 1890 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 1891 ret = 0;
4be74634 1892 } else if (!hob) {
c45c3d00 1893 ret = s->lcyl;
4be74634 1894 } else {
c2ff060f 1895 ret = s->hob_lcyl;
4be74634 1896 }
5391d806
FB		 1897 break;
1898 case 5:
4be74634 1899 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 1900 ret = 0;
4be74634 1901 } else if (!hob) {
c45c3d00 1902 ret = s->hcyl;
4be74634 1903 } else {
c2ff060f 1904 ret = s->hob_hcyl;
4be74634 1905 }
5391d806
FB		 1906 break;
1907 case 6:
4be74634 1908 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
c45c3d00 1909 ret = 0;
4be74634 1910 } else {
7ae98627 1911 ret = s->select;
4be74634 1912 }
5391d806
FB		 1913 break;
1914 default:
1915 case 7:
4be74634
MA		 1916 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1917 (s != bus->ifs && !s->blk)) {
c45c3d00 1918 ret = 0;
4be74634 1919 } else {
c45c3d00 1920 ret = s->status;
4be74634 1921 }
9cdd03a7 1922 qemu_irq_lower(bus->irq);
5391d806
FB		 1923 break;
1924 }
1925#ifdef DEBUG_IDE
1926 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1927#endif
1928 return ret;
1929}
1930
356721ae 1931uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 1932{
bcbdc4d3
GH		 1933 IDEBus *bus = opaque;
1934 IDEState *s = idebus_active_if(bus);
5391d806 1935 int ret;
7ae98627 1936
4be74634
MA		 1937 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1938 (s != bus->ifs && !s->blk)) {
7ae98627 1939 ret = 0;
4be74634 1940 } else {
7ae98627 1941 ret = s->status;
4be74634 1942 }
5391d806
FB		 1943#ifdef DEBUG_IDE
1944 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1945#endif
1946 return ret;
1947}
1948
356721ae 1949void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 1950{
bcbdc4d3 1951 IDEBus *bus = opaque;
5391d806
FB		 1952 IDEState *s;
1953 int i;
1954
1955#ifdef DEBUG_IDE
1956 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1957#endif
1958 /* common for both drives */
9cdd03a7 1959 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1960 (val & IDE_CMD_RESET)) {
1961 /* reset low to high */
1962 for(i = 0;i < 2; i++) {
bcbdc4d3 1963 s = &bus->ifs[i];
5391d806
FB		 1964 s->status = BUSY_STAT | SEEK_STAT;
1965 s->error = 0x01;
1966 }
9cdd03a7 1967 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1968 !(val & IDE_CMD_RESET)) {
1969 /* high to low */
1970 for(i = 0;i < 2; i++) {
bcbdc4d3 1971 s = &bus->ifs[i];
cd8722bb 1972 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 1973 s->status = 0x00; /* NOTE: READY is _not_ set */
1974 else
56bf1d37 1975 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 1976 ide_set_signature(s);
1977 }
1978 }
1979
9cdd03a7 1980 bus->cmd = val;
5391d806
FB		 1981}
1982
40c4ed3f
KW		 1983/*
1984 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1985 * transferred from the device to the guest), false if it's a PIO in
1986 */
1987static bool ide_is_pio_out(IDEState *s)
1988{
1989 if (s->end_transfer_func == ide_sector_write ||
1990 s->end_transfer_func == ide_atapi_cmd) {
1991 return false;
1992 } else if (s->end_transfer_func == ide_sector_read ||
1993 s->end_transfer_func == ide_transfer_stop ||
1994 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1995 s->end_transfer_func == ide_dummy_transfer_stop) {
1996 return true;
1997 }
1998
1999 abort();
2000}
2001
356721ae 2002void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 2003{
bcbdc4d3
GH		 2004 IDEBus *bus = opaque;
2005 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2006 uint8_t *p;
2007
40c4ed3f
KW		 2008 /* PIO data access allowed only when DRQ bit is set. The result of a write
2009 * during PIO out is indeterminate, just ignore it. */
2010 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2011 return;
40c4ed3f 2012 }
fcdd25ab 2013
5391d806 2014 p = s->data_ptr;
0c4ad8dc 2015 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 2016 p += 2;
2017 s->data_ptr = p;
2018 if (p >= s->data_end)
2019 s->end_transfer_func(s);
2020}
2021
356721ae 2022uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 2023{
bcbdc4d3
GH		 2024 IDEBus *bus = opaque;
2025 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2026 uint8_t *p;
2027 int ret;
fcdd25ab 2028
40c4ed3f
KW		 2029 /* PIO data access allowed only when DRQ bit is set. The result of a read
2030 * during PIO in is indeterminate, return 0 and don't move forward. */
2031 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 2032 return 0;
40c4ed3f 2033 }
fcdd25ab 2034
5391d806 2035 p = s->data_ptr;
0c4ad8dc 2036 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 2037 p += 2;
2038 s->data_ptr = p;
2039 if (p >= s->data_end)
2040 s->end_transfer_func(s);
2041 return ret;
2042}
2043
356721ae 2044void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 2045{
bcbdc4d3
GH		 2046 IDEBus *bus = opaque;
2047 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2048 uint8_t *p;
2049
40c4ed3f
KW		 2050 /* PIO data access allowed only when DRQ bit is set. The result of a write
2051 * during PIO out is indeterminate, just ignore it. */
2052 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 2053 return;
40c4ed3f 2054 }
fcdd25ab 2055
5391d806 2056 p = s->data_ptr;
0c4ad8dc 2057 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 2058 p += 4;
2059 s->data_ptr = p;
2060 if (p >= s->data_end)
2061 s->end_transfer_func(s);
2062}
2063
356721ae 2064uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 2065{
bcbdc4d3
GH		 2066 IDEBus *bus = opaque;
2067 IDEState *s = idebus_active_if(bus);
5391d806
FB		 2068 uint8_t *p;
2069 int ret;
3b46e624 2070
40c4ed3f
KW		 2071 /* PIO data access allowed only when DRQ bit is set. The result of a read
2072 * during PIO in is indeterminate, return 0 and don't move forward. */
2073 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 2074 return 0;
40c4ed3f 2075 }
fcdd25ab 2076
5391d806 2077 p = s->data_ptr;
0c4ad8dc 2078 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 2079 p += 4;
2080 s->data_ptr = p;
2081 if (p >= s->data_end)
2082 s->end_transfer_func(s);
2083 return ret;
2084}
2085
a7dfe172
FB		 2086static void ide_dummy_transfer_stop(IDEState *s)
2087{
2088 s->data_ptr = s->io_buffer;
2089 s->data_end = s->io_buffer;
2090 s->io_buffer[0] = 0xff;
2091 s->io_buffer[1] = 0xff;
2092 s->io_buffer[2] = 0xff;
2093 s->io_buffer[3] = 0xff;
2094}
2095
4a643563 2096static void ide_reset(IDEState *s)
5391d806 2097{
4a643563
BS		 2098#ifdef DEBUG_IDE
2099 printf("ide: reset\n");
2100#endif
bef0fd59
SH		 2101
2102 if (s->pio_aiocb) {
4be74634 2103 blk_aio_cancel(s->pio_aiocb);
bef0fd59
SH		 2104 s->pio_aiocb = NULL;
2105 }
2106
cd8722bb 2107 if (s->drive_kind == IDE_CFATA)
201a51fc
AZ		 2108 s->mult_sectors = 0;
2109 else
2110 s->mult_sectors = MAX_MULT_SECTORS;
4a643563
BS		 2111 /* ide regs */
2112 s->feature = 0;
2113 s->error = 0;
2114 s->nsector = 0;
2115 s->sector = 0;
2116 s->lcyl = 0;
2117 s->hcyl = 0;
2118
2119 /* lba48 */
2120 s->hob_feature = 0;
2121 s->hob_sector = 0;
2122 s->hob_nsector = 0;
2123 s->hob_lcyl = 0;
2124 s->hob_hcyl = 0;
2125
5391d806 2126 s->select = 0xa0;
41a2b959 2127 s->status = READY_STAT | SEEK_STAT;
4a643563
BS		 2128
2129 s->lba48 = 0;
2130
2131 /* ATAPI specific */
2132 s->sense_key = 0;
2133 s->asc = 0;
2134 s->cdrom_changed = 0;
2135 s->packet_transfer_size = 0;
2136 s->elementary_transfer_size = 0;
2137 s->io_buffer_index = 0;
2138 s->cd_sector_size = 0;
2139 s->atapi_dma = 0;
a7f3d65b
PH		 2140 s->tray_locked = 0;
2141 s->tray_open = 0;
4a643563
BS		 2142 /* ATA DMA state */
2143 s->io_buffer_size = 0;
2144 s->req_nb_sectors = 0;
2145
5391d806 2146 ide_set_signature(s);
a7dfe172
FB		 2147 /* init the transfer handler so that 0xffff is returned on data
2148 accesses */
2149 s->end_transfer_func = ide_dummy_transfer_stop;
2150 ide_dummy_transfer_stop(s);
201a51fc 2151 s->media_changed = 0;
5391d806
FB		 2152}
2153
4a643563
BS		 2154void ide_bus_reset(IDEBus *bus)
2155{
2156 bus->unit = 0;
2157 bus->cmd = 0;
2158 ide_reset(&bus->ifs[0]);
2159 ide_reset(&bus->ifs[1]);
2160 ide_clear_hob(bus);
40a6238a
AG		 2161
2162 /* pending async DMA */
2163 if (bus->dma->aiocb) {
2164#ifdef DEBUG_AIO
2165 printf("aio_cancel\n");
2166#endif
4be74634 2167 blk_aio_cancel(bus->dma->aiocb);
40a6238a
AG		 2168 bus->dma->aiocb = NULL;
2169 }
2170
2171 /* reset dma provider too */
1374bec0
PB		 2172 if (bus->dma->ops->reset) {
2173 bus->dma->ops->reset(bus->dma);
2174 }
4a643563
BS		 2175}
2176
e4def80b
MA		 2177static bool ide_cd_is_tray_open(void *opaque)
2178{
2179 return ((IDEState *)opaque)->tray_open;
2180}
2181
f107639a
MA		 2182static bool ide_cd_is_medium_locked(void *opaque)
2183{
2184 return ((IDEState *)opaque)->tray_locked;
2185}
2186
01ce352e
JS		 2187static void ide_resize_cb(void *opaque)
2188{
2189 IDEState *s = opaque;
2190 uint64_t nb_sectors;
2191
2192 if (!s->identify_set) {
2193 return;
2194 }
2195
4be74634 2196 blk_get_geometry(s->blk, &nb_sectors);
01ce352e
JS		 2197 s->nb_sectors = nb_sectors;
2198
2199 /* Update the identify data buffer. */
2200 if (s->drive_kind == IDE_CFATA) {
2201 ide_cfata_identify_size(s);
2202 } else {
2203 /* IDE_CD uses a different set of callbacks entirely. */
2204 assert(s->drive_kind != IDE_CD);
2205 ide_identify_size(s);
2206 }
2207}
2208
0e49de52 2209static const BlockDevOps ide_cd_block_ops = {
145feb17 2210 .change_media_cb = ide_cd_change_cb,
2df0a3a3 2211 .eject_request_cb = ide_cd_eject_request_cb,
e4def80b 2212 .is_tray_open = ide_cd_is_tray_open,
f107639a 2213 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 2214};
2215
01ce352e
JS		 2216static const BlockDevOps ide_hd_block_ops = {
2217 .resize_cb = ide_resize_cb,
2218};
2219
4be74634 2220int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
95ebda85 2221 const char *version, const char *serial, const char *model,
ba801960
MA		 2222 uint64_t wwn,
2223 uint32_t cylinders, uint32_t heads, uint32_t secs,
2224 int chs_trans)
88804180 2225{
88804180
GH		 2226 uint64_t nb_sectors;
2227
4be74634 2228 s->blk = blk;
1f56e32a
MA		 2229 s->drive_kind = kind;
2230
4be74634 2231 blk_get_geometry(blk, &nb_sectors);
870111c8
MA		 2232 s->cylinders = cylinders;
2233 s->heads = heads;
2234 s->sectors = secs;
ba801960 2235 s->chs_trans = chs_trans;
870111c8 2236 s->nb_sectors = nb_sectors;
95ebda85 2237 s->wwn = wwn;
870111c8
MA		 2238 /* The SMART values should be preserved across power cycles
2239 but they aren't. */
2240 s->smart_enabled = 1;
2241 s->smart_autosave = 1;
2242 s->smart_errors = 0;
2243 s->smart_selftest_count = 0;
1f56e32a 2244 if (kind == IDE_CD) {
4be74634
MA		 2245 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2246 blk_set_guest_block_size(blk, 2048);
7aa9c811 2247 } else {
4be74634 2248 if (!blk_is_inserted(s->blk)) {
98f28ad7
MA		 2249 error_report("Device needs media, but drive is empty");
2250 return -1;
2251 }
4be74634 2252 if (blk_is_read_only(blk)) {
7aa9c811
MA		 2253 error_report("Can't use a read-only drive");
2254 return -1;
2255 }
4be74634 2256 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
88804180 2257 }
f8b6cc00 2258 if (serial) {
aa2c91bd 2259 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
6ced55a5 2260 } else {
88804180
GH		 2261 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2262 "QM%05d", s->drive_serial);
870111c8 2263 }
27e0c9a1
FB		 2264 if (model) {
2265 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2266 } else {
2267 switch (kind) {
2268 case IDE_CD:
2269 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2270 break;
2271 case IDE_CFATA:
2272 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2273 break;
2274 default:
2275 strcpy(s->drive_model_str, "QEMU HARDDISK");
2276 break;
2277 }
2278 }
2279
47c06340
GH		 2280 if (version) {
2281 pstrcpy(s->version, sizeof(s->version), version);
2282 } else {
93bfef4c 2283 pstrcpy(s->version, sizeof(s->version), qemu_get_version());
47c06340 2284 }
40a6238a 2285
88804180 2286 ide_reset(s);
4be74634 2287 blk_iostatus_enable(blk);
c4d74df7 2288 return 0;
88804180
GH		 2289}
2290
57234ee4 2291static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 2292{
2293 static int drive_serial = 1;
2294 IDEState *s = &bus->ifs[unit];
2295
2296 s->bus = bus;
2297 s->unit = unit;
2298 s->drive_serial = drive_serial++;
1b2adf28 2299 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 2300 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 2301 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2302 memset(s->io_buffer, 0, s->io_buffer_total_len);
2303
4be74634 2304 s->smart_selftest_data = blk_blockalign(s->blk, 512);
c925400b
KW		 2305 memset(s->smart_selftest_data, 0, 512);
2306
bc72ad67 2307 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
d459da0e 2308 ide_sector_write_timer_cb, s);
57234ee4
MA		 2309}
2310
40a6238a
AG		 2311static int ide_nop_int(IDEDMA *dma, int x)
2312{
2313 return 0;
2314}
2315
1dfb4dd9 2316static void ide_nop_restart(void *opaque, int x, RunState y)
40a6238a
AG		 2317{
2318}
2319
2320static const IDEDMAOps ide_dma_nop_ops = {
40a6238a
AG		 2321 .prepare_buf = ide_nop_int,
2322 .rw_buf = ide_nop_int,
2323 .set_unit = ide_nop_int,
40a6238a 2324 .restart_cb = ide_nop_restart,
40a6238a
AG		 2325};
2326
2327static IDEDMA ide_dma_nop = {
2328 .ops = &ide_dma_nop_ops,
2329 .aiocb = NULL,
2330};
2331
57234ee4
MA		 2332void ide_init2(IDEBus *bus, qemu_irq irq)
2333{
2334 int i;
2335
2336 for(i = 0; i < 2; i++) {
2337 ide_init1(bus, i);
2338 ide_reset(&bus->ifs[i]);
870111c8 2339 }
57234ee4 2340 bus->irq = irq;
40a6238a 2341 bus->dma = &ide_dma_nop;
d459da0e
MA		 2342}
2343
4a91d3b3
RH		 2344static const MemoryRegionPortio ide_portio_list[] = {
2345 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2346 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2347 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2348 PORTIO_END_OF_LIST(),
2349};
2350
2351static const MemoryRegionPortio ide_portio2_list[] = {
2352 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2353 PORTIO_END_OF_LIST(),
2354};
2355
2356void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
69b91039 2357{
4a91d3b3
RH		 2358 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2359 bridge has been setup properly to always register with ISA. */
2360 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2361
caed8802 2362 if (iobase2) {
4a91d3b3 2363 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
5391d806 2364 }
5391d806 2365}
69b91039 2366
37159f13 2367static bool is_identify_set(void *opaque, int version_id)
aa941b94 2368{
37159f13
JQ		 2369 IDEState *s = opaque;
2370
2371 return s->identify_set != 0;
2372}
2373
50641c5c
JQ		 2374static EndTransferFunc* transfer_end_table[] = {
2375 ide_sector_read,
2376 ide_sector_write,
2377 ide_transfer_stop,
2378 ide_atapi_cmd_reply_end,
2379 ide_atapi_cmd,
2380 ide_dummy_transfer_stop,
2381};
2382
2383static int transfer_end_table_idx(EndTransferFunc *fn)
2384{
2385 int i;
2386
2387 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2388 if (transfer_end_table[i] == fn)
2389 return i;
2390
2391 return -1;
2392}
2393
37159f13 2394static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2395{
37159f13
JQ		 2396 IDEState *s = opaque;
2397
7cdd481c 2398 if (s->identify_set) {
4be74634 2399 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
7cdd481c 2400 }
37159f13 2401 return 0;
aa941b94
AZ		 2402}
2403
50641c5c
JQ		 2404static int ide_drive_pio_post_load(void *opaque, int version_id)
2405{
2406 IDEState *s = opaque;
2407
fb60105d 2408 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2409 return -EINVAL;
2410 }
2411 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2412 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2413 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2414
2415 return 0;
2416}
2417
2418static void ide_drive_pio_pre_save(void *opaque)
2419{
2420 IDEState *s = opaque;
2421 int idx;
2422
2423 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2424 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2425
2426 idx = transfer_end_table_idx(s->end_transfer_func);
2427 if (idx == -1) {
2428 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2429 __func__);
2430 s->end_transfer_fn_idx = 2;
2431 } else {
2432 s->end_transfer_fn_idx = idx;
2433 }
2434}
2435
2436static bool ide_drive_pio_state_needed(void *opaque)
2437{
2438 IDEState *s = opaque;
2439
fdc650d7 2440 return ((s->status & DRQ_STAT) != 0)
fd648f10 2441 || (s->bus->error_status & IDE_RETRY_PIO);
50641c5c
JQ		 2442}
2443
db118fe7
MA		 2444static bool ide_tray_state_needed(void *opaque)
2445{
2446 IDEState *s = opaque;
2447
2448 return s->tray_open || s->tray_locked;
2449}
2450
996faf1a
AS		 2451static bool ide_atapi_gesn_needed(void *opaque)
2452{
2453 IDEState *s = opaque;
2454
2455 return s->events.new_media || s->events.eject_request;
2456}
2457
def93791
KW		 2458static bool ide_error_needed(void *opaque)
2459{
2460 IDEBus *bus = opaque;
2461
2462 return (bus->error_status != 0);
2463}
2464
996faf1a 2465/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2466static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2467 .name ="ide_drive/atapi/gesn_state",
2468 .version_id = 1,
2469 .minimum_version_id = 1,
35d08458 2470 .fields = (VMStateField[]) {
996faf1a
AS		 2471 VMSTATE_BOOL(events.new_media, IDEState),
2472 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2473 VMSTATE_END_OF_LIST()
996faf1a
AS		 2474 }
2475};
2476
db118fe7
MA		 2477static const VMStateDescription vmstate_ide_tray_state = {
2478 .name = "ide_drive/tray_state",
2479 .version_id = 1,
2480 .minimum_version_id = 1,
db118fe7
MA		 2481 .fields = (VMStateField[]) {
2482 VMSTATE_BOOL(tray_open, IDEState),
2483 VMSTATE_BOOL(tray_locked, IDEState),
2484 VMSTATE_END_OF_LIST()
2485 }
2486};
2487
656fbeff 2488static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2489 .name = "ide_drive/pio_state",
2490 .version_id = 1,
2491 .minimum_version_id = 1,
50641c5c
JQ		 2492 .pre_save = ide_drive_pio_pre_save,
2493 .post_load = ide_drive_pio_post_load,
35d08458 2494 .fields = (VMStateField[]) {
50641c5c
JQ		 2495 VMSTATE_INT32(req_nb_sectors, IDEState),
2496 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2497 vmstate_info_uint8, uint8_t),
2498 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2499 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2500 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2501 VMSTATE_INT32(elementary_transfer_size, IDEState),
2502 VMSTATE_INT32(packet_transfer_size, IDEState),
2503 VMSTATE_END_OF_LIST()
2504 }
2505};
2506
37159f13
JQ		 2507const VMStateDescription vmstate_ide_drive = {
2508 .name = "ide_drive",
3abb6260 2509 .version_id = 3,
37159f13 2510 .minimum_version_id = 0,
37159f13 2511 .post_load = ide_drive_post_load,
35d08458 2512 .fields = (VMStateField[]) {
37159f13
JQ		 2513 VMSTATE_INT32(mult_sectors, IDEState),
2514 VMSTATE_INT32(identify_set, IDEState),
2515 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2516 VMSTATE_UINT8(feature, IDEState),
2517 VMSTATE_UINT8(error, IDEState),
2518 VMSTATE_UINT32(nsector, IDEState),
2519 VMSTATE_UINT8(sector, IDEState),
2520 VMSTATE_UINT8(lcyl, IDEState),
2521 VMSTATE_UINT8(hcyl, IDEState),
2522 VMSTATE_UINT8(hob_feature, IDEState),
2523 VMSTATE_UINT8(hob_sector, IDEState),
2524 VMSTATE_UINT8(hob_nsector, IDEState),
2525 VMSTATE_UINT8(hob_lcyl, IDEState),
2526 VMSTATE_UINT8(hob_hcyl, IDEState),
2527 VMSTATE_UINT8(select, IDEState),
2528 VMSTATE_UINT8(status, IDEState),
2529 VMSTATE_UINT8(lba48, IDEState),
2530 VMSTATE_UINT8(sense_key, IDEState),
2531 VMSTATE_UINT8(asc, IDEState),
2532 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2533 VMSTATE_END_OF_LIST()
50641c5c
JQ		 2534 },
2535 .subsections = (VMStateSubsection []) {
2536 {
2537 .vmsd = &vmstate_ide_drive_pio_state,
2538 .needed = ide_drive_pio_state_needed,
db118fe7
MA		 2539 }, {
2540 .vmsd = &vmstate_ide_tray_state,
2541 .needed = ide_tray_state_needed,
996faf1a
AS		 2542 }, {
2543 .vmsd = &vmstate_ide_atapi_gesn_state,
2544 .needed = ide_atapi_gesn_needed,
50641c5c
JQ		 2545 }, {
2546 /* empty */
2547 }
37159f13
JQ		 2548 }
2549};
2550
656fbeff 2551static const VMStateDescription vmstate_ide_error_status = {
def93791
KW		 2552 .name ="ide_bus/error",
2553 .version_id = 1,
2554 .minimum_version_id = 1,
35d08458 2555 .fields = (VMStateField[]) {
def93791
KW		 2556 VMSTATE_INT32(error_status, IDEBus),
2557 VMSTATE_END_OF_LIST()
2558 }
2559};
2560
6521dc62
JQ		 2561const VMStateDescription vmstate_ide_bus = {
2562 .name = "ide_bus",
2563 .version_id = 1,
2564 .minimum_version_id = 1,
35d08458 2565 .fields = (VMStateField[]) {
6521dc62
JQ		 2566 VMSTATE_UINT8(cmd, IDEBus),
2567 VMSTATE_UINT8(unit, IDEBus),
2568 VMSTATE_END_OF_LIST()
def93791
KW		 2569 },
2570 .subsections = (VMStateSubsection []) {
2571 {
2572 .vmsd = &vmstate_ide_error_status,
2573 .needed = ide_error_needed,
2574 }, {
2575 /* empty */
2576 }
6521dc62
JQ		 2577 }
2578};
75717903 2579
d8f94e1b 2580void ide_drive_get(DriveInfo **hd, int n)
75717903
IY		 2581{
2582 int i;
d8f94e1b
JS		 2583 int highest_bus = drive_get_max_bus(IF_IDE) + 1;
2584 int max_devs = drive_get_max_devs(IF_IDE);
2585 int n_buses = max_devs ? (n / max_devs) : n;
75717903 2586
d8f94e1b
JS		 2587 /*
2588 * Note: The number of actual buses available is not known.
2589 * We compute this based on the size of the DriveInfo* array, n.
2590 * If it is less than max_devs * <num_real_buses>,
2591 * We will stop looking for drives prematurely instead of overfilling
2592 * the array.
2593 */
2594
2595 if (highest_bus > n_buses) {
2596 error_report("Too many IDE buses defined (%d > %d)",
2597 highest_bus, n_buses);
75717903
IY		 2598 exit(1);
2599 }
2600
d8f94e1b
JS		 2601 for (i = 0; i < n; i++) {
2602 hd[i] = drive_get_by_index(IF_IDE, i);
75717903
IY		 2603 }
2604}
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