[mirror_qemu.git] / hw / ide / ich.c

/*
 * QEMU ICH Emulation
 *
 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * lspci dump of a ICH-9 real device
 *
 * 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0])
 *         Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922]
 *         Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
 *         Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
 *         Latency: 0
 *         Interrupt: pin B routed to IRQ 222
 *         Region 0: I/O ports at d000 [size=8]
 *         Region 1: I/O ports at cc00 [size=4]
 *         Region 2: I/O ports at c880 [size=8]
 *         Region 3: I/O ports at c800 [size=4]
 *         Region 4: I/O ports at c480 [size=32]
 *         Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
 *         Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
 *                 Address: fee0f00c  Data: 41d9
 *         Capabilities: [70] Power Management version 3
 *                 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
 *                 Status: D0 PME-Enable- DSel=0 DScale=0 PME-
 *         Capabilities: [a8] SATA HBA <?>
 *         Capabilities: [b0] Vendor Specific Information <?>
 *         Kernel driver in use: ahci
 *         Kernel modules: ahci
 * 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00
 * 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00
 * 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29
 * 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00
 * 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00
 * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 * 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00
 * 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00
 * 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00
 * a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00
 * b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00
 * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 * f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00
 *
 */

#include <hw/hw.h>
#include <hw/pci/msi.h>
#include <hw/i386/pc.h>
#include <hw/pci/pci.h>
#include <hw/isa/isa.h>
#include "block/block.h"
#include "sysemu/dma.h"

#include <hw/ide/pci.h>
#include <hw/ide/ahci.h>

#define ICH9_SATA_CAP_OFFSET    0xA8

#define ICH9_IDP_BAR            4
#define ICH9_MEM_BAR            5

#define ICH9_IDP_INDEX          0x10
#define ICH9_IDP_INDEX_LOG2     0x04

static const VMStateDescription vmstate_ich9_ahci = {
    .name = "ich9_ahci",
    .unmigratable = 1, /* Still buggy under I/O load */
    .version_id = 1,
    .fields = (VMStateField []) {
        VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState),
        VMSTATE_AHCI(ahci, AHCIPCIState),
        VMSTATE_END_OF_LIST()
    },
};

static void pci_ich9_reset(DeviceState *dev)
{
    AHCIPCIState *d = ICH_AHCI(dev);

    ahci_reset(&d->ahci);
}

static int pci_ich9_ahci_init(PCIDevice *dev)
{
    struct AHCIPCIState *d;
    int sata_cap_offset;
    uint8_t *sata_cap;
    d = ICH_AHCI(dev);

    ahci_init(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);

    pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);

    dev->config[PCI_CACHE_LINE_SIZE] = 0x08;  /* Cache line size */
    dev->config[PCI_LATENCY_TIMER]   = 0x00;  /* Latency timer */
    pci_config_set_interrupt_pin(dev->config, 1);

    /* XXX Software should program this register */
    dev->config[0x90]   = 1 << 6; /* Address Map Register - AHCI mode */

    msi_init(dev, 0x50, 1, true, false);
    d->ahci.irq = dev->irq[0];

    pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
                     &d->ahci.idp);
    pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
                     &d->ahci.mem);

    sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA,
                                         ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE);
    if (sata_cap_offset < 0) {
        return sata_cap_offset;
    }

    sata_cap = dev->config + sata_cap_offset;
    pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
    pci_set_long(sata_cap + SATA_CAP_BAR,
                 (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4));
    d->ahci.idp_offset = ICH9_IDP_INDEX;

    return 0;
}

static void pci_ich9_uninit(PCIDevice *dev)
{
    struct AHCIPCIState *d;
    d = ICH_AHCI(dev);

    msi_uninit(dev);
    ahci_uninit(&d->ahci);
}

static void ich_ahci_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = pci_ich9_ahci_init;
    k->exit = pci_ich9_uninit;
    k->vendor_id = PCI_VENDOR_ID_INTEL;
    k->device_id = PCI_DEVICE_ID_INTEL_82801IR;
    k->revision = 0x02;
    k->class_id = PCI_CLASS_STORAGE_SATA;
    dc->vmsd = &vmstate_ich9_ahci;
    dc->reset = pci_ich9_reset;
}

static const TypeInfo ich_ahci_info = {
    .name          = TYPE_ICH9_AHCI,
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(AHCIPCIState),
    .class_init    = ich_ahci_class_init,
};

static void ich_ahci_register_types(void)
{
    type_register_static(&ich_ahci_info);
}

type_init(ich_ahci_register_types)
Commit	Line	Data
7fb6577b AG	1	/*
	2	* QEMU ICH Emulation
	3	*
	4	* Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
	5	* Copyright (c) 2010 Alexander Graf <agraf@suse.de>
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*
	20	*
	21	* lspci dump of a ICH-9 real device
	22	*
	23	* 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0])
	24	* Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922]
	25	* Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	26	* Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	27	* Latency: 0
	28	* Interrupt: pin B routed to IRQ 222
	29	* Region 0: I/O ports at d000 [size=8]
	30	* Region 1: I/O ports at cc00 [size=4]
	31	* Region 2: I/O ports at c880 [size=8]
	32	* Region 3: I/O ports at c800 [size=4]
	33	* Region 4: I/O ports at c480 [size=32]
	34	* Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
	35	* Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
	36	* Address: fee0f00c Data: 41d9
	37	* Capabilities: [70] Power Management version 3
	38	* Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
	39	* Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	40	* Capabilities: [a8] SATA HBA <?>
	41	* Capabilities: [b0] Vendor Specific Information <?>
	42	* Kernel driver in use: ahci
	43	* Kernel modules: ahci
	44	* 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00
	45	* 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00
	46	* 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29
	47	* 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00
	48	* 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00
	49	* 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
	50	* 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
	51	* 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00
	52	* 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00
	53	* 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00
	54	* a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00
	55	* b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00
	56	* c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
	57	* d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
	58	* e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
	59	* f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00
	60	*
	61	*/
	62
03c7a6a8	63	#include <hw/hw.h>
a2cb15b0	64	#include <hw/pci/msi.h>
0d09e41a	65	#include <hw/i386/pc.h>
a2cb15b0	66	#include <hw/pci/pci.h>
0d09e41a	67	#include <hw/isa/isa.h>
737e150e	68	#include "block/block.h"
9c17d615	69	#include "sysemu/dma.h"
03c7a6a8 SH	70
	71	#include <hw/ide/pci.h>
	72	#include <hw/ide/ahci.h>
	73
465f1ab1 DV	74	#define ICH9_SATA_CAP_OFFSET 0xA8
	75
	76	#define ICH9_IDP_BAR 4
	77	#define ICH9_MEM_BAR 5
	78
	79	#define ICH9_IDP_INDEX 0x10
	80	#define ICH9_IDP_INDEX_LOG2 0x04
	81
a2623021 JB	82	static const VMStateDescription vmstate_ich9_ahci = {
	83	.name = "ich9_ahci",
	84	.unmigratable = 1, /* Still buggy under I/O load */
	85	.version_id = 1,
	86	.fields = (VMStateField []) {
0d3aea56	87	VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState),
a2623021 JB	88	VMSTATE_AHCI(ahci, AHCIPCIState),
	89	VMSTATE_END_OF_LIST()
	90	},
b7ce1b27 GH	91	};
b7ce1b27 GH	92
8ab60a07	93	static void pci_ich9_reset(DeviceState *dev)
868a1a52	94	{
fd58922c	95	AHCIPCIState *d = ICH_AHCI(dev);
868a1a52	96
8ab60a07	97	ahci_reset(&d->ahci);
868a1a52 JK	98	}
868a1a52 JK	99
7fb6577b	100	static int pci_ich9_ahci_init(PCIDevice *dev)
03c7a6a8 SH	101	{
03c7a6a8 SH	102	struct AHCIPCIState *d;
465f1ab1 DV	103	int sata_cap_offset;
465f1ab1 DV	104	uint8_t *sata_cap;
fd58922c	105	d = ICH_AHCI(dev);
03c7a6a8	106
fd58922c	107	ahci_init(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
69c8944f	108
0d3aea56	109	pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
03c7a6a8	110
0d3aea56 AF	111	dev->config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
	112	dev->config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
	113	pci_config_set_interrupt_pin(dev->config, 1);
03c7a6a8 SH	114
03c7a6a8 SH	115	/* XXX Software should program this register */
0d3aea56	116	dev->config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */
03c7a6a8	117
03c7a6a8	118	msi_init(dev, 0x50, 1, true, false);
0d3aea56	119	d->ahci.irq = dev->irq[0];
03c7a6a8	120
0d3aea56	121	pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
465f1ab1	122	&d->ahci.idp);
0d3aea56	123	pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
465f1ab1 DV	124	&d->ahci.mem);
465f1ab1 DV	125
0d3aea56	126	sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA,
465f1ab1 DV	127	ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE);
	128	if (sata_cap_offset < 0) {
	129	return sata_cap_offset;
	130	}
	131
0d3aea56	132	sata_cap = dev->config + sata_cap_offset;
465f1ab1 DV	133	pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
	134	pci_set_long(sata_cap + SATA_CAP_BAR,
	135	(ICH9_IDP_BAR + 0x4) \| (ICH9_IDP_INDEX_LOG2 << 4));
	136	d->ahci.idp_offset = ICH9_IDP_INDEX;
96d19bcb	137
03c7a6a8 SH	138	return 0;
	139	}
	140
f90c2bcd	141	static void pci_ich9_uninit(PCIDevice *dev)
7fb6577b AG	142	{
7fb6577b AG	143	struct AHCIPCIState *d;
fd58922c	144	d = ICH_AHCI(dev);
7fb6577b	145
45fe15c2	146	msi_uninit(dev);
2c4b9d0e	147	ahci_uninit(&d->ahci);
7fb6577b AG	148	}
7fb6577b AG	149
40021f08 AL	150	static void ich_ahci_class_init(ObjectClass klass, void data)
40021f08 AL	151	{
39bffca2	152	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	153	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	154
	155	k->init = pci_ich9_ahci_init;
	156	k->exit = pci_ich9_uninit;
40021f08 AL	157	k->vendor_id = PCI_VENDOR_ID_INTEL;
	158	k->device_id = PCI_DEVICE_ID_INTEL_82801IR;
	159	k->revision = 0x02;
	160	k->class_id = PCI_CLASS_STORAGE_SATA;
a2623021	161	dc->vmsd = &vmstate_ich9_ahci;
8ab60a07	162	dc->reset = pci_ich9_reset;
40021f08 AL	163	}
40021f08 AL	164
8c43a6f0	165	static const TypeInfo ich_ahci_info = {
fd58922c	166	.name = TYPE_ICH9_AHCI,
39bffca2 AL	167	.parent = TYPE_PCI_DEVICE,
	168	.instance_size = sizeof(AHCIPCIState),
	169	.class_init = ich_ahci_class_init,
03c7a6a8 SH	170	};
03c7a6a8 SH	171
83f7d43a	172	static void ich_ahci_register_types(void)
03c7a6a8	173	{
39bffca2	174	type_register_static(&ich_ahci_info);
03c7a6a8	175	}
83f7d43a AF	176
83f7d43a AF	177	type_init(ich_ahci_register_types)