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Commit | Line | Data |
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b8842209 GH |
1 | /* |
2 | * QEMU IDE Emulation: MacIO support. | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
53239262 | 25 | #include "qemu/osdep.h" |
baec1910 AF |
26 | #include "hw/hw.h" |
27 | #include "hw/ppc/mac.h" | |
0d09e41a | 28 | #include "hw/ppc/mac_dbdma.h" |
4be74634 | 29 | #include "sysemu/block-backend.h" |
9c17d615 | 30 | #include "sysemu/dma.h" |
59f2a787 GH |
31 | |
32 | #include <hw/ide/internal.h> | |
b8842209 | 33 | |
33ce36bb AG |
34 | /* debug MACIO */ |
35 | // #define DEBUG_MACIO | |
36 | ||
37 | #ifdef DEBUG_MACIO | |
38 | static const int debug_macio = 1; | |
39 | #else | |
40 | static const int debug_macio = 0; | |
41 | #endif | |
42 | ||
43 | #define MACIO_DPRINTF(fmt, ...) do { \ | |
44 | if (debug_macio) { \ | |
45 | printf(fmt , ## __VA_ARGS__); \ | |
46 | } \ | |
47 | } while (0) | |
48 | ||
49 | ||
b8842209 GH |
50 | /***********************************************************/ |
51 | /* MacIO based PowerPC IDE */ | |
52 | ||
02c7c992 BS |
53 | #define MACIO_PAGE_SIZE 4096 |
54 | ||
b01d44cd MCA |
55 | /* |
56 | * Unaligned DMA read/write access functions required for OS X/Darwin which | |
57 | * don't perform DMA transactions on sector boundaries. These functions are | |
cab3a356 KW |
58 | * modelled on bdrv_co_preadv()/bdrv_co_pwritev() and so should be easy to |
59 | * remove if the unaligned block APIs are ever exposed. | |
b01d44cd MCA |
60 | */ |
61 | ||
4827ac1e | 62 | static void pmac_dma_read(BlockBackend *blk, |
0389b8f8 | 63 | int64_t offset, unsigned int bytes, |
4827ac1e | 64 | void (*cb)(void *opaque, int ret), void *opaque) |
b8842209 GH |
65 | { |
66 | DBDMA_io *io = opaque; | |
67 | MACIOIDEState *m = io->opaque; | |
68 | IDEState *s = idebus_active_if(&m->bus); | |
bc9ca595 | 69 | dma_addr_t dma_addr; |
0389b8f8 MCA |
70 | int64_t sector_num; |
71 | int nsector; | |
72 | uint64_t align = BDRV_SECTOR_SIZE; | |
73 | size_t head_bytes, tail_bytes; | |
b8842209 | 74 | |
4827ac1e MCA |
75 | qemu_iovec_destroy(&io->iov); |
76 | qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1); | |
77 | ||
0389b8f8 MCA |
78 | sector_num = (offset >> 9); |
79 | nsector = (io->len >> 9); | |
4827ac1e | 80 | |
0389b8f8 MCA |
81 | MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx ",0x%x): " |
82 | "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len, | |
83 | sector_num, nsector); | |
4827ac1e | 84 | |
0389b8f8 | 85 | dma_addr = io->addr; |
bc9ca595 MCA |
86 | io->dir = DMA_DIRECTION_FROM_DEVICE; |
87 | io->dma_len = io->len; | |
88 | io->dma_mem = dma_memory_map(&address_space_memory, dma_addr, &io->dma_len, | |
89 | io->dir); | |
4827ac1e | 90 | |
0389b8f8 MCA |
91 | if (offset & (align - 1)) { |
92 | head_bytes = offset & (align - 1); | |
4827ac1e | 93 | |
0389b8f8 MCA |
94 | MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64 ", " |
95 | "discarding %zu bytes\n", sector_num, head_bytes); | |
4827ac1e | 96 | |
ac58fe7b | 97 | qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes); |
4827ac1e | 98 | |
0389b8f8 MCA |
99 | bytes += offset & (align - 1); |
100 | offset = offset & ~(align - 1); | |
b8842209 GH |
101 | } |
102 | ||
bc9ca595 | 103 | qemu_iovec_add(&io->iov, io->dma_mem, io->len); |
cae32357 | 104 | |
0389b8f8 MCA |
105 | if ((offset + bytes) & (align - 1)) { |
106 | tail_bytes = (offset + bytes) & (align - 1); | |
33ce36bb | 107 | |
0389b8f8 MCA |
108 | MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64 ", " |
109 | "discarding bytes %zu\n", sector_num, tail_bytes); | |
4827ac1e | 110 | |
ac58fe7b | 111 | qemu_iovec_add(&io->iov, &io->tail_remainder, align - tail_bytes); |
0389b8f8 | 112 | bytes = ROUND_UP(bytes, align); |
b8842209 GH |
113 | } |
114 | ||
4827ac1e MCA |
115 | s->io_buffer_size -= io->len; |
116 | s->io_buffer_index += io->len; | |
80fc95d8 | 117 | |
4827ac1e | 118 | io->len = 0; |
80fc95d8 | 119 | |
0389b8f8 MCA |
120 | MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 " " |
121 | "nsector: %x\n", (offset >> 9), (bytes >> 9)); | |
80fc95d8 | 122 | |
d4f510eb | 123 | s->bus->dma->aiocb = blk_aio_preadv(blk, offset, &io->iov, 0, cb, io); |
4827ac1e | 124 | } |
80fc95d8 | 125 | |
bd4214fc | 126 | static void pmac_dma_write(BlockBackend *blk, |
ac58fe7b | 127 | int64_t offset, int bytes, |
bd4214fc MCA |
128 | void (*cb)(void *opaque, int ret), void *opaque) |
129 | { | |
130 | DBDMA_io *io = opaque; | |
131 | MACIOIDEState *m = io->opaque; | |
132 | IDEState *s = idebus_active_if(&m->bus); | |
bc9ca595 | 133 | dma_addr_t dma_addr; |
ac58fe7b MCA |
134 | int64_t sector_num; |
135 | int nsector; | |
136 | uint64_t align = BDRV_SECTOR_SIZE; | |
137 | size_t head_bytes, tail_bytes; | |
138 | bool unaligned_head = false, unaligned_tail = false; | |
bd4214fc MCA |
139 | |
140 | qemu_iovec_destroy(&io->iov); | |
141 | qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1); | |
142 | ||
ac58fe7b MCA |
143 | sector_num = (offset >> 9); |
144 | nsector = (io->len >> 9); | |
bd4214fc | 145 | |
ac58fe7b MCA |
146 | MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx ",0x%x): " |
147 | "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len, | |
148 | sector_num, nsector); | |
bd4214fc | 149 | |
ac58fe7b | 150 | dma_addr = io->addr; |
bc9ca595 MCA |
151 | io->dir = DMA_DIRECTION_TO_DEVICE; |
152 | io->dma_len = io->len; | |
153 | io->dma_mem = dma_memory_map(&address_space_memory, dma_addr, &io->dma_len, | |
154 | io->dir); | |
bd4214fc | 155 | |
ac58fe7b MCA |
156 | if (offset & (align - 1)) { |
157 | head_bytes = offset & (align - 1); | |
158 | sector_num = ((offset & ~(align - 1)) >> 9); | |
bd4214fc | 159 | |
ac58fe7b MCA |
160 | MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %" |
161 | PRId64 "\n", sector_num); | |
bd4214fc | 162 | |
ac58fe7b | 163 | blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align); |
bd4214fc | 164 | |
ac58fe7b | 165 | qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes); |
bc9ca595 | 166 | qemu_iovec_add(&io->iov, io->dma_mem, io->len); |
bd4214fc | 167 | |
ac58fe7b MCA |
168 | bytes += offset & (align - 1); |
169 | offset = offset & ~(align - 1); | |
170 | ||
171 | unaligned_head = true; | |
bd4214fc MCA |
172 | } |
173 | ||
ac58fe7b MCA |
174 | if ((offset + bytes) & (align - 1)) { |
175 | tail_bytes = (offset + bytes) & (align - 1); | |
176 | sector_num = (((offset + bytes) & ~(align - 1)) >> 9); | |
bd4214fc | 177 | |
ac58fe7b MCA |
178 | MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %" |
179 | PRId64 "\n", sector_num); | |
bd4214fc | 180 | |
ac58fe7b | 181 | blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align); |
bd4214fc | 182 | |
ac58fe7b | 183 | if (!unaligned_head) { |
bc9ca595 | 184 | qemu_iovec_add(&io->iov, io->dma_mem, io->len); |
ac58fe7b | 185 | } |
bd4214fc | 186 | |
ac58fe7b MCA |
187 | qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes, |
188 | align - tail_bytes); | |
bd4214fc | 189 | |
ac58fe7b | 190 | bytes = ROUND_UP(bytes, align); |
bd4214fc | 191 | |
ac58fe7b | 192 | unaligned_tail = true; |
bd4214fc MCA |
193 | } |
194 | ||
ac58fe7b | 195 | if (!unaligned_head && !unaligned_tail) { |
bc9ca595 | 196 | qemu_iovec_add(&io->iov, io->dma_mem, io->len); |
ac58fe7b MCA |
197 | } |
198 | ||
199 | s->io_buffer_size -= io->len; | |
200 | s->io_buffer_index += io->len; | |
bd4214fc MCA |
201 | |
202 | io->len = 0; | |
203 | ||
ac58fe7b MCA |
204 | MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 " " |
205 | "nsector: %x\n", (offset >> 9), (bytes >> 9)); | |
bd4214fc | 206 | |
d4f510eb | 207 | s->bus->dma->aiocb = blk_aio_pwritev(blk, offset, &io->iov, 0, cb, io); |
bd4214fc MCA |
208 | } |
209 | ||
0e826a06 AJ |
210 | static void pmac_dma_trim(BlockBackend *blk, |
211 | int64_t offset, int bytes, | |
212 | void (*cb)(void *opaque, int ret), void *opaque) | |
213 | { | |
214 | DBDMA_io *io = opaque; | |
215 | MACIOIDEState *m = io->opaque; | |
216 | IDEState *s = idebus_active_if(&m->bus); | |
bc9ca595 | 217 | dma_addr_t dma_addr; |
0e826a06 AJ |
218 | |
219 | qemu_iovec_destroy(&io->iov); | |
220 | qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1); | |
221 | ||
222 | dma_addr = io->addr; | |
bc9ca595 MCA |
223 | io->dir = DMA_DIRECTION_TO_DEVICE; |
224 | io->dma_len = io->len; | |
225 | io->dma_mem = dma_memory_map(&address_space_memory, dma_addr, &io->dma_len, | |
226 | io->dir); | |
0e826a06 | 227 | |
bc9ca595 | 228 | qemu_iovec_add(&io->iov, io->dma_mem, io->len); |
0e826a06 AJ |
229 | s->io_buffer_size -= io->len; |
230 | s->io_buffer_index += io->len; | |
231 | io->len = 0; | |
232 | ||
8a8e63eb | 233 | s->bus->dma->aiocb = ide_issue_trim(offset, &io->iov, cb, io, blk); |
0e826a06 AJ |
234 | } |
235 | ||
4827ac1e MCA |
236 | static void pmac_ide_atapi_transfer_cb(void *opaque, int ret) |
237 | { | |
238 | DBDMA_io *io = opaque; | |
239 | MACIOIDEState *m = io->opaque; | |
240 | IDEState *s = idebus_active_if(&m->bus); | |
0389b8f8 | 241 | int64_t offset; |
4827ac1e | 242 | |
b01d44cd | 243 | MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n"); |
4827ac1e MCA |
244 | |
245 | if (ret < 0) { | |
b01d44cd | 246 | MACIO_DPRINTF("DMA error: %d\n", ret); |
4827ac1e MCA |
247 | ide_atapi_io_error(s, ret); |
248 | goto done; | |
249 | } | |
250 | ||
251 | if (!m->dma_active) { | |
252 | MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n", | |
253 | s->nsector, io->len, s->status); | |
254 | /* data not ready yet, wait for the channel to get restarted */ | |
255 | io->processing = false; | |
80fc95d8 AG |
256 | return; |
257 | } | |
258 | ||
4827ac1e | 259 | if (s->io_buffer_size <= 0) { |
b01d44cd | 260 | MACIO_DPRINTF("End of IDE transfer\n"); |
b8842209 | 261 | ide_atapi_cmd_ok(s); |
cae32357 | 262 | m->dma_active = false; |
4827ac1e | 263 | goto done; |
33ce36bb | 264 | } |
b8842209 GH |
265 | |
266 | if (io->len == 0) { | |
4827ac1e | 267 | MACIO_DPRINTF("End of DMA transfer\n"); |
a597e79c | 268 | goto done; |
b8842209 GH |
269 | } |
270 | ||
4827ac1e MCA |
271 | if (s->lba == -1) { |
272 | /* Non-block ATAPI transfer - just copy to RAM */ | |
273 | s->io_buffer_size = MIN(s->io_buffer_size, io->len); | |
ddd495e5 MCA |
274 | dma_memory_write(&address_space_memory, io->addr, s->io_buffer, |
275 | s->io_buffer_size); | |
4827ac1e MCA |
276 | ide_atapi_cmd_ok(s); |
277 | m->dma_active = false; | |
278 | goto done; | |
80fc95d8 AG |
279 | } |
280 | ||
0389b8f8 | 281 | /* Calculate current offset */ |
97225170 | 282 | offset = ((int64_t)s->lba << 11) + s->io_buffer_index; |
0389b8f8 | 283 | |
0389b8f8 | 284 | pmac_dma_read(s->blk, offset, io->len, pmac_ide_atapi_transfer_cb, io); |
a597e79c CH |
285 | return; |
286 | ||
287 | done: | |
bc9ca595 MCA |
288 | dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len, |
289 | io->dir, io->dma_len); | |
290 | ||
b88b3c8b AG |
291 | if (ret < 0) { |
292 | block_acct_failed(blk_get_stats(s->blk), &s->acct); | |
293 | } else { | |
294 | block_acct_done(blk_get_stats(s->blk), &s->acct); | |
295 | } | |
03c1280b MCA |
296 | |
297 | ide_set_inactive(s, false); | |
a597e79c | 298 | io->dma_end(opaque); |
b8842209 GH |
299 | } |
300 | ||
301 | static void pmac_ide_transfer_cb(void *opaque, int ret) | |
302 | { | |
303 | DBDMA_io *io = opaque; | |
304 | MACIOIDEState *m = io->opaque; | |
305 | IDEState *s = idebus_active_if(&m->bus); | |
0389b8f8 | 306 | int64_t offset; |
bd4214fc MCA |
307 | |
308 | MACIO_DPRINTF("pmac_ide_transfer_cb\n"); | |
b8842209 GH |
309 | |
310 | if (ret < 0) { | |
b01d44cd | 311 | MACIO_DPRINTF("DMA error: %d\n", ret); |
8aef291f | 312 | ide_dma_error(s); |
a597e79c | 313 | goto done; |
b8842209 GH |
314 | } |
315 | ||
cae32357 AG |
316 | if (!m->dma_active) { |
317 | MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n", | |
318 | s->nsector, io->len, s->status); | |
319 | /* data not ready yet, wait for the channel to get restarted */ | |
320 | io->processing = false; | |
321 | return; | |
322 | } | |
323 | ||
bd4214fc | 324 | if (s->io_buffer_size <= 0) { |
b01d44cd | 325 | MACIO_DPRINTF("End of IDE transfer\n"); |
b8842209 | 326 | s->status = READY_STAT | SEEK_STAT; |
9cdd03a7 | 327 | ide_set_irq(s->bus); |
cae32357 | 328 | m->dma_active = false; |
bd4214fc | 329 | goto done; |
b8842209 GH |
330 | } |
331 | ||
b8842209 | 332 | if (io->len == 0) { |
bd4214fc | 333 | MACIO_DPRINTF("End of DMA transfer\n"); |
a597e79c | 334 | goto done; |
b8842209 GH |
335 | } |
336 | ||
bd4214fc | 337 | /* Calculate number of sectors */ |
0389b8f8 | 338 | offset = (ide_get_sector(s) << 9) + s->io_buffer_index; |
33ce36bb | 339 | |
4e1e0051 CH |
340 | switch (s->dma_cmd) { |
341 | case IDE_DMA_READ: | |
0389b8f8 | 342 | pmac_dma_read(s->blk, offset, io->len, pmac_ide_transfer_cb, io); |
4e1e0051 CH |
343 | break; |
344 | case IDE_DMA_WRITE: | |
ac58fe7b | 345 | pmac_dma_write(s->blk, offset, io->len, pmac_ide_transfer_cb, io); |
4e1e0051 | 346 | break; |
d353fb72 | 347 | case IDE_DMA_TRIM: |
0e826a06 | 348 | pmac_dma_trim(s->blk, offset, io->len, pmac_ide_transfer_cb, io); |
d353fb72 | 349 | break; |
502356ee PB |
350 | default: |
351 | abort(); | |
4e1e0051 | 352 | } |
3e300fa6 | 353 | |
a597e79c | 354 | return; |
b9b2008b | 355 | |
a597e79c | 356 | done: |
bc9ca595 MCA |
357 | dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len, |
358 | io->dir, io->dma_len); | |
359 | ||
a597e79c | 360 | if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { |
b88b3c8b AG |
361 | if (ret < 0) { |
362 | block_acct_failed(blk_get_stats(s->blk), &s->acct); | |
363 | } else { | |
364 | block_acct_done(blk_get_stats(s->blk), &s->acct); | |
365 | } | |
a597e79c | 366 | } |
03c1280b MCA |
367 | |
368 | ide_set_inactive(s, false); | |
bd4214fc | 369 | io->dma_end(opaque); |
b8842209 GH |
370 | } |
371 | ||
372 | static void pmac_ide_transfer(DBDMA_io *io) | |
373 | { | |
374 | MACIOIDEState *m = io->opaque; | |
375 | IDEState *s = idebus_active_if(&m->bus); | |
376 | ||
33ce36bb AG |
377 | MACIO_DPRINTF("\n"); |
378 | ||
cd8722bb | 379 | if (s->drive_kind == IDE_CD) { |
4be74634 | 380 | block_acct_start(blk_get_stats(s->blk), &s->acct, io->len, |
5366d0c8 | 381 | BLOCK_ACCT_READ); |
4827ac1e | 382 | |
b8842209 GH |
383 | pmac_ide_atapi_transfer_cb(io, 0); |
384 | return; | |
385 | } | |
386 | ||
a597e79c CH |
387 | switch (s->dma_cmd) { |
388 | case IDE_DMA_READ: | |
4be74634 | 389 | block_acct_start(blk_get_stats(s->blk), &s->acct, io->len, |
5366d0c8 | 390 | BLOCK_ACCT_READ); |
a597e79c CH |
391 | break; |
392 | case IDE_DMA_WRITE: | |
4be74634 | 393 | block_acct_start(blk_get_stats(s->blk), &s->acct, io->len, |
5366d0c8 | 394 | BLOCK_ACCT_WRITE); |
a597e79c CH |
395 | break; |
396 | default: | |
397 | break; | |
398 | } | |
399 | ||
b8842209 GH |
400 | pmac_ide_transfer_cb(io, 0); |
401 | } | |
402 | ||
403 | static void pmac_ide_flush(DBDMA_io *io) | |
404 | { | |
405 | MACIOIDEState *m = io->opaque; | |
03c1280b | 406 | IDEState *s = idebus_active_if(&m->bus); |
b8842209 | 407 | |
03c1280b | 408 | if (s->bus->dma->aiocb) { |
0d0437aa | 409 | blk_drain(s->blk); |
922453bc | 410 | } |
b8842209 GH |
411 | } |
412 | ||
413 | /* PowerMac IDE memory IO */ | |
414 | static void pmac_ide_writeb (void *opaque, | |
a8170e5e | 415 | hwaddr addr, uint32_t val) |
b8842209 GH |
416 | { |
417 | MACIOIDEState *d = opaque; | |
418 | ||
419 | addr = (addr & 0xFFF) >> 4; | |
420 | switch (addr) { | |
421 | case 1 ... 7: | |
422 | ide_ioport_write(&d->bus, addr, val); | |
423 | break; | |
424 | case 8: | |
425 | case 22: | |
426 | ide_cmd_write(&d->bus, 0, val); | |
427 | break; | |
428 | default: | |
429 | break; | |
430 | } | |
431 | } | |
432 | ||
a8170e5e | 433 | static uint32_t pmac_ide_readb (void *opaque,hwaddr addr) |
b8842209 GH |
434 | { |
435 | uint8_t retval; | |
436 | MACIOIDEState *d = opaque; | |
437 | ||
438 | addr = (addr & 0xFFF) >> 4; | |
439 | switch (addr) { | |
440 | case 1 ... 7: | |
441 | retval = ide_ioport_read(&d->bus, addr); | |
442 | break; | |
443 | case 8: | |
444 | case 22: | |
445 | retval = ide_status_read(&d->bus, 0); | |
446 | break; | |
447 | default: | |
448 | retval = 0xFF; | |
449 | break; | |
450 | } | |
451 | return retval; | |
452 | } | |
453 | ||
454 | static void pmac_ide_writew (void *opaque, | |
a8170e5e | 455 | hwaddr addr, uint32_t val) |
b8842209 GH |
456 | { |
457 | MACIOIDEState *d = opaque; | |
458 | ||
459 | addr = (addr & 0xFFF) >> 4; | |
b8842209 | 460 | val = bswap16(val); |
b8842209 GH |
461 | if (addr == 0) { |
462 | ide_data_writew(&d->bus, 0, val); | |
463 | } | |
464 | } | |
465 | ||
a8170e5e | 466 | static uint32_t pmac_ide_readw (void *opaque,hwaddr addr) |
b8842209 GH |
467 | { |
468 | uint16_t retval; | |
469 | MACIOIDEState *d = opaque; | |
470 | ||
471 | addr = (addr & 0xFFF) >> 4; | |
472 | if (addr == 0) { | |
473 | retval = ide_data_readw(&d->bus, 0); | |
474 | } else { | |
475 | retval = 0xFFFF; | |
476 | } | |
b8842209 | 477 | retval = bswap16(retval); |
b8842209 GH |
478 | return retval; |
479 | } | |
480 | ||
481 | static void pmac_ide_writel (void *opaque, | |
a8170e5e | 482 | hwaddr addr, uint32_t val) |
b8842209 GH |
483 | { |
484 | MACIOIDEState *d = opaque; | |
485 | ||
486 | addr = (addr & 0xFFF) >> 4; | |
b8842209 | 487 | val = bswap32(val); |
b8842209 GH |
488 | if (addr == 0) { |
489 | ide_data_writel(&d->bus, 0, val); | |
490 | } | |
491 | } | |
492 | ||
a8170e5e | 493 | static uint32_t pmac_ide_readl (void *opaque,hwaddr addr) |
b8842209 GH |
494 | { |
495 | uint32_t retval; | |
496 | MACIOIDEState *d = opaque; | |
497 | ||
498 | addr = (addr & 0xFFF) >> 4; | |
499 | if (addr == 0) { | |
500 | retval = ide_data_readl(&d->bus, 0); | |
501 | } else { | |
502 | retval = 0xFFFFFFFF; | |
503 | } | |
b8842209 | 504 | retval = bswap32(retval); |
b8842209 GH |
505 | return retval; |
506 | } | |
507 | ||
a348f108 | 508 | static const MemoryRegionOps pmac_ide_ops = { |
23c5e4ca AK |
509 | .old_mmio = { |
510 | .write = { | |
511 | pmac_ide_writeb, | |
512 | pmac_ide_writew, | |
513 | pmac_ide_writel, | |
514 | }, | |
515 | .read = { | |
516 | pmac_ide_readb, | |
517 | pmac_ide_readw, | |
518 | pmac_ide_readl, | |
519 | }, | |
520 | }, | |
521 | .endianness = DEVICE_NATIVE_ENDIAN, | |
b8842209 GH |
522 | }; |
523 | ||
44bfa332 JQ |
524 | static const VMStateDescription vmstate_pmac = { |
525 | .name = "ide", | |
bb37a8e8 | 526 | .version_id = 4, |
44bfa332 | 527 | .minimum_version_id = 0, |
35d08458 | 528 | .fields = (VMStateField[]) { |
44bfa332 JQ |
529 | VMSTATE_IDE_BUS(bus, MACIOIDEState), |
530 | VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState), | |
bb37a8e8 | 531 | VMSTATE_BOOL(dma_active, MACIOIDEState), |
44bfa332 | 532 | VMSTATE_END_OF_LIST() |
b8842209 | 533 | } |
44bfa332 | 534 | }; |
b8842209 | 535 | |
07a7484e | 536 | static void macio_ide_reset(DeviceState *dev) |
b8842209 | 537 | { |
07a7484e | 538 | MACIOIDEState *d = MACIO_IDE(dev); |
b8842209 | 539 | |
4a643563 | 540 | ide_bus_reset(&d->bus); |
b8842209 GH |
541 | } |
542 | ||
4aa3510f AG |
543 | static int ide_nop_int(IDEDMA *dma, int x) |
544 | { | |
545 | return 0; | |
546 | } | |
547 | ||
a718978e | 548 | static int32_t ide_nop_int32(IDEDMA *dma, int32_t l) |
3251bdcf JS |
549 | { |
550 | return 0; | |
551 | } | |
552 | ||
4aa3510f | 553 | static void ide_dbdma_start(IDEDMA *dma, IDEState *s, |
097310b5 | 554 | BlockCompletionFunc *cb) |
4aa3510f AG |
555 | { |
556 | MACIOIDEState *m = container_of(dma, MACIOIDEState, dma); | |
4827ac1e | 557 | |
bd4214fc | 558 | s->io_buffer_index = 0; |
4827ac1e | 559 | if (s->drive_kind == IDE_CD) { |
4827ac1e | 560 | s->io_buffer_size = s->packet_transfer_size; |
bd4214fc | 561 | } else { |
b01d44cd | 562 | s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE; |
bd4214fc | 563 | } |
4827ac1e | 564 | |
bd4214fc MCA |
565 | MACIO_DPRINTF("\n\n------------ IDE transfer\n"); |
566 | MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n", | |
567 | s->io_buffer_size, s->io_buffer_index); | |
568 | MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size); | |
569 | MACIO_DPRINTF("-------------------------\n"); | |
4827ac1e | 570 | |
cae32357 | 571 | m->dma_active = true; |
4aa3510f AG |
572 | DBDMA_kick(m->dbdma); |
573 | } | |
574 | ||
575 | static const IDEDMAOps dbdma_ops = { | |
576 | .start_dma = ide_dbdma_start, | |
3251bdcf | 577 | .prepare_buf = ide_nop_int32, |
4aa3510f | 578 | .rw_buf = ide_nop_int, |
4aa3510f AG |
579 | }; |
580 | ||
07a7484e | 581 | static void macio_ide_realizefn(DeviceState *dev, Error **errp) |
b8842209 | 582 | { |
07a7484e AF |
583 | MACIOIDEState *s = MACIO_IDE(dev); |
584 | ||
585 | ide_init2(&s->bus, s->irq); | |
4aa3510f AG |
586 | |
587 | /* Register DMA callbacks */ | |
588 | s->dma.ops = &dbdma_ops; | |
589 | s->bus.dma = &s->dma; | |
07a7484e AF |
590 | } |
591 | ||
592 | static void macio_ide_initfn(Object *obj) | |
593 | { | |
594 | SysBusDevice *d = SYS_BUS_DEVICE(obj); | |
595 | MACIOIDEState *s = MACIO_IDE(obj); | |
596 | ||
c6baf942 | 597 | ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); |
1437c94b | 598 | memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000); |
07a7484e AF |
599 | sysbus_init_mmio(d, &s->mem); |
600 | sysbus_init_irq(d, &s->irq); | |
601 | sysbus_init_irq(d, &s->dma_irq); | |
602 | } | |
603 | ||
604 | static void macio_ide_class_init(ObjectClass *oc, void *data) | |
605 | { | |
606 | DeviceClass *dc = DEVICE_CLASS(oc); | |
607 | ||
608 | dc->realize = macio_ide_realizefn; | |
609 | dc->reset = macio_ide_reset; | |
610 | dc->vmsd = &vmstate_pmac; | |
3469d9bc | 611 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
07a7484e | 612 | } |
b8842209 | 613 | |
07a7484e AF |
614 | static const TypeInfo macio_ide_type_info = { |
615 | .name = TYPE_MACIO_IDE, | |
616 | .parent = TYPE_SYS_BUS_DEVICE, | |
617 | .instance_size = sizeof(MACIOIDEState), | |
618 | .instance_init = macio_ide_initfn, | |
619 | .class_init = macio_ide_class_init, | |
620 | }; | |
b8842209 | 621 | |
07a7484e AF |
622 | static void macio_ide_register_types(void) |
623 | { | |
624 | type_register_static(&macio_ide_type_info); | |
625 | } | |
b8842209 | 626 | |
14eefd0e | 627 | /* hd_table must contain 2 block drivers */ |
07a7484e AF |
628 | void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table) |
629 | { | |
630 | int i; | |
b8842209 | 631 | |
07a7484e AF |
632 | for (i = 0; i < 2; i++) { |
633 | if (hd_table[i]) { | |
634 | ide_create_drive(&s->bus, i, hd_table[i]); | |
635 | } | |
636 | } | |
b8842209 | 637 | } |
07a7484e AF |
638 | |
639 | void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel) | |
640 | { | |
4aa3510f | 641 | s->dbdma = dbdma; |
07a7484e AF |
642 | DBDMA_register_channel(dbdma, channel, s->dma_irq, |
643 | pmac_ide_transfer, pmac_ide_flush, s); | |
644 | } | |
645 | ||
646 | type_init(macio_ide_register_types) |