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Commit | Line | Data |
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b8842209 GH |
1 | /* |
2 | * QEMU IDE Emulation: MacIO support. | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
0b8fa32f | 25 | |
53239262 | 26 | #include "qemu/osdep.h" |
baec1910 | 27 | #include "hw/ppc/mac.h" |
0d09e41a | 28 | #include "hw/ppc/mac_dbdma.h" |
a27bd6c7 | 29 | #include "hw/qdev-properties.h" |
d6454270 | 30 | #include "migration/vmstate.h" |
0b8fa32f | 31 | #include "qemu/module.h" |
9b164a46 | 32 | #include "hw/misc/macio/macio.h" |
4be74634 | 33 | #include "sysemu/block-backend.h" |
9c17d615 | 34 | #include "sysemu/dma.h" |
59f2a787 | 35 | |
a9c94277 | 36 | #include "hw/ide/internal.h" |
b8842209 | 37 | |
33ce36bb AG |
38 | /* debug MACIO */ |
39 | // #define DEBUG_MACIO | |
40 | ||
41 | #ifdef DEBUG_MACIO | |
42 | static const int debug_macio = 1; | |
43 | #else | |
44 | static const int debug_macio = 0; | |
45 | #endif | |
46 | ||
47 | #define MACIO_DPRINTF(fmt, ...) do { \ | |
48 | if (debug_macio) { \ | |
49 | printf(fmt , ## __VA_ARGS__); \ | |
50 | } \ | |
51 | } while (0) | |
52 | ||
53 | ||
b8842209 GH |
54 | /***********************************************************/ |
55 | /* MacIO based PowerPC IDE */ | |
56 | ||
02c7c992 BS |
57 | #define MACIO_PAGE_SIZE 4096 |
58 | ||
4827ac1e MCA |
59 | static void pmac_ide_atapi_transfer_cb(void *opaque, int ret) |
60 | { | |
61 | DBDMA_io *io = opaque; | |
62 | MACIOIDEState *m = io->opaque; | |
63 | IDEState *s = idebus_active_if(&m->bus); | |
0389b8f8 | 64 | int64_t offset; |
4827ac1e | 65 | |
b01d44cd | 66 | MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n"); |
4827ac1e MCA |
67 | |
68 | if (ret < 0) { | |
b01d44cd | 69 | MACIO_DPRINTF("DMA error: %d\n", ret); |
be1e3439 | 70 | qemu_sglist_destroy(&s->sg); |
4827ac1e MCA |
71 | ide_atapi_io_error(s, ret); |
72 | goto done; | |
73 | } | |
74 | ||
75 | if (!m->dma_active) { | |
76 | MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n", | |
77 | s->nsector, io->len, s->status); | |
78 | /* data not ready yet, wait for the channel to get restarted */ | |
79 | io->processing = false; | |
80fc95d8 AG |
80 | return; |
81 | } | |
82 | ||
4827ac1e | 83 | if (s->io_buffer_size <= 0) { |
b01d44cd | 84 | MACIO_DPRINTF("End of IDE transfer\n"); |
be1e3439 | 85 | qemu_sglist_destroy(&s->sg); |
b8842209 | 86 | ide_atapi_cmd_ok(s); |
cae32357 | 87 | m->dma_active = false; |
4827ac1e | 88 | goto done; |
33ce36bb | 89 | } |
b8842209 GH |
90 | |
91 | if (io->len == 0) { | |
4827ac1e | 92 | MACIO_DPRINTF("End of DMA transfer\n"); |
a597e79c | 93 | goto done; |
b8842209 GH |
94 | } |
95 | ||
4827ac1e MCA |
96 | if (s->lba == -1) { |
97 | /* Non-block ATAPI transfer - just copy to RAM */ | |
98 | s->io_buffer_size = MIN(s->io_buffer_size, io->len); | |
ddd495e5 MCA |
99 | dma_memory_write(&address_space_memory, io->addr, s->io_buffer, |
100 | s->io_buffer_size); | |
16275edb | 101 | io->len = 0; |
4827ac1e MCA |
102 | ide_atapi_cmd_ok(s); |
103 | m->dma_active = false; | |
104 | goto done; | |
80fc95d8 AG |
105 | } |
106 | ||
0389b8f8 | 107 | /* Calculate current offset */ |
97225170 | 108 | offset = ((int64_t)s->lba << 11) + s->io_buffer_index; |
0389b8f8 | 109 | |
be1e3439 MCA |
110 | qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1, |
111 | &address_space_memory); | |
112 | qemu_sglist_add(&s->sg, io->addr, io->len); | |
113 | s->io_buffer_size -= io->len; | |
114 | s->io_buffer_index += io->len; | |
115 | io->len = 0; | |
116 | ||
117 | s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1, | |
118 | pmac_ide_atapi_transfer_cb, io); | |
a597e79c CH |
119 | return; |
120 | ||
121 | done: | |
bc9ca595 MCA |
122 | dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len, |
123 | io->dir, io->dma_len); | |
124 | ||
b88b3c8b AG |
125 | if (ret < 0) { |
126 | block_acct_failed(blk_get_stats(s->blk), &s->acct); | |
127 | } else { | |
128 | block_acct_done(blk_get_stats(s->blk), &s->acct); | |
129 | } | |
03c1280b MCA |
130 | |
131 | ide_set_inactive(s, false); | |
a597e79c | 132 | io->dma_end(opaque); |
b8842209 GH |
133 | } |
134 | ||
135 | static void pmac_ide_transfer_cb(void *opaque, int ret) | |
136 | { | |
137 | DBDMA_io *io = opaque; | |
138 | MACIOIDEState *m = io->opaque; | |
139 | IDEState *s = idebus_active_if(&m->bus); | |
0389b8f8 | 140 | int64_t offset; |
bd4214fc MCA |
141 | |
142 | MACIO_DPRINTF("pmac_ide_transfer_cb\n"); | |
b8842209 GH |
143 | |
144 | if (ret < 0) { | |
b01d44cd | 145 | MACIO_DPRINTF("DMA error: %d\n", ret); |
be1e3439 | 146 | qemu_sglist_destroy(&s->sg); |
8aef291f | 147 | ide_dma_error(s); |
a597e79c | 148 | goto done; |
b8842209 GH |
149 | } |
150 | ||
cae32357 AG |
151 | if (!m->dma_active) { |
152 | MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n", | |
153 | s->nsector, io->len, s->status); | |
154 | /* data not ready yet, wait for the channel to get restarted */ | |
155 | io->processing = false; | |
156 | return; | |
157 | } | |
158 | ||
bd4214fc | 159 | if (s->io_buffer_size <= 0) { |
b01d44cd | 160 | MACIO_DPRINTF("End of IDE transfer\n"); |
be1e3439 | 161 | qemu_sglist_destroy(&s->sg); |
b8842209 | 162 | s->status = READY_STAT | SEEK_STAT; |
9cdd03a7 | 163 | ide_set_irq(s->bus); |
cae32357 | 164 | m->dma_active = false; |
bd4214fc | 165 | goto done; |
b8842209 GH |
166 | } |
167 | ||
b8842209 | 168 | if (io->len == 0) { |
bd4214fc | 169 | MACIO_DPRINTF("End of DMA transfer\n"); |
a597e79c | 170 | goto done; |
b8842209 GH |
171 | } |
172 | ||
bd4214fc | 173 | /* Calculate number of sectors */ |
0389b8f8 | 174 | offset = (ide_get_sector(s) << 9) + s->io_buffer_index; |
33ce36bb | 175 | |
be1e3439 MCA |
176 | qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1, |
177 | &address_space_memory); | |
178 | qemu_sglist_add(&s->sg, io->addr, io->len); | |
179 | s->io_buffer_size -= io->len; | |
180 | s->io_buffer_index += io->len; | |
181 | io->len = 0; | |
182 | ||
4e1e0051 CH |
183 | switch (s->dma_cmd) { |
184 | case IDE_DMA_READ: | |
be1e3439 MCA |
185 | s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1, |
186 | pmac_ide_atapi_transfer_cb, io); | |
4e1e0051 CH |
187 | break; |
188 | case IDE_DMA_WRITE: | |
be1e3439 MCA |
189 | s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset, 0x1, |
190 | pmac_ide_transfer_cb, io); | |
4e1e0051 | 191 | break; |
d353fb72 | 192 | case IDE_DMA_TRIM: |
be1e3439 | 193 | s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk), &s->sg, |
eb69953e | 194 | offset, 0x1, ide_issue_trim, s, |
be1e3439 MCA |
195 | pmac_ide_transfer_cb, io, |
196 | DMA_DIRECTION_TO_DEVICE); | |
d353fb72 | 197 | break; |
502356ee PB |
198 | default: |
199 | abort(); | |
4e1e0051 | 200 | } |
3e300fa6 | 201 | |
a597e79c | 202 | return; |
b9b2008b | 203 | |
a597e79c | 204 | done: |
bc9ca595 MCA |
205 | dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len, |
206 | io->dir, io->dma_len); | |
207 | ||
a597e79c | 208 | if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { |
b88b3c8b AG |
209 | if (ret < 0) { |
210 | block_acct_failed(blk_get_stats(s->blk), &s->acct); | |
211 | } else { | |
212 | block_acct_done(blk_get_stats(s->blk), &s->acct); | |
213 | } | |
a597e79c | 214 | } |
03c1280b MCA |
215 | |
216 | ide_set_inactive(s, false); | |
bd4214fc | 217 | io->dma_end(opaque); |
b8842209 GH |
218 | } |
219 | ||
220 | static void pmac_ide_transfer(DBDMA_io *io) | |
221 | { | |
222 | MACIOIDEState *m = io->opaque; | |
223 | IDEState *s = idebus_active_if(&m->bus); | |
224 | ||
33ce36bb AG |
225 | MACIO_DPRINTF("\n"); |
226 | ||
cd8722bb | 227 | if (s->drive_kind == IDE_CD) { |
4be74634 | 228 | block_acct_start(blk_get_stats(s->blk), &s->acct, io->len, |
5366d0c8 | 229 | BLOCK_ACCT_READ); |
4827ac1e | 230 | |
b8842209 GH |
231 | pmac_ide_atapi_transfer_cb(io, 0); |
232 | return; | |
233 | } | |
234 | ||
a597e79c CH |
235 | switch (s->dma_cmd) { |
236 | case IDE_DMA_READ: | |
4be74634 | 237 | block_acct_start(blk_get_stats(s->blk), &s->acct, io->len, |
5366d0c8 | 238 | BLOCK_ACCT_READ); |
a597e79c CH |
239 | break; |
240 | case IDE_DMA_WRITE: | |
4be74634 | 241 | block_acct_start(blk_get_stats(s->blk), &s->acct, io->len, |
5366d0c8 | 242 | BLOCK_ACCT_WRITE); |
a597e79c CH |
243 | break; |
244 | default: | |
245 | break; | |
246 | } | |
247 | ||
b8842209 GH |
248 | pmac_ide_transfer_cb(io, 0); |
249 | } | |
250 | ||
251 | static void pmac_ide_flush(DBDMA_io *io) | |
252 | { | |
253 | MACIOIDEState *m = io->opaque; | |
03c1280b | 254 | IDEState *s = idebus_active_if(&m->bus); |
b8842209 | 255 | |
03c1280b | 256 | if (s->bus->dma->aiocb) { |
0d0437aa | 257 | blk_drain(s->blk); |
922453bc | 258 | } |
b8842209 GH |
259 | } |
260 | ||
261 | /* PowerMac IDE memory IO */ | |
5abdf670 | 262 | static uint64_t pmac_ide_read(void *opaque, hwaddr addr, unsigned size) |
b8842209 GH |
263 | { |
264 | MACIOIDEState *d = opaque; | |
5abdf670 MCA |
265 | uint64_t retval = 0xffffffff; |
266 | int reg = addr >> 4; | |
267 | ||
268 | switch (reg) { | |
269 | case 0x0: | |
270 | if (size == 2) { | |
271 | retval = ide_data_readw(&d->bus, 0); | |
272 | } else if (size == 4) { | |
273 | retval = ide_data_readl(&d->bus, 0); | |
274 | } | |
b8842209 | 275 | break; |
5abdf670 MCA |
276 | case 0x1 ... 0x7: |
277 | if (size == 1) { | |
278 | retval = ide_ioport_read(&d->bus, reg); | |
279 | } | |
b8842209 | 280 | break; |
5abdf670 MCA |
281 | case 0x8: |
282 | case 0x16: | |
283 | if (size == 1) { | |
284 | retval = ide_status_read(&d->bus, 0); | |
285 | } | |
b8842209 | 286 | break; |
5abdf670 MCA |
287 | case 0x20: |
288 | if (size == 4) { | |
289 | retval = d->timing_reg; | |
290 | } | |
b8842209 | 291 | break; |
5abdf670 MCA |
292 | case 0x30: |
293 | /* This is an interrupt state register that only exists | |
294 | * in the KeyLargo and later variants. Bit 0x8000_0000 | |
295 | * latches the DMA interrupt and has to be written to | |
296 | * clear. Bit 0x4000_0000 is an image of the disk | |
297 | * interrupt. MacOS X relies on this and will hang if | |
298 | * we don't provide at least the disk interrupt | |
299 | */ | |
300 | if (size == 4) { | |
301 | retval = d->irq_reg; | |
302 | } | |
b8842209 GH |
303 | break; |
304 | } | |
b8842209 | 305 | |
b8842209 GH |
306 | return retval; |
307 | } | |
308 | ||
b8842209 | 309 | |
5abdf670 MCA |
310 | static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val, |
311 | unsigned size) | |
b8842209 | 312 | { |
b8842209 | 313 | MACIOIDEState *d = opaque; |
5abdf670 MCA |
314 | int reg = addr >> 4; |
315 | ||
316 | switch (reg) { | |
317 | case 0x0: | |
318 | if (size == 2) { | |
319 | ide_data_writew(&d->bus, 0, val); | |
320 | } else if (size == 4) { | |
321 | ide_data_writel(&d->bus, 0, val); | |
322 | } | |
323 | break; | |
324 | case 0x1 ... 0x7: | |
325 | if (size == 1) { | |
326 | ide_ioport_write(&d->bus, reg, val); | |
327 | } | |
328 | break; | |
329 | case 0x8: | |
330 | case 0x16: | |
331 | if (size == 1) { | |
98d98912 | 332 | ide_ctrl_write(&d->bus, 0, val); |
5abdf670 MCA |
333 | } |
334 | break; | |
335 | case 0x20: | |
336 | if (size == 4) { | |
337 | d->timing_reg = val; | |
338 | } | |
339 | break; | |
340 | case 0x30: | |
341 | if (size == 4) { | |
342 | if (val & 0x80000000u) { | |
343 | d->irq_reg &= 0x7fffffff; | |
344 | } | |
345 | } | |
346 | break; | |
b8842209 | 347 | } |
b8842209 GH |
348 | } |
349 | ||
a348f108 | 350 | static const MemoryRegionOps pmac_ide_ops = { |
5abdf670 MCA |
351 | .read = pmac_ide_read, |
352 | .write = pmac_ide_write, | |
353 | .valid.min_access_size = 1, | |
354 | .valid.max_access_size = 4, | |
355 | .endianness = DEVICE_LITTLE_ENDIAN, | |
b8842209 GH |
356 | }; |
357 | ||
44bfa332 JQ |
358 | static const VMStateDescription vmstate_pmac = { |
359 | .name = "ide", | |
c2a0125a | 360 | .version_id = 5, |
44bfa332 | 361 | .minimum_version_id = 0, |
35d08458 | 362 | .fields = (VMStateField[]) { |
44bfa332 JQ |
363 | VMSTATE_IDE_BUS(bus, MACIOIDEState), |
364 | VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState), | |
bb37a8e8 | 365 | VMSTATE_BOOL(dma_active, MACIOIDEState), |
c2a0125a MCA |
366 | VMSTATE_UINT32(timing_reg, MACIOIDEState), |
367 | VMSTATE_UINT32(irq_reg, MACIOIDEState), | |
44bfa332 | 368 | VMSTATE_END_OF_LIST() |
b8842209 | 369 | } |
44bfa332 | 370 | }; |
b8842209 | 371 | |
07a7484e | 372 | static void macio_ide_reset(DeviceState *dev) |
b8842209 | 373 | { |
07a7484e | 374 | MACIOIDEState *d = MACIO_IDE(dev); |
b8842209 | 375 | |
4a643563 | 376 | ide_bus_reset(&d->bus); |
b8842209 GH |
377 | } |
378 | ||
ae0cebd7 | 379 | static int ide_nop_int(const IDEDMA *dma, bool is_write) |
4aa3510f AG |
380 | { |
381 | return 0; | |
382 | } | |
383 | ||
ae0cebd7 | 384 | static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l) |
3251bdcf JS |
385 | { |
386 | return 0; | |
387 | } | |
388 | ||
ae0cebd7 | 389 | static void ide_dbdma_start(const IDEDMA *dma, IDEState *s, |
097310b5 | 390 | BlockCompletionFunc *cb) |
4aa3510f AG |
391 | { |
392 | MACIOIDEState *m = container_of(dma, MACIOIDEState, dma); | |
4827ac1e | 393 | |
bd4214fc | 394 | s->io_buffer_index = 0; |
4827ac1e | 395 | if (s->drive_kind == IDE_CD) { |
4827ac1e | 396 | s->io_buffer_size = s->packet_transfer_size; |
bd4214fc | 397 | } else { |
b01d44cd | 398 | s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE; |
bd4214fc | 399 | } |
4827ac1e | 400 | |
bd4214fc MCA |
401 | MACIO_DPRINTF("\n\n------------ IDE transfer\n"); |
402 | MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n", | |
403 | s->io_buffer_size, s->io_buffer_index); | |
404 | MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size); | |
405 | MACIO_DPRINTF("-------------------------\n"); | |
4827ac1e | 406 | |
cae32357 | 407 | m->dma_active = true; |
4aa3510f AG |
408 | DBDMA_kick(m->dbdma); |
409 | } | |
410 | ||
411 | static const IDEDMAOps dbdma_ops = { | |
412 | .start_dma = ide_dbdma_start, | |
3251bdcf | 413 | .prepare_buf = ide_nop_int32, |
4aa3510f | 414 | .rw_buf = ide_nop_int, |
4aa3510f AG |
415 | }; |
416 | ||
07a7484e | 417 | static void macio_ide_realizefn(DeviceState *dev, Error **errp) |
b8842209 | 418 | { |
07a7484e AF |
419 | MACIOIDEState *s = MACIO_IDE(dev); |
420 | ||
4f7265ff | 421 | ide_init2(&s->bus, s->ide_irq); |
4aa3510f AG |
422 | |
423 | /* Register DMA callbacks */ | |
424 | s->dma.ops = &dbdma_ops; | |
425 | s->bus.dma = &s->dma; | |
07a7484e AF |
426 | } |
427 | ||
4f7265ff BH |
428 | static void pmac_ide_irq(void *opaque, int n, int level) |
429 | { | |
430 | MACIOIDEState *s = opaque; | |
431 | uint32_t mask = 0x80000000u >> n; | |
432 | ||
433 | /* We need to reflect the IRQ state in the irq register */ | |
434 | if (level) { | |
435 | s->irq_reg |= mask; | |
436 | } else { | |
437 | s->irq_reg &= ~mask; | |
438 | } | |
439 | ||
440 | if (n) { | |
441 | qemu_set_irq(s->real_ide_irq, level); | |
442 | } else { | |
443 | qemu_set_irq(s->real_dma_irq, level); | |
444 | } | |
445 | } | |
446 | ||
07a7484e AF |
447 | static void macio_ide_initfn(Object *obj) |
448 | { | |
449 | SysBusDevice *d = SYS_BUS_DEVICE(obj); | |
450 | MACIOIDEState *s = MACIO_IDE(obj); | |
451 | ||
c6baf942 | 452 | ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); |
1437c94b | 453 | memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000); |
07a7484e | 454 | sysbus_init_mmio(d, &s->mem); |
4f7265ff BH |
455 | sysbus_init_irq(d, &s->real_ide_irq); |
456 | sysbus_init_irq(d, &s->real_dma_irq); | |
457 | s->dma_irq = qemu_allocate_irq(pmac_ide_irq, s, 0); | |
458 | s->ide_irq = qemu_allocate_irq(pmac_ide_irq, s, 1); | |
e451b85f MCA |
459 | |
460 | object_property_add_link(obj, "dbdma", TYPE_MAC_DBDMA, | |
461 | (Object **) &s->dbdma, | |
d2623129 | 462 | qdev_prop_allow_set_link_before_realize, 0); |
07a7484e AF |
463 | } |
464 | ||
0fc84331 MCA |
465 | static Property macio_ide_properties[] = { |
466 | DEFINE_PROP_UINT32("channel", MACIOIDEState, channel, 0), | |
5c8e3d17 | 467 | DEFINE_PROP_UINT32("addr", MACIOIDEState, addr, -1), |
0fc84331 MCA |
468 | DEFINE_PROP_END_OF_LIST(), |
469 | }; | |
470 | ||
07a7484e AF |
471 | static void macio_ide_class_init(ObjectClass *oc, void *data) |
472 | { | |
473 | DeviceClass *dc = DEVICE_CLASS(oc); | |
474 | ||
475 | dc->realize = macio_ide_realizefn; | |
476 | dc->reset = macio_ide_reset; | |
4f67d30b | 477 | device_class_set_props(dc, macio_ide_properties); |
07a7484e | 478 | dc->vmsd = &vmstate_pmac; |
3469d9bc | 479 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
07a7484e | 480 | } |
b8842209 | 481 | |
07a7484e AF |
482 | static const TypeInfo macio_ide_type_info = { |
483 | .name = TYPE_MACIO_IDE, | |
484 | .parent = TYPE_SYS_BUS_DEVICE, | |
485 | .instance_size = sizeof(MACIOIDEState), | |
486 | .instance_init = macio_ide_initfn, | |
487 | .class_init = macio_ide_class_init, | |
488 | }; | |
b8842209 | 489 | |
07a7484e AF |
490 | static void macio_ide_register_types(void) |
491 | { | |
492 | type_register_static(&macio_ide_type_info); | |
493 | } | |
b8842209 | 494 | |
14eefd0e | 495 | /* hd_table must contain 2 block drivers */ |
07a7484e AF |
496 | void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table) |
497 | { | |
498 | int i; | |
b8842209 | 499 | |
07a7484e AF |
500 | for (i = 0; i < 2; i++) { |
501 | if (hd_table[i]) { | |
502 | ide_create_drive(&s->bus, i, hd_table[i]); | |
503 | } | |
504 | } | |
b8842209 | 505 | } |
07a7484e | 506 | |
e451b85f | 507 | void macio_ide_register_dma(MACIOIDEState *s) |
07a7484e | 508 | { |
e451b85f | 509 | DBDMA_register_channel(s->dbdma, s->channel, s->dma_irq, |
07a7484e AF |
510 | pmac_ide_transfer, pmac_ide_flush, s); |
511 | } | |
512 | ||
513 | type_init(macio_ide_register_types) |