[mirror_qemu.git] / hw / ide / macio.c

/*
 * QEMU IDE Emulation: MacIO support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/ppc_mac.h>
#include <hw/mac_dbdma.h>
#include "block.h"
#include "block_int.h"
#include "dma.h"

#include <hw/ide/internal.h>

/***********************************************************/
/* MacIO based PowerPC IDE */

typedef struct MACIOIDEState {
    IDEBus bus;
    BlockDriverAIOCB *aiocb;
} MACIOIDEState;

#define MACIO_PAGE_SIZE 4096

static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
{
    DBDMA_io *io = opaque;
    MACIOIDEState *m = io->opaque;
    IDEState *s = idebus_active_if(&m->bus);

    if (ret < 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);
        ide_atapi_io_error(s, ret);
        io->dma_end(opaque);
        return;
    }

    if (s->io_buffer_size > 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);

        s->packet_transfer_size -= s->io_buffer_size;

        s->io_buffer_index += s->io_buffer_size;
	s->lba += s->io_buffer_index >> 11;
        s->io_buffer_index &= 0x7ff;
    }

    if (s->packet_transfer_size <= 0)
        ide_atapi_cmd_ok(s);

    if (io->len == 0) {
        io->dma_end(opaque);
        return;
    }

    /* launch next transfer */

    s->io_buffer_size = io->len;

    qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
    qemu_sglist_add(&s->sg, io->addr, io->len);
    io->addr += io->len;
    io->len = 0;

    m->aiocb = dma_bdrv_read(s->bs, &s->sg,
                             (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
                             pmac_ide_atapi_transfer_cb, io);
    if (!m->aiocb) {
        qemu_sglist_destroy(&s->sg);
        /* Note: media not present is the most likely case */
        ide_atapi_cmd_error(s, SENSE_NOT_READY,
                            ASC_MEDIUM_NOT_PRESENT);
        io->dma_end(opaque);
        return;
    }
}

static void pmac_ide_transfer_cb(void *opaque, int ret)
{
    DBDMA_io *io = opaque;
    MACIOIDEState *m = io->opaque;
    IDEState *s = idebus_active_if(&m->bus);
    int n;
    int64_t sector_num;

    if (ret < 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);
	ide_dma_error(s);
        io->dma_end(io);
        return;
    }

    sector_num = ide_get_sector(s);
    if (s->io_buffer_size > 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);
        n = (s->io_buffer_size + 0x1ff) >> 9;
        sector_num += n;
        ide_set_sector(s, sector_num);
        s->nsector -= n;
    }

    /* end of transfer ? */
    if (s->nsector == 0) {
        s->status = READY_STAT | SEEK_STAT;
        ide_set_irq(s->bus);
    }

    /* end of DMA ? */

    if (io->len == 0) {
        io->dma_end(io);
	return;
    }

    /* launch next transfer */

    s->io_buffer_index = 0;
    s->io_buffer_size = io->len;

    qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
    qemu_sglist_add(&s->sg, io->addr, io->len);
    io->addr += io->len;
    io->len = 0;

    switch (s->dma_cmd) {
    case IDE_DMA_READ:
        m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
		                 pmac_ide_transfer_cb, io);
        break;
    case IDE_DMA_WRITE:
        m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
		                  pmac_ide_transfer_cb, io);
        break;
    }

    if (!m->aiocb)
        pmac_ide_transfer_cb(io, -1);
}

static void pmac_ide_transfer(DBDMA_io *io)
{
    MACIOIDEState *m = io->opaque;
    IDEState *s = idebus_active_if(&m->bus);

    s->io_buffer_size = 0;
    if (s->drive_kind == IDE_CD) {
        pmac_ide_atapi_transfer_cb(io, 0);
        return;
    }

    pmac_ide_transfer_cb(io, 0);
}

static void pmac_ide_flush(DBDMA_io *io)
{
    MACIOIDEState *m = io->opaque;

    if (m->aiocb)
        qemu_aio_flush();
}

/* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque,
                             target_phys_addr_t addr, uint32_t val)
{
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    switch (addr) {
    case 1 ... 7:
        ide_ioport_write(&d->bus, addr, val);
        break;
    case 8:
    case 22:
        ide_cmd_write(&d->bus, 0, val);
        break;
    default:
        break;
    }
}

static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
{
    uint8_t retval;
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    switch (addr) {
    case 1 ... 7:
        retval = ide_ioport_read(&d->bus, addr);
        break;
    case 8:
    case 22:
        retval = ide_status_read(&d->bus, 0);
        break;
    default:
        retval = 0xFF;
        break;
    }
    return retval;
}

static void pmac_ide_writew (void *opaque,
                             target_phys_addr_t addr, uint32_t val)
{
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    val = bswap16(val);
    if (addr == 0) {
        ide_data_writew(&d->bus, 0, val);
    }
}

static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
{
    uint16_t retval;
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    if (addr == 0) {
        retval = ide_data_readw(&d->bus, 0);
    } else {
        retval = 0xFFFF;
    }
    retval = bswap16(retval);
    return retval;
}

static void pmac_ide_writel (void *opaque,
                             target_phys_addr_t addr, uint32_t val)
{
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    val = bswap32(val);
    if (addr == 0) {
        ide_data_writel(&d->bus, 0, val);
    }
}

static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
{
    uint32_t retval;
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    if (addr == 0) {
        retval = ide_data_readl(&d->bus, 0);
    } else {
        retval = 0xFFFFFFFF;
    }
    retval = bswap32(retval);
    return retval;
}

static CPUWriteMemoryFunc * const pmac_ide_write[] = {
    pmac_ide_writeb,
    pmac_ide_writew,
    pmac_ide_writel,
};

static CPUReadMemoryFunc * const pmac_ide_read[] = {
    pmac_ide_readb,
    pmac_ide_readw,
    pmac_ide_readl,
};

static const VMStateDescription vmstate_pmac = {
    .name = "ide",
    .version_id = 3,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField []) {
        VMSTATE_IDE_BUS(bus, MACIOIDEState),
        VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
        VMSTATE_END_OF_LIST()
    }
};

static void pmac_ide_reset(void *opaque)
{
    MACIOIDEState *d = opaque;

    ide_bus_reset(&d->bus);
}

/* hd_table must contain 4 block drivers */
/* PowerMac uses memory mapped registers, not I/O. Return the memory
   I/O index to access the ide. */
int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
		   void *dbdma, int channel, qemu_irq dma_irq)
{
    MACIOIDEState *d;
    int pmac_ide_memory;

    d = qemu_mallocz(sizeof(MACIOIDEState));
    ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);

    if (dbdma)
        DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);

    pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
                                             pmac_ide_write, d,
                                             DEVICE_NATIVE_ENDIAN);
    vmstate_register(NULL, 0, &vmstate_pmac, d);
    qemu_register_reset(pmac_ide_reset, d);

    return pmac_ide_memory;
}
Commit	Line	Data
b8842209 GH	1	/*
	2	* QEMU IDE Emulation: MacIO support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
59f2a787 GH	25	#include <hw/hw.h>
	26	#include <hw/ppc_mac.h>
	27	#include <hw/mac_dbdma.h>
b8842209 GH	28	#include "block.h"
b8842209 GH	29	#include "block_int.h"
b8842209	30	#include "dma.h"
59f2a787 GH	31
59f2a787 GH	32	#include <hw/ide/internal.h>
b8842209 GH	33
	34	/***********************************************************/
	35	/* MacIO based PowerPC IDE */
	36
	37	typedef struct MACIOIDEState {
	38	IDEBus bus;
	39	BlockDriverAIOCB *aiocb;
	40	} MACIOIDEState;
	41
02c7c992 BS	42	#define MACIO_PAGE_SIZE 4096
02c7c992 BS	43
b8842209 GH	44	static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
	45	{
	46	DBDMA_io *io = opaque;
	47	MACIOIDEState *m = io->opaque;
	48	IDEState *s = idebus_active_if(&m->bus);
	49
	50	if (ret < 0) {
	51	m->aiocb = NULL;
	52	qemu_sglist_destroy(&s->sg);
	53	ide_atapi_io_error(s, ret);
	54	io->dma_end(opaque);
	55	return;
	56	}
	57
	58	if (s->io_buffer_size > 0) {
	59	m->aiocb = NULL;
	60	qemu_sglist_destroy(&s->sg);
	61
	62	s->packet_transfer_size -= s->io_buffer_size;
	63
	64	s->io_buffer_index += s->io_buffer_size;
	65	s->lba += s->io_buffer_index >> 11;
	66	s->io_buffer_index &= 0x7ff;
	67	}
	68
	69	if (s->packet_transfer_size <= 0)
	70	ide_atapi_cmd_ok(s);
	71
	72	if (io->len == 0) {
	73	io->dma_end(opaque);
	74	return;
	75	}
	76
	77	/* launch next transfer */
	78
	79	s->io_buffer_size = io->len;
	80
02c7c992	81	qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
b8842209 GH	82	qemu_sglist_add(&s->sg, io->addr, io->len);
	83	io->addr += io->len;
	84	io->len = 0;
	85
	86	m->aiocb = dma_bdrv_read(s->bs, &s->sg,
	87	(int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
	88	pmac_ide_atapi_transfer_cb, io);
	89	if (!m->aiocb) {
	90	qemu_sglist_destroy(&s->sg);
	91	/* Note: media not present is the most likely case */
	92	ide_atapi_cmd_error(s, SENSE_NOT_READY,
	93	ASC_MEDIUM_NOT_PRESENT);
	94	io->dma_end(opaque);
	95	return;
	96	}
	97	}
	98
	99	static void pmac_ide_transfer_cb(void *opaque, int ret)
	100	{
	101	DBDMA_io *io = opaque;
	102	MACIOIDEState *m = io->opaque;
	103	IDEState *s = idebus_active_if(&m->bus);
	104	int n;
	105	int64_t sector_num;
	106
	107	if (ret < 0) {
	108	m->aiocb = NULL;
	109	qemu_sglist_destroy(&s->sg);
	110	ide_dma_error(s);
	111	io->dma_end(io);
	112	return;
	113	}
	114
	115	sector_num = ide_get_sector(s);
	116	if (s->io_buffer_size > 0) {
	117	m->aiocb = NULL;
	118	qemu_sglist_destroy(&s->sg);
	119	n = (s->io_buffer_size + 0x1ff) >> 9;
	120	sector_num += n;
	121	ide_set_sector(s, sector_num);
	122	s->nsector -= n;
	123	}
	124
	125	/* end of transfer ? */
	126	if (s->nsector == 0) {
	127	s->status = READY_STAT \| SEEK_STAT;
9cdd03a7	128	ide_set_irq(s->bus);
b8842209 GH	129	}
	130
	131	/* end of DMA ? */
	132
	133	if (io->len == 0) {
	134	io->dma_end(io);
	135	return;
	136	}
	137
	138	/* launch next transfer */
	139
	140	s->io_buffer_index = 0;
	141	s->io_buffer_size = io->len;
	142
02c7c992	143	qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
b8842209 GH	144	qemu_sglist_add(&s->sg, io->addr, io->len);
	145	io->addr += io->len;
	146	io->len = 0;
	147
4e1e0051 CH	148	switch (s->dma_cmd) {
4e1e0051 CH	149	case IDE_DMA_READ:
b8842209 GH	150	m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
b8842209 GH	151	pmac_ide_transfer_cb, io);
4e1e0051 CH	152	break;
4e1e0051 CH	153	case IDE_DMA_WRITE:
b8842209 GH	154	m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
b8842209 GH	155	pmac_ide_transfer_cb, io);
4e1e0051 CH	156	break;
	157	}
	158
b8842209 GH	159	if (!m->aiocb)
	160	pmac_ide_transfer_cb(io, -1);
	161	}
	162
	163	static void pmac_ide_transfer(DBDMA_io *io)
	164	{
	165	MACIOIDEState *m = io->opaque;
	166	IDEState *s = idebus_active_if(&m->bus);
	167
	168	s->io_buffer_size = 0;
cd8722bb	169	if (s->drive_kind == IDE_CD) {
b8842209 GH	170	pmac_ide_atapi_transfer_cb(io, 0);
	171	return;
	172	}
	173
	174	pmac_ide_transfer_cb(io, 0);
	175	}
	176
	177	static void pmac_ide_flush(DBDMA_io *io)
	178	{
	179	MACIOIDEState *m = io->opaque;
	180
	181	if (m->aiocb)
	182	qemu_aio_flush();
	183	}
	184
	185	/* PowerMac IDE memory IO */
	186	static void pmac_ide_writeb (void *opaque,
c227f099	187	target_phys_addr_t addr, uint32_t val)
b8842209 GH	188	{
	189	MACIOIDEState *d = opaque;
	190
	191	addr = (addr & 0xFFF) >> 4;
	192	switch (addr) {
	193	case 1 ... 7:
	194	ide_ioport_write(&d->bus, addr, val);
	195	break;
	196	case 8:
	197	case 22:
	198	ide_cmd_write(&d->bus, 0, val);
	199	break;
	200	default:
	201	break;
	202	}
	203	}
	204
c227f099	205	static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
b8842209 GH	206	{
	207	uint8_t retval;
	208	MACIOIDEState *d = opaque;
	209
	210	addr = (addr & 0xFFF) >> 4;
	211	switch (addr) {
	212	case 1 ... 7:
	213	retval = ide_ioport_read(&d->bus, addr);
	214	break;
	215	case 8:
	216	case 22:
	217	retval = ide_status_read(&d->bus, 0);
	218	break;
	219	default:
	220	retval = 0xFF;
	221	break;
	222	}
	223	return retval;
	224	}
	225
	226	static void pmac_ide_writew (void *opaque,
c227f099	227	target_phys_addr_t addr, uint32_t val)
b8842209 GH	228	{
	229	MACIOIDEState *d = opaque;
	230
	231	addr = (addr & 0xFFF) >> 4;
b8842209	232	val = bswap16(val);
b8842209 GH	233	if (addr == 0) {
	234	ide_data_writew(&d->bus, 0, val);
	235	}
	236	}
	237
c227f099	238	static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
b8842209 GH	239	{
	240	uint16_t retval;
	241	MACIOIDEState *d = opaque;
	242
	243	addr = (addr & 0xFFF) >> 4;
	244	if (addr == 0) {
	245	retval = ide_data_readw(&d->bus, 0);
	246	} else {
	247	retval = 0xFFFF;
	248	}
b8842209	249	retval = bswap16(retval);
b8842209 GH	250	return retval;
	251	}
	252
	253	static void pmac_ide_writel (void *opaque,
c227f099	254	target_phys_addr_t addr, uint32_t val)
b8842209 GH	255	{
	256	MACIOIDEState *d = opaque;
	257
	258	addr = (addr & 0xFFF) >> 4;
b8842209	259	val = bswap32(val);
b8842209 GH	260	if (addr == 0) {
	261	ide_data_writel(&d->bus, 0, val);
	262	}
	263	}
	264
c227f099	265	static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
b8842209 GH	266	{
	267	uint32_t retval;
	268	MACIOIDEState *d = opaque;
	269
	270	addr = (addr & 0xFFF) >> 4;
	271	if (addr == 0) {
	272	retval = ide_data_readl(&d->bus, 0);
	273	} else {
	274	retval = 0xFFFFFFFF;
	275	}
b8842209	276	retval = bswap32(retval);
b8842209 GH	277	return retval;
	278	}
	279
bdae2298	280	static CPUWriteMemoryFunc * const pmac_ide_write[] = {
b8842209 GH	281	pmac_ide_writeb,
	282	pmac_ide_writew,
	283	pmac_ide_writel,
	284	};
	285
bdae2298	286	static CPUReadMemoryFunc * const pmac_ide_read[] = {
b8842209 GH	287	pmac_ide_readb,
	288	pmac_ide_readw,
	289	pmac_ide_readl,
	290	};
	291
44bfa332 JQ	292	static const VMStateDescription vmstate_pmac = {
	293	.name = "ide",
	294	.version_id = 3,
	295	.minimum_version_id = 0,
	296	.minimum_version_id_old = 0,
	297	.fields = (VMStateField []) {
	298	VMSTATE_IDE_BUS(bus, MACIOIDEState),
	299	VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
	300	VMSTATE_END_OF_LIST()
b8842209	301	}
44bfa332	302	};
b8842209 GH	303
	304	static void pmac_ide_reset(void *opaque)
	305	{
	306	MACIOIDEState *d = opaque;
	307
4a643563	308	ide_bus_reset(&d->bus);
b8842209 GH	309	}
	310
	311	/* hd_table must contain 4 block drivers */
	312	/* PowerMac uses memory mapped registers, not I/O. Return the memory
	313	I/O index to access the ide. */
f455e98c	314	int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
b8842209 GH	315	void *dbdma, int channel, qemu_irq dma_irq)
	316	{
	317	MACIOIDEState *d;
	318	int pmac_ide_memory;
	319
	320	d = qemu_mallocz(sizeof(MACIOIDEState));
57234ee4	321	ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);
b8842209 GH	322
	323	if (dbdma)
	324	DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
	325
	326	pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
2507c12a AG	327	pmac_ide_write, d,
2507c12a AG	328	DEVICE_NATIVE_ENDIAN);
0be71e32	329	vmstate_register(NULL, 0, &vmstate_pmac, d);
b8842209	330	qemu_register_reset(pmac_ide_reset, d);
b8842209 GH	331
	332	return pmac_ide_memory;
	333	}